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Commit | Line | Data |
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c1b6a3d8 TB |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* Driver for SGI's IOC3 based Ethernet cards as found in the PCI card. | |
1da177e4 | 3 | * |
bbfb86c5 | 4 | * Copyright (C) 1999, 2000, 01, 03, 06 Ralf Baechle |
1da177e4 LT |
5 | * Copyright (C) 1995, 1999, 2000, 2001 by Silicon Graphics, Inc. |
6 | * | |
7 | * References: | |
8 | * o IOC3 ASIC specification 4.51, 1996-04-18 | |
9 | * o IEEE 802.3 specification, 2000 edition | |
10 | * o DP38840A Specification, National Semiconductor, March 1997 | |
11 | * | |
12 | * To do: | |
13 | * | |
1da177e4 LT |
14 | * o Use prefetching for large packets. What is a good lower limit for |
15 | * prefetching? | |
1da177e4 | 16 | * o Use hardware checksums. |
1da177e4 LT |
17 | * o Which PHYs might possibly be attached to the IOC3 in real live, |
18 | * which workarounds are required for them? Do we ever have Lucent's? | |
19 | * o For the 2.5 branch kill the mii-tool ioctls. | |
20 | */ | |
21 | ||
22 | #define IOC3_NAME "ioc3-eth" | |
d5b20697 | 23 | #define IOC3_VERSION "2.6.3-4" |
1da177e4 | 24 | |
1da177e4 LT |
25 | #include <linux/delay.h> |
26 | #include <linux/kernel.h> | |
27 | #include <linux/mm.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/module.h> | |
0ce5ebd2 TB |
30 | #include <linux/init.h> |
31 | #include <linux/crc16.h> | |
1da177e4 LT |
32 | #include <linux/crc32.h> |
33 | #include <linux/mii.h> | |
34 | #include <linux/in.h> | |
c1b6a3d8 | 35 | #include <linux/io.h> |
1da177e4 LT |
36 | #include <linux/ip.h> |
37 | #include <linux/tcp.h> | |
38 | #include <linux/udp.h> | |
5a0e3ad6 | 39 | #include <linux/gfp.h> |
1da177e4 LT |
40 | #include <linux/netdevice.h> |
41 | #include <linux/etherdevice.h> | |
42 | #include <linux/ethtool.h> | |
43 | #include <linux/skbuff.h> | |
4dd14747 | 44 | #include <linux/dma-mapping.h> |
0ce5ebd2 TB |
45 | #include <linux/platform_device.h> |
46 | #include <linux/nvmem-consumer.h> | |
ed870f6a | 47 | |
1da177e4 LT |
48 | #include <net/ip.h> |
49 | ||
1da177e4 | 50 | #include <asm/sn/ioc3.h> |
1da177e4 LT |
51 | #include <asm/pci/bridge.h> |
52 | ||
0ce5ebd2 TB |
53 | #define CRC16_INIT 0 |
54 | #define CRC16_VALID 0xb001 | |
55 | ||
141a7dbb TB |
56 | /* Number of RX buffers. This is tunable in the range of 16 <= x < 512. |
57 | * The value must be a power of two. | |
1da177e4 | 58 | */ |
141a7dbb TB |
59 | #define RX_BUFFS 64 |
60 | #define RX_RING_ENTRIES 512 /* fixed in hardware */ | |
61 | #define RX_RING_MASK (RX_RING_ENTRIES - 1) | |
ed870f6a | 62 | #define RX_RING_SIZE (RX_RING_ENTRIES * sizeof(u64)) |
141a7dbb TB |
63 | |
64 | /* 128 TX buffers (not tunable) */ | |
65 | #define TX_RING_ENTRIES 128 | |
66 | #define TX_RING_MASK (TX_RING_ENTRIES - 1) | |
ed870f6a | 67 | #define TX_RING_SIZE (TX_RING_ENTRIES * sizeof(struct ioc3_etxd)) |
1da177e4 | 68 | |
850d2fed TB |
69 | /* IOC3 does dma transfers in 128 byte blocks */ |
70 | #define IOC3_DMA_XFER_LEN 128UL | |
71 | ||
72 | /* Every RX buffer starts with 8 byte descriptor data */ | |
73 | #define RX_OFFSET (sizeof(struct ioc3_erxbuf) + NET_IP_ALIGN) | |
74 | #define RX_BUF_SIZE (13 * IOC3_DMA_XFER_LEN) | |
75 | ||
3498cb27 TB |
76 | #define ETCSR_FD ((21 << ETCSR_IPGR2_SHIFT) | (21 << ETCSR_IPGR1_SHIFT) | 21) |
77 | #define ETCSR_HD ((17 << ETCSR_IPGR2_SHIFT) | (11 << ETCSR_IPGR1_SHIFT) | 21) | |
1da177e4 LT |
78 | |
79 | /* Private per NIC data of the driver. */ | |
80 | struct ioc3_private { | |
cbe7d517 | 81 | struct ioc3_ethregs *regs; |
ed870f6a | 82 | struct device *dma_dev; |
cbe7d517 | 83 | u32 *ssram; |
1da177e4 | 84 | unsigned long *rxr; /* pointer to receiver ring */ |
369a782a | 85 | void *tx_ring; |
1da177e4 | 86 | struct ioc3_etxd *txr; |
ed870f6a TB |
87 | dma_addr_t rxr_dma; |
88 | dma_addr_t txr_dma; | |
141a7dbb TB |
89 | struct sk_buff *rx_skbs[RX_RING_ENTRIES]; |
90 | struct sk_buff *tx_skbs[TX_RING_ENTRIES]; | |
1da177e4 LT |
91 | int rx_ci; /* RX consumer index */ |
92 | int rx_pi; /* RX producer index */ | |
93 | int tx_ci; /* TX consumer index */ | |
94 | int tx_pi; /* TX producer index */ | |
95 | int txqlen; | |
96 | u32 emcr, ehar_h, ehar_l; | |
97 | spinlock_t ioc3_lock; | |
98 | struct mii_if_info mii; | |
bbfb86c5 | 99 | |
1da177e4 LT |
100 | /* Members used by autonegotiation */ |
101 | struct timer_list ioc3_timer; | |
102 | }; | |
103 | ||
1da177e4 LT |
104 | static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); |
105 | static void ioc3_set_multicast_list(struct net_device *dev); | |
28d304ef | 106 | static netdev_tx_t ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev); |
0290bd29 | 107 | static void ioc3_timeout(struct net_device *dev, unsigned int txqueue); |
1da177e4 | 108 | static inline unsigned int ioc3_hash(const unsigned char *addr); |
fcd0da5a | 109 | static void ioc3_start(struct ioc3_private *ip); |
1da177e4 LT |
110 | static inline void ioc3_stop(struct ioc3_private *ip); |
111 | static void ioc3_init(struct net_device *dev); | |
850d2fed | 112 | static int ioc3_alloc_rx_bufs(struct net_device *dev); |
19a957b6 TB |
113 | static void ioc3_free_rx_bufs(struct ioc3_private *ip); |
114 | static inline void ioc3_clean_tx_ring(struct ioc3_private *ip); | |
1da177e4 | 115 | |
7282d491 | 116 | static const struct ethtool_ops ioc3_ethtool_ops; |
1da177e4 | 117 | |
1da177e4 LT |
118 | static inline unsigned long aligned_rx_skb_addr(unsigned long addr) |
119 | { | |
850d2fed | 120 | return (~addr + 1) & (IOC3_DMA_XFER_LEN - 1UL); |
1da177e4 LT |
121 | } |
122 | ||
ed870f6a TB |
123 | static inline int ioc3_alloc_skb(struct ioc3_private *ip, struct sk_buff **skb, |
124 | struct ioc3_erxbuf **rxb, dma_addr_t *rxb_dma) | |
1da177e4 | 125 | { |
850d2fed | 126 | struct sk_buff *new_skb; |
ed870f6a | 127 | dma_addr_t d; |
850d2fed | 128 | int offset; |
1da177e4 | 129 | |
850d2fed TB |
130 | new_skb = alloc_skb(RX_BUF_SIZE + IOC3_DMA_XFER_LEN - 1, GFP_ATOMIC); |
131 | if (!new_skb) | |
132 | return -ENOMEM; | |
c1b6a3d8 | 133 | |
850d2fed TB |
134 | /* ensure buffer is aligned to IOC3_DMA_XFER_LEN */ |
135 | offset = aligned_rx_skb_addr((unsigned long)new_skb->data); | |
136 | if (offset) | |
137 | skb_reserve(new_skb, offset); | |
138 | ||
ed870f6a TB |
139 | d = dma_map_single(ip->dma_dev, new_skb->data, |
140 | RX_BUF_SIZE, DMA_FROM_DEVICE); | |
141 | ||
142 | if (dma_mapping_error(ip->dma_dev, d)) { | |
143 | dev_kfree_skb_any(new_skb); | |
144 | return -ENOMEM; | |
145 | } | |
146 | *rxb_dma = d; | |
850d2fed TB |
147 | *rxb = (struct ioc3_erxbuf *)new_skb->data; |
148 | skb_reserve(new_skb, RX_OFFSET); | |
149 | *skb = new_skb; | |
1da177e4 | 150 | |
850d2fed | 151 | return 0; |
1da177e4 LT |
152 | } |
153 | ||
ed870f6a TB |
154 | #ifdef CONFIG_PCI_XTALK_BRIDGE |
155 | static inline unsigned long ioc3_map(dma_addr_t addr, unsigned long attr) | |
1da177e4 | 156 | { |
ed870f6a TB |
157 | return (addr & ~PCI64_ATTR_BAR) | attr; |
158 | } | |
1da177e4 | 159 | |
ed870f6a | 160 | #define ERBAR_VAL (ERBAR_BARRIER_BIT << ERBAR_RXBARR_SHIFT) |
1da177e4 | 161 | #else |
ed870f6a TB |
162 | static inline unsigned long ioc3_map(dma_addr_t addr, unsigned long attr) |
163 | { | |
164 | return addr; | |
1da177e4 | 165 | } |
ed870f6a TB |
166 | |
167 | #define ERBAR_VAL 0 | |
168 | #endif | |
169 | ||
0ce5ebd2 | 170 | static int ioc3eth_nvmem_match(struct device *dev, const void *data) |
1da177e4 | 171 | { |
0ce5ebd2 TB |
172 | const char *name = dev_name(dev); |
173 | const char *prefix = data; | |
174 | int prefix_len; | |
1da177e4 | 175 | |
0ce5ebd2 TB |
176 | prefix_len = strlen(prefix); |
177 | if (strlen(name) < (prefix_len + 3)) | |
178 | return 0; | |
1da177e4 | 179 | |
0ce5ebd2 TB |
180 | if (memcmp(prefix, name, prefix_len) != 0) |
181 | return 0; | |
1da177e4 | 182 | |
0ce5ebd2 TB |
183 | /* found nvmem device which is attached to our ioc3 |
184 | * now check for one wire family code 09, 89 and 91 | |
185 | */ | |
186 | if (memcmp(name + prefix_len, "09-", 3) == 0) | |
187 | return 1; | |
188 | if (memcmp(name + prefix_len, "89-", 3) == 0) | |
189 | return 1; | |
190 | if (memcmp(name + prefix_len, "91-", 3) == 0) | |
191 | return 1; | |
1da177e4 LT |
192 | |
193 | return 0; | |
194 | } | |
195 | ||
0ce5ebd2 | 196 | static int ioc3eth_get_mac_addr(struct resource *res, u8 mac_addr[6]) |
1da177e4 | 197 | { |
0ce5ebd2 TB |
198 | struct nvmem_device *nvmem; |
199 | char prefix[24]; | |
200 | u8 prom[16]; | |
201 | int ret; | |
1da177e4 LT |
202 | int i; |
203 | ||
0ce5ebd2 TB |
204 | snprintf(prefix, sizeof(prefix), "ioc3-%012llx-", |
205 | res->start & ~0xffff); | |
1da177e4 | 206 | |
0ce5ebd2 TB |
207 | nvmem = nvmem_device_find(prefix, ioc3eth_nvmem_match); |
208 | if (IS_ERR(nvmem)) | |
209 | return PTR_ERR(nvmem); | |
1da177e4 | 210 | |
0ce5ebd2 TB |
211 | ret = nvmem_device_read(nvmem, 0, 16, prom); |
212 | nvmem_device_put(nvmem); | |
213 | if (ret < 0) | |
214 | return ret; | |
1da177e4 | 215 | |
0ce5ebd2 TB |
216 | /* check, if content is valid */ |
217 | if (prom[0] != 0x0a || | |
218 | crc16(CRC16_INIT, prom, 13) != CRC16_VALID) | |
219 | return -EINVAL; | |
1da177e4 | 220 | |
0ce5ebd2 TB |
221 | for (i = 0; i < 6; i++) |
222 | mac_addr[i] = prom[10 - i]; | |
1da177e4 | 223 | |
0ce5ebd2 | 224 | return 0; |
1da177e4 LT |
225 | } |
226 | ||
227 | static void __ioc3_set_mac_address(struct net_device *dev) | |
228 | { | |
229 | struct ioc3_private *ip = netdev_priv(dev); | |
1da177e4 | 230 | |
cbe7d517 TB |
231 | writel((dev->dev_addr[5] << 8) | |
232 | dev->dev_addr[4], | |
233 | &ip->regs->emar_h); | |
234 | writel((dev->dev_addr[3] << 24) | | |
235 | (dev->dev_addr[2] << 16) | | |
236 | (dev->dev_addr[1] << 8) | | |
237 | dev->dev_addr[0], | |
238 | &ip->regs->emar_l); | |
1da177e4 LT |
239 | } |
240 | ||
241 | static int ioc3_set_mac_address(struct net_device *dev, void *addr) | |
242 | { | |
243 | struct ioc3_private *ip = netdev_priv(dev); | |
244 | struct sockaddr *sa = addr; | |
245 | ||
246 | memcpy(dev->dev_addr, sa->sa_data, dev->addr_len); | |
247 | ||
248 | spin_lock_irq(&ip->ioc3_lock); | |
249 | __ioc3_set_mac_address(dev); | |
250 | spin_unlock_irq(&ip->ioc3_lock); | |
251 | ||
252 | return 0; | |
253 | } | |
254 | ||
c1b6a3d8 | 255 | /* Caller must hold the ioc3_lock ever for MII readers. This is also |
1da177e4 LT |
256 | * used to protect the transmitter side but it's low contention. |
257 | */ | |
258 | static int ioc3_mdio_read(struct net_device *dev, int phy, int reg) | |
259 | { | |
260 | struct ioc3_private *ip = netdev_priv(dev); | |
cbe7d517 | 261 | struct ioc3_ethregs *regs = ip->regs; |
1da177e4 | 262 | |
cbe7d517 TB |
263 | while (readl(®s->micr) & MICR_BUSY) |
264 | ; | |
265 | writel((phy << MICR_PHYADDR_SHIFT) | reg | MICR_READTRIG, | |
266 | ®s->micr); | |
267 | while (readl(®s->micr) & MICR_BUSY) | |
268 | ; | |
1da177e4 | 269 | |
cbe7d517 | 270 | return readl(®s->midr_r) & MIDR_DATA_MASK; |
1da177e4 LT |
271 | } |
272 | ||
273 | static void ioc3_mdio_write(struct net_device *dev, int phy, int reg, int data) | |
274 | { | |
275 | struct ioc3_private *ip = netdev_priv(dev); | |
cbe7d517 TB |
276 | struct ioc3_ethregs *regs = ip->regs; |
277 | ||
278 | while (readl(®s->micr) & MICR_BUSY) | |
279 | ; | |
280 | writel(data, ®s->midr_w); | |
281 | writel((phy << MICR_PHYADDR_SHIFT) | reg, ®s->micr); | |
282 | while (readl(®s->micr) & MICR_BUSY) | |
283 | ; | |
1da177e4 LT |
284 | } |
285 | ||
286 | static int ioc3_mii_init(struct ioc3_private *ip); | |
287 | ||
288 | static struct net_device_stats *ioc3_get_stats(struct net_device *dev) | |
289 | { | |
290 | struct ioc3_private *ip = netdev_priv(dev); | |
cbe7d517 | 291 | struct ioc3_ethregs *regs = ip->regs; |
1da177e4 | 292 | |
cbe7d517 | 293 | dev->stats.collisions += readl(®s->etcdc) & ETCDC_COLLCNT_MASK; |
0a17ee90 | 294 | return &dev->stats; |
1da177e4 LT |
295 | } |
296 | ||
c1b6a3d8 | 297 | static void ioc3_tcpudp_checksum(struct sk_buff *skb, u32 hwsum, int len) |
1da177e4 LT |
298 | { |
299 | struct ethhdr *eh = eth_hdr(skb); | |
1da177e4 | 300 | unsigned int proto; |
1da177e4 | 301 | unsigned char *cp; |
c1b6a3d8 TB |
302 | struct iphdr *ih; |
303 | u32 csum, ehsum; | |
304 | u16 *ew; | |
1da177e4 | 305 | |
c1b6a3d8 | 306 | /* Did hardware handle the checksum at all? The cases we can handle |
1da177e4 LT |
307 | * are: |
308 | * | |
309 | * - TCP and UDP checksums of IPv4 only. | |
310 | * - IPv6 would be doable but we keep that for later ... | |
311 | * - Only unfragmented packets. Did somebody already tell you | |
312 | * fragmentation is evil? | |
313 | * - don't care about packet size. Worst case when processing a | |
314 | * malformed packet we'll try to access the packet at ip header + | |
315 | * 64 bytes which is still inside the skb. Even in the unlikely | |
316 | * case where the checksum is right the higher layers will still | |
317 | * drop the packet as appropriate. | |
318 | */ | |
17d0cdfa | 319 | if (eh->h_proto != htons(ETH_P_IP)) |
1da177e4 LT |
320 | return; |
321 | ||
c1b6a3d8 | 322 | ih = (struct iphdr *)((char *)eh + ETH_HLEN); |
56f8a75c | 323 | if (ip_is_fragment(ih)) |
1da177e4 LT |
324 | return; |
325 | ||
326 | proto = ih->protocol; | |
327 | if (proto != IPPROTO_TCP && proto != IPPROTO_UDP) | |
328 | return; | |
329 | ||
330 | /* Same as tx - compute csum of pseudo header */ | |
331 | csum = hwsum + | |
332 | (ih->tot_len - (ih->ihl << 2)) + | |
c1b6a3d8 | 333 | htons((u16)ih->protocol) + |
1da177e4 LT |
334 | (ih->saddr >> 16) + (ih->saddr & 0xffff) + |
335 | (ih->daddr >> 16) + (ih->daddr & 0xffff); | |
336 | ||
337 | /* Sum up ethernet dest addr, src addr and protocol */ | |
c1b6a3d8 | 338 | ew = (u16 *)eh; |
1da177e4 LT |
339 | ehsum = ew[0] + ew[1] + ew[2] + ew[3] + ew[4] + ew[5] + ew[6]; |
340 | ||
341 | ehsum = (ehsum & 0xffff) + (ehsum >> 16); | |
342 | ehsum = (ehsum & 0xffff) + (ehsum >> 16); | |
343 | ||
344 | csum += 0xffff ^ ehsum; | |
345 | ||
346 | /* In the next step we also subtract the 1's complement | |
c1b6a3d8 TB |
347 | * checksum of the trailing ethernet CRC. |
348 | */ | |
1da177e4 LT |
349 | cp = (char *)eh + len; /* points at trailing CRC */ |
350 | if (len & 1) { | |
c1b6a3d8 TB |
351 | csum += 0xffff ^ (u16)((cp[1] << 8) | cp[0]); |
352 | csum += 0xffff ^ (u16)((cp[3] << 8) | cp[2]); | |
1da177e4 | 353 | } else { |
c1b6a3d8 TB |
354 | csum += 0xffff ^ (u16)((cp[0] << 8) | cp[1]); |
355 | csum += 0xffff ^ (u16)((cp[2] << 8) | cp[3]); | |
1da177e4 LT |
356 | } |
357 | ||
358 | csum = (csum & 0xffff) + (csum >> 16); | |
359 | csum = (csum & 0xffff) + (csum >> 16); | |
360 | ||
361 | if (csum == 0xffff) | |
362 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
363 | } | |
1da177e4 | 364 | |
0a17ee90 | 365 | static inline void ioc3_rx(struct net_device *dev) |
1da177e4 | 366 | { |
0a17ee90 | 367 | struct ioc3_private *ip = netdev_priv(dev); |
1da177e4 | 368 | struct sk_buff *skb, *new_skb; |
1da177e4 LT |
369 | int rx_entry, n_entry, len; |
370 | struct ioc3_erxbuf *rxb; | |
371 | unsigned long *rxr; | |
ed870f6a | 372 | dma_addr_t d; |
1da177e4 LT |
373 | u32 w0, err; |
374 | ||
64699336 | 375 | rxr = ip->rxr; /* Ring base */ |
1da177e4 LT |
376 | rx_entry = ip->rx_ci; /* RX consume index */ |
377 | n_entry = ip->rx_pi; | |
378 | ||
379 | skb = ip->rx_skbs[rx_entry]; | |
c1b6a3d8 | 380 | rxb = (struct ioc3_erxbuf *)(skb->data - RX_OFFSET); |
1da177e4 LT |
381 | w0 = be32_to_cpu(rxb->w0); |
382 | ||
383 | while (w0 & ERXBUF_V) { | |
384 | err = be32_to_cpu(rxb->err); /* It's valid ... */ | |
385 | if (err & ERXBUF_GOODPKT) { | |
386 | len = ((w0 >> ERXBUF_BYTECNT_SHIFT) & 0x7ff) - 4; | |
850d2fed | 387 | skb_put(skb, len); |
0a17ee90 | 388 | skb->protocol = eth_type_trans(skb, dev); |
1da177e4 | 389 | |
ed870f6a | 390 | if (ioc3_alloc_skb(ip, &new_skb, &rxb, &d)) { |
1da177e4 | 391 | /* Ouch, drop packet and just recycle packet |
c1b6a3d8 TB |
392 | * to keep the ring filled. |
393 | */ | |
0a17ee90 | 394 | dev->stats.rx_dropped++; |
1da177e4 | 395 | new_skb = skb; |
ed870f6a | 396 | d = rxr[rx_entry]; |
1da177e4 LT |
397 | goto next; |
398 | } | |
399 | ||
6d95ff97 | 400 | if (likely(dev->features & NETIF_F_RXCSUM)) |
bbfb86c5 | 401 | ioc3_tcpudp_checksum(skb, |
c1b6a3d8 TB |
402 | w0 & ERXBUF_IPCKSUM_MASK, |
403 | len); | |
1da177e4 | 404 | |
ed870f6a TB |
405 | dma_unmap_single(ip->dma_dev, rxr[rx_entry], |
406 | RX_BUF_SIZE, DMA_FROM_DEVICE); | |
407 | ||
1da177e4 LT |
408 | netif_rx(skb); |
409 | ||
410 | ip->rx_skbs[rx_entry] = NULL; /* Poison */ | |
411 | ||
0a17ee90 RB |
412 | dev->stats.rx_packets++; /* Statistics */ |
413 | dev->stats.rx_bytes += len; | |
1da177e4 | 414 | } else { |
0a17ee90 | 415 | /* The frame is invalid and the skb never |
c1b6a3d8 TB |
416 | * reached the network layer so we can just |
417 | * recycle it. | |
418 | */ | |
0a17ee90 | 419 | new_skb = skb; |
ed870f6a | 420 | d = rxr[rx_entry]; |
0a17ee90 | 421 | dev->stats.rx_errors++; |
1da177e4 LT |
422 | } |
423 | if (err & ERXBUF_CRCERR) /* Statistics */ | |
0a17ee90 | 424 | dev->stats.rx_crc_errors++; |
1da177e4 | 425 | if (err & ERXBUF_FRAMERR) |
0a17ee90 | 426 | dev->stats.rx_frame_errors++; |
ed870f6a | 427 | |
1da177e4 LT |
428 | next: |
429 | ip->rx_skbs[n_entry] = new_skb; | |
ed870f6a | 430 | rxr[n_entry] = cpu_to_be64(ioc3_map(d, PCI64_ATTR_BAR)); |
1da177e4 | 431 | rxb->w0 = 0; /* Clear valid flag */ |
141a7dbb | 432 | n_entry = (n_entry + 1) & RX_RING_MASK; /* Update erpir */ |
1da177e4 LT |
433 | |
434 | /* Now go on to the next ring entry. */ | |
141a7dbb | 435 | rx_entry = (rx_entry + 1) & RX_RING_MASK; |
1da177e4 | 436 | skb = ip->rx_skbs[rx_entry]; |
c1b6a3d8 | 437 | rxb = (struct ioc3_erxbuf *)(skb->data - RX_OFFSET); |
1da177e4 LT |
438 | w0 = be32_to_cpu(rxb->w0); |
439 | } | |
cbe7d517 | 440 | writel((n_entry << 3) | ERPIR_ARM, &ip->regs->erpir); |
1da177e4 LT |
441 | ip->rx_pi = n_entry; |
442 | ip->rx_ci = rx_entry; | |
443 | } | |
444 | ||
0a17ee90 | 445 | static inline void ioc3_tx(struct net_device *dev) |
1da177e4 | 446 | { |
0a17ee90 | 447 | struct ioc3_private *ip = netdev_priv(dev); |
cbe7d517 | 448 | struct ioc3_ethregs *regs = ip->regs; |
1da177e4 | 449 | unsigned long packets, bytes; |
1da177e4 LT |
450 | int tx_entry, o_entry; |
451 | struct sk_buff *skb; | |
452 | u32 etcir; | |
453 | ||
454 | spin_lock(&ip->ioc3_lock); | |
cbe7d517 | 455 | etcir = readl(®s->etcir); |
1da177e4 | 456 | |
141a7dbb | 457 | tx_entry = (etcir >> 7) & TX_RING_MASK; |
1da177e4 LT |
458 | o_entry = ip->tx_ci; |
459 | packets = 0; | |
460 | bytes = 0; | |
461 | ||
462 | while (o_entry != tx_entry) { | |
463 | packets++; | |
464 | skb = ip->tx_skbs[o_entry]; | |
465 | bytes += skb->len; | |
d1a096c2 | 466 | dev_consume_skb_irq(skb); |
1da177e4 LT |
467 | ip->tx_skbs[o_entry] = NULL; |
468 | ||
141a7dbb | 469 | o_entry = (o_entry + 1) & TX_RING_MASK; /* Next */ |
1da177e4 | 470 | |
cbe7d517 | 471 | etcir = readl(®s->etcir); /* More pkts sent? */ |
141a7dbb | 472 | tx_entry = (etcir >> 7) & TX_RING_MASK; |
1da177e4 LT |
473 | } |
474 | ||
0a17ee90 RB |
475 | dev->stats.tx_packets += packets; |
476 | dev->stats.tx_bytes += bytes; | |
1da177e4 LT |
477 | ip->txqlen -= packets; |
478 | ||
141a7dbb | 479 | if (netif_queue_stopped(dev) && ip->txqlen < TX_RING_ENTRIES) |
0a17ee90 | 480 | netif_wake_queue(dev); |
1da177e4 LT |
481 | |
482 | ip->tx_ci = o_entry; | |
483 | spin_unlock(&ip->ioc3_lock); | |
484 | } | |
485 | ||
c1b6a3d8 | 486 | /* Deal with fatal IOC3 errors. This condition might be caused by a hard or |
1da177e4 LT |
487 | * software problems, so we should try to recover |
488 | * more gracefully if this ever happens. In theory we might be flooded | |
489 | * with such error interrupts if something really goes wrong, so we might | |
490 | * also consider to take the interface down. | |
491 | */ | |
0a17ee90 | 492 | static void ioc3_error(struct net_device *dev, u32 eisr) |
1da177e4 | 493 | { |
0a17ee90 | 494 | struct ioc3_private *ip = netdev_priv(dev); |
1da177e4 LT |
495 | |
496 | spin_lock(&ip->ioc3_lock); | |
497 | ||
498 | if (eisr & EISR_RXOFLO) | |
c1b6a3d8 | 499 | net_err_ratelimited("%s: RX overflow.\n", dev->name); |
1da177e4 | 500 | if (eisr & EISR_RXBUFOFLO) |
c1b6a3d8 | 501 | net_err_ratelimited("%s: RX buffer overflow.\n", dev->name); |
1da177e4 | 502 | if (eisr & EISR_RXMEMERR) |
c1b6a3d8 | 503 | net_err_ratelimited("%s: RX PCI error.\n", dev->name); |
1da177e4 | 504 | if (eisr & EISR_RXPARERR) |
c1b6a3d8 | 505 | net_err_ratelimited("%s: RX SSRAM parity error.\n", dev->name); |
1da177e4 | 506 | if (eisr & EISR_TXBUFUFLO) |
c1b6a3d8 | 507 | net_err_ratelimited("%s: TX buffer underflow.\n", dev->name); |
1da177e4 | 508 | if (eisr & EISR_TXMEMERR) |
c1b6a3d8 | 509 | net_err_ratelimited("%s: TX PCI error.\n", dev->name); |
1da177e4 LT |
510 | |
511 | ioc3_stop(ip); | |
19a957b6 TB |
512 | ioc3_free_rx_bufs(ip); |
513 | ioc3_clean_tx_ring(ip); | |
514 | ||
1da177e4 | 515 | ioc3_init(dev); |
850d2fed TB |
516 | if (ioc3_alloc_rx_bufs(dev)) { |
517 | netdev_err(dev, "%s: rx buffer allocation failed\n", __func__); | |
518 | spin_unlock(&ip->ioc3_lock); | |
519 | return; | |
520 | } | |
fcd0da5a | 521 | ioc3_start(ip); |
1da177e4 LT |
522 | ioc3_mii_init(ip); |
523 | ||
524 | netif_wake_queue(dev); | |
525 | ||
526 | spin_unlock(&ip->ioc3_lock); | |
527 | } | |
528 | ||
529 | /* The interrupt handler does all of the Rx thread work and cleans up | |
c1b6a3d8 TB |
530 | * after the Tx thread. |
531 | */ | |
cbe7d517 | 532 | static irqreturn_t ioc3_interrupt(int irq, void *dev_id) |
1da177e4 | 533 | { |
cbe7d517 TB |
534 | struct ioc3_private *ip = netdev_priv(dev_id); |
535 | struct ioc3_ethregs *regs = ip->regs; | |
1da177e4 LT |
536 | u32 eisr; |
537 | ||
cbe7d517 TB |
538 | eisr = readl(®s->eisr); |
539 | writel(eisr, ®s->eisr); | |
540 | readl(®s->eisr); /* Flush */ | |
1da177e4 LT |
541 | |
542 | if (eisr & (EISR_RXOFLO | EISR_RXBUFOFLO | EISR_RXMEMERR | | |
c1b6a3d8 | 543 | EISR_RXPARERR | EISR_TXBUFUFLO | EISR_TXMEMERR)) |
cbe7d517 | 544 | ioc3_error(dev_id, eisr); |
1da177e4 | 545 | if (eisr & EISR_RXTIMERINT) |
cbe7d517 | 546 | ioc3_rx(dev_id); |
1da177e4 | 547 | if (eisr & EISR_TXEXPLICIT) |
cbe7d517 | 548 | ioc3_tx(dev_id); |
1da177e4 LT |
549 | |
550 | return IRQ_HANDLED; | |
551 | } | |
552 | ||
553 | static inline void ioc3_setup_duplex(struct ioc3_private *ip) | |
554 | { | |
cbe7d517 | 555 | struct ioc3_ethregs *regs = ip->regs; |
1da177e4 | 556 | |
d1c94542 TB |
557 | spin_lock_irq(&ip->ioc3_lock); |
558 | ||
1da177e4 | 559 | if (ip->mii.full_duplex) { |
cbe7d517 | 560 | writel(ETCSR_FD, ®s->etcsr); |
1da177e4 LT |
561 | ip->emcr |= EMCR_DUPLEX; |
562 | } else { | |
cbe7d517 | 563 | writel(ETCSR_HD, ®s->etcsr); |
1da177e4 LT |
564 | ip->emcr &= ~EMCR_DUPLEX; |
565 | } | |
cbe7d517 | 566 | writel(ip->emcr, ®s->emcr); |
d1c94542 TB |
567 | |
568 | spin_unlock_irq(&ip->ioc3_lock); | |
1da177e4 LT |
569 | } |
570 | ||
dfc57004 | 571 | static void ioc3_timer(struct timer_list *t) |
1da177e4 | 572 | { |
dfc57004 | 573 | struct ioc3_private *ip = from_timer(ip, t, ioc3_timer); |
1da177e4 LT |
574 | |
575 | /* Print the link status if it has changed */ | |
576 | mii_check_media(&ip->mii, 1, 0); | |
577 | ioc3_setup_duplex(ip); | |
578 | ||
c1b6a3d8 | 579 | ip->ioc3_timer.expires = jiffies + ((12 * HZ) / 10); /* 1.2s */ |
1da177e4 LT |
580 | add_timer(&ip->ioc3_timer); |
581 | } | |
582 | ||
c1b6a3d8 | 583 | /* Try to find a PHY. There is no apparent relation between the MII addresses |
1da177e4 | 584 | * in the SGI documentation and what we find in reality, so we simply probe |
34a568a2 | 585 | * for the PHY. |
1da177e4 LT |
586 | */ |
587 | static int ioc3_mii_init(struct ioc3_private *ip) | |
588 | { | |
1da177e4 | 589 | u16 word; |
34a568a2 | 590 | int i; |
1da177e4 LT |
591 | |
592 | for (i = 0; i < 32; i++) { | |
0ce5ebd2 | 593 | word = ioc3_mdio_read(ip->mii.dev, i, MII_PHYSID1); |
1da177e4 LT |
594 | |
595 | if (word != 0xffff && word != 0x0000) { | |
34a568a2 TB |
596 | ip->mii.phy_id = i; |
597 | return 0; | |
1da177e4 LT |
598 | } |
599 | } | |
34a568a2 TB |
600 | ip->mii.phy_id = -1; |
601 | return -ENODEV; | |
f0ba7358 RB |
602 | } |
603 | ||
604 | static void ioc3_mii_start(struct ioc3_private *ip) | |
605 | { | |
c1b6a3d8 | 606 | ip->ioc3_timer.expires = jiffies + (12 * HZ) / 10; /* 1.2 sec. */ |
1da177e4 | 607 | add_timer(&ip->ioc3_timer); |
1da177e4 LT |
608 | } |
609 | ||
ed870f6a TB |
610 | static inline void ioc3_tx_unmap(struct ioc3_private *ip, int entry) |
611 | { | |
612 | struct ioc3_etxd *desc; | |
613 | u32 cmd, bufcnt, len; | |
614 | ||
615 | desc = &ip->txr[entry]; | |
616 | cmd = be32_to_cpu(desc->cmd); | |
617 | bufcnt = be32_to_cpu(desc->bufcnt); | |
618 | if (cmd & ETXD_B1V) { | |
619 | len = (bufcnt & ETXD_B1CNT_MASK) >> ETXD_B1CNT_SHIFT; | |
620 | dma_unmap_single(ip->dma_dev, be64_to_cpu(desc->p1), | |
621 | len, DMA_TO_DEVICE); | |
622 | } | |
623 | if (cmd & ETXD_B2V) { | |
624 | len = (bufcnt & ETXD_B2CNT_MASK) >> ETXD_B2CNT_SHIFT; | |
625 | dma_unmap_single(ip->dma_dev, be64_to_cpu(desc->p2), | |
626 | len, DMA_TO_DEVICE); | |
627 | } | |
628 | } | |
629 | ||
1da177e4 LT |
630 | static inline void ioc3_clean_tx_ring(struct ioc3_private *ip) |
631 | { | |
632 | struct sk_buff *skb; | |
633 | int i; | |
634 | ||
141a7dbb | 635 | for (i = 0; i < TX_RING_ENTRIES; i++) { |
1da177e4 LT |
636 | skb = ip->tx_skbs[i]; |
637 | if (skb) { | |
ed870f6a | 638 | ioc3_tx_unmap(ip, i); |
1da177e4 LT |
639 | ip->tx_skbs[i] = NULL; |
640 | dev_kfree_skb_any(skb); | |
641 | } | |
642 | ip->txr[i].cmd = 0; | |
643 | } | |
644 | ip->tx_pi = 0; | |
645 | ip->tx_ci = 0; | |
646 | } | |
647 | ||
9c328b05 | 648 | static void ioc3_free_rx_bufs(struct ioc3_private *ip) |
1da177e4 | 649 | { |
1da177e4 | 650 | int rx_entry, n_entry; |
ed870f6a | 651 | struct sk_buff *skb; |
1da177e4 | 652 | |
c7b57274 TB |
653 | n_entry = ip->rx_ci; |
654 | rx_entry = ip->rx_pi; | |
1da177e4 | 655 | |
c7b57274 | 656 | while (n_entry != rx_entry) { |
ed870f6a TB |
657 | skb = ip->rx_skbs[n_entry]; |
658 | if (skb) { | |
659 | dma_unmap_single(ip->dma_dev, | |
660 | be64_to_cpu(ip->rxr[n_entry]), | |
661 | RX_BUF_SIZE, DMA_FROM_DEVICE); | |
662 | dev_kfree_skb_any(skb); | |
663 | } | |
c7b57274 | 664 | n_entry = (n_entry + 1) & RX_RING_MASK; |
1da177e4 LT |
665 | } |
666 | } | |
667 | ||
850d2fed | 668 | static int ioc3_alloc_rx_bufs(struct net_device *dev) |
1da177e4 LT |
669 | { |
670 | struct ioc3_private *ip = netdev_priv(dev); | |
671 | struct ioc3_erxbuf *rxb; | |
ed870f6a | 672 | dma_addr_t d; |
1da177e4 LT |
673 | int i; |
674 | ||
c7b57274 TB |
675 | /* Now the rx buffers. The RX ring may be larger but |
676 | * we only allocate 16 buffers for now. Need to tune | |
677 | * this for performance and memory later. | |
678 | */ | |
679 | for (i = 0; i < RX_BUFFS; i++) { | |
ed870f6a | 680 | if (ioc3_alloc_skb(ip, &ip->rx_skbs[i], &rxb, &d)) |
850d2fed | 681 | return -ENOMEM; |
c7b57274 | 682 | |
489467e5 | 683 | rxb->w0 = 0; /* Clear valid flag */ |
ed870f6a | 684 | ip->rxr[i] = cpu_to_be64(ioc3_map(d, PCI64_ATTR_BAR)); |
1da177e4 | 685 | } |
c7b57274 TB |
686 | ip->rx_ci = 0; |
687 | ip->rx_pi = RX_BUFFS; | |
850d2fed TB |
688 | |
689 | return 0; | |
1da177e4 LT |
690 | } |
691 | ||
1da177e4 LT |
692 | static inline void ioc3_ssram_disc(struct ioc3_private *ip) |
693 | { | |
cbe7d517 TB |
694 | struct ioc3_ethregs *regs = ip->regs; |
695 | u32 *ssram0 = &ip->ssram[0x0000]; | |
696 | u32 *ssram1 = &ip->ssram[0x4000]; | |
697 | u32 pattern = 0x5555; | |
1da177e4 LT |
698 | |
699 | /* Assume the larger size SSRAM and enable parity checking */ | |
cbe7d517 TB |
700 | writel(readl(®s->emcr) | (EMCR_BUFSIZ | EMCR_RAMPAR), ®s->emcr); |
701 | readl(®s->emcr); /* Flush */ | |
1da177e4 | 702 | |
cbe7d517 TB |
703 | writel(pattern, ssram0); |
704 | writel(~pattern & IOC3_SSRAM_DM, ssram1); | |
1da177e4 | 705 | |
cbe7d517 TB |
706 | if ((readl(ssram0) & IOC3_SSRAM_DM) != pattern || |
707 | (readl(ssram1) & IOC3_SSRAM_DM) != (~pattern & IOC3_SSRAM_DM)) { | |
1da177e4 | 708 | /* set ssram size to 64 KB */ |
cbe7d517 TB |
709 | ip->emcr |= EMCR_RAMPAR; |
710 | writel(readl(®s->emcr) & ~EMCR_BUFSIZ, ®s->emcr); | |
711 | } else { | |
712 | ip->emcr |= EMCR_BUFSIZ | EMCR_RAMPAR; | |
713 | } | |
1da177e4 LT |
714 | } |
715 | ||
716 | static void ioc3_init(struct net_device *dev) | |
717 | { | |
718 | struct ioc3_private *ip = netdev_priv(dev); | |
cbe7d517 | 719 | struct ioc3_ethregs *regs = ip->regs; |
1da177e4 | 720 | |
cfadbd29 | 721 | del_timer_sync(&ip->ioc3_timer); /* Kill if running */ |
1da177e4 | 722 | |
cbe7d517 TB |
723 | writel(EMCR_RST, ®s->emcr); /* Reset */ |
724 | readl(®s->emcr); /* Flush WB */ | |
1da177e4 | 725 | udelay(4); /* Give it time ... */ |
cbe7d517 TB |
726 | writel(0, ®s->emcr); |
727 | readl(®s->emcr); | |
1da177e4 LT |
728 | |
729 | /* Misc registers */ | |
ed870f6a | 730 | writel(ERBAR_VAL, ®s->erbar); |
cbe7d517 TB |
731 | readl(®s->etcdc); /* Clear on read */ |
732 | writel(15, ®s->ercsr); /* RX low watermark */ | |
733 | writel(0, ®s->ertr); /* Interrupt immediately */ | |
1da177e4 | 734 | __ioc3_set_mac_address(dev); |
cbe7d517 TB |
735 | writel(ip->ehar_h, ®s->ehar_h); |
736 | writel(ip->ehar_l, ®s->ehar_l); | |
737 | writel(42, ®s->ersr); /* XXX should be random */ | |
fcd0da5a TB |
738 | } |
739 | ||
740 | static void ioc3_start(struct ioc3_private *ip) | |
741 | { | |
742 | struct ioc3_ethregs *regs = ip->regs; | |
743 | unsigned long ring; | |
744 | ||
745 | /* Now the rx ring base, consume & produce registers. */ | |
ed870f6a | 746 | ring = ioc3_map(ip->rxr_dma, PCI64_ATTR_PREC); |
fcd0da5a TB |
747 | writel(ring >> 32, ®s->erbr_h); |
748 | writel(ring & 0xffffffff, ®s->erbr_l); | |
749 | writel(ip->rx_ci << 3, ®s->ercir); | |
750 | writel((ip->rx_pi << 3) | ERPIR_ARM, ®s->erpir); | |
751 | ||
ed870f6a | 752 | ring = ioc3_map(ip->txr_dma, PCI64_ATTR_PREC); |
fcd0da5a TB |
753 | |
754 | ip->txqlen = 0; /* nothing queued */ | |
755 | ||
756 | /* Now the tx ring base, consume & produce registers. */ | |
757 | writel(ring >> 32, ®s->etbr_h); | |
758 | writel(ring & 0xffffffff, ®s->etbr_l); | |
759 | writel(ip->tx_pi << 7, ®s->etpir); | |
760 | writel(ip->tx_ci << 7, ®s->etcir); | |
761 | readl(®s->etcir); /* Flush */ | |
1da177e4 LT |
762 | |
763 | ip->emcr |= ((RX_OFFSET / 2) << EMCR_RXOFF_SHIFT) | EMCR_TXDMAEN | | |
c1b6a3d8 | 764 | EMCR_TXEN | EMCR_RXDMAEN | EMCR_RXEN | EMCR_PADEN; |
cbe7d517 TB |
765 | writel(ip->emcr, ®s->emcr); |
766 | writel(EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO | | |
767 | EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO | | |
768 | EISR_TXEXPLICIT | EISR_TXMEMERR, ®s->eier); | |
769 | readl(®s->eier); | |
1da177e4 LT |
770 | } |
771 | ||
772 | static inline void ioc3_stop(struct ioc3_private *ip) | |
773 | { | |
cbe7d517 | 774 | struct ioc3_ethregs *regs = ip->regs; |
1da177e4 | 775 | |
cbe7d517 TB |
776 | writel(0, ®s->emcr); /* Shutup */ |
777 | writel(0, ®s->eier); /* Disable interrupts */ | |
778 | readl(®s->eier); /* Flush */ | |
1da177e4 LT |
779 | } |
780 | ||
781 | static int ioc3_open(struct net_device *dev) | |
782 | { | |
783 | struct ioc3_private *ip = netdev_priv(dev); | |
784 | ||
1da177e4 LT |
785 | ip->ehar_h = 0; |
786 | ip->ehar_l = 0; | |
19a957b6 | 787 | |
1da177e4 | 788 | ioc3_init(dev); |
850d2fed TB |
789 | if (ioc3_alloc_rx_bufs(dev)) { |
790 | netdev_err(dev, "%s: rx buffer allocation failed\n", __func__); | |
791 | return -ENOMEM; | |
792 | } | |
fcd0da5a | 793 | ioc3_start(ip); |
f0ba7358 | 794 | ioc3_mii_start(ip); |
1da177e4 LT |
795 | |
796 | netif_start_queue(dev); | |
797 | return 0; | |
798 | } | |
799 | ||
800 | static int ioc3_close(struct net_device *dev) | |
801 | { | |
802 | struct ioc3_private *ip = netdev_priv(dev); | |
803 | ||
cfadbd29 | 804 | del_timer_sync(&ip->ioc3_timer); |
1da177e4 LT |
805 | |
806 | netif_stop_queue(dev); | |
807 | ||
808 | ioc3_stop(ip); | |
1da177e4 | 809 | |
9c328b05 TB |
810 | ioc3_free_rx_bufs(ip); |
811 | ioc3_clean_tx_ring(ip); | |
812 | ||
1da177e4 LT |
813 | return 0; |
814 | } | |
815 | ||
2b142542 AB |
816 | static const struct net_device_ops ioc3_netdev_ops = { |
817 | .ndo_open = ioc3_open, | |
818 | .ndo_stop = ioc3_close, | |
819 | .ndo_start_xmit = ioc3_start_xmit, | |
820 | .ndo_tx_timeout = ioc3_timeout, | |
821 | .ndo_get_stats = ioc3_get_stats, | |
afc4b13d | 822 | .ndo_set_rx_mode = ioc3_set_multicast_list, |
2b142542 AB |
823 | .ndo_do_ioctl = ioc3_ioctl, |
824 | .ndo_validate_addr = eth_validate_addr, | |
825 | .ndo_set_mac_address = ioc3_set_mac_address, | |
2b142542 AB |
826 | }; |
827 | ||
0ce5ebd2 | 828 | static int ioc3eth_probe(struct platform_device *pdev) |
1da177e4 | 829 | { |
0ce5ebd2 | 830 | u32 sw_physid1, sw_physid2, vendor, model, rev; |
1da177e4 | 831 | struct ioc3_private *ip; |
0ce5ebd2 TB |
832 | struct net_device *dev; |
833 | struct resource *regs; | |
834 | u8 mac_addr[6]; | |
051a07ec | 835 | int err; |
1da177e4 | 836 | |
0ce5ebd2 TB |
837 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
838 | /* get mac addr from one wire prom */ | |
839 | if (ioc3eth_get_mac_addr(regs, mac_addr)) | |
840 | return -EPROBE_DEFER; /* not available yet */ | |
1da177e4 LT |
841 | |
842 | dev = alloc_etherdev(sizeof(struct ioc3_private)); | |
0ce5ebd2 TB |
843 | if (!dev) |
844 | return -ENOMEM; | |
1da177e4 | 845 | |
1da177e4 LT |
846 | SET_NETDEV_DEV(dev, &pdev->dev); |
847 | ||
848 | ip = netdev_priv(dev); | |
0ce5ebd2 TB |
849 | ip->dma_dev = pdev->dev.parent; |
850 | ip->regs = devm_platform_ioremap_resource(pdev, 0); | |
a7654211 TB |
851 | if (IS_ERR(ip->regs)) { |
852 | err = PTR_ERR(ip->regs); | |
0ce5ebd2 TB |
853 | goto out_free; |
854 | } | |
1da177e4 | 855 | |
0ce5ebd2 | 856 | ip->ssram = devm_platform_ioremap_resource(pdev, 1); |
a7654211 TB |
857 | if (IS_ERR(ip->ssram)) { |
858 | err = PTR_ERR(ip->ssram); | |
0ce5ebd2 | 859 | goto out_free; |
1da177e4 | 860 | } |
1da177e4 | 861 | |
0ce5ebd2 TB |
862 | dev->irq = platform_get_irq(pdev, 0); |
863 | if (dev->irq < 0) { | |
864 | err = dev->irq; | |
865 | goto out_free; | |
866 | } | |
867 | ||
868 | if (devm_request_irq(&pdev->dev, dev->irq, ioc3_interrupt, | |
869 | IRQF_SHARED, "ioc3-eth", dev)) { | |
870 | dev_err(&pdev->dev, "Can't get irq %d\n", dev->irq); | |
871 | err = -ENODEV; | |
872 | goto out_free; | |
873 | } | |
1da177e4 LT |
874 | |
875 | spin_lock_init(&ip->ioc3_lock); | |
dfc57004 | 876 | timer_setup(&ip->ioc3_timer, ioc3_timer, 0); |
1da177e4 LT |
877 | |
878 | ioc3_stop(ip); | |
c7b57274 TB |
879 | |
880 | /* Allocate rx ring. 4kb = 512 entries, must be 4kb aligned */ | |
4dd14747 | 881 | ip->rxr = dma_alloc_coherent(ip->dma_dev, RX_RING_SIZE, &ip->rxr_dma, |
59511bcf | 882 | GFP_KERNEL); |
c7b57274 TB |
883 | if (!ip->rxr) { |
884 | pr_err("ioc3-eth: rx ring allocation failed\n"); | |
885 | err = -ENOMEM; | |
886 | goto out_stop; | |
887 | } | |
888 | ||
889 | /* Allocate tx rings. 16kb = 128 bufs, must be 16kb aligned */ | |
369a782a TB |
890 | ip->tx_ring = dma_alloc_coherent(ip->dma_dev, TX_RING_SIZE + SZ_16K - 1, |
891 | &ip->txr_dma, GFP_KERNEL); | |
892 | if (!ip->tx_ring) { | |
c7b57274 TB |
893 | pr_err("ioc3-eth: tx ring allocation failed\n"); |
894 | err = -ENOMEM; | |
895 | goto out_stop; | |
896 | } | |
369a782a TB |
897 | /* Align TX ring */ |
898 | ip->txr = PTR_ALIGN(ip->tx_ring, SZ_16K); | |
899 | ip->txr_dma = ALIGN(ip->txr_dma, SZ_16K); | |
c7b57274 | 900 | |
1da177e4 LT |
901 | ioc3_init(dev); |
902 | ||
1da177e4 LT |
903 | ip->mii.phy_id_mask = 0x1f; |
904 | ip->mii.reg_num_mask = 0x1f; | |
905 | ip->mii.dev = dev; | |
906 | ip->mii.mdio_read = ioc3_mdio_read; | |
907 | ip->mii.mdio_write = ioc3_mdio_write; | |
908 | ||
909 | ioc3_mii_init(ip); | |
910 | ||
911 | if (ip->mii.phy_id == -1) { | |
0ce5ebd2 | 912 | netdev_err(dev, "Didn't find a PHY, goodbye.\n"); |
1da177e4 LT |
913 | err = -ENODEV; |
914 | goto out_stop; | |
915 | } | |
916 | ||
f0ba7358 | 917 | ioc3_mii_start(ip); |
1da177e4 | 918 | ioc3_ssram_disc(ip); |
0ce5ebd2 | 919 | memcpy(dev->dev_addr, mac_addr, ETH_ALEN); |
1da177e4 LT |
920 | |
921 | /* The IOC3-specific entries in the device structure. */ | |
1da177e4 | 922 | dev->watchdog_timeo = 5 * HZ; |
2b142542 | 923 | dev->netdev_ops = &ioc3_netdev_ops; |
1da177e4 | 924 | dev->ethtool_ops = &ioc3_ethtool_ops; |
6d95ff97 | 925 | dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM; |
7ca2c4c2 | 926 | dev->features = NETIF_F_IP_CSUM | NETIF_F_HIGHDMA; |
1da177e4 | 927 | |
1da177e4 LT |
928 | sw_physid1 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID1); |
929 | sw_physid2 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID2); | |
930 | ||
931 | err = register_netdev(dev); | |
932 | if (err) | |
933 | goto out_stop; | |
934 | ||
935 | mii_check_media(&ip->mii, 1, 1); | |
852ea22a | 936 | ioc3_setup_duplex(ip); |
1da177e4 LT |
937 | |
938 | vendor = (sw_physid1 << 12) | (sw_physid2 >> 4); | |
939 | model = (sw_physid2 >> 4) & 0x3f; | |
940 | rev = sw_physid2 & 0xf; | |
c1b6a3d8 TB |
941 | netdev_info(dev, "Using PHY %d, vendor 0x%x, model %d, rev %d.\n", |
942 | ip->mii.phy_id, vendor, model, rev); | |
943 | netdev_info(dev, "IOC3 SSRAM has %d kbyte.\n", | |
944 | ip->emcr & EMCR_BUFSIZ ? 128 : 64); | |
1da177e4 LT |
945 | |
946 | return 0; | |
947 | ||
948 | out_stop: | |
f0ba7358 | 949 | del_timer_sync(&ip->ioc3_timer); |
c7b57274 | 950 | if (ip->rxr) |
4dd14747 CH |
951 | dma_free_coherent(ip->dma_dev, RX_RING_SIZE, ip->rxr, |
952 | ip->rxr_dma); | |
369a782a TB |
953 | if (ip->tx_ring) |
954 | dma_free_coherent(ip->dma_dev, TX_RING_SIZE, ip->tx_ring, | |
4dd14747 | 955 | ip->txr_dma); |
1da177e4 LT |
956 | out_free: |
957 | free_netdev(dev); | |
1da177e4 LT |
958 | return err; |
959 | } | |
960 | ||
0ce5ebd2 | 961 | static int ioc3eth_remove(struct platform_device *pdev) |
1da177e4 | 962 | { |
0ce5ebd2 | 963 | struct net_device *dev = platform_get_drvdata(pdev); |
1da177e4 | 964 | struct ioc3_private *ip = netdev_priv(dev); |
1da177e4 | 965 | |
4dd14747 | 966 | dma_free_coherent(ip->dma_dev, RX_RING_SIZE, ip->rxr, ip->rxr_dma); |
369a782a | 967 | dma_free_coherent(ip->dma_dev, TX_RING_SIZE, ip->tx_ring, ip->txr_dma); |
c7b57274 | 968 | |
1da177e4 | 969 | unregister_netdev(dev); |
f0ba7358 | 970 | del_timer_sync(&ip->ioc3_timer); |
1da177e4 | 971 | free_netdev(dev); |
1da177e4 | 972 | |
0ce5ebd2 TB |
973 | return 0; |
974 | } | |
1da177e4 | 975 | |
1da177e4 | 976 | |
28d304ef | 977 | static netdev_tx_t ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 978 | { |
1da177e4 | 979 | struct ioc3_private *ip = netdev_priv(dev); |
1da177e4 | 980 | struct ioc3_etxd *desc; |
cbe7d517 TB |
981 | unsigned long data; |
982 | unsigned int len; | |
1da177e4 | 983 | int produce; |
c1b6a3d8 | 984 | u32 w0 = 0; |
1da177e4 | 985 | |
c1b6a3d8 | 986 | /* IOC3 has a fairly simple minded checksumming hardware which simply |
1da177e4 LT |
987 | * adds up the 1's complement checksum for the entire packet and |
988 | * inserts it at an offset which can be specified in the descriptor | |
989 | * into the transmit packet. This means we have to compensate for the | |
990 | * MAC header which should not be summed and the TCP/UDP pseudo headers | |
991 | * manually. | |
992 | */ | |
84fa7933 | 993 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
eddc9ec5 ACM |
994 | const struct iphdr *ih = ip_hdr(skb); |
995 | const int proto = ntohs(ih->protocol); | |
1da177e4 | 996 | unsigned int csoff; |
c1b6a3d8 TB |
997 | u32 csum, ehsum; |
998 | u16 *eh; | |
1da177e4 LT |
999 | |
1000 | /* The MAC header. skb->mac seem the logic approach | |
c1b6a3d8 TB |
1001 | * to find the MAC header - except it's a NULL pointer ... |
1002 | */ | |
1003 | eh = (u16 *)skb->data; | |
1da177e4 LT |
1004 | |
1005 | /* Sum up dest addr, src addr and protocol */ | |
1006 | ehsum = eh[0] + eh[1] + eh[2] + eh[3] + eh[4] + eh[5] + eh[6]; | |
1007 | ||
1da177e4 | 1008 | /* Skip IP header; it's sum is always zero and was |
c1b6a3d8 TB |
1009 | * already filled in by ip_output.c |
1010 | */ | |
1da177e4 | 1011 | csum = csum_tcpudp_nofold(ih->saddr, ih->daddr, |
c1b6a3d8 | 1012 | ih->tot_len - (ih->ihl << 2), |
8dff19a6 | 1013 | proto, csum_fold(ehsum)); |
1da177e4 LT |
1014 | |
1015 | csum = (csum & 0xffff) + (csum >> 16); /* Fold again */ | |
1016 | csum = (csum & 0xffff) + (csum >> 16); | |
1017 | ||
1018 | csoff = ETH_HLEN + (ih->ihl << 2); | |
1019 | if (proto == IPPROTO_UDP) { | |
1020 | csoff += offsetof(struct udphdr, check); | |
4bedb452 | 1021 | udp_hdr(skb)->check = csum; |
1da177e4 LT |
1022 | } |
1023 | if (proto == IPPROTO_TCP) { | |
1024 | csoff += offsetof(struct tcphdr, check); | |
aa8223c7 | 1025 | tcp_hdr(skb)->check = csum; |
1da177e4 LT |
1026 | } |
1027 | ||
1028 | w0 = ETXD_DOCHECKSUM | (csoff << ETXD_CHKOFF_SHIFT); | |
1029 | } | |
1da177e4 LT |
1030 | |
1031 | spin_lock_irq(&ip->ioc3_lock); | |
1032 | ||
c1b6a3d8 | 1033 | data = (unsigned long)skb->data; |
1da177e4 LT |
1034 | len = skb->len; |
1035 | ||
1036 | produce = ip->tx_pi; | |
1037 | desc = &ip->txr[produce]; | |
1038 | ||
1039 | if (len <= 104) { | |
1040 | /* Short packet, let's copy it directly into the ring. */ | |
d626f62b | 1041 | skb_copy_from_linear_data(skb, desc->data, skb->len); |
1da177e4 LT |
1042 | if (len < ETH_ZLEN) { |
1043 | /* Very short packet, pad with zeros at the end. */ | |
1044 | memset(desc->data + len, 0, ETH_ZLEN - len); | |
1045 | len = ETH_ZLEN; | |
1046 | } | |
1047 | desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_D0V | w0); | |
1048 | desc->bufcnt = cpu_to_be32(len); | |
1049 | } else if ((data ^ (data + len - 1)) & 0x4000) { | |
1050 | unsigned long b2 = (data | 0x3fffUL) + 1UL; | |
1051 | unsigned long s1 = b2 - data; | |
1052 | unsigned long s2 = data + len - b2; | |
ed870f6a | 1053 | dma_addr_t d1, d2; |
1da177e4 LT |
1054 | |
1055 | desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | | |
c1b6a3d8 | 1056 | ETXD_B1V | ETXD_B2V | w0); |
1da177e4 | 1057 | desc->bufcnt = cpu_to_be32((s1 << ETXD_B1CNT_SHIFT) | |
c1b6a3d8 | 1058 | (s2 << ETXD_B2CNT_SHIFT)); |
ed870f6a TB |
1059 | d1 = dma_map_single(ip->dma_dev, skb->data, s1, DMA_TO_DEVICE); |
1060 | if (dma_mapping_error(ip->dma_dev, d1)) | |
1061 | goto drop_packet; | |
1062 | d2 = dma_map_single(ip->dma_dev, (void *)b2, s1, DMA_TO_DEVICE); | |
1063 | if (dma_mapping_error(ip->dma_dev, d2)) { | |
1064 | dma_unmap_single(ip->dma_dev, d1, len, DMA_TO_DEVICE); | |
1065 | goto drop_packet; | |
1066 | } | |
1067 | desc->p1 = cpu_to_be64(ioc3_map(d1, PCI64_ATTR_PREF)); | |
1068 | desc->p2 = cpu_to_be64(ioc3_map(d2, PCI64_ATTR_PREF)); | |
1da177e4 | 1069 | } else { |
ed870f6a TB |
1070 | dma_addr_t d; |
1071 | ||
1da177e4 LT |
1072 | /* Normal sized packet that doesn't cross a page boundary. */ |
1073 | desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_B1V | w0); | |
1074 | desc->bufcnt = cpu_to_be32(len << ETXD_B1CNT_SHIFT); | |
ed870f6a TB |
1075 | d = dma_map_single(ip->dma_dev, skb->data, len, DMA_TO_DEVICE); |
1076 | if (dma_mapping_error(ip->dma_dev, d)) | |
1077 | goto drop_packet; | |
1078 | desc->p1 = cpu_to_be64(ioc3_map(d, PCI64_ATTR_PREF)); | |
1da177e4 LT |
1079 | } |
1080 | ||
c1b6a3d8 | 1081 | mb(); /* make sure all descriptor changes are visible */ |
1da177e4 | 1082 | |
1da177e4 | 1083 | ip->tx_skbs[produce] = skb; /* Remember skb */ |
141a7dbb | 1084 | produce = (produce + 1) & TX_RING_MASK; |
1da177e4 | 1085 | ip->tx_pi = produce; |
cbe7d517 | 1086 | writel(produce << 7, &ip->regs->etpir); /* Fire ... */ |
1da177e4 LT |
1087 | |
1088 | ip->txqlen++; | |
1089 | ||
141a7dbb | 1090 | if (ip->txqlen >= (TX_RING_ENTRIES - 1)) |
1da177e4 LT |
1091 | netif_stop_queue(dev); |
1092 | ||
1093 | spin_unlock_irq(&ip->ioc3_lock); | |
1094 | ||
ed870f6a TB |
1095 | return NETDEV_TX_OK; |
1096 | ||
1097 | drop_packet: | |
1098 | dev_kfree_skb_any(skb); | |
1099 | dev->stats.tx_dropped++; | |
1100 | ||
1101 | spin_unlock_irq(&ip->ioc3_lock); | |
1102 | ||
6ed10654 | 1103 | return NETDEV_TX_OK; |
1da177e4 LT |
1104 | } |
1105 | ||
0290bd29 | 1106 | static void ioc3_timeout(struct net_device *dev, unsigned int txqueue) |
1da177e4 LT |
1107 | { |
1108 | struct ioc3_private *ip = netdev_priv(dev); | |
1109 | ||
c1b6a3d8 | 1110 | netdev_err(dev, "transmit timed out, resetting\n"); |
1da177e4 LT |
1111 | |
1112 | spin_lock_irq(&ip->ioc3_lock); | |
1113 | ||
1114 | ioc3_stop(ip); | |
19a957b6 TB |
1115 | ioc3_free_rx_bufs(ip); |
1116 | ioc3_clean_tx_ring(ip); | |
1117 | ||
1da177e4 | 1118 | ioc3_init(dev); |
850d2fed TB |
1119 | if (ioc3_alloc_rx_bufs(dev)) { |
1120 | netdev_err(dev, "%s: rx buffer allocation failed\n", __func__); | |
1121 | spin_unlock_irq(&ip->ioc3_lock); | |
1122 | return; | |
1123 | } | |
fcd0da5a | 1124 | ioc3_start(ip); |
1da177e4 | 1125 | ioc3_mii_init(ip); |
f0ba7358 | 1126 | ioc3_mii_start(ip); |
1da177e4 LT |
1127 | |
1128 | spin_unlock_irq(&ip->ioc3_lock); | |
1129 | ||
1130 | netif_wake_queue(dev); | |
1131 | } | |
1132 | ||
c1b6a3d8 | 1133 | /* Given a multicast ethernet address, this routine calculates the |
1da177e4 LT |
1134 | * address's bit index in the logical address filter mask |
1135 | */ | |
1da177e4 LT |
1136 | static inline unsigned int ioc3_hash(const unsigned char *addr) |
1137 | { | |
1138 | unsigned int temp = 0; | |
1da177e4 | 1139 | int bits; |
c1b6a3d8 | 1140 | u32 crc; |
1da177e4 LT |
1141 | |
1142 | crc = ether_crc_le(ETH_ALEN, addr); | |
1143 | ||
1144 | crc &= 0x3f; /* bit reverse lowest 6 bits for hash index */ | |
1145 | for (bits = 6; --bits >= 0; ) { | |
1146 | temp <<= 1; | |
1147 | temp |= (crc & 0x1); | |
1148 | crc >>= 1; | |
1149 | } | |
1150 | ||
1151 | return temp; | |
1152 | } | |
1153 | ||
c1b6a3d8 TB |
1154 | static void ioc3_get_drvinfo(struct net_device *dev, |
1155 | struct ethtool_drvinfo *info) | |
1da177e4 | 1156 | { |
7826d43f JP |
1157 | strlcpy(info->driver, IOC3_NAME, sizeof(info->driver)); |
1158 | strlcpy(info->version, IOC3_VERSION, sizeof(info->version)); | |
0ce5ebd2 TB |
1159 | strlcpy(info->bus_info, pci_name(to_pci_dev(dev->dev.parent)), |
1160 | sizeof(info->bus_info)); | |
1da177e4 LT |
1161 | } |
1162 | ||
b61a26f8 PR |
1163 | static int ioc3_get_link_ksettings(struct net_device *dev, |
1164 | struct ethtool_link_ksettings *cmd) | |
1da177e4 LT |
1165 | { |
1166 | struct ioc3_private *ip = netdev_priv(dev); | |
1da177e4 LT |
1167 | |
1168 | spin_lock_irq(&ip->ioc3_lock); | |
82c01a84 | 1169 | mii_ethtool_get_link_ksettings(&ip->mii, cmd); |
1da177e4 LT |
1170 | spin_unlock_irq(&ip->ioc3_lock); |
1171 | ||
82c01a84 | 1172 | return 0; |
1da177e4 LT |
1173 | } |
1174 | ||
b61a26f8 PR |
1175 | static int ioc3_set_link_ksettings(struct net_device *dev, |
1176 | const struct ethtool_link_ksettings *cmd) | |
1da177e4 LT |
1177 | { |
1178 | struct ioc3_private *ip = netdev_priv(dev); | |
1179 | int rc; | |
1180 | ||
1181 | spin_lock_irq(&ip->ioc3_lock); | |
b61a26f8 | 1182 | rc = mii_ethtool_set_link_ksettings(&ip->mii, cmd); |
1da177e4 | 1183 | spin_unlock_irq(&ip->ioc3_lock); |
852ea22a | 1184 | |
1da177e4 LT |
1185 | return rc; |
1186 | } | |
1187 | ||
1188 | static int ioc3_nway_reset(struct net_device *dev) | |
1189 | { | |
1190 | struct ioc3_private *ip = netdev_priv(dev); | |
1191 | int rc; | |
1192 | ||
1193 | spin_lock_irq(&ip->ioc3_lock); | |
1194 | rc = mii_nway_restart(&ip->mii); | |
1195 | spin_unlock_irq(&ip->ioc3_lock); | |
1196 | ||
1197 | return rc; | |
1198 | } | |
1199 | ||
1200 | static u32 ioc3_get_link(struct net_device *dev) | |
1201 | { | |
1202 | struct ioc3_private *ip = netdev_priv(dev); | |
1203 | int rc; | |
1204 | ||
1205 | spin_lock_irq(&ip->ioc3_lock); | |
1206 | rc = mii_link_ok(&ip->mii); | |
1207 | spin_unlock_irq(&ip->ioc3_lock); | |
1208 | ||
1209 | return rc; | |
1210 | } | |
1211 | ||
7282d491 | 1212 | static const struct ethtool_ops ioc3_ethtool_ops = { |
1da177e4 | 1213 | .get_drvinfo = ioc3_get_drvinfo, |
1da177e4 LT |
1214 | .nway_reset = ioc3_nway_reset, |
1215 | .get_link = ioc3_get_link, | |
b61a26f8 PR |
1216 | .get_link_ksettings = ioc3_get_link_ksettings, |
1217 | .set_link_ksettings = ioc3_set_link_ksettings, | |
1da177e4 LT |
1218 | }; |
1219 | ||
1220 | static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
1221 | { | |
1222 | struct ioc3_private *ip = netdev_priv(dev); | |
1223 | int rc; | |
1224 | ||
1225 | spin_lock_irq(&ip->ioc3_lock); | |
1226 | rc = generic_mii_ioctl(&ip->mii, if_mii(rq), cmd, NULL); | |
1227 | spin_unlock_irq(&ip->ioc3_lock); | |
1228 | ||
1229 | return rc; | |
1230 | } | |
1231 | ||
1232 | static void ioc3_set_multicast_list(struct net_device *dev) | |
1233 | { | |
1da177e4 | 1234 | struct ioc3_private *ip = netdev_priv(dev); |
cbe7d517 TB |
1235 | struct ioc3_ethregs *regs = ip->regs; |
1236 | struct netdev_hw_addr *ha; | |
1da177e4 | 1237 | u64 ehar = 0; |
1da177e4 | 1238 | |
d1c94542 TB |
1239 | spin_lock_irq(&ip->ioc3_lock); |
1240 | ||
1da177e4 | 1241 | if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ |
1da177e4 | 1242 | ip->emcr |= EMCR_PROMISC; |
cbe7d517 TB |
1243 | writel(ip->emcr, ®s->emcr); |
1244 | readl(®s->emcr); | |
1da177e4 LT |
1245 | } else { |
1246 | ip->emcr &= ~EMCR_PROMISC; | |
cbe7d517 TB |
1247 | writel(ip->emcr, ®s->emcr); /* Clear promiscuous. */ |
1248 | readl(®s->emcr); | |
1da177e4 | 1249 | |
4cd24eaf JP |
1250 | if ((dev->flags & IFF_ALLMULTI) || |
1251 | (netdev_mc_count(dev) > 64)) { | |
1da177e4 | 1252 | /* Too many for hashing to make sense or we want all |
c1b6a3d8 TB |
1253 | * multicast packets anyway, so skip computing all the |
1254 | * hashes and just accept all packets. | |
1255 | */ | |
1da177e4 LT |
1256 | ip->ehar_h = 0xffffffff; |
1257 | ip->ehar_l = 0xffffffff; | |
1258 | } else { | |
22bedad3 | 1259 | netdev_for_each_mc_addr(ha, dev) { |
498d8e23 | 1260 | ehar |= (1UL << ioc3_hash(ha->addr)); |
1da177e4 LT |
1261 | } |
1262 | ip->ehar_h = ehar >> 32; | |
1263 | ip->ehar_l = ehar & 0xffffffff; | |
1264 | } | |
cbe7d517 TB |
1265 | writel(ip->ehar_h, ®s->ehar_h); |
1266 | writel(ip->ehar_l, ®s->ehar_l); | |
1da177e4 LT |
1267 | } |
1268 | ||
d1c94542 | 1269 | spin_unlock_irq(&ip->ioc3_lock); |
1da177e4 LT |
1270 | } |
1271 | ||
0ce5ebd2 TB |
1272 | static struct platform_driver ioc3eth_driver = { |
1273 | .probe = ioc3eth_probe, | |
1274 | .remove = ioc3eth_remove, | |
1275 | .driver = { | |
1276 | .name = "ioc3-eth", | |
1277 | } | |
1278 | }; | |
1279 | ||
1280 | module_platform_driver(ioc3eth_driver); | |
1281 | ||
1da177e4 LT |
1282 | MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>"); |
1283 | MODULE_DESCRIPTION("SGI IOC3 Ethernet driver"); | |
1284 | MODULE_LICENSE("GPL"); |