[thirdparty/kernel/stable.git] / drivers / net / ethernet / stmicro / stmmac / stmmac.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*******************************************************************************
  Copyright (C) 2007-2009  STMicroelectronics Ltd


  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*******************************************************************************/

#ifndef __STMMAC_H__
#define __STMMAC_H__

#define STMMAC_RESOURCE_NAME   "stmmaceth"

#include <linux/clk.h>
#include <linux/hrtimer.h>
#include <linux/if_vlan.h>
#include <linux/stmmac.h>
#include <linux/phylink.h>
#include <linux/pci.h>
#include "common.h"
#include <linux/ptp_clock_kernel.h>
#include <linux/net_tstamp.h>
#include <linux/reset.h>
#include <net/page_pool/types.h>
#include <net/xdp.h>
#include <uapi/linux/bpf.h>

struct stmmac_resources {
	void __iomem *addr;
	u8 mac[ETH_ALEN];
	int wol_irq;
	int lpi_irq;
	int irq;
	int sfty_ce_irq;
	int sfty_ue_irq;
	int rx_irq[MTL_MAX_RX_QUEUES];
	int tx_irq[MTL_MAX_TX_QUEUES];
};

enum stmmac_txbuf_type {
	STMMAC_TXBUF_T_SKB,
	STMMAC_TXBUF_T_XDP_TX,
	STMMAC_TXBUF_T_XDP_NDO,
	STMMAC_TXBUF_T_XSK_TX,
};

struct stmmac_tx_info {
	dma_addr_t buf;
	bool map_as_page;
	unsigned len;
	bool last_segment;
	bool is_jumbo;
	enum stmmac_txbuf_type buf_type;
};

#define STMMAC_TBS_AVAIL	BIT(0)
#define STMMAC_TBS_EN		BIT(1)

/* Frequently used values are kept adjacent for cache effect */
struct stmmac_tx_queue {
	u32 tx_count_frames;
	int tbs;
	struct hrtimer txtimer;
	u32 queue_index;
	struct stmmac_priv *priv_data;
	struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp;
	struct dma_edesc *dma_entx;
	struct dma_desc *dma_tx;
	union {
		struct sk_buff **tx_skbuff;
		struct xdp_frame **xdpf;
	};
	struct stmmac_tx_info *tx_skbuff_dma;
	struct xsk_buff_pool *xsk_pool;
	u32 xsk_frames_done;
	unsigned int cur_tx;
	unsigned int dirty_tx;
	dma_addr_t dma_tx_phy;
	dma_addr_t tx_tail_addr;
	u32 mss;
};

struct stmmac_rx_buffer {
	union {
		struct {
			struct page *page;
			dma_addr_t addr;
			__u32 page_offset;
		};
		struct xdp_buff *xdp;
	};
	struct page *sec_page;
	dma_addr_t sec_addr;
};

struct stmmac_xdp_buff {
	struct xdp_buff xdp;
	struct stmmac_priv *priv;
	struct dma_desc *desc;
	struct dma_desc *ndesc;
};

struct stmmac_rx_queue {
	u32 rx_count_frames;
	u32 queue_index;
	struct xdp_rxq_info xdp_rxq;
	struct xsk_buff_pool *xsk_pool;
	struct page_pool *page_pool;
	struct stmmac_rx_buffer *buf_pool;
	struct stmmac_priv *priv_data;
	struct dma_extended_desc *dma_erx;
	struct dma_desc *dma_rx ____cacheline_aligned_in_smp;
	unsigned int cur_rx;
	unsigned int dirty_rx;
	unsigned int buf_alloc_num;
	u32 rx_zeroc_thresh;
	dma_addr_t dma_rx_phy;
	u32 rx_tail_addr;
	unsigned int state_saved;
	struct {
		struct sk_buff *skb;
		unsigned int len;
		unsigned int error;
	} state;
};

struct stmmac_channel {
	struct napi_struct rx_napi ____cacheline_aligned_in_smp;
	struct napi_struct tx_napi ____cacheline_aligned_in_smp;
	struct napi_struct rxtx_napi ____cacheline_aligned_in_smp;
	struct stmmac_priv *priv_data;
	spinlock_t lock;
	u32 index;
};

struct stmmac_tc_entry {
	bool in_use;
	bool in_hw;
	bool is_last;
	bool is_frag;
	void *frag_ptr;
	unsigned int table_pos;
	u32 handle;
	u32 prio;
	struct {
		u32 match_data;
		u32 match_en;
		u8 af:1;
		u8 rf:1;
		u8 im:1;
		u8 nc:1;
		u8 res1:4;
		u8 frame_offset;
		u8 ok_index;
		u8 dma_ch_no;
		u32 res2;
	} __packed val;
};

#define STMMAC_PPS_MAX		4
struct stmmac_pps_cfg {
	bool available;
	struct timespec64 start;
	struct timespec64 period;
};

struct stmmac_rss {
	int enable;
	u8 key[STMMAC_RSS_HASH_KEY_SIZE];
	u32 table[STMMAC_RSS_MAX_TABLE_SIZE];
};

#define STMMAC_FLOW_ACTION_DROP		BIT(0)
struct stmmac_flow_entry {
	unsigned long cookie;
	unsigned long action;
	u8 ip_proto;
	int in_use;
	int idx;
	int is_l4;
};

/* Rx Frame Steering */
enum stmmac_rfs_type {
	STMMAC_RFS_T_VLAN,
	STMMAC_RFS_T_LLDP,
	STMMAC_RFS_T_1588,
	STMMAC_RFS_T_MAX,
};

struct stmmac_rfs_entry {
	unsigned long cookie;
	u16 etype;
	int in_use;
	int type;
	int tc;
};

struct stmmac_dma_conf {
	unsigned int dma_buf_sz;

	/* RX Queue */
	struct stmmac_rx_queue rx_queue[MTL_MAX_RX_QUEUES];
	unsigned int dma_rx_size;

	/* TX Queue */
	struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES];
	unsigned int dma_tx_size;
};

struct stmmac_priv {
	/* Frequently used values are kept adjacent for cache effect */
	u32 tx_coal_frames[MTL_MAX_TX_QUEUES];
	u32 tx_coal_timer[MTL_MAX_TX_QUEUES];
	u32 rx_coal_frames[MTL_MAX_TX_QUEUES];

	int hwts_tx_en;
	bool tx_path_in_lpi_mode;
	bool tso;
	int sph;
	int sph_cap;
	u32 sarc_type;

	unsigned int rx_copybreak;
	u32 rx_riwt[MTL_MAX_TX_QUEUES];
	int hwts_rx_en;

	void __iomem *ioaddr;
	struct net_device *dev;
	struct device *device;
	struct mac_device_info *hw;
	int (*hwif_quirks)(struct stmmac_priv *priv);
	struct mutex lock;

	struct stmmac_dma_conf dma_conf;

	/* Generic channel for NAPI */
	struct stmmac_channel channel[STMMAC_CH_MAX];

	int speed;
	unsigned int flow_ctrl;
	unsigned int pause;
	struct mii_bus *mii;

	struct phylink_config phylink_config;
	struct phylink *phylink;

	struct stmmac_extra_stats xstats ____cacheline_aligned_in_smp;
	struct stmmac_safety_stats sstats;
	struct plat_stmmacenet_data *plat;
	struct dma_features dma_cap;
	struct stmmac_counters mmc;
	int hw_cap_support;
	int synopsys_id;
	u32 msg_enable;
	int wolopts;
	int wol_irq;
	int clk_csr;
	struct timer_list eee_ctrl_timer;
	int lpi_irq;
	int eee_enabled;
	int eee_active;
	int tx_lpi_timer;
	int tx_lpi_enabled;
	int eee_tw_timer;
	bool eee_sw_timer_en;
	unsigned int mode;
	unsigned int chain_mode;
	int extend_desc;
	struct hwtstamp_config tstamp_config;
	struct ptp_clock *ptp_clock;
	struct ptp_clock_info ptp_clock_ops;
	unsigned int default_addend;
	u32 sub_second_inc;
	u32 systime_flags;
	u32 adv_ts;
	int use_riwt;
	int irq_wake;
	rwlock_t ptp_lock;
	/* Protects auxiliary snapshot registers from concurrent access. */
	struct mutex aux_ts_lock;
	wait_queue_head_t tstamp_busy_wait;

	void __iomem *mmcaddr;
	void __iomem *ptpaddr;
	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
	int sfty_ce_irq;
	int sfty_ue_irq;
	int rx_irq[MTL_MAX_RX_QUEUES];
	int tx_irq[MTL_MAX_TX_QUEUES];
	/*irq name */
	char int_name_mac[IFNAMSIZ + 9];
	char int_name_wol[IFNAMSIZ + 9];
	char int_name_lpi[IFNAMSIZ + 9];
	char int_name_sfty_ce[IFNAMSIZ + 10];
	char int_name_sfty_ue[IFNAMSIZ + 10];
	char int_name_rx_irq[MTL_MAX_TX_QUEUES][IFNAMSIZ + 14];
	char int_name_tx_irq[MTL_MAX_TX_QUEUES][IFNAMSIZ + 18];

#ifdef CONFIG_DEBUG_FS
	struct dentry *dbgfs_dir;
#endif

	unsigned long state;
	struct workqueue_struct *wq;
	struct work_struct service_task;

	/* Workqueue for handling FPE hand-shaking */
	unsigned long fpe_task_state;
	struct workqueue_struct *fpe_wq;
	struct work_struct fpe_task;
	char wq_name[IFNAMSIZ + 4];

	/* TC Handling */
	unsigned int tc_entries_max;
	unsigned int tc_off_max;
	struct stmmac_tc_entry *tc_entries;
	unsigned int flow_entries_max;
	struct stmmac_flow_entry *flow_entries;
	unsigned int rfs_entries_max[STMMAC_RFS_T_MAX];
	unsigned int rfs_entries_cnt[STMMAC_RFS_T_MAX];
	unsigned int rfs_entries_total;
	struct stmmac_rfs_entry *rfs_entries;

	/* Pulse Per Second output */
	struct stmmac_pps_cfg pps[STMMAC_PPS_MAX];

	/* Receive Side Scaling */
	struct stmmac_rss rss;

	/* XDP BPF Program */
	unsigned long *af_xdp_zc_qps;
	struct bpf_prog *xdp_prog;
};

enum stmmac_state {
	STMMAC_DOWN,
	STMMAC_RESET_REQUESTED,
	STMMAC_RESETING,
	STMMAC_SERVICE_SCHED,
};

int stmmac_mdio_unregister(struct net_device *ndev);
int stmmac_mdio_register(struct net_device *ndev);
int stmmac_mdio_reset(struct mii_bus *mii);
int stmmac_xpcs_setup(struct mii_bus *mii);
void stmmac_set_ethtool_ops(struct net_device *netdev);

int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags);
void stmmac_ptp_register(struct stmmac_priv *priv);
void stmmac_ptp_unregister(struct stmmac_priv *priv);
int stmmac_xdp_open(struct net_device *dev);
void stmmac_xdp_release(struct net_device *dev);
int stmmac_resume(struct device *dev);
int stmmac_suspend(struct device *dev);
void stmmac_dvr_remove(struct device *dev);
int stmmac_dvr_probe(struct device *device,
		     struct plat_stmmacenet_data *plat_dat,
		     struct stmmac_resources *res);
void stmmac_disable_eee_mode(struct stmmac_priv *priv);
bool stmmac_eee_init(struct stmmac_priv *priv);
int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt);
int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size);
int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled);
void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable);

static inline bool stmmac_xdp_is_enabled(struct stmmac_priv *priv)
{
	return !!priv->xdp_prog;
}

static inline unsigned int stmmac_rx_offset(struct stmmac_priv *priv)
{
	if (stmmac_xdp_is_enabled(priv))
		return XDP_PACKET_HEADROOM;

	return 0;
}

void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue);
void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue);
void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue);
void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue);
int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags);
struct timespec64 stmmac_calc_tas_basetime(ktime_t old_base_time,
					   ktime_t current_time,
					   u64 cycle_time);

#if IS_ENABLED(CONFIG_STMMAC_SELFTESTS)
void stmmac_selftest_run(struct net_device *dev,
			 struct ethtool_test *etest, u64 *buf);
void stmmac_selftest_get_strings(struct stmmac_priv *priv, u8 *data);
int stmmac_selftest_get_count(struct stmmac_priv *priv);
#else
static inline void stmmac_selftest_run(struct net_device *dev,
				       struct ethtool_test *etest, u64 *buf)
{
	/* Not enabled */
}
static inline void stmmac_selftest_get_strings(struct stmmac_priv *priv,
					       u8 *data)
{
	/* Not enabled */
}
static inline int stmmac_selftest_get_count(struct stmmac_priv *priv)
{
	return -EOPNOTSUPP;
}
#endif /* CONFIG_STMMAC_SELFTESTS */

#endif /* __STMMAC_H__ */
Commit	Line	Data
4fa9c49f	1	/* SPDX-License-Identifier: GPL-2.0-only */
47dd7a54 GC	2	/*******************************************************************************
	3	Copyright (C) 2007-2009 STMicroelectronics Ltd
	4
47dd7a54 GC	5
	6	Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	7	*******************************************************************************/
	8
bd4242df RK	9	#ifndef __STMMAC_H__
	10	#define __STMMAC_H__
	11
bfab27a1	12	#define STMMAC_RESOURCE_NAME "stmmaceth"
ba1377ff GC	13
ba1377ff GC	14	#include <linux/clk.h>
d5a05e69	15	#include <linux/hrtimer.h>
3cd1cfcb	16	#include <linux/if_vlan.h>
ee7946a7	17	#include <linux/stmmac.h>
eeef2f6b	18	#include <linux/phylink.h>
33d5e332	19	#include <linux/pci.h>
47dd7a54	20	#include "common.h"
92ba6888	21	#include <linux/ptp_clock_kernel.h>
d6228b7c	22	#include <linux/net_tstamp.h>
c5e4ddbd	23	#include <linux/reset.h>
a9ca9f9c	24	#include <net/page_pool/types.h>
92272ec4	25	#include <net/xdp.h>
3b80b73a	26	#include <uapi/linux/bpf.h>
47dd7a54	27
e56788cf JE	28	struct stmmac_resources {
e56788cf JE	29	void __iomem *addr;
83216e39	30	u8 mac[ETH_ALEN];
e56788cf JE	31	int wol_irq;
	32	int lpi_irq;
	33	int irq;
8532f613 OBL	34	int sfty_ce_irq;
	35	int sfty_ue_irq;
	36	int rx_irq[MTL_MAX_RX_QUEUES];
	37	int tx_irq[MTL_MAX_TX_QUEUES];
e56788cf JE	38	};
e56788cf JE	39
be8b38a7 OBL	40	enum stmmac_txbuf_type {
	41	STMMAC_TXBUF_T_SKB,
	42	STMMAC_TXBUF_T_XDP_TX,
8b278a5b	43	STMMAC_TXBUF_T_XDP_NDO,
132c32ee	44	STMMAC_TXBUF_T_XSK_TX,
be8b38a7 OBL	45	};
be8b38a7 OBL	46
362b37be GC	47	struct stmmac_tx_info {
	48	dma_addr_t buf;
	49	bool map_as_page;
553e2ab3	50	unsigned len;
2a6d8e17	51	bool last_segment;
96951366	52	bool is_jumbo;
be8b38a7	53	enum stmmac_txbuf_type buf_type;
362b37be GC	54	};
362b37be GC	55
579a25a8 JA	56	#define STMMAC_TBS_AVAIL BIT(0)
	57	#define STMMAC_TBS_EN BIT(1)
	58
ce736788 JP	59	/* Frequently used values are kept adjacent for cache effect */
ce736788 JP	60	struct stmmac_tx_queue {
8fce3331	61	u32 tx_count_frames;
579a25a8	62	int tbs;
d5a05e69	63	struct hrtimer txtimer;
ce736788 JP	64	u32 queue_index;
	65	struct stmmac_priv *priv_data;
	66	struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp;
579a25a8	67	struct dma_edesc *dma_entx;
ce736788	68	struct dma_desc *dma_tx;
be8b38a7 OBL	69	union {
	70	struct sk_buff **tx_skbuff;
	71	struct xdp_frame **xdpf;
	72	};
ce736788	73	struct stmmac_tx_info *tx_skbuff_dma;
132c32ee OBL	74	struct xsk_buff_pool *xsk_pool;
132c32ee OBL	75	u32 xsk_frames_done;
ce736788 JP	76	unsigned int cur_tx;
	77	unsigned int dirty_tx;
	78	dma_addr_t dma_tx_phy;
52e597d3	79	dma_addr_t tx_tail_addr;
8d212a9e	80	u32 mss;
ce736788 JP	81	};
ce736788 JP	82
2af6106a	83	struct stmmac_rx_buffer {
bba2556e OBL	84	union {
	85	struct {
	86	struct page *page;
	87	dma_addr_t addr;
	88	__u32 page_offset;
	89	};
	90	struct xdp_buff *xdp;
	91	};
5fabb012	92	struct page *sec_page;
67afd6d1	93	dma_addr_t sec_addr;
2af6106a JA	94	};
2af6106a JA	95
5b24324a SYS	96	struct stmmac_xdp_buff {
5b24324a SYS	97	struct xdp_buff xdp;
e3f9c3e3 SYS	98	struct stmmac_priv *priv;
	99	struct dma_desc *desc;
	100	struct dma_desc *ndesc;
5b24324a SYS	101	};
5b24324a SYS	102
54139cf3	103	struct stmmac_rx_queue {
d429b66e	104	u32 rx_count_frames;
54139cf3	105	u32 queue_index;
be8b38a7	106	struct xdp_rxq_info xdp_rxq;
bba2556e	107	struct xsk_buff_pool *xsk_pool;
2af6106a JA	108	struct page_pool *page_pool;
2af6106a JA	109	struct stmmac_rx_buffer *buf_pool;
54139cf3 JP	110	struct stmmac_priv *priv_data;
	111	struct dma_extended_desc *dma_erx;
	112	struct dma_desc *dma_rx ____cacheline_aligned_in_smp;
54139cf3 JP	113	unsigned int cur_rx;
54139cf3 JP	114	unsigned int dirty_rx;
bba2556e	115	unsigned int buf_alloc_num;
54139cf3 JP	116	u32 rx_zeroc_thresh;
	117	dma_addr_t dma_rx_phy;
	118	u32 rx_tail_addr;
ec222003 JA	119	unsigned int state_saved;
	120	struct {
	121	struct sk_buff *skb;
	122	unsigned int len;
	123	unsigned int error;
	124	} state;
8fce3331 JA	125	};
	126
	127	struct stmmac_channel {
4ccb4585 JA	128	struct napi_struct rx_napi ____cacheline_aligned_in_smp;
4ccb4585 JA	129	struct napi_struct tx_napi ____cacheline_aligned_in_smp;
132c32ee	130	struct napi_struct rxtx_napi ____cacheline_aligned_in_smp;
8fce3331	131	struct stmmac_priv *priv_data;
021bd5e3	132	spinlock_t lock;
8fce3331	133	u32 index;
54139cf3 JP	134	};
54139cf3 JP	135
4dbbe8dd JA	136	struct stmmac_tc_entry {
	137	bool in_use;
	138	bool in_hw;
	139	bool is_last;
	140	bool is_frag;
	141	void *frag_ptr;
	142	unsigned int table_pos;
	143	u32 handle;
	144	u32 prio;
	145	struct {
	146	u32 match_data;
	147	u32 match_en;
	148	u8 af:1;
	149	u8 rf:1;
	150	u8 im:1;
	151	u8 nc:1;
	152	u8 res1:4;
	153	u8 frame_offset;
	154	u8 ok_index;
	155	u8 dma_ch_no;
	156	u32 res2;
	157	} __packed val;
	158	};
	159
9a8a02c9 JA	160	#define STMMAC_PPS_MAX 4
	161	struct stmmac_pps_cfg {
	162	bool available;
	163	struct timespec64 start;
	164	struct timespec64 period;
	165	};
	166
76067459 JA	167	struct stmmac_rss {
	168	int enable;
	169	u8 key[STMMAC_RSS_HASH_KEY_SIZE];
	170	u32 table[STMMAC_RSS_MAX_TABLE_SIZE];
	171	};
	172
425eabdd JA	173	#define STMMAC_FLOW_ACTION_DROP BIT(0)
	174	struct stmmac_flow_entry {
	175	unsigned long cookie;
	176	unsigned long action;
	177	u8 ip_proto;
	178	int in_use;
	179	int idx;
	180	int is_l4;
	181	};
	182
aeb7c75c OBL	183	/* Rx Frame Steering */
	184	enum stmmac_rfs_type {
	185	STMMAC_RFS_T_VLAN,
e48cb313 OBL	186	STMMAC_RFS_T_LLDP,
e48cb313 OBL	187	STMMAC_RFS_T_1588,
aeb7c75c OBL	188	STMMAC_RFS_T_MAX,
	189	};
	190
	191	struct stmmac_rfs_entry {
	192	unsigned long cookie;
e48cb313	193	u16 etype;
aeb7c75c OBL	194	int in_use;
	195	int type;
	196	int tc;
	197	};
	198
8531c808 CM	199	struct stmmac_dma_conf {
	200	unsigned int dma_buf_sz;
	201
	202	/* RX Queue */
	203	struct stmmac_rx_queue rx_queue[MTL_MAX_RX_QUEUES];
	204	unsigned int dma_rx_size;
	205
	206	/* TX Queue */
	207	struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES];
	208	unsigned int dma_tx_size;
	209	};
	210
47dd7a54 GC	211	struct stmmac_priv {
47dd7a54 GC	212	/* Frequently used values are kept adjacent for cache effect */
db2f2842 OBL	213	u32 tx_coal_frames[MTL_MAX_TX_QUEUES];
	214	u32 tx_coal_timer[MTL_MAX_TX_QUEUES];
	215	u32 rx_coal_frames[MTL_MAX_TX_QUEUES];
ce736788	216
1bb6dea8	217	int hwts_tx_en;
1bb6dea8	218	bool tx_path_in_lpi_mode;
f748be53	219	bool tso;
67afd6d1	220	int sph;
d08d32d1	221	int sph_cap;
8000ddc0	222	u32 sarc_type;
47dd7a54	223
22ad3838	224	unsigned int rx_copybreak;
db2f2842	225	u32 rx_riwt[MTL_MAX_TX_QUEUES];
1bb6dea8	226	int hwts_rx_en;
5bacd778	227
1bb6dea8	228	void __iomem *ioaddr;
47dd7a54	229	struct net_device *dev;
47dd7a54	230	struct device *device;
db98a0b0	231	struct mac_device_info *hw;
7cfde0af	232	int (hwif_quirks)(struct stmmac_priv priv);
29555fa3	233	struct mutex lock;
47dd7a54	234
8531c808	235	struct stmmac_dma_conf dma_conf;
ce736788	236
8fce3331 JA	237	/* Generic channel for NAPI */
	238	struct stmmac_channel channel[STMMAC_CH_MAX];
	239
47dd7a54	240	int speed;
47dd7a54 GC	241	unsigned int flow_ctrl;
	242	unsigned int pause;
	243	struct mii_bus *mii;
	244
eeef2f6b JA	245	struct phylink_config phylink_config;
	246	struct phylink *phylink;
	247
1bb6dea8	248	struct stmmac_extra_stats xstats ____cacheline_aligned_in_smp;
8bf993a5	249	struct stmmac_safety_stats sstats;
9dfeb4d9	250	struct plat_stmmacenet_data *plat;
e7434821	251	struct dma_features dma_cap;
1bb6dea8	252	struct stmmac_counters mmc;
19e30c14	253	int hw_cap_support;
1bb6dea8 GC	254	int synopsys_id;
	255	u32 msg_enable;
	256	int wolopts;
	257	int wol_irq;
cd7201f4	258	int clk_csr;
d765955d	259	struct timer_list eee_ctrl_timer;
d765955d GC	260	int lpi_irq;
	261	int eee_enabled;
	262	int eee_active;
	263	int tx_lpi_timer;
388e201d VJK	264	int tx_lpi_enabled;
388e201d VJK	265	int eee_tw_timer;
be1c7eae	266	bool eee_sw_timer_en;
4a7d666a	267	unsigned int mode;
5f0456b4	268	unsigned int chain_mode;
c24602ef	269	int extend_desc;
d6228b7c	270	struct hwtstamp_config tstamp_config;
92ba6888 RK	271	struct ptp_clock *ptp_clock;
92ba6888 RK	272	struct ptp_clock_info ptp_clock_ops;
1bb6dea8	273	unsigned int default_addend;
9a8a02c9 JA	274	u32 sub_second_inc;
9a8a02c9 JA	275	u32 systime_flags;
1bb6dea8 GC	276	u32 adv_ts;
1bb6dea8 GC	277	int use_riwt;
89f7f2cf	278	int irq_wake;
642436a1	279	rwlock_t ptp_lock;
f4da5652 TTM	280	/* Protects auxiliary snapshot registers from concurrent access. */
f4da5652 TTM	281	struct mutex aux_ts_lock;
76c16d3e	282	wait_queue_head_t tstamp_busy_wait;
f4da5652	283
36ff7c1e	284	void __iomem *mmcaddr;
ba1ffd74	285	void __iomem *ptpaddr;
3cd1cfcb	286	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
8532f613 OBL	287	int sfty_ce_irq;
	288	int sfty_ue_irq;
	289	int rx_irq[MTL_MAX_RX_QUEUES];
	290	int tx_irq[MTL_MAX_TX_QUEUES];
	291	/irq name /
	292	char int_name_mac[IFNAMSIZ + 9];
	293	char int_name_wol[IFNAMSIZ + 9];
	294	char int_name_lpi[IFNAMSIZ + 9];
	295	char int_name_sfty_ce[IFNAMSIZ + 10];
	296	char int_name_sfty_ue[IFNAMSIZ + 10];
	297	char int_name_rx_irq[MTL_MAX_TX_QUEUES][IFNAMSIZ + 14];
	298	char int_name_tx_irq[MTL_MAX_TX_QUEUES][IFNAMSIZ + 18];
466c5ac8 MO	299
	300	#ifdef CONFIG_DEBUG_FS
	301	struct dentry *dbgfs_dir;
466c5ac8	302	#endif
34877a15 JA	303
	304	unsigned long state;
	305	struct workqueue_struct *wq;
	306	struct work_struct service_task;
4dbbe8dd	307
5a558611 OBL	308	/* Workqueue for handling FPE hand-shaking */
	309	unsigned long fpe_task_state;
	310	struct workqueue_struct *fpe_wq;
	311	struct work_struct fpe_task;
	312	char wq_name[IFNAMSIZ + 4];
	313
4dbbe8dd JA	314	/* TC Handling */
	315	unsigned int tc_entries_max;
	316	unsigned int tc_off_max;
	317	struct stmmac_tc_entry *tc_entries;
425eabdd JA	318	unsigned int flow_entries_max;
425eabdd JA	319	struct stmmac_flow_entry *flow_entries;
aeb7c75c OBL	320	unsigned int rfs_entries_max[STMMAC_RFS_T_MAX];
	321	unsigned int rfs_entries_cnt[STMMAC_RFS_T_MAX];
	322	unsigned int rfs_entries_total;
	323	struct stmmac_rfs_entry *rfs_entries;
9a8a02c9 JA	324
	325	/* Pulse Per Second output */
	326	struct stmmac_pps_cfg pps[STMMAC_PPS_MAX];
76067459 JA	327
	328	/* Receive Side Scaling */
	329	struct stmmac_rss rss;
5fabb012 OBL	330
5fabb012 OBL	331	/* XDP BPF Program */
bba2556e	332	unsigned long *af_xdp_zc_qps;
5fabb012	333	struct bpf_prog *xdp_prog;
34877a15 JA	334	};
	335
	336	enum stmmac_state {
	337	STMMAC_DOWN,
	338	STMMAC_RESET_REQUESTED,
	339	STMMAC_RESETING,
	340	STMMAC_SERVICE_SCHED,
47dd7a54 GC	341	};
47dd7a54 GC	342
d6cc64ef JP	343	int stmmac_mdio_unregister(struct net_device *ndev);
d6cc64ef JP	344	int stmmac_mdio_register(struct net_device *ndev);
073752aa	345	int stmmac_mdio_reset(struct mii_bus *mii);
597a68ce	346	int stmmac_xpcs_setup(struct mii_bus *mii);
d6cc64ef	347	void stmmac_set_ethtool_ops(struct net_device *netdev);
915af656	348
a6da2bbb	349	int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags);
c30a70d3	350	void stmmac_ptp_register(struct stmmac_priv *priv);
d6cc64ef	351	void stmmac_ptp_unregister(struct stmmac_priv *priv);
ac746c85 OBL	352	int stmmac_xdp_open(struct net_device *dev);
ac746c85 OBL	353	void stmmac_xdp_release(struct net_device *dev);
f4e7bd81 JE	354	int stmmac_resume(struct device *dev);
f4e7bd81 JE	355	int stmmac_suspend(struct device *dev);
ff0011cf	356	void stmmac_dvr_remove(struct device *dev);
15ffac73 JE	357	int stmmac_dvr_probe(struct device *device,
	358	struct plat_stmmacenet_data *plat_dat,
	359	struct stmmac_resources *res);
d765955d GC	360	void stmmac_disable_eee_mode(struct stmmac_priv *priv);
d765955d GC	361	bool stmmac_eee_init(struct stmmac_priv *priv);
0366f7e0	362	int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt);
aa042f60	363	int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size);
5ec55823	364	int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled);
5a558611	365	void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable);
ba1377ff	366
5fabb012 OBL	367	static inline bool stmmac_xdp_is_enabled(struct stmmac_priv *priv)
	368	{
	369	return !!priv->xdp_prog;
	370	}
	371
	372	static inline unsigned int stmmac_rx_offset(struct stmmac_priv *priv)
	373	{
	374	if (stmmac_xdp_is_enabled(priv))
12d125b4	375	return XDP_PACKET_HEADROOM;
5fabb012	376
12d125b4	377	return 0;
5fabb012 OBL	378	}
5fabb012 OBL	379
bba2556e OBL	380	void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue);
bba2556e OBL	381	void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue);
132c32ee OBL	382	void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue);
132c32ee OBL	383	void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue);
bba2556e	384	int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags);
81c52c42 XY	385	struct timespec64 stmmac_calc_tas_basetime(ktime_t old_base_time,
	386	ktime_t current_time,
	387	u64 cycle_time);
bba2556e	388
091810db JA	389	#if IS_ENABLED(CONFIG_STMMAC_SELFTESTS)
	390	void stmmac_selftest_run(struct net_device *dev,
	391	struct ethtool_test etest, u64 buf);
	392	void stmmac_selftest_get_strings(struct stmmac_priv priv, u8 data);
	393	int stmmac_selftest_get_count(struct stmmac_priv *priv);
	394	#else
	395	static inline void stmmac_selftest_run(struct net_device *dev,
	396	struct ethtool_test etest, u64 buf)
	397	{
	398	/* Not enabled */
	399	}
	400	static inline void stmmac_selftest_get_strings(struct stmmac_priv *priv,
	401	u8 *data)
	402	{
	403	/* Not enabled */
	404	}
	405	static inline int stmmac_selftest_get_count(struct stmmac_priv *priv)
	406	{
	407	return -EOPNOTSUPP;
	408	}
	409	#endif /* CONFIG_STMMAC_SELFTESTS */
	410
bd4242df	411	#endif /* __STMMAC_H__ */