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Commit | Line | Data |
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eea221ce AN |
1 | /* |
2 | * tc35815.c: A TOSHIBA TC35815CF PCI 10/100Mbps ethernet driver for linux. | |
1da177e4 LT |
3 | * |
4 | * Based on skelton.c by Donald Becker. | |
1da177e4 | 5 | * |
eea221ce AN |
6 | * This driver is a replacement of older and less maintained version. |
7 | * This is a header of the older version: | |
8 | * -----<snip>----- | |
9 | * Copyright 2001 MontaVista Software Inc. | |
10 | * Author: MontaVista Software, Inc. | |
11 | * ahennessy@mvista.com | |
12 | * Copyright (C) 2000-2001 Toshiba Corporation | |
13 | * static const char *version = | |
14 | * "tc35815.c:v0.00 26/07/2000 by Toshiba Corporation\n"; | |
15 | * -----<snip>----- | |
1da177e4 | 16 | * |
eea221ce AN |
17 | * This file is subject to the terms and conditions of the GNU General Public |
18 | * License. See the file "COPYING" in the main directory of this archive | |
19 | * for more details. | |
1da177e4 | 20 | * |
eea221ce AN |
21 | * (C) Copyright TOSHIBA CORPORATION 2004-2005 |
22 | * All Rights Reserved. | |
1da177e4 LT |
23 | */ |
24 | ||
c6a2dbba | 25 | #define DRV_VERSION "1.39" |
06324664 | 26 | static const char version[] = "tc35815.c:v" DRV_VERSION "\n"; |
eea221ce | 27 | #define MODNAME "tc35815" |
1da177e4 LT |
28 | |
29 | #include <linux/module.h> | |
30 | #include <linux/kernel.h> | |
31 | #include <linux/types.h> | |
32 | #include <linux/fcntl.h> | |
33 | #include <linux/interrupt.h> | |
34 | #include <linux/ioport.h> | |
35 | #include <linux/in.h> | |
82a9928d | 36 | #include <linux/if_vlan.h> |
1da177e4 LT |
37 | #include <linux/slab.h> |
38 | #include <linux/string.h> | |
eea221ce | 39 | #include <linux/spinlock.h> |
1da177e4 | 40 | #include <linux/errno.h> |
1da177e4 LT |
41 | #include <linux/netdevice.h> |
42 | #include <linux/etherdevice.h> | |
43 | #include <linux/skbuff.h> | |
44 | #include <linux/delay.h> | |
45 | #include <linux/pci.h> | |
c6686fe3 AN |
46 | #include <linux/phy.h> |
47 | #include <linux/workqueue.h> | |
bd43da8f | 48 | #include <linux/platform_device.h> |
70c71606 | 49 | #include <linux/prefetch.h> |
1da177e4 | 50 | #include <asm/io.h> |
1da177e4 LT |
51 | #include <asm/byteorder.h> |
52 | ||
c6686fe3 | 53 | enum tc35815_chiptype { |
eea221ce AN |
54 | TC35815CF = 0, |
55 | TC35815_NWU, | |
56 | TC35815_TX4939, | |
c6686fe3 | 57 | }; |
eea221ce | 58 | |
c6686fe3 | 59 | /* indexed by tc35815_chiptype, above */ |
eea221ce AN |
60 | static const struct { |
61 | const char *name; | |
b38d1306 | 62 | } chip_info[] = { |
eea221ce AN |
63 | { "TOSHIBA TC35815CF 10/100BaseTX" }, |
64 | { "TOSHIBA TC35815 with Wake on LAN" }, | |
65 | { "TOSHIBA TC35815/TX4939" }, | |
66 | }; | |
67 | ||
9baa3c34 | 68 | static const struct pci_device_id tc35815_pci_tbl[] = { |
eea221ce AN |
69 | {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815CF), .driver_data = TC35815CF }, |
70 | {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_NWU), .driver_data = TC35815_NWU }, | |
71 | {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939), .driver_data = TC35815_TX4939 }, | |
72 | {0,} | |
73 | }; | |
7f225b42 | 74 | MODULE_DEVICE_TABLE(pci, tc35815_pci_tbl); |
1da177e4 | 75 | |
eea221ce AN |
76 | /* see MODULE_PARM_DESC */ |
77 | static struct tc35815_options { | |
78 | int speed; | |
79 | int duplex; | |
eea221ce | 80 | } options; |
1da177e4 LT |
81 | |
82 | /* | |
83 | * Registers | |
84 | */ | |
85 | struct tc35815_regs { | |
22adf7e5 AN |
86 | __u32 DMA_Ctl; /* 0x00 */ |
87 | __u32 TxFrmPtr; | |
88 | __u32 TxThrsh; | |
89 | __u32 TxPollCtr; | |
90 | __u32 BLFrmPtr; | |
91 | __u32 RxFragSize; | |
92 | __u32 Int_En; | |
93 | __u32 FDA_Bas; | |
94 | __u32 FDA_Lim; /* 0x20 */ | |
95 | __u32 Int_Src; | |
96 | __u32 unused0[2]; | |
97 | __u32 PauseCnt; | |
98 | __u32 RemPauCnt; | |
99 | __u32 TxCtlFrmStat; | |
100 | __u32 unused1; | |
101 | __u32 MAC_Ctl; /* 0x40 */ | |
102 | __u32 CAM_Ctl; | |
103 | __u32 Tx_Ctl; | |
104 | __u32 Tx_Stat; | |
105 | __u32 Rx_Ctl; | |
106 | __u32 Rx_Stat; | |
107 | __u32 MD_Data; | |
108 | __u32 MD_CA; | |
109 | __u32 CAM_Adr; /* 0x60 */ | |
110 | __u32 CAM_Data; | |
111 | __u32 CAM_Ena; | |
112 | __u32 PROM_Ctl; | |
113 | __u32 PROM_Data; | |
114 | __u32 Algn_Cnt; | |
115 | __u32 CRC_Cnt; | |
116 | __u32 Miss_Cnt; | |
1da177e4 LT |
117 | }; |
118 | ||
119 | /* | |
120 | * Bit assignments | |
121 | */ | |
25985edc | 122 | /* DMA_Ctl bit assign ------------------------------------------------------- */ |
7f225b42 AN |
123 | #define DMA_RxAlign 0x00c00000 /* 1:Reception Alignment */ |
124 | #define DMA_RxAlign_1 0x00400000 | |
125 | #define DMA_RxAlign_2 0x00800000 | |
126 | #define DMA_RxAlign_3 0x00c00000 | |
127 | #define DMA_M66EnStat 0x00080000 /* 1:66MHz Enable State */ | |
25985edc | 128 | #define DMA_IntMask 0x00040000 /* 1:Interrupt mask */ |
7f225b42 AN |
129 | #define DMA_SWIntReq 0x00020000 /* 1:Software Interrupt request */ |
130 | #define DMA_TxWakeUp 0x00010000 /* 1:Transmit Wake Up */ | |
131 | #define DMA_RxBigE 0x00008000 /* 1:Receive Big Endian */ | |
132 | #define DMA_TxBigE 0x00004000 /* 1:Transmit Big Endian */ | |
133 | #define DMA_TestMode 0x00002000 /* 1:Test Mode */ | |
134 | #define DMA_PowrMgmnt 0x00001000 /* 1:Power Management */ | |
135 | #define DMA_DmBurst_Mask 0x000001fc /* DMA Burst size */ | |
1da177e4 | 136 | |
25985edc | 137 | /* RxFragSize bit assign ---------------------------------------------------- */ |
7f225b42 AN |
138 | #define RxFrag_EnPack 0x00008000 /* 1:Enable Packing */ |
139 | #define RxFrag_MinFragMask 0x00000ffc /* Minimum Fragment */ | |
1da177e4 | 140 | |
25985edc | 141 | /* MAC_Ctl bit assign ------------------------------------------------------- */ |
7f225b42 AN |
142 | #define MAC_Link10 0x00008000 /* 1:Link Status 10Mbits */ |
143 | #define MAC_EnMissRoll 0x00002000 /* 1:Enable Missed Roll */ | |
144 | #define MAC_MissRoll 0x00000400 /* 1:Missed Roll */ | |
145 | #define MAC_Loop10 0x00000080 /* 1:Loop 10 Mbps */ | |
146 | #define MAC_Conn_Auto 0x00000000 /*00:Connection mode (Automatic) */ | |
147 | #define MAC_Conn_10M 0x00000020 /*01: (10Mbps endec)*/ | |
148 | #define MAC_Conn_Mll 0x00000040 /*10: (Mll clock) */ | |
149 | #define MAC_MacLoop 0x00000010 /* 1:MAC Loopback */ | |
150 | #define MAC_FullDup 0x00000008 /* 1:Full Duplex 0:Half Duplex */ | |
151 | #define MAC_Reset 0x00000004 /* 1:Software Reset */ | |
152 | #define MAC_HaltImm 0x00000002 /* 1:Halt Immediate */ | |
153 | #define MAC_HaltReq 0x00000001 /* 1:Halt request */ | |
1da177e4 | 154 | |
25985edc | 155 | /* PROM_Ctl bit assign ------------------------------------------------------ */ |
7f225b42 AN |
156 | #define PROM_Busy 0x00008000 /* 1:Busy (Start Operation) */ |
157 | #define PROM_Read 0x00004000 /*10:Read operation */ | |
158 | #define PROM_Write 0x00002000 /*01:Write operation */ | |
159 | #define PROM_Erase 0x00006000 /*11:Erase operation */ | |
160 | /*00:Enable or Disable Writting, */ | |
161 | /* as specified in PROM_Addr. */ | |
162 | #define PROM_Addr_Ena 0x00000030 /*11xxxx:PROM Write enable */ | |
163 | /*00xxxx: disable */ | |
1da177e4 | 164 | |
25985edc | 165 | /* CAM_Ctl bit assign ------------------------------------------------------- */ |
7f225b42 AN |
166 | #define CAM_CompEn 0x00000010 /* 1:CAM Compare Enable */ |
167 | #define CAM_NegCAM 0x00000008 /* 1:Reject packets CAM recognizes,*/ | |
168 | /* accept other */ | |
169 | #define CAM_BroadAcc 0x00000004 /* 1:Broadcast assept */ | |
170 | #define CAM_GroupAcc 0x00000002 /* 1:Multicast assept */ | |
171 | #define CAM_StationAcc 0x00000001 /* 1:unicast accept */ | |
1da177e4 | 172 | |
25985edc | 173 | /* CAM_Ena bit assign ------------------------------------------------------- */ |
7f225b42 | 174 | #define CAM_ENTRY_MAX 21 /* CAM Data entry max count */ |
1da177e4 | 175 | #define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits) */ |
7f225b42 | 176 | #define CAM_Ena_Bit(index) (1 << (index)) |
1da177e4 LT |
177 | #define CAM_ENTRY_DESTINATION 0 |
178 | #define CAM_ENTRY_SOURCE 1 | |
179 | #define CAM_ENTRY_MACCTL 20 | |
180 | ||
25985edc | 181 | /* Tx_Ctl bit assign -------------------------------------------------------- */ |
7f225b42 AN |
182 | #define Tx_En 0x00000001 /* 1:Transmit enable */ |
183 | #define Tx_TxHalt 0x00000002 /* 1:Transmit Halt Request */ | |
184 | #define Tx_NoPad 0x00000004 /* 1:Suppress Padding */ | |
185 | #define Tx_NoCRC 0x00000008 /* 1:Suppress Padding */ | |
186 | #define Tx_FBack 0x00000010 /* 1:Fast Back-off */ | |
187 | #define Tx_EnUnder 0x00000100 /* 1:Enable Underrun */ | |
188 | #define Tx_EnExDefer 0x00000200 /* 1:Enable Excessive Deferral */ | |
189 | #define Tx_EnLCarr 0x00000400 /* 1:Enable Lost Carrier */ | |
190 | #define Tx_EnExColl 0x00000800 /* 1:Enable Excessive Collision */ | |
191 | #define Tx_EnLateColl 0x00001000 /* 1:Enable Late Collision */ | |
192 | #define Tx_EnTxPar 0x00002000 /* 1:Enable Transmit Parity */ | |
193 | #define Tx_EnComp 0x00004000 /* 1:Enable Completion */ | |
1da177e4 | 194 | |
25985edc | 195 | /* Tx_Stat bit assign ------------------------------------------------------- */ |
7f225b42 AN |
196 | #define Tx_TxColl_MASK 0x0000000F /* Tx Collision Count */ |
197 | #define Tx_ExColl 0x00000010 /* Excessive Collision */ | |
198 | #define Tx_TXDefer 0x00000020 /* Transmit Defered */ | |
199 | #define Tx_Paused 0x00000040 /* Transmit Paused */ | |
200 | #define Tx_IntTx 0x00000080 /* Interrupt on Tx */ | |
201 | #define Tx_Under 0x00000100 /* Underrun */ | |
202 | #define Tx_Defer 0x00000200 /* Deferral */ | |
203 | #define Tx_NCarr 0x00000400 /* No Carrier */ | |
204 | #define Tx_10Stat 0x00000800 /* 10Mbps Status */ | |
205 | #define Tx_LateColl 0x00001000 /* Late Collision */ | |
206 | #define Tx_TxPar 0x00002000 /* Tx Parity Error */ | |
207 | #define Tx_Comp 0x00004000 /* Completion */ | |
208 | #define Tx_Halted 0x00008000 /* Tx Halted */ | |
209 | #define Tx_SQErr 0x00010000 /* Signal Quality Error(SQE) */ | |
1da177e4 | 210 | |
25985edc | 211 | /* Rx_Ctl bit assign -------------------------------------------------------- */ |
7f225b42 AN |
212 | #define Rx_EnGood 0x00004000 /* 1:Enable Good */ |
213 | #define Rx_EnRxPar 0x00002000 /* 1:Enable Receive Parity */ | |
214 | #define Rx_EnLongErr 0x00000800 /* 1:Enable Long Error */ | |
215 | #define Rx_EnOver 0x00000400 /* 1:Enable OverFlow */ | |
216 | #define Rx_EnCRCErr 0x00000200 /* 1:Enable CRC Error */ | |
217 | #define Rx_EnAlign 0x00000100 /* 1:Enable Alignment */ | |
218 | #define Rx_IgnoreCRC 0x00000040 /* 1:Ignore CRC Value */ | |
219 | #define Rx_StripCRC 0x00000010 /* 1:Strip CRC Value */ | |
220 | #define Rx_ShortEn 0x00000008 /* 1:Short Enable */ | |
221 | #define Rx_LongEn 0x00000004 /* 1:Long Enable */ | |
222 | #define Rx_RxHalt 0x00000002 /* 1:Receive Halt Request */ | |
223 | #define Rx_RxEn 0x00000001 /* 1:Receive Intrrupt Enable */ | |
1da177e4 | 224 | |
25985edc | 225 | /* Rx_Stat bit assign ------------------------------------------------------- */ |
7f225b42 AN |
226 | #define Rx_Halted 0x00008000 /* Rx Halted */ |
227 | #define Rx_Good 0x00004000 /* Rx Good */ | |
228 | #define Rx_RxPar 0x00002000 /* Rx Parity Error */ | |
842e08bd | 229 | #define Rx_TypePkt 0x00001000 /* Rx Type Packet */ |
7f225b42 AN |
230 | #define Rx_LongErr 0x00000800 /* Rx Long Error */ |
231 | #define Rx_Over 0x00000400 /* Rx Overflow */ | |
232 | #define Rx_CRCErr 0x00000200 /* Rx CRC Error */ | |
233 | #define Rx_Align 0x00000100 /* Rx Alignment Error */ | |
234 | #define Rx_10Stat 0x00000080 /* Rx 10Mbps Status */ | |
235 | #define Rx_IntRx 0x00000040 /* Rx Interrupt */ | |
236 | #define Rx_CtlRecd 0x00000020 /* Rx Control Receive */ | |
842e08bd | 237 | #define Rx_InLenErr 0x00000010 /* Rx In Range Frame Length Error */ |
7f225b42 | 238 | |
842e08bd | 239 | #define Rx_Stat_Mask 0x0000FFF0 /* Rx All Status Mask */ |
1da177e4 | 240 | |
25985edc | 241 | /* Int_En bit assign -------------------------------------------------------- */ |
7f225b42 AN |
242 | #define Int_NRAbtEn 0x00000800 /* 1:Non-recoverable Abort Enable */ |
243 | #define Int_TxCtlCmpEn 0x00000400 /* 1:Transmit Ctl Complete Enable */ | |
244 | #define Int_DmParErrEn 0x00000200 /* 1:DMA Parity Error Enable */ | |
245 | #define Int_DParDEn 0x00000100 /* 1:Data Parity Error Enable */ | |
246 | #define Int_EarNotEn 0x00000080 /* 1:Early Notify Enable */ | |
247 | #define Int_DParErrEn 0x00000040 /* 1:Detected Parity Error Enable */ | |
248 | #define Int_SSysErrEn 0x00000020 /* 1:Signalled System Error Enable */ | |
249 | #define Int_RMasAbtEn 0x00000010 /* 1:Received Master Abort Enable */ | |
250 | #define Int_RTargAbtEn 0x00000008 /* 1:Received Target Abort Enable */ | |
251 | #define Int_STargAbtEn 0x00000004 /* 1:Signalled Target Abort Enable */ | |
252 | #define Int_BLExEn 0x00000002 /* 1:Buffer List Exhausted Enable */ | |
253 | #define Int_FDAExEn 0x00000001 /* 1:Free Descriptor Area */ | |
254 | /* Exhausted Enable */ | |
1da177e4 | 255 | |
25985edc | 256 | /* Int_Src bit assign ------------------------------------------------------- */ |
7f225b42 AN |
257 | #define Int_NRabt 0x00004000 /* 1:Non Recoverable error */ |
258 | #define Int_DmParErrStat 0x00002000 /* 1:DMA Parity Error & Clear */ | |
259 | #define Int_BLEx 0x00001000 /* 1:Buffer List Empty & Clear */ | |
260 | #define Int_FDAEx 0x00000800 /* 1:FDA Empty & Clear */ | |
261 | #define Int_IntNRAbt 0x00000400 /* 1:Non Recoverable Abort */ | |
262 | #define Int_IntCmp 0x00000200 /* 1:MAC control packet complete */ | |
263 | #define Int_IntExBD 0x00000100 /* 1:Interrupt Extra BD & Clear */ | |
264 | #define Int_DmParErr 0x00000080 /* 1:DMA Parity Error & Clear */ | |
265 | #define Int_IntEarNot 0x00000040 /* 1:Receive Data write & Clear */ | |
266 | #define Int_SWInt 0x00000020 /* 1:Software request & Clear */ | |
267 | #define Int_IntBLEx 0x00000010 /* 1:Buffer List Empty & Clear */ | |
268 | #define Int_IntFDAEx 0x00000008 /* 1:FDA Empty & Clear */ | |
269 | #define Int_IntPCI 0x00000004 /* 1:PCI controller & Clear */ | |
270 | #define Int_IntMacRx 0x00000002 /* 1:Rx controller & Clear */ | |
271 | #define Int_IntMacTx 0x00000001 /* 1:Tx controller & Clear */ | |
1da177e4 | 272 | |
25985edc LDM |
273 | /* MD_CA bit assign --------------------------------------------------------- */ |
274 | #define MD_CA_PreSup 0x00001000 /* 1:Preamble Suppress */ | |
7f225b42 AN |
275 | #define MD_CA_Busy 0x00000800 /* 1:Busy (Start Operation) */ |
276 | #define MD_CA_Wr 0x00000400 /* 1:Write 0:Read */ | |
1da177e4 LT |
277 | |
278 | ||
1da177e4 LT |
279 | /* |
280 | * Descriptors | |
281 | */ | |
282 | ||
1b283247 | 283 | /* Frame descriptor */ |
1da177e4 LT |
284 | struct FDesc { |
285 | volatile __u32 FDNext; | |
286 | volatile __u32 FDSystem; | |
287 | volatile __u32 FDStat; | |
288 | volatile __u32 FDCtl; | |
289 | }; | |
290 | ||
1b283247 | 291 | /* Buffer descriptor */ |
1da177e4 LT |
292 | struct BDesc { |
293 | volatile __u32 BuffData; | |
294 | volatile __u32 BDCtl; | |
295 | }; | |
296 | ||
297 | #define FD_ALIGN 16 | |
298 | ||
1b283247 | 299 | /* Frame Descriptor bit assign ---------------------------------------------- */ |
7f225b42 AN |
300 | #define FD_FDLength_MASK 0x0000FFFF /* Length MASK */ |
301 | #define FD_BDCnt_MASK 0x001F0000 /* BD count MASK in FD */ | |
302 | #define FD_FrmOpt_MASK 0x7C000000 /* Frame option MASK */ | |
1da177e4 | 303 | #define FD_FrmOpt_BigEndian 0x40000000 /* Tx/Rx */ |
7f225b42 AN |
304 | #define FD_FrmOpt_IntTx 0x20000000 /* Tx only */ |
305 | #define FD_FrmOpt_NoCRC 0x10000000 /* Tx only */ | |
1da177e4 LT |
306 | #define FD_FrmOpt_NoPadding 0x08000000 /* Tx only */ |
307 | #define FD_FrmOpt_Packing 0x04000000 /* Rx only */ | |
7f225b42 AN |
308 | #define FD_CownsFD 0x80000000 /* FD Controller owner bit */ |
309 | #define FD_Next_EOL 0x00000001 /* FD EOL indicator */ | |
310 | #define FD_BDCnt_SHIFT 16 | |
1da177e4 | 311 | |
1b283247 | 312 | /* Buffer Descriptor bit assign --------------------------------------------- */ |
25985edc | 313 | #define BD_BuffLength_MASK 0x0000FFFF /* Receive Data Size */ |
7f225b42 AN |
314 | #define BD_RxBDID_MASK 0x00FF0000 /* BD ID Number MASK */ |
315 | #define BD_RxBDSeqN_MASK 0x7F000000 /* Rx BD Sequence Number */ | |
316 | #define BD_CownsBD 0x80000000 /* BD Controller owner bit */ | |
317 | #define BD_RxBDID_SHIFT 16 | |
1da177e4 LT |
318 | #define BD_RxBDSeqN_SHIFT 24 |
319 | ||
320 | ||
321 | /* Some useful constants. */ | |
1da177e4 | 322 | |
a02b7b7a | 323 | #define TX_CTL_CMD (Tx_EnTxPar | Tx_EnLateColl | \ |
eea221ce AN |
324 | Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | Tx_EnUnder | \ |
325 | Tx_En) /* maybe 0x7b01 */ | |
297713de | 326 | /* Do not use Rx_StripCRC -- it causes trouble on BLEx/FDAEx condition */ |
1da177e4 | 327 | #define RX_CTL_CMD (Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver \ |
297713de | 328 | | Rx_EnCRCErr | Rx_EnAlign | Rx_RxEn) /* maybe 0x6f01 */ |
1da177e4 | 329 | #define INT_EN_CMD (Int_NRAbtEn | \ |
eea221ce | 330 | Int_DmParErrEn | Int_DParDEn | Int_DParErrEn | \ |
1da177e4 LT |
331 | Int_SSysErrEn | Int_RMasAbtEn | Int_RTargAbtEn | \ |
332 | Int_STargAbtEn | \ | |
333 | Int_BLExEn | Int_FDAExEn) /* maybe 0xb7f*/ | |
eea221ce | 334 | #define DMA_CTL_CMD DMA_BURST_SIZE |
c6686fe3 | 335 | #define HAVE_DMA_RXALIGN(lp) likely((lp)->chiptype != TC35815CF) |
1da177e4 LT |
336 | |
337 | /* Tuning parameters */ | |
338 | #define DMA_BURST_SIZE 32 | |
339 | #define TX_THRESHOLD 1024 | |
7f225b42 AN |
340 | /* used threshold with packet max byte for low pci transfer ability.*/ |
341 | #define TX_THRESHOLD_MAX 1536 | |
25985edc | 342 | /* setting threshold max value when overrun error occurred this count. */ |
7f225b42 | 343 | #define TX_THRESHOLD_KEEP_LIMIT 10 |
1da177e4 | 344 | |
eea221ce | 345 | /* 16 + RX_BUF_NUM * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*FD_PAGE_NUM */ |
eea221ce AN |
346 | #define FD_PAGE_NUM 4 |
347 | #define RX_BUF_NUM 128 /* < 256 */ | |
348 | #define RX_FD_NUM 256 /* >= 32 */ | |
349 | #define TX_FD_NUM 128 | |
350 | #if RX_CTL_CMD & Rx_LongEn | |
351 | #define RX_BUF_SIZE PAGE_SIZE | |
352 | #elif RX_CTL_CMD & Rx_StripCRC | |
82a9928d AN |
353 | #define RX_BUF_SIZE \ |
354 | L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + NET_IP_ALIGN) | |
eea221ce | 355 | #else |
82a9928d AN |
356 | #define RX_BUF_SIZE \ |
357 | L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN + NET_IP_ALIGN) | |
eea221ce | 358 | #endif |
eea221ce AN |
359 | #define RX_FD_RESERVE (2 / 2) /* max 2 BD per RxFD */ |
360 | #define NAPI_WEIGHT 16 | |
1da177e4 LT |
361 | |
362 | struct TxFD { | |
363 | struct FDesc fd; | |
364 | struct BDesc bd; | |
365 | struct BDesc unused; | |
366 | }; | |
367 | ||
368 | struct RxFD { | |
369 | struct FDesc fd; | |
f49b2759 | 370 | struct BDesc bd[]; /* variable length */ |
1da177e4 LT |
371 | }; |
372 | ||
373 | struct FrFD { | |
374 | struct FDesc fd; | |
eea221ce | 375 | struct BDesc bd[RX_BUF_NUM]; |
1da177e4 LT |
376 | }; |
377 | ||
378 | ||
22adf7e5 AN |
379 | #define tc_readl(addr) ioread32(addr) |
380 | #define tc_writel(d, addr) iowrite32(d, addr) | |
1da177e4 | 381 | |
eea221ce AN |
382 | #define TC35815_TX_TIMEOUT msecs_to_jiffies(400) |
383 | ||
c6686fe3 | 384 | /* Information that need to be kept for each controller. */ |
1da177e4 | 385 | struct tc35815_local { |
eea221ce | 386 | struct pci_dev *pci_dev; |
1da177e4 | 387 | |
bea3348e SH |
388 | struct net_device *dev; |
389 | struct napi_struct napi; | |
390 | ||
1da177e4 | 391 | /* statistics */ |
1da177e4 LT |
392 | struct { |
393 | int max_tx_qlen; | |
394 | int tx_ints; | |
395 | int rx_ints; | |
7f225b42 | 396 | int tx_underrun; |
1da177e4 LT |
397 | } lstats; |
398 | ||
eea221ce AN |
399 | /* Tx control lock. This protects the transmit buffer ring |
400 | * state along with the "tx full" state of the driver. This | |
401 | * means all netif_queue flow control actions are protected | |
402 | * by this lock as well. | |
403 | */ | |
404 | spinlock_t lock; | |
dee7399c | 405 | spinlock_t rx_lock; |
eea221ce | 406 | |
298cf9be | 407 | struct mii_bus *mii_bus; |
c6686fe3 AN |
408 | int duplex; |
409 | int speed; | |
410 | int link; | |
411 | struct work_struct restart_work; | |
1da177e4 LT |
412 | |
413 | /* | |
414 | * Transmitting: Batch Mode. | |
415 | * 1 BD in 1 TxFD. | |
a02b7b7a | 416 | * Receiving: Non-Packing Mode. |
eea221ce AN |
417 | * 1 circular FD for Free Buffer List. |
418 | * RX_BUF_NUM BD in Free Buffer FD. | |
419 | * One Free Buffer BD has ETH_FRAME_LEN data buffer. | |
1da177e4 | 420 | */ |
7f225b42 | 421 | void *fd_buf; /* for TxFD, RxFD, FrFD */ |
eea221ce | 422 | dma_addr_t fd_buf_dma; |
1da177e4 | 423 | struct TxFD *tfd_base; |
eea221ce AN |
424 | unsigned int tfd_start; |
425 | unsigned int tfd_end; | |
1da177e4 LT |
426 | struct RxFD *rfd_base; |
427 | struct RxFD *rfd_limit; | |
428 | struct RxFD *rfd_cur; | |
429 | struct FrFD *fbl_ptr; | |
eea221ce AN |
430 | unsigned int fbl_count; |
431 | struct { | |
432 | struct sk_buff *skb; | |
433 | dma_addr_t skb_dma; | |
434 | } tx_skbs[TX_FD_NUM], rx_skbs[RX_BUF_NUM]; | |
eea221ce | 435 | u32 msg_enable; |
c6686fe3 | 436 | enum tc35815_chiptype chiptype; |
1da177e4 LT |
437 | }; |
438 | ||
eea221ce AN |
439 | static inline dma_addr_t fd_virt_to_bus(struct tc35815_local *lp, void *virt) |
440 | { | |
441 | return lp->fd_buf_dma + ((u8 *)virt - (u8 *)lp->fd_buf); | |
442 | } | |
443 | #ifdef DEBUG | |
444 | static inline void *fd_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus) | |
445 | { | |
446 | return (void *)((u8 *)lp->fd_buf + (bus - lp->fd_buf_dma)); | |
447 | } | |
448 | #endif | |
eea221ce AN |
449 | static struct sk_buff *alloc_rxbuf_skb(struct net_device *dev, |
450 | struct pci_dev *hwdev, | |
451 | dma_addr_t *dma_handle) | |
452 | { | |
453 | struct sk_buff *skb; | |
dae2e9f4 | 454 | skb = netdev_alloc_skb(dev, RX_BUF_SIZE); |
eea221ce AN |
455 | if (!skb) |
456 | return NULL; | |
eea221ce AN |
457 | *dma_handle = pci_map_single(hwdev, skb->data, RX_BUF_SIZE, |
458 | PCI_DMA_FROMDEVICE); | |
8d8bb39b | 459 | if (pci_dma_mapping_error(hwdev, *dma_handle)) { |
eea221ce AN |
460 | dev_kfree_skb_any(skb); |
461 | return NULL; | |
462 | } | |
463 | skb_reserve(skb, 2); /* make IP header 4byte aligned */ | |
464 | return skb; | |
465 | } | |
466 | ||
467 | static void free_rxbuf_skb(struct pci_dev *hwdev, struct sk_buff *skb, dma_addr_t dma_handle) | |
468 | { | |
469 | pci_unmap_single(hwdev, dma_handle, RX_BUF_SIZE, | |
470 | PCI_DMA_FROMDEVICE); | |
471 | dev_kfree_skb_any(skb); | |
472 | } | |
1da177e4 | 473 | |
eea221ce | 474 | /* Index to functions, as function prototypes. */ |
1da177e4 LT |
475 | |
476 | static int tc35815_open(struct net_device *dev); | |
bacade82 Y |
477 | static netdev_tx_t tc35815_send_packet(struct sk_buff *skb, |
478 | struct net_device *dev); | |
eea221ce | 479 | static irqreturn_t tc35815_interrupt(int irq, void *dev_id); |
eea221ce | 480 | static int tc35815_rx(struct net_device *dev, int limit); |
bea3348e | 481 | static int tc35815_poll(struct napi_struct *napi, int budget); |
1da177e4 LT |
482 | static void tc35815_txdone(struct net_device *dev); |
483 | static int tc35815_close(struct net_device *dev); | |
484 | static struct net_device_stats *tc35815_get_stats(struct net_device *dev); | |
485 | static void tc35815_set_multicast_list(struct net_device *dev); | |
0290bd29 | 486 | static void tc35815_tx_timeout(struct net_device *dev, unsigned int txqueue); |
eea221ce AN |
487 | #ifdef CONFIG_NET_POLL_CONTROLLER |
488 | static void tc35815_poll_controller(struct net_device *dev); | |
489 | #endif | |
490 | static const struct ethtool_ops tc35815_ethtool_ops; | |
1da177e4 | 491 | |
eea221ce | 492 | /* Example routines you must write ;->. */ |
7f225b42 AN |
493 | static void tc35815_chip_reset(struct net_device *dev); |
494 | static void tc35815_chip_init(struct net_device *dev); | |
1da177e4 | 495 | |
eea221ce AN |
496 | #ifdef DEBUG |
497 | static void panic_queues(struct net_device *dev); | |
498 | #endif | |
1da177e4 | 499 | |
c6686fe3 AN |
500 | static void tc35815_restart_work(struct work_struct *work); |
501 | ||
502 | static int tc_mdio_read(struct mii_bus *bus, int mii_id, int regnum) | |
503 | { | |
504 | struct net_device *dev = bus->priv; | |
505 | struct tc35815_regs __iomem *tr = | |
506 | (struct tc35815_regs __iomem *)dev->base_addr; | |
c60a5cf7 | 507 | unsigned long timeout = jiffies + HZ; |
c6686fe3 AN |
508 | |
509 | tc_writel(MD_CA_Busy | (mii_id << 5) | (regnum & 0x1f), &tr->MD_CA); | |
c60a5cf7 | 510 | udelay(12); /* it takes 32 x 400ns at least */ |
c6686fe3 AN |
511 | while (tc_readl(&tr->MD_CA) & MD_CA_Busy) { |
512 | if (time_after(jiffies, timeout)) | |
513 | return -EIO; | |
514 | cpu_relax(); | |
515 | } | |
516 | return tc_readl(&tr->MD_Data) & 0xffff; | |
517 | } | |
518 | ||
519 | static int tc_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 val) | |
520 | { | |
521 | struct net_device *dev = bus->priv; | |
522 | struct tc35815_regs __iomem *tr = | |
523 | (struct tc35815_regs __iomem *)dev->base_addr; | |
c60a5cf7 | 524 | unsigned long timeout = jiffies + HZ; |
c6686fe3 AN |
525 | |
526 | tc_writel(val, &tr->MD_Data); | |
527 | tc_writel(MD_CA_Busy | MD_CA_Wr | (mii_id << 5) | (regnum & 0x1f), | |
528 | &tr->MD_CA); | |
c60a5cf7 | 529 | udelay(12); /* it takes 32 x 400ns at least */ |
c6686fe3 AN |
530 | while (tc_readl(&tr->MD_CA) & MD_CA_Busy) { |
531 | if (time_after(jiffies, timeout)) | |
532 | return -EIO; | |
533 | cpu_relax(); | |
534 | } | |
535 | return 0; | |
536 | } | |
537 | ||
538 | static void tc_handle_link_change(struct net_device *dev) | |
539 | { | |
540 | struct tc35815_local *lp = netdev_priv(dev); | |
a4fc549a | 541 | struct phy_device *phydev = dev->phydev; |
c6686fe3 AN |
542 | unsigned long flags; |
543 | int status_change = 0; | |
544 | ||
545 | spin_lock_irqsave(&lp->lock, flags); | |
546 | if (phydev->link && | |
547 | (lp->speed != phydev->speed || lp->duplex != phydev->duplex)) { | |
548 | struct tc35815_regs __iomem *tr = | |
549 | (struct tc35815_regs __iomem *)dev->base_addr; | |
550 | u32 reg; | |
551 | ||
552 | reg = tc_readl(&tr->MAC_Ctl); | |
553 | reg |= MAC_HaltReq; | |
554 | tc_writel(reg, &tr->MAC_Ctl); | |
555 | if (phydev->duplex == DUPLEX_FULL) | |
556 | reg |= MAC_FullDup; | |
557 | else | |
558 | reg &= ~MAC_FullDup; | |
559 | tc_writel(reg, &tr->MAC_Ctl); | |
560 | reg &= ~MAC_HaltReq; | |
561 | tc_writel(reg, &tr->MAC_Ctl); | |
562 | ||
563 | /* | |
564 | * TX4939 PCFG.SPEEDn bit will be changed on | |
565 | * NETDEV_CHANGE event. | |
566 | */ | |
c6686fe3 AN |
567 | /* |
568 | * WORKAROUND: enable LostCrS only if half duplex | |
569 | * operation. | |
570 | * (TX4939 does not have EnLCarr) | |
571 | */ | |
572 | if (phydev->duplex == DUPLEX_HALF && | |
573 | lp->chiptype != TC35815_TX4939) | |
574 | tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr, | |
575 | &tr->Tx_Ctl); | |
c6686fe3 AN |
576 | |
577 | lp->speed = phydev->speed; | |
578 | lp->duplex = phydev->duplex; | |
579 | status_change = 1; | |
580 | } | |
581 | ||
582 | if (phydev->link != lp->link) { | |
583 | if (phydev->link) { | |
c6686fe3 AN |
584 | /* delayed promiscuous enabling */ |
585 | if (dev->flags & IFF_PROMISC) | |
586 | tc35815_set_multicast_list(dev); | |
c6686fe3 AN |
587 | } else { |
588 | lp->speed = 0; | |
589 | lp->duplex = -1; | |
590 | } | |
591 | lp->link = phydev->link; | |
592 | ||
593 | status_change = 1; | |
594 | } | |
595 | spin_unlock_irqrestore(&lp->lock, flags); | |
596 | ||
597 | if (status_change && netif_msg_link(lp)) { | |
598 | phy_print_status(phydev); | |
72903831 JP |
599 | pr_debug("%s: MII BMCR %04x BMSR %04x LPA %04x\n", |
600 | dev->name, | |
601 | phy_read(phydev, MII_BMCR), | |
602 | phy_read(phydev, MII_BMSR), | |
603 | phy_read(phydev, MII_LPA)); | |
c6686fe3 AN |
604 | } |
605 | } | |
606 | ||
607 | static int tc_mii_probe(struct net_device *dev) | |
608 | { | |
3c1bcc86 | 609 | __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; |
c6686fe3 | 610 | struct tc35815_local *lp = netdev_priv(dev); |
a05876b3 | 611 | struct phy_device *phydev; |
c6686fe3 | 612 | |
a05876b3 | 613 | phydev = phy_find_first(lp->mii_bus); |
c6686fe3 AN |
614 | if (!phydev) { |
615 | printk(KERN_ERR "%s: no PHY found\n", dev->name); | |
616 | return -ENODEV; | |
617 | } | |
618 | ||
619 | /* attach the mac to the phy */ | |
84eff6d1 | 620 | phydev = phy_connect(dev, phydev_name(phydev), |
f9a8f83b FF |
621 | &tc_handle_link_change, |
622 | lp->chiptype == TC35815_TX4939 ? PHY_INTERFACE_MODE_RMII : PHY_INTERFACE_MODE_MII); | |
c6686fe3 AN |
623 | if (IS_ERR(phydev)) { |
624 | printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); | |
625 | return PTR_ERR(phydev); | |
626 | } | |
2220943a AL |
627 | |
628 | phy_attached_info(phydev); | |
c6686fe3 AN |
629 | |
630 | /* mask with MAC supported features */ | |
58056c1e | 631 | phy_set_max_speed(phydev, SPEED_100); |
3c1bcc86 AL |
632 | if (options.speed == 10) { |
633 | linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask); | |
634 | linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask); | |
635 | } else if (options.speed == 100) { | |
636 | linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, mask); | |
637 | linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, mask); | |
638 | } | |
639 | if (options.duplex == 1) { | |
640 | linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, mask); | |
641 | linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask); | |
642 | } else if (options.duplex == 2) { | |
643 | linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, mask); | |
644 | linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask); | |
645 | } | |
4b5b71f7 | 646 | linkmode_andnot(phydev->supported, phydev->supported, mask); |
3c1bcc86 | 647 | linkmode_copy(phydev->advertising, phydev->supported); |
c6686fe3 AN |
648 | |
649 | lp->link = 0; | |
650 | lp->speed = 0; | |
651 | lp->duplex = -1; | |
c6686fe3 AN |
652 | |
653 | return 0; | |
654 | } | |
655 | ||
656 | static int tc_mii_init(struct net_device *dev) | |
657 | { | |
658 | struct tc35815_local *lp = netdev_priv(dev); | |
659 | int err; | |
c6686fe3 | 660 | |
298cf9be LB |
661 | lp->mii_bus = mdiobus_alloc(); |
662 | if (lp->mii_bus == NULL) { | |
c6686fe3 AN |
663 | err = -ENOMEM; |
664 | goto err_out; | |
665 | } | |
666 | ||
298cf9be LB |
667 | lp->mii_bus->name = "tc35815_mii_bus"; |
668 | lp->mii_bus->read = tc_mdio_read; | |
669 | lp->mii_bus->write = tc_mdio_write; | |
670 | snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%x", | |
671 | (lp->pci_dev->bus->number << 8) | lp->pci_dev->devfn); | |
672 | lp->mii_bus->priv = dev; | |
673 | lp->mii_bus->parent = &lp->pci_dev->dev; | |
298cf9be | 674 | err = mdiobus_register(lp->mii_bus); |
c6686fe3 | 675 | if (err) |
e7f4dc35 | 676 | goto err_out_free_mii_bus; |
c6686fe3 AN |
677 | err = tc_mii_probe(dev); |
678 | if (err) | |
679 | goto err_out_unregister_bus; | |
680 | return 0; | |
681 | ||
682 | err_out_unregister_bus: | |
298cf9be | 683 | mdiobus_unregister(lp->mii_bus); |
51cf756c | 684 | err_out_free_mii_bus: |
298cf9be | 685 | mdiobus_free(lp->mii_bus); |
c6686fe3 AN |
686 | err_out: |
687 | return err; | |
688 | } | |
1da177e4 | 689 | |
bd43da8f AN |
690 | #ifdef CONFIG_CPU_TX49XX |
691 | /* | |
692 | * Find a platform_device providing a MAC address. The platform code | |
693 | * should provide a "tc35815-mac" device with a MAC address in its | |
694 | * platform_data. | |
695 | */ | |
418e3ea1 | 696 | static int tc35815_mac_match(struct device *dev, const void *data) |
bd43da8f AN |
697 | { |
698 | struct platform_device *plat_dev = to_platform_device(dev); | |
418e3ea1 | 699 | const struct pci_dev *pci_dev = data; |
06675e6f | 700 | unsigned int id = pci_dev->irq; |
bd43da8f AN |
701 | return !strcmp(plat_dev->name, "tc35815-mac") && plat_dev->id == id; |
702 | } | |
703 | ||
b38d1306 | 704 | static int tc35815_read_plat_dev_addr(struct net_device *dev) |
bd43da8f | 705 | { |
ee79b7fb | 706 | struct tc35815_local *lp = netdev_priv(dev); |
bd43da8f AN |
707 | struct device *pd = bus_find_device(&platform_bus_type, NULL, |
708 | lp->pci_dev, tc35815_mac_match); | |
709 | if (pd) { | |
710 | if (pd->platform_data) | |
711 | memcpy(dev->dev_addr, pd->platform_data, ETH_ALEN); | |
712 | put_device(pd); | |
713 | return is_valid_ether_addr(dev->dev_addr) ? 0 : -ENODEV; | |
714 | } | |
715 | return -ENODEV; | |
716 | } | |
717 | #else | |
b38d1306 | 718 | static int tc35815_read_plat_dev_addr(struct net_device *dev) |
bd43da8f AN |
719 | { |
720 | return -ENODEV; | |
721 | } | |
722 | #endif | |
723 | ||
b38d1306 | 724 | static int tc35815_init_dev_addr(struct net_device *dev) |
eea221ce AN |
725 | { |
726 | struct tc35815_regs __iomem *tr = | |
727 | (struct tc35815_regs __iomem *)dev->base_addr; | |
728 | int i; | |
729 | ||
eea221ce AN |
730 | while (tc_readl(&tr->PROM_Ctl) & PROM_Busy) |
731 | ; | |
732 | for (i = 0; i < 6; i += 2) { | |
733 | unsigned short data; | |
734 | tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl); | |
735 | while (tc_readl(&tr->PROM_Ctl) & PROM_Busy) | |
736 | ; | |
737 | data = tc_readl(&tr->PROM_Data); | |
738 | dev->dev_addr[i] = data & 0xff; | |
739 | dev->dev_addr[i+1] = data >> 8; | |
740 | } | |
bd43da8f AN |
741 | if (!is_valid_ether_addr(dev->dev_addr)) |
742 | return tc35815_read_plat_dev_addr(dev); | |
743 | return 0; | |
eea221ce | 744 | } |
1da177e4 | 745 | |
5a1c28b3 AB |
746 | static const struct net_device_ops tc35815_netdev_ops = { |
747 | .ndo_open = tc35815_open, | |
748 | .ndo_stop = tc35815_close, | |
749 | .ndo_start_xmit = tc35815_send_packet, | |
750 | .ndo_get_stats = tc35815_get_stats, | |
afc4b13d | 751 | .ndo_set_rx_mode = tc35815_set_multicast_list, |
5a1c28b3 | 752 | .ndo_tx_timeout = tc35815_tx_timeout, |
fd786fb1 | 753 | .ndo_do_ioctl = phy_do_ioctl_running, |
5a1c28b3 | 754 | .ndo_validate_addr = eth_validate_addr, |
5a1c28b3 AB |
755 | .ndo_set_mac_address = eth_mac_addr, |
756 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
757 | .ndo_poll_controller = tc35815_poll_controller, | |
758 | #endif | |
759 | }; | |
760 | ||
b38d1306 | 761 | static int tc35815_init_one(struct pci_dev *pdev, |
1dd06ae8 | 762 | const struct pci_device_id *ent) |
1da177e4 | 763 | { |
eea221ce AN |
764 | void __iomem *ioaddr = NULL; |
765 | struct net_device *dev; | |
766 | struct tc35815_local *lp; | |
767 | int rc; | |
eea221ce AN |
768 | |
769 | static int printed_version; | |
770 | if (!printed_version++) { | |
771 | printk(version); | |
772 | dev_printk(KERN_DEBUG, &pdev->dev, | |
c6686fe3 AN |
773 | "speed:%d duplex:%d\n", |
774 | options.speed, options.duplex); | |
eea221ce AN |
775 | } |
776 | ||
777 | if (!pdev->irq) { | |
778 | dev_warn(&pdev->dev, "no IRQ assigned.\n"); | |
779 | return -ENODEV; | |
780 | } | |
1da177e4 | 781 | |
eea221ce | 782 | /* dev zeroed in alloc_etherdev */ |
7f225b42 | 783 | dev = alloc_etherdev(sizeof(*lp)); |
41de8d4c | 784 | if (dev == NULL) |
eea221ce | 785 | return -ENOMEM; |
41de8d4c | 786 | |
eea221ce | 787 | SET_NETDEV_DEV(dev, &pdev->dev); |
ee79b7fb | 788 | lp = netdev_priv(dev); |
bea3348e | 789 | lp->dev = dev; |
1da177e4 | 790 | |
eea221ce | 791 | /* enable device (incl. PCI PM wakeup), and bus-mastering */ |
22adf7e5 | 792 | rc = pcim_enable_device(pdev); |
eea221ce AN |
793 | if (rc) |
794 | goto err_out; | |
22adf7e5 | 795 | rc = pcim_iomap_regions(pdev, 1 << 1, MODNAME); |
eea221ce | 796 | if (rc) |
1da177e4 | 797 | goto err_out; |
22adf7e5 AN |
798 | pci_set_master(pdev); |
799 | ioaddr = pcim_iomap_table(pdev)[1]; | |
1da177e4 | 800 | |
eea221ce | 801 | /* Initialize the device structure. */ |
5a1c28b3 | 802 | dev->netdev_ops = &tc35815_netdev_ops; |
eea221ce | 803 | dev->ethtool_ops = &tc35815_ethtool_ops; |
eea221ce | 804 | dev->watchdog_timeo = TC35815_TX_TIMEOUT; |
bea3348e | 805 | netif_napi_add(dev, &lp->napi, tc35815_poll, NAPI_WEIGHT); |
1da177e4 | 806 | |
eea221ce | 807 | dev->irq = pdev->irq; |
7f225b42 | 808 | dev->base_addr = (unsigned long)ioaddr; |
1da177e4 | 809 | |
c6686fe3 | 810 | INIT_WORK(&lp->restart_work, tc35815_restart_work); |
eea221ce | 811 | spin_lock_init(&lp->lock); |
dee7399c | 812 | spin_lock_init(&lp->rx_lock); |
eea221ce | 813 | lp->pci_dev = pdev; |
c6686fe3 | 814 | lp->chiptype = ent->driver_data; |
1da177e4 | 815 | |
eea221ce AN |
816 | lp->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK; |
817 | pci_set_drvdata(pdev, dev); | |
1da177e4 | 818 | |
eea221ce | 819 | /* Soft reset the chip. */ |
1da177e4 LT |
820 | tc35815_chip_reset(dev); |
821 | ||
eea221ce | 822 | /* Retrieve the ethernet address. */ |
bd43da8f AN |
823 | if (tc35815_init_dev_addr(dev)) { |
824 | dev_warn(&pdev->dev, "not valid ether addr\n"); | |
f2cedb63 | 825 | eth_hw_addr_random(dev); |
bd43da8f | 826 | } |
eea221ce | 827 | |
7f225b42 | 828 | rc = register_netdev(dev); |
eea221ce | 829 | if (rc) |
1e2cfeef | 830 | goto err_out; |
eea221ce | 831 | |
e174961c | 832 | printk(KERN_INFO "%s: %s at 0x%lx, %pM, IRQ %d\n", |
eea221ce | 833 | dev->name, |
c6686fe3 | 834 | chip_info[ent->driver_data].name, |
eea221ce | 835 | dev->base_addr, |
e174961c | 836 | dev->dev_addr, |
eea221ce AN |
837 | dev->irq); |
838 | ||
c6686fe3 AN |
839 | rc = tc_mii_init(dev); |
840 | if (rc) | |
841 | goto err_out_unregister; | |
1da177e4 | 842 | |
eea221ce | 843 | return 0; |
1da177e4 | 844 | |
c6686fe3 AN |
845 | err_out_unregister: |
846 | unregister_netdev(dev); | |
eea221ce | 847 | err_out: |
7f225b42 | 848 | free_netdev(dev); |
eea221ce AN |
849 | return rc; |
850 | } | |
1da177e4 | 851 | |
1da177e4 | 852 | |
b38d1306 | 853 | static void tc35815_remove_one(struct pci_dev *pdev) |
eea221ce | 854 | { |
7f225b42 | 855 | struct net_device *dev = pci_get_drvdata(pdev); |
c6686fe3 | 856 | struct tc35815_local *lp = netdev_priv(dev); |
1da177e4 | 857 | |
a4fc549a | 858 | phy_disconnect(dev->phydev); |
298cf9be | 859 | mdiobus_unregister(lp->mii_bus); |
298cf9be | 860 | mdiobus_free(lp->mii_bus); |
7f225b42 AN |
861 | unregister_netdev(dev); |
862 | free_netdev(dev); | |
1da177e4 LT |
863 | } |
864 | ||
1da177e4 LT |
865 | static int |
866 | tc35815_init_queues(struct net_device *dev) | |
867 | { | |
ee79b7fb | 868 | struct tc35815_local *lp = netdev_priv(dev); |
1da177e4 LT |
869 | int i; |
870 | unsigned long fd_addr; | |
871 | ||
872 | if (!lp->fd_buf) { | |
eea221ce AN |
873 | BUG_ON(sizeof(struct FDesc) + |
874 | sizeof(struct BDesc) * RX_BUF_NUM + | |
875 | sizeof(struct FDesc) * RX_FD_NUM + | |
876 | sizeof(struct TxFD) * TX_FD_NUM > | |
877 | PAGE_SIZE * FD_PAGE_NUM); | |
1da177e4 | 878 | |
7f225b42 AN |
879 | lp->fd_buf = pci_alloc_consistent(lp->pci_dev, |
880 | PAGE_SIZE * FD_PAGE_NUM, | |
881 | &lp->fd_buf_dma); | |
882 | if (!lp->fd_buf) | |
1da177e4 | 883 | return -ENOMEM; |
eea221ce | 884 | for (i = 0; i < RX_BUF_NUM; i++) { |
eea221ce AN |
885 | lp->rx_skbs[i].skb = |
886 | alloc_rxbuf_skb(dev, lp->pci_dev, | |
887 | &lp->rx_skbs[i].skb_dma); | |
888 | if (!lp->rx_skbs[i].skb) { | |
889 | while (--i >= 0) { | |
890 | free_rxbuf_skb(lp->pci_dev, | |
891 | lp->rx_skbs[i].skb, | |
892 | lp->rx_skbs[i].skb_dma); | |
893 | lp->rx_skbs[i].skb = NULL; | |
894 | } | |
895 | pci_free_consistent(lp->pci_dev, | |
896 | PAGE_SIZE * FD_PAGE_NUM, | |
897 | lp->fd_buf, | |
898 | lp->fd_buf_dma); | |
899 | lp->fd_buf = NULL; | |
1da177e4 LT |
900 | return -ENOMEM; |
901 | } | |
1da177e4 | 902 | } |
eea221ce AN |
903 | printk(KERN_DEBUG "%s: FD buf %p DataBuf", |
904 | dev->name, lp->fd_buf); | |
eea221ce | 905 | printk("\n"); |
1da177e4 | 906 | } else { |
7f225b42 AN |
907 | for (i = 0; i < FD_PAGE_NUM; i++) |
908 | clear_page((void *)((unsigned long)lp->fd_buf + | |
909 | i * PAGE_SIZE)); | |
1da177e4 | 910 | } |
1da177e4 | 911 | fd_addr = (unsigned long)lp->fd_buf; |
1da177e4 LT |
912 | |
913 | /* Free Descriptors (for Receive) */ | |
914 | lp->rfd_base = (struct RxFD *)fd_addr; | |
915 | fd_addr += sizeof(struct RxFD) * RX_FD_NUM; | |
7f225b42 | 916 | for (i = 0; i < RX_FD_NUM; i++) |
1da177e4 | 917 | lp->rfd_base[i].fd.FDCtl = cpu_to_le32(FD_CownsFD); |
1da177e4 | 918 | lp->rfd_cur = lp->rfd_base; |
eea221ce | 919 | lp->rfd_limit = (struct RxFD *)fd_addr - (RX_FD_RESERVE + 1); |
1da177e4 LT |
920 | |
921 | /* Transmit Descriptors */ | |
922 | lp->tfd_base = (struct TxFD *)fd_addr; | |
923 | fd_addr += sizeof(struct TxFD) * TX_FD_NUM; | |
924 | for (i = 0; i < TX_FD_NUM; i++) { | |
eea221ce AN |
925 | lp->tfd_base[i].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[i+1])); |
926 | lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff); | |
1da177e4 LT |
927 | lp->tfd_base[i].fd.FDCtl = cpu_to_le32(0); |
928 | } | |
eea221ce | 929 | lp->tfd_base[TX_FD_NUM-1].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[0])); |
1da177e4 LT |
930 | lp->tfd_start = 0; |
931 | lp->tfd_end = 0; | |
932 | ||
933 | /* Buffer List (for Receive) */ | |
934 | lp->fbl_ptr = (struct FrFD *)fd_addr; | |
eea221ce AN |
935 | lp->fbl_ptr->fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, lp->fbl_ptr)); |
936 | lp->fbl_ptr->fd.FDCtl = cpu_to_le32(RX_BUF_NUM | FD_CownsFD); | |
eea221ce AN |
937 | /* |
938 | * move all allocated skbs to head of rx_skbs[] array. | |
939 | * fbl_count mighe not be RX_BUF_NUM if alloc_rxbuf_skb() in | |
940 | * tc35815_rx() had failed. | |
941 | */ | |
942 | lp->fbl_count = 0; | |
943 | for (i = 0; i < RX_BUF_NUM; i++) { | |
944 | if (lp->rx_skbs[i].skb) { | |
945 | if (i != lp->fbl_count) { | |
946 | lp->rx_skbs[lp->fbl_count].skb = | |
947 | lp->rx_skbs[i].skb; | |
948 | lp->rx_skbs[lp->fbl_count].skb_dma = | |
949 | lp->rx_skbs[i].skb_dma; | |
950 | } | |
951 | lp->fbl_count++; | |
952 | } | |
953 | } | |
eea221ce | 954 | for (i = 0; i < RX_BUF_NUM; i++) { |
eea221ce AN |
955 | if (i >= lp->fbl_count) { |
956 | lp->fbl_ptr->bd[i].BuffData = 0; | |
957 | lp->fbl_ptr->bd[i].BDCtl = 0; | |
958 | continue; | |
959 | } | |
960 | lp->fbl_ptr->bd[i].BuffData = | |
961 | cpu_to_le32(lp->rx_skbs[i].skb_dma); | |
1da177e4 LT |
962 | /* BDID is index of FrFD.bd[] */ |
963 | lp->fbl_ptr->bd[i].BDCtl = | |
eea221ce AN |
964 | cpu_to_le32(BD_CownsBD | (i << BD_RxBDID_SHIFT) | |
965 | RX_BUF_SIZE); | |
1da177e4 | 966 | } |
1da177e4 | 967 | |
eea221ce AN |
968 | printk(KERN_DEBUG "%s: TxFD %p RxFD %p FrFD %p\n", |
969 | dev->name, lp->tfd_base, lp->rfd_base, lp->fbl_ptr); | |
1da177e4 LT |
970 | return 0; |
971 | } | |
972 | ||
973 | static void | |
974 | tc35815_clear_queues(struct net_device *dev) | |
975 | { | |
ee79b7fb | 976 | struct tc35815_local *lp = netdev_priv(dev); |
1da177e4 LT |
977 | int i; |
978 | ||
979 | for (i = 0; i < TX_FD_NUM; i++) { | |
eea221ce AN |
980 | u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem); |
981 | struct sk_buff *skb = | |
982 | fdsystem != 0xffffffff ? | |
983 | lp->tx_skbs[fdsystem].skb : NULL; | |
984 | #ifdef DEBUG | |
985 | if (lp->tx_skbs[i].skb != skb) { | |
986 | printk("%s: tx_skbs mismatch(%d).\n", dev->name, i); | |
987 | panic_queues(dev); | |
988 | } | |
989 | #else | |
990 | BUG_ON(lp->tx_skbs[i].skb != skb); | |
991 | #endif | |
992 | if (skb) { | |
993 | pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE); | |
994 | lp->tx_skbs[i].skb = NULL; | |
995 | lp->tx_skbs[i].skb_dma = 0; | |
1da177e4 | 996 | dev_kfree_skb_any(skb); |
eea221ce AN |
997 | } |
998 | lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff); | |
1da177e4 LT |
999 | } |
1000 | ||
1001 | tc35815_init_queues(dev); | |
1002 | } | |
1003 | ||
1004 | static void | |
1005 | tc35815_free_queues(struct net_device *dev) | |
1006 | { | |
ee79b7fb | 1007 | struct tc35815_local *lp = netdev_priv(dev); |
1da177e4 LT |
1008 | int i; |
1009 | ||
1010 | if (lp->tfd_base) { | |
1011 | for (i = 0; i < TX_FD_NUM; i++) { | |
eea221ce AN |
1012 | u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem); |
1013 | struct sk_buff *skb = | |
1014 | fdsystem != 0xffffffff ? | |
1015 | lp->tx_skbs[fdsystem].skb : NULL; | |
1016 | #ifdef DEBUG | |
1017 | if (lp->tx_skbs[i].skb != skb) { | |
1018 | printk("%s: tx_skbs mismatch(%d).\n", dev->name, i); | |
1019 | panic_queues(dev); | |
1020 | } | |
1021 | #else | |
1022 | BUG_ON(lp->tx_skbs[i].skb != skb); | |
1023 | #endif | |
1024 | if (skb) { | |
eea221ce | 1025 | pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE); |
11faa7b0 | 1026 | dev_kfree_skb(skb); |
eea221ce AN |
1027 | lp->tx_skbs[i].skb = NULL; |
1028 | lp->tx_skbs[i].skb_dma = 0; | |
1029 | } | |
1030 | lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff); | |
1da177e4 LT |
1031 | } |
1032 | } | |
1033 | ||
1da177e4 LT |
1034 | lp->rfd_base = NULL; |
1035 | lp->rfd_limit = NULL; | |
1036 | lp->rfd_cur = NULL; | |
1037 | lp->fbl_ptr = NULL; | |
1038 | ||
eea221ce | 1039 | for (i = 0; i < RX_BUF_NUM; i++) { |
eea221ce AN |
1040 | if (lp->rx_skbs[i].skb) { |
1041 | free_rxbuf_skb(lp->pci_dev, lp->rx_skbs[i].skb, | |
1042 | lp->rx_skbs[i].skb_dma); | |
1043 | lp->rx_skbs[i].skb = NULL; | |
1044 | } | |
eea221ce AN |
1045 | } |
1046 | if (lp->fd_buf) { | |
1047 | pci_free_consistent(lp->pci_dev, PAGE_SIZE * FD_PAGE_NUM, | |
1048 | lp->fd_buf, lp->fd_buf_dma); | |
1049 | lp->fd_buf = NULL; | |
1da177e4 | 1050 | } |
1da177e4 LT |
1051 | } |
1052 | ||
1053 | static void | |
1054 | dump_txfd(struct TxFD *fd) | |
1055 | { | |
1056 | printk("TxFD(%p): %08x %08x %08x %08x\n", fd, | |
1057 | le32_to_cpu(fd->fd.FDNext), | |
1058 | le32_to_cpu(fd->fd.FDSystem), | |
1059 | le32_to_cpu(fd->fd.FDStat), | |
1060 | le32_to_cpu(fd->fd.FDCtl)); | |
1061 | printk("BD: "); | |
1062 | printk(" %08x %08x", | |
1063 | le32_to_cpu(fd->bd.BuffData), | |
1064 | le32_to_cpu(fd->bd.BDCtl)); | |
1065 | printk("\n"); | |
1066 | } | |
1067 | ||
1068 | static int | |
1069 | dump_rxfd(struct RxFD *fd) | |
1070 | { | |
1071 | int i, bd_count = (le32_to_cpu(fd->fd.FDCtl) & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT; | |
1072 | if (bd_count > 8) | |
1073 | bd_count = 8; | |
1074 | printk("RxFD(%p): %08x %08x %08x %08x\n", fd, | |
1075 | le32_to_cpu(fd->fd.FDNext), | |
1076 | le32_to_cpu(fd->fd.FDSystem), | |
1077 | le32_to_cpu(fd->fd.FDStat), | |
1078 | le32_to_cpu(fd->fd.FDCtl)); | |
1079 | if (le32_to_cpu(fd->fd.FDCtl) & FD_CownsFD) | |
7f225b42 | 1080 | return 0; |
1da177e4 LT |
1081 | printk("BD: "); |
1082 | for (i = 0; i < bd_count; i++) | |
1083 | printk(" %08x %08x", | |
1084 | le32_to_cpu(fd->bd[i].BuffData), | |
1085 | le32_to_cpu(fd->bd[i].BDCtl)); | |
1086 | printk("\n"); | |
1087 | return bd_count; | |
1088 | } | |
1089 | ||
a02b7b7a | 1090 | #ifdef DEBUG |
1da177e4 LT |
1091 | static void |
1092 | dump_frfd(struct FrFD *fd) | |
1093 | { | |
1094 | int i; | |
1095 | printk("FrFD(%p): %08x %08x %08x %08x\n", fd, | |
1096 | le32_to_cpu(fd->fd.FDNext), | |
1097 | le32_to_cpu(fd->fd.FDSystem), | |
1098 | le32_to_cpu(fd->fd.FDStat), | |
1099 | le32_to_cpu(fd->fd.FDCtl)); | |
1100 | printk("BD: "); | |
eea221ce | 1101 | for (i = 0; i < RX_BUF_NUM; i++) |
1da177e4 LT |
1102 | printk(" %08x %08x", |
1103 | le32_to_cpu(fd->bd[i].BuffData), | |
1104 | le32_to_cpu(fd->bd[i].BDCtl)); | |
1105 | printk("\n"); | |
1106 | } | |
1107 | ||
1108 | static void | |
1109 | panic_queues(struct net_device *dev) | |
1110 | { | |
ee79b7fb | 1111 | struct tc35815_local *lp = netdev_priv(dev); |
1da177e4 LT |
1112 | int i; |
1113 | ||
eea221ce | 1114 | printk("TxFD base %p, start %u, end %u\n", |
1da177e4 LT |
1115 | lp->tfd_base, lp->tfd_start, lp->tfd_end); |
1116 | printk("RxFD base %p limit %p cur %p\n", | |
1117 | lp->rfd_base, lp->rfd_limit, lp->rfd_cur); | |
1118 | printk("FrFD %p\n", lp->fbl_ptr); | |
1119 | for (i = 0; i < TX_FD_NUM; i++) | |
1120 | dump_txfd(&lp->tfd_base[i]); | |
1121 | for (i = 0; i < RX_FD_NUM; i++) { | |
1122 | int bd_count = dump_rxfd(&lp->rfd_base[i]); | |
1123 | i += (bd_count + 1) / 2; /* skip BDs */ | |
1124 | } | |
1125 | dump_frfd(lp->fbl_ptr); | |
1126 | panic("%s: Illegal queue state.", dev->name); | |
1127 | } | |
1da177e4 LT |
1128 | #endif |
1129 | ||
958eb80b | 1130 | static void print_eth(const u8 *add) |
1da177e4 | 1131 | { |
958eb80b | 1132 | printk(KERN_DEBUG "print_eth(%p)\n", add); |
e174961c JB |
1133 | printk(KERN_DEBUG " %pM => %pM : %02x%02x\n", |
1134 | add + 6, add, add[12], add[13]); | |
1da177e4 LT |
1135 | } |
1136 | ||
eea221ce AN |
1137 | static int tc35815_tx_full(struct net_device *dev) |
1138 | { | |
ee79b7fb | 1139 | struct tc35815_local *lp = netdev_priv(dev); |
807540ba | 1140 | return (lp->tfd_start + 1) % TX_FD_NUM == lp->tfd_end; |
eea221ce AN |
1141 | } |
1142 | ||
1143 | static void tc35815_restart(struct net_device *dev) | |
1144 | { | |
ee79b7fb | 1145 | struct tc35815_local *lp = netdev_priv(dev); |
01b0114e | 1146 | int ret; |
eea221ce | 1147 | |
a4fc549a PR |
1148 | if (dev->phydev) { |
1149 | ret = phy_init_hw(dev->phydev); | |
01b0114e FF |
1150 | if (ret) |
1151 | printk(KERN_ERR "%s: PHY init failed.\n", dev->name); | |
eea221ce AN |
1152 | } |
1153 | ||
dee7399c | 1154 | spin_lock_bh(&lp->rx_lock); |
c6686fe3 | 1155 | spin_lock_irq(&lp->lock); |
eea221ce AN |
1156 | tc35815_chip_reset(dev); |
1157 | tc35815_clear_queues(dev); | |
1158 | tc35815_chip_init(dev); | |
1159 | /* Reconfigure CAM again since tc35815_chip_init() initialize it. */ | |
1160 | tc35815_set_multicast_list(dev); | |
c6686fe3 | 1161 | spin_unlock_irq(&lp->lock); |
dee7399c | 1162 | spin_unlock_bh(&lp->rx_lock); |
c6686fe3 AN |
1163 | |
1164 | netif_wake_queue(dev); | |
eea221ce AN |
1165 | } |
1166 | ||
c6686fe3 AN |
1167 | static void tc35815_restart_work(struct work_struct *work) |
1168 | { | |
1169 | struct tc35815_local *lp = | |
1170 | container_of(work, struct tc35815_local, restart_work); | |
1171 | struct net_device *dev = lp->dev; | |
1172 | ||
1173 | tc35815_restart(dev); | |
1174 | } | |
1175 | ||
1176 | static void tc35815_schedule_restart(struct net_device *dev) | |
eea221ce | 1177 | { |
ee79b7fb | 1178 | struct tc35815_local *lp = netdev_priv(dev); |
eea221ce AN |
1179 | struct tc35815_regs __iomem *tr = |
1180 | (struct tc35815_regs __iomem *)dev->base_addr; | |
dee7399c | 1181 | unsigned long flags; |
eea221ce | 1182 | |
c6686fe3 | 1183 | /* disable interrupts */ |
dee7399c | 1184 | spin_lock_irqsave(&lp->lock, flags); |
c6686fe3 AN |
1185 | tc_writel(0, &tr->Int_En); |
1186 | tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl); | |
1187 | schedule_work(&lp->restart_work); | |
dee7399c | 1188 | spin_unlock_irqrestore(&lp->lock, flags); |
c6686fe3 AN |
1189 | } |
1190 | ||
0290bd29 | 1191 | static void tc35815_tx_timeout(struct net_device *dev, unsigned int txqueue) |
c6686fe3 AN |
1192 | { |
1193 | struct tc35815_regs __iomem *tr = | |
1194 | (struct tc35815_regs __iomem *)dev->base_addr; | |
1195 | ||
eea221ce AN |
1196 | printk(KERN_WARNING "%s: transmit timed out, status %#x\n", |
1197 | dev->name, tc_readl(&tr->Tx_Stat)); | |
1198 | ||
1199 | /* Try to restart the adaptor. */ | |
c6686fe3 | 1200 | tc35815_schedule_restart(dev); |
c201abd9 | 1201 | dev->stats.tx_errors++; |
eea221ce AN |
1202 | } |
1203 | ||
1da177e4 | 1204 | /* |
c6686fe3 | 1205 | * Open/initialize the controller. This is called (in the current kernel) |
1da177e4 LT |
1206 | * sometime after booting when the 'ifconfig' program is run. |
1207 | * | |
1208 | * This routine should set everything up anew at each open, even | |
1209 | * registers that "should" only need to be set once at boot, so that | |
1210 | * there is non-reboot way to recover if something goes wrong. | |
1211 | */ | |
1212 | static int | |
1213 | tc35815_open(struct net_device *dev) | |
1214 | { | |
ee79b7fb | 1215 | struct tc35815_local *lp = netdev_priv(dev); |
eea221ce | 1216 | |
1da177e4 LT |
1217 | /* |
1218 | * This is used if the interrupt line can turned off (shared). | |
1219 | * See 3c503.c for an example of selecting the IRQ at config-time. | |
1220 | */ | |
a0607fd3 | 1221 | if (request_irq(dev->irq, tc35815_interrupt, IRQF_SHARED, |
7f225b42 | 1222 | dev->name, dev)) |
1da177e4 | 1223 | return -EAGAIN; |
1da177e4 LT |
1224 | |
1225 | tc35815_chip_reset(dev); | |
1226 | ||
1227 | if (tc35815_init_queues(dev) != 0) { | |
1228 | free_irq(dev->irq, dev); | |
1229 | return -EAGAIN; | |
1230 | } | |
1231 | ||
bea3348e | 1232 | napi_enable(&lp->napi); |
bea3348e | 1233 | |
1da177e4 | 1234 | /* Reset the hardware here. Don't forget to set the station address. */ |
eea221ce | 1235 | spin_lock_irq(&lp->lock); |
1da177e4 | 1236 | tc35815_chip_init(dev); |
eea221ce | 1237 | spin_unlock_irq(&lp->lock); |
1da177e4 | 1238 | |
59524a37 | 1239 | netif_carrier_off(dev); |
c6686fe3 | 1240 | /* schedule a link state check */ |
a4fc549a | 1241 | phy_start(dev->phydev); |
c6686fe3 | 1242 | |
eea221ce AN |
1243 | /* We are now ready to accept transmit requeusts from |
1244 | * the queueing layer of the networking. | |
1245 | */ | |
1da177e4 LT |
1246 | netif_start_queue(dev); |
1247 | ||
1248 | return 0; | |
1249 | } | |
1250 | ||
eea221ce AN |
1251 | /* This will only be invoked if your driver is _not_ in XOFF state. |
1252 | * What this means is that you need not check it, and that this | |
1253 | * invariant will hold if you make sure that the netif_*_queue() | |
1254 | * calls are done at the proper times. | |
1255 | */ | |
bacade82 Y |
1256 | static netdev_tx_t |
1257 | tc35815_send_packet(struct sk_buff *skb, struct net_device *dev) | |
1da177e4 | 1258 | { |
ee79b7fb | 1259 | struct tc35815_local *lp = netdev_priv(dev); |
eea221ce | 1260 | struct TxFD *txfd; |
1da177e4 LT |
1261 | unsigned long flags; |
1262 | ||
eea221ce AN |
1263 | /* If some error occurs while trying to transmit this |
1264 | * packet, you should return '1' from this function. | |
1265 | * In such a case you _may not_ do anything to the | |
1266 | * SKB, it is still owned by the network queueing | |
1267 | * layer when an error is returned. This means you | |
1268 | * may not modify any SKB fields, you may not free | |
1269 | * the SKB, etc. | |
1270 | */ | |
1271 | ||
1272 | /* This is the most common case for modern hardware. | |
1273 | * The spinlock protects this code from the TX complete | |
1274 | * hardware interrupt handler. Queue flow control is | |
1275 | * thus managed under this lock as well. | |
1276 | */ | |
1da177e4 | 1277 | spin_lock_irqsave(&lp->lock, flags); |
1da177e4 | 1278 | |
eea221ce AN |
1279 | /* failsafe... (handle txdone now if half of FDs are used) */ |
1280 | if ((lp->tfd_start + TX_FD_NUM - lp->tfd_end) % TX_FD_NUM > | |
1281 | TX_FD_NUM / 2) | |
1282 | tc35815_txdone(dev); | |
1283 | ||
1284 | if (netif_msg_pktdata(lp)) | |
1285 | print_eth(skb->data); | |
1286 | #ifdef DEBUG | |
1287 | if (lp->tx_skbs[lp->tfd_start].skb) { | |
1288 | printk("%s: tx_skbs conflict.\n", dev->name); | |
1289 | panic_queues(dev); | |
1da177e4 | 1290 | } |
eea221ce AN |
1291 | #else |
1292 | BUG_ON(lp->tx_skbs[lp->tfd_start].skb); | |
1da177e4 | 1293 | #endif |
eea221ce AN |
1294 | lp->tx_skbs[lp->tfd_start].skb = skb; |
1295 | lp->tx_skbs[lp->tfd_start].skb_dma = pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE); | |
1296 | ||
1297 | /*add to ring */ | |
1298 | txfd = &lp->tfd_base[lp->tfd_start]; | |
1299 | txfd->bd.BuffData = cpu_to_le32(lp->tx_skbs[lp->tfd_start].skb_dma); | |
1300 | txfd->bd.BDCtl = cpu_to_le32(skb->len); | |
1301 | txfd->fd.FDSystem = cpu_to_le32(lp->tfd_start); | |
1302 | txfd->fd.FDCtl = cpu_to_le32(FD_CownsFD | (1 << FD_BDCnt_SHIFT)); | |
1303 | ||
1304 | if (lp->tfd_start == lp->tfd_end) { | |
1305 | struct tc35815_regs __iomem *tr = | |
1306 | (struct tc35815_regs __iomem *)dev->base_addr; | |
1307 | /* Start DMA Transmitter. */ | |
1308 | txfd->fd.FDNext |= cpu_to_le32(FD_Next_EOL); | |
eea221ce | 1309 | txfd->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx); |
eea221ce AN |
1310 | if (netif_msg_tx_queued(lp)) { |
1311 | printk("%s: starting TxFD.\n", dev->name); | |
1312 | dump_txfd(txfd); | |
1313 | } | |
1314 | tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr); | |
1315 | } else { | |
1316 | txfd->fd.FDNext &= cpu_to_le32(~FD_Next_EOL); | |
1317 | if (netif_msg_tx_queued(lp)) { | |
1318 | printk("%s: queueing TxFD.\n", dev->name); | |
1319 | dump_txfd(txfd); | |
1da177e4 | 1320 | } |
eea221ce AN |
1321 | } |
1322 | lp->tfd_start = (lp->tfd_start + 1) % TX_FD_NUM; | |
1da177e4 | 1323 | |
eea221ce AN |
1324 | /* If we just used up the very last entry in the |
1325 | * TX ring on this device, tell the queueing | |
1326 | * layer to send no more. | |
1327 | */ | |
1328 | if (tc35815_tx_full(dev)) { | |
1329 | if (netif_msg_tx_queued(lp)) | |
1330 | printk(KERN_WARNING "%s: TxFD Exhausted.\n", dev->name); | |
1331 | netif_stop_queue(dev); | |
1da177e4 LT |
1332 | } |
1333 | ||
eea221ce AN |
1334 | /* When the TX completion hw interrupt arrives, this |
1335 | * is when the transmit statistics are updated. | |
1336 | */ | |
1337 | ||
1338 | spin_unlock_irqrestore(&lp->lock, flags); | |
6ed10654 | 1339 | return NETDEV_TX_OK; |
1da177e4 LT |
1340 | } |
1341 | ||
1342 | #define FATAL_ERROR_INT \ | |
1343 | (Int_IntPCI | Int_DmParErr | Int_IntNRAbt) | |
eea221ce | 1344 | static void tc35815_fatal_error_interrupt(struct net_device *dev, u32 status) |
1da177e4 LT |
1345 | { |
1346 | static int count; | |
b103ec73 | 1347 | printk(KERN_WARNING "%s: Fatal Error Interrupt (%#x):", |
1da177e4 | 1348 | dev->name, status); |
1da177e4 LT |
1349 | if (status & Int_IntPCI) |
1350 | printk(" IntPCI"); | |
1351 | if (status & Int_DmParErr) | |
1352 | printk(" DmParErr"); | |
1353 | if (status & Int_IntNRAbt) | |
1354 | printk(" IntNRAbt"); | |
1355 | printk("\n"); | |
1356 | if (count++ > 100) | |
1357 | panic("%s: Too many fatal errors.", dev->name); | |
eea221ce | 1358 | printk(KERN_WARNING "%s: Resetting ...\n", dev->name); |
1da177e4 | 1359 | /* Try to restart the adaptor. */ |
c6686fe3 | 1360 | tc35815_schedule_restart(dev); |
eea221ce AN |
1361 | } |
1362 | ||
eea221ce | 1363 | static int tc35815_do_interrupt(struct net_device *dev, u32 status, int limit) |
eea221ce | 1364 | { |
ee79b7fb | 1365 | struct tc35815_local *lp = netdev_priv(dev); |
eea221ce AN |
1366 | int ret = -1; |
1367 | ||
1368 | /* Fatal errors... */ | |
1369 | if (status & FATAL_ERROR_INT) { | |
1370 | tc35815_fatal_error_interrupt(dev, status); | |
1371 | return 0; | |
1372 | } | |
1373 | /* recoverable errors */ | |
1374 | if (status & Int_IntFDAEx) { | |
db30f5ef AN |
1375 | if (netif_msg_rx_err(lp)) |
1376 | dev_warn(&dev->dev, | |
1377 | "Free Descriptor Area Exhausted (%#x).\n", | |
1378 | status); | |
c201abd9 | 1379 | dev->stats.rx_dropped++; |
eea221ce AN |
1380 | ret = 0; |
1381 | } | |
1382 | if (status & Int_IntBLEx) { | |
db30f5ef AN |
1383 | if (netif_msg_rx_err(lp)) |
1384 | dev_warn(&dev->dev, | |
1385 | "Buffer List Exhausted (%#x).\n", | |
1386 | status); | |
c201abd9 | 1387 | dev->stats.rx_dropped++; |
eea221ce AN |
1388 | ret = 0; |
1389 | } | |
1390 | if (status & Int_IntExBD) { | |
db30f5ef AN |
1391 | if (netif_msg_rx_err(lp)) |
1392 | dev_warn(&dev->dev, | |
1b283247 | 1393 | "Excessive Buffer Descriptors (%#x).\n", |
db30f5ef | 1394 | status); |
c201abd9 | 1395 | dev->stats.rx_length_errors++; |
eea221ce AN |
1396 | ret = 0; |
1397 | } | |
1398 | ||
1399 | /* normal notification */ | |
1400 | if (status & Int_IntMacRx) { | |
1401 | /* Got a packet(s). */ | |
eea221ce | 1402 | ret = tc35815_rx(dev, limit); |
eea221ce AN |
1403 | lp->lstats.rx_ints++; |
1404 | } | |
1405 | if (status & Int_IntMacTx) { | |
1406 | /* Transmit complete. */ | |
1407 | lp->lstats.tx_ints++; | |
dee7399c | 1408 | spin_lock_irq(&lp->lock); |
eea221ce | 1409 | tc35815_txdone(dev); |
dee7399c | 1410 | spin_unlock_irq(&lp->lock); |
02c5c8ec AN |
1411 | if (ret < 0) |
1412 | ret = 0; | |
eea221ce AN |
1413 | } |
1414 | return ret; | |
1da177e4 LT |
1415 | } |
1416 | ||
1417 | /* | |
1418 | * The typical workload of the driver: | |
eea221ce | 1419 | * Handle the network interface interrupts. |
1da177e4 | 1420 | */ |
7d12e780 | 1421 | static irqreturn_t tc35815_interrupt(int irq, void *dev_id) |
1da177e4 LT |
1422 | { |
1423 | struct net_device *dev = dev_id; | |
bea3348e | 1424 | struct tc35815_local *lp = netdev_priv(dev); |
eea221ce AN |
1425 | struct tc35815_regs __iomem *tr = |
1426 | (struct tc35815_regs __iomem *)dev->base_addr; | |
eea221ce AN |
1427 | u32 dmactl = tc_readl(&tr->DMA_Ctl); |
1428 | ||
1429 | if (!(dmactl & DMA_IntMask)) { | |
1430 | /* disable interrupts */ | |
1431 | tc_writel(dmactl | DMA_IntMask, &tr->DMA_Ctl); | |
288379f0 BH |
1432 | if (napi_schedule_prep(&lp->napi)) |
1433 | __napi_schedule(&lp->napi); | |
eea221ce AN |
1434 | else { |
1435 | printk(KERN_ERR "%s: interrupt taken in poll\n", | |
1436 | dev->name); | |
1437 | BUG(); | |
1da177e4 | 1438 | } |
eea221ce AN |
1439 | (void)tc_readl(&tr->Int_Src); /* flush */ |
1440 | return IRQ_HANDLED; | |
1441 | } | |
1442 | return IRQ_NONE; | |
eea221ce | 1443 | } |
1da177e4 | 1444 | |
eea221ce AN |
1445 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1446 | static void tc35815_poll_controller(struct net_device *dev) | |
1447 | { | |
1448 | disable_irq(dev->irq); | |
1449 | tc35815_interrupt(dev->irq, dev); | |
1450 | enable_irq(dev->irq); | |
1da177e4 | 1451 | } |
eea221ce | 1452 | #endif |
1da177e4 LT |
1453 | |
1454 | /* We have a good packet(s), get it/them out of the buffers. */ | |
eea221ce AN |
1455 | static int |
1456 | tc35815_rx(struct net_device *dev, int limit) | |
1da177e4 | 1457 | { |
ee79b7fb | 1458 | struct tc35815_local *lp = netdev_priv(dev); |
1da177e4 LT |
1459 | unsigned int fdctl; |
1460 | int i; | |
eea221ce | 1461 | int received = 0; |
1da177e4 LT |
1462 | |
1463 | while (!((fdctl = le32_to_cpu(lp->rfd_cur->fd.FDCtl)) & FD_CownsFD)) { | |
1464 | int status = le32_to_cpu(lp->rfd_cur->fd.FDStat); | |
1465 | int pkt_len = fdctl & FD_FDLength_MASK; | |
1da177e4 | 1466 | int bd_count = (fdctl & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT; |
eea221ce AN |
1467 | #ifdef DEBUG |
1468 | struct RxFD *next_rfd; | |
1469 | #endif | |
1470 | #if (RX_CTL_CMD & Rx_StripCRC) == 0 | |
82a9928d | 1471 | pkt_len -= ETH_FCS_LEN; |
eea221ce | 1472 | #endif |
1da177e4 | 1473 | |
eea221ce | 1474 | if (netif_msg_rx_status(lp)) |
1da177e4 LT |
1475 | dump_rxfd(lp->rfd_cur); |
1476 | if (status & Rx_Good) { | |
1da177e4 LT |
1477 | struct sk_buff *skb; |
1478 | unsigned char *data; | |
eea221ce | 1479 | int cur_bd; |
6aa20a22 | 1480 | |
eea221ce AN |
1481 | if (--limit < 0) |
1482 | break; | |
eea221ce AN |
1483 | BUG_ON(bd_count > 1); |
1484 | cur_bd = (le32_to_cpu(lp->rfd_cur->bd[0].BDCtl) | |
1485 | & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT; | |
1486 | #ifdef DEBUG | |
1487 | if (cur_bd >= RX_BUF_NUM) { | |
1488 | printk("%s: invalid BDID.\n", dev->name); | |
1489 | panic_queues(dev); | |
1490 | } | |
1491 | BUG_ON(lp->rx_skbs[cur_bd].skb_dma != | |
1492 | (le32_to_cpu(lp->rfd_cur->bd[0].BuffData) & ~3)); | |
1493 | if (!lp->rx_skbs[cur_bd].skb) { | |
1494 | printk("%s: NULL skb.\n", dev->name); | |
1495 | panic_queues(dev); | |
1496 | } | |
1497 | #else | |
1498 | BUG_ON(cur_bd >= RX_BUF_NUM); | |
1da177e4 | 1499 | #endif |
eea221ce AN |
1500 | skb = lp->rx_skbs[cur_bd].skb; |
1501 | prefetch(skb->data); | |
1502 | lp->rx_skbs[cur_bd].skb = NULL; | |
eea221ce AN |
1503 | pci_unmap_single(lp->pci_dev, |
1504 | lp->rx_skbs[cur_bd].skb_dma, | |
1505 | RX_BUF_SIZE, PCI_DMA_FROMDEVICE); | |
125b7e09 | 1506 | if (!HAVE_DMA_RXALIGN(lp) && NET_IP_ALIGN != 0) |
82a9928d AN |
1507 | memmove(skb->data, skb->data - NET_IP_ALIGN, |
1508 | pkt_len); | |
eea221ce | 1509 | data = skb_put(skb, pkt_len); |
eea221ce | 1510 | if (netif_msg_pktdata(lp)) |
1da177e4 LT |
1511 | print_eth(data); |
1512 | skb->protocol = eth_type_trans(skb, dev); | |
eea221ce AN |
1513 | netif_receive_skb(skb); |
1514 | received++; | |
c201abd9 AN |
1515 | dev->stats.rx_packets++; |
1516 | dev->stats.rx_bytes += pkt_len; | |
1da177e4 | 1517 | } else { |
c201abd9 | 1518 | dev->stats.rx_errors++; |
db30f5ef AN |
1519 | if (netif_msg_rx_err(lp)) |
1520 | dev_info(&dev->dev, "Rx error (status %x)\n", | |
1521 | status & Rx_Stat_Mask); | |
1da177e4 LT |
1522 | /* WORKAROUND: LongErr and CRCErr means Overflow. */ |
1523 | if ((status & Rx_LongErr) && (status & Rx_CRCErr)) { | |
1524 | status &= ~(Rx_LongErr|Rx_CRCErr); | |
1525 | status |= Rx_Over; | |
1526 | } | |
c201abd9 AN |
1527 | if (status & Rx_LongErr) |
1528 | dev->stats.rx_length_errors++; | |
1529 | if (status & Rx_Over) | |
1530 | dev->stats.rx_fifo_errors++; | |
1531 | if (status & Rx_CRCErr) | |
1532 | dev->stats.rx_crc_errors++; | |
1533 | if (status & Rx_Align) | |
1534 | dev->stats.rx_frame_errors++; | |
1da177e4 LT |
1535 | } |
1536 | ||
1537 | if (bd_count > 0) { | |
1538 | /* put Free Buffer back to controller */ | |
1539 | int bdctl = le32_to_cpu(lp->rfd_cur->bd[bd_count - 1].BDCtl); | |
1540 | unsigned char id = | |
1541 | (bdctl & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT; | |
eea221ce AN |
1542 | #ifdef DEBUG |
1543 | if (id >= RX_BUF_NUM) { | |
1da177e4 LT |
1544 | printk("%s: invalid BDID.\n", dev->name); |
1545 | panic_queues(dev); | |
1546 | } | |
eea221ce AN |
1547 | #else |
1548 | BUG_ON(id >= RX_BUF_NUM); | |
1549 | #endif | |
1da177e4 | 1550 | /* free old buffers */ |
ccc57aac | 1551 | lp->fbl_count--; |
eea221ce | 1552 | while (lp->fbl_count < RX_BUF_NUM) |
eea221ce | 1553 | { |
eea221ce AN |
1554 | unsigned char curid = |
1555 | (id + 1 + lp->fbl_count) % RX_BUF_NUM; | |
eea221ce AN |
1556 | struct BDesc *bd = &lp->fbl_ptr->bd[curid]; |
1557 | #ifdef DEBUG | |
1558 | bdctl = le32_to_cpu(bd->BDCtl); | |
1da177e4 LT |
1559 | if (bdctl & BD_CownsBD) { |
1560 | printk("%s: Freeing invalid BD.\n", | |
1561 | dev->name); | |
1562 | panic_queues(dev); | |
1563 | } | |
eea221ce | 1564 | #endif |
3a4fa0a2 | 1565 | /* pass BD to controller */ |
eea221ce AN |
1566 | if (!lp->rx_skbs[curid].skb) { |
1567 | lp->rx_skbs[curid].skb = | |
1568 | alloc_rxbuf_skb(dev, | |
1569 | lp->pci_dev, | |
1570 | &lp->rx_skbs[curid].skb_dma); | |
1571 | if (!lp->rx_skbs[curid].skb) | |
1572 | break; /* try on next reception */ | |
1573 | bd->BuffData = cpu_to_le32(lp->rx_skbs[curid].skb_dma); | |
1574 | } | |
1da177e4 | 1575 | /* Note: BDLength was modified by chip. */ |
eea221ce AN |
1576 | bd->BDCtl = cpu_to_le32(BD_CownsBD | |
1577 | (curid << BD_RxBDID_SHIFT) | | |
1578 | RX_BUF_SIZE); | |
eea221ce | 1579 | lp->fbl_count++; |
1da177e4 LT |
1580 | } |
1581 | } | |
1582 | ||
1583 | /* put RxFD back to controller */ | |
eea221ce AN |
1584 | #ifdef DEBUG |
1585 | next_rfd = fd_bus_to_virt(lp, | |
1586 | le32_to_cpu(lp->rfd_cur->fd.FDNext)); | |
1da177e4 LT |
1587 | if (next_rfd < lp->rfd_base || next_rfd > lp->rfd_limit) { |
1588 | printk("%s: RxFD FDNext invalid.\n", dev->name); | |
1589 | panic_queues(dev); | |
1590 | } | |
eea221ce | 1591 | #endif |
1da177e4 | 1592 | for (i = 0; i < (bd_count + 1) / 2 + 1; i++) { |
3a4fa0a2 | 1593 | /* pass FD to controller */ |
eea221ce AN |
1594 | #ifdef DEBUG |
1595 | lp->rfd_cur->fd.FDNext = cpu_to_le32(0xdeaddead); | |
1596 | #else | |
1597 | lp->rfd_cur->fd.FDNext = cpu_to_le32(FD_Next_EOL); | |
1598 | #endif | |
1da177e4 LT |
1599 | lp->rfd_cur->fd.FDCtl = cpu_to_le32(FD_CownsFD); |
1600 | lp->rfd_cur++; | |
1da177e4 | 1601 | } |
eea221ce AN |
1602 | if (lp->rfd_cur > lp->rfd_limit) |
1603 | lp->rfd_cur = lp->rfd_base; | |
1604 | #ifdef DEBUG | |
1605 | if (lp->rfd_cur != next_rfd) | |
1606 | printk("rfd_cur = %p, next_rfd %p\n", | |
1607 | lp->rfd_cur, next_rfd); | |
1608 | #endif | |
1da177e4 LT |
1609 | } |
1610 | ||
eea221ce | 1611 | return received; |
1da177e4 LT |
1612 | } |
1613 | ||
bea3348e | 1614 | static int tc35815_poll(struct napi_struct *napi, int budget) |
eea221ce | 1615 | { |
bea3348e SH |
1616 | struct tc35815_local *lp = container_of(napi, struct tc35815_local, napi); |
1617 | struct net_device *dev = lp->dev; | |
eea221ce AN |
1618 | struct tc35815_regs __iomem *tr = |
1619 | (struct tc35815_regs __iomem *)dev->base_addr; | |
eea221ce AN |
1620 | int received = 0, handled; |
1621 | u32 status; | |
1622 | ||
176f792f EB |
1623 | if (budget <= 0) |
1624 | return received; | |
1625 | ||
dee7399c | 1626 | spin_lock(&lp->rx_lock); |
eea221ce AN |
1627 | status = tc_readl(&tr->Int_Src); |
1628 | do { | |
db30f5ef AN |
1629 | /* BLEx, FDAEx will be cleared later */ |
1630 | tc_writel(status & ~(Int_BLEx | Int_FDAEx), | |
1631 | &tr->Int_Src); /* write to clear */ | |
eea221ce | 1632 | |
a2c465db | 1633 | handled = tc35815_do_interrupt(dev, status, budget - received); |
db30f5ef AN |
1634 | if (status & (Int_BLEx | Int_FDAEx)) |
1635 | tc_writel(status & (Int_BLEx | Int_FDAEx), | |
1636 | &tr->Int_Src); | |
eea221ce AN |
1637 | if (handled >= 0) { |
1638 | received += handled; | |
bea3348e | 1639 | if (received >= budget) |
eea221ce AN |
1640 | break; |
1641 | } | |
1642 | status = tc_readl(&tr->Int_Src); | |
1643 | } while (status); | |
dee7399c | 1644 | spin_unlock(&lp->rx_lock); |
eea221ce | 1645 | |
bea3348e | 1646 | if (received < budget) { |
6ad20165 | 1647 | napi_complete_done(napi, received); |
bea3348e SH |
1648 | /* enable interrupts */ |
1649 | tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl); | |
1650 | } | |
1651 | return received; | |
eea221ce | 1652 | } |
eea221ce | 1653 | |
1da177e4 | 1654 | #define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_NCarr|Tx_LateColl|Tx_TxPar|Tx_SQErr) |
1da177e4 LT |
1655 | |
1656 | static void | |
1657 | tc35815_check_tx_stat(struct net_device *dev, int status) | |
1658 | { | |
ee79b7fb | 1659 | struct tc35815_local *lp = netdev_priv(dev); |
1da177e4 LT |
1660 | const char *msg = NULL; |
1661 | ||
1662 | /* count collisions */ | |
1663 | if (status & Tx_ExColl) | |
c201abd9 | 1664 | dev->stats.collisions += 16; |
1da177e4 | 1665 | if (status & Tx_TxColl_MASK) |
c201abd9 | 1666 | dev->stats.collisions += status & Tx_TxColl_MASK; |
1da177e4 | 1667 | |
eea221ce | 1668 | /* TX4939 does not have NCarr */ |
c6686fe3 | 1669 | if (lp->chiptype == TC35815_TX4939) |
eea221ce | 1670 | status &= ~Tx_NCarr; |
1da177e4 | 1671 | /* WORKAROUND: ignore LostCrS in full duplex operation */ |
c6686fe3 | 1672 | if (!lp->link || lp->duplex == DUPLEX_FULL) |
1da177e4 LT |
1673 | status &= ~Tx_NCarr; |
1674 | ||
1675 | if (!(status & TX_STA_ERR)) { | |
1676 | /* no error. */ | |
c201abd9 | 1677 | dev->stats.tx_packets++; |
1da177e4 LT |
1678 | return; |
1679 | } | |
1680 | ||
c201abd9 | 1681 | dev->stats.tx_errors++; |
1da177e4 | 1682 | if (status & Tx_ExColl) { |
c201abd9 | 1683 | dev->stats.tx_aborted_errors++; |
1da177e4 LT |
1684 | msg = "Excessive Collision."; |
1685 | } | |
1686 | if (status & Tx_Under) { | |
c201abd9 | 1687 | dev->stats.tx_fifo_errors++; |
1da177e4 | 1688 | msg = "Tx FIFO Underrun."; |
eea221ce AN |
1689 | if (lp->lstats.tx_underrun < TX_THRESHOLD_KEEP_LIMIT) { |
1690 | lp->lstats.tx_underrun++; | |
1691 | if (lp->lstats.tx_underrun >= TX_THRESHOLD_KEEP_LIMIT) { | |
1692 | struct tc35815_regs __iomem *tr = | |
1693 | (struct tc35815_regs __iomem *)dev->base_addr; | |
1694 | tc_writel(TX_THRESHOLD_MAX, &tr->TxThrsh); | |
1695 | msg = "Tx FIFO Underrun.Change Tx threshold to max."; | |
1696 | } | |
1697 | } | |
1da177e4 LT |
1698 | } |
1699 | if (status & Tx_Defer) { | |
c201abd9 | 1700 | dev->stats.tx_fifo_errors++; |
1da177e4 LT |
1701 | msg = "Excessive Deferral."; |
1702 | } | |
1da177e4 | 1703 | if (status & Tx_NCarr) { |
c201abd9 | 1704 | dev->stats.tx_carrier_errors++; |
1da177e4 LT |
1705 | msg = "Lost Carrier Sense."; |
1706 | } | |
1da177e4 | 1707 | if (status & Tx_LateColl) { |
c201abd9 | 1708 | dev->stats.tx_aborted_errors++; |
1da177e4 LT |
1709 | msg = "Late Collision."; |
1710 | } | |
1711 | if (status & Tx_TxPar) { | |
c201abd9 | 1712 | dev->stats.tx_fifo_errors++; |
1da177e4 LT |
1713 | msg = "Transmit Parity Error."; |
1714 | } | |
1715 | if (status & Tx_SQErr) { | |
c201abd9 | 1716 | dev->stats.tx_heartbeat_errors++; |
1da177e4 LT |
1717 | msg = "Signal Quality Error."; |
1718 | } | |
eea221ce | 1719 | if (msg && netif_msg_tx_err(lp)) |
1da177e4 LT |
1720 | printk(KERN_WARNING "%s: %s (%#x)\n", dev->name, msg, status); |
1721 | } | |
1722 | ||
eea221ce AN |
1723 | /* This handles TX complete events posted by the device |
1724 | * via interrupts. | |
1725 | */ | |
1da177e4 LT |
1726 | static void |
1727 | tc35815_txdone(struct net_device *dev) | |
1728 | { | |
ee79b7fb | 1729 | struct tc35815_local *lp = netdev_priv(dev); |
1da177e4 LT |
1730 | struct TxFD *txfd; |
1731 | unsigned int fdctl; | |
1da177e4 LT |
1732 | |
1733 | txfd = &lp->tfd_base[lp->tfd_end]; | |
1734 | while (lp->tfd_start != lp->tfd_end && | |
1735 | !((fdctl = le32_to_cpu(txfd->fd.FDCtl)) & FD_CownsFD)) { | |
1736 | int status = le32_to_cpu(txfd->fd.FDStat); | |
1737 | struct sk_buff *skb; | |
1738 | unsigned long fdnext = le32_to_cpu(txfd->fd.FDNext); | |
eea221ce | 1739 | u32 fdsystem = le32_to_cpu(txfd->fd.FDSystem); |
1da177e4 | 1740 | |
eea221ce | 1741 | if (netif_msg_tx_done(lp)) { |
1da177e4 LT |
1742 | printk("%s: complete TxFD.\n", dev->name); |
1743 | dump_txfd(txfd); | |
1744 | } | |
1745 | tc35815_check_tx_stat(dev, status); | |
1746 | ||
eea221ce AN |
1747 | skb = fdsystem != 0xffffffff ? |
1748 | lp->tx_skbs[fdsystem].skb : NULL; | |
1749 | #ifdef DEBUG | |
1750 | if (lp->tx_skbs[lp->tfd_end].skb != skb) { | |
1751 | printk("%s: tx_skbs mismatch.\n", dev->name); | |
1752 | panic_queues(dev); | |
1753 | } | |
1754 | #else | |
1755 | BUG_ON(lp->tx_skbs[lp->tfd_end].skb != skb); | |
1756 | #endif | |
1da177e4 | 1757 | if (skb) { |
c201abd9 | 1758 | dev->stats.tx_bytes += skb->len; |
eea221ce AN |
1759 | pci_unmap_single(lp->pci_dev, lp->tx_skbs[lp->tfd_end].skb_dma, skb->len, PCI_DMA_TODEVICE); |
1760 | lp->tx_skbs[lp->tfd_end].skb = NULL; | |
1761 | lp->tx_skbs[lp->tfd_end].skb_dma = 0; | |
1da177e4 LT |
1762 | dev_kfree_skb_any(skb); |
1763 | } | |
eea221ce | 1764 | txfd->fd.FDSystem = cpu_to_le32(0xffffffff); |
1da177e4 | 1765 | |
1da177e4 LT |
1766 | lp->tfd_end = (lp->tfd_end + 1) % TX_FD_NUM; |
1767 | txfd = &lp->tfd_base[lp->tfd_end]; | |
eea221ce AN |
1768 | #ifdef DEBUG |
1769 | if ((fdnext & ~FD_Next_EOL) != fd_virt_to_bus(lp, txfd)) { | |
1da177e4 LT |
1770 | printk("%s: TxFD FDNext invalid.\n", dev->name); |
1771 | panic_queues(dev); | |
1772 | } | |
eea221ce | 1773 | #endif |
1da177e4 LT |
1774 | if (fdnext & FD_Next_EOL) { |
1775 | /* DMA Transmitter has been stopping... */ | |
1776 | if (lp->tfd_end != lp->tfd_start) { | |
eea221ce AN |
1777 | struct tc35815_regs __iomem *tr = |
1778 | (struct tc35815_regs __iomem *)dev->base_addr; | |
1da177e4 | 1779 | int head = (lp->tfd_start + TX_FD_NUM - 1) % TX_FD_NUM; |
7f225b42 | 1780 | struct TxFD *txhead = &lp->tfd_base[head]; |
1da177e4 LT |
1781 | int qlen = (lp->tfd_start + TX_FD_NUM |
1782 | - lp->tfd_end) % TX_FD_NUM; | |
1783 | ||
eea221ce | 1784 | #ifdef DEBUG |
1da177e4 LT |
1785 | if (!(le32_to_cpu(txfd->fd.FDCtl) & FD_CownsFD)) { |
1786 | printk("%s: TxFD FDCtl invalid.\n", dev->name); | |
1787 | panic_queues(dev); | |
1788 | } | |
eea221ce | 1789 | #endif |
1da177e4 LT |
1790 | /* log max queue length */ |
1791 | if (lp->lstats.max_tx_qlen < qlen) | |
1792 | lp->lstats.max_tx_qlen = qlen; | |
1793 | ||
1794 | ||
1795 | /* start DMA Transmitter again */ | |
1796 | txhead->fd.FDNext |= cpu_to_le32(FD_Next_EOL); | |
1da177e4 | 1797 | txhead->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx); |
eea221ce | 1798 | if (netif_msg_tx_queued(lp)) { |
1da177e4 LT |
1799 | printk("%s: start TxFD on queue.\n", |
1800 | dev->name); | |
1801 | dump_txfd(txfd); | |
1802 | } | |
eea221ce | 1803 | tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr); |
1da177e4 LT |
1804 | } |
1805 | break; | |
1806 | } | |
1807 | } | |
1808 | ||
eea221ce AN |
1809 | /* If we had stopped the queue due to a "tx full" |
1810 | * condition, and space has now been made available, | |
1811 | * wake up the queue. | |
1812 | */ | |
7f225b42 | 1813 | if (netif_queue_stopped(dev) && !tc35815_tx_full(dev)) |
eea221ce | 1814 | netif_wake_queue(dev); |
1da177e4 LT |
1815 | } |
1816 | ||
1817 | /* The inverse routine to tc35815_open(). */ | |
1818 | static int | |
1819 | tc35815_close(struct net_device *dev) | |
1820 | { | |
ee79b7fb | 1821 | struct tc35815_local *lp = netdev_priv(dev); |
bea3348e | 1822 | |
1da177e4 | 1823 | netif_stop_queue(dev); |
bea3348e | 1824 | napi_disable(&lp->napi); |
a4fc549a PR |
1825 | if (dev->phydev) |
1826 | phy_stop(dev->phydev); | |
c6686fe3 | 1827 | cancel_work_sync(&lp->restart_work); |
1da177e4 LT |
1828 | |
1829 | /* Flush the Tx and disable Rx here. */ | |
1da177e4 LT |
1830 | tc35815_chip_reset(dev); |
1831 | free_irq(dev->irq, dev); | |
1832 | ||
1833 | tc35815_free_queues(dev); | |
1834 | ||
1835 | return 0; | |
eea221ce | 1836 | |
1da177e4 LT |
1837 | } |
1838 | ||
1839 | /* | |
1840 | * Get the current statistics. | |
1841 | * This may be called with the card open or closed. | |
1842 | */ | |
1843 | static struct net_device_stats *tc35815_get_stats(struct net_device *dev) | |
1844 | { | |
eea221ce AN |
1845 | struct tc35815_regs __iomem *tr = |
1846 | (struct tc35815_regs __iomem *)dev->base_addr; | |
c201abd9 | 1847 | if (netif_running(dev)) |
1da177e4 | 1848 | /* Update the statistics from the device registers. */ |
7bb82e83 | 1849 | dev->stats.rx_missed_errors += tc_readl(&tr->Miss_Cnt); |
1da177e4 | 1850 | |
c201abd9 | 1851 | return &dev->stats; |
1da177e4 LT |
1852 | } |
1853 | ||
eea221ce | 1854 | static void tc35815_set_cam_entry(struct net_device *dev, int index, unsigned char *addr) |
1da177e4 | 1855 | { |
ee79b7fb | 1856 | struct tc35815_local *lp = netdev_priv(dev); |
eea221ce AN |
1857 | struct tc35815_regs __iomem *tr = |
1858 | (struct tc35815_regs __iomem *)dev->base_addr; | |
1da177e4 | 1859 | int cam_index = index * 6; |
eea221ce AN |
1860 | u32 cam_data; |
1861 | u32 saved_addr; | |
958eb80b | 1862 | |
1da177e4 LT |
1863 | saved_addr = tc_readl(&tr->CAM_Adr); |
1864 | ||
958eb80b | 1865 | if (netif_msg_hw(lp)) |
e174961c JB |
1866 | printk(KERN_DEBUG "%s: CAM %d: %pM\n", |
1867 | dev->name, index, addr); | |
1da177e4 LT |
1868 | if (index & 1) { |
1869 | /* read modify write */ | |
1870 | tc_writel(cam_index - 2, &tr->CAM_Adr); | |
1871 | cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000; | |
1872 | cam_data |= addr[0] << 8 | addr[1]; | |
1873 | tc_writel(cam_data, &tr->CAM_Data); | |
1874 | /* write whole word */ | |
1875 | tc_writel(cam_index + 2, &tr->CAM_Adr); | |
1876 | cam_data = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5]; | |
1877 | tc_writel(cam_data, &tr->CAM_Data); | |
1878 | } else { | |
1879 | /* write whole word */ | |
1880 | tc_writel(cam_index, &tr->CAM_Adr); | |
1881 | cam_data = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; | |
1882 | tc_writel(cam_data, &tr->CAM_Data); | |
1883 | /* read modify write */ | |
1884 | tc_writel(cam_index + 4, &tr->CAM_Adr); | |
1885 | cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff; | |
1886 | cam_data |= addr[4] << 24 | (addr[5] << 16); | |
1887 | tc_writel(cam_data, &tr->CAM_Data); | |
1888 | } | |
1889 | ||
1da177e4 LT |
1890 | tc_writel(saved_addr, &tr->CAM_Adr); |
1891 | } | |
1892 | ||
1893 | ||
1894 | /* | |
1895 | * Set or clear the multicast filter for this adaptor. | |
1896 | * num_addrs == -1 Promiscuous mode, receive all packets | |
1897 | * num_addrs == 0 Normal mode, clear multicast list | |
1898 | * num_addrs > 0 Multicast mode, receive normal and MC packets, | |
1899 | * and do best-effort filtering. | |
1900 | */ | |
1901 | static void | |
1902 | tc35815_set_multicast_list(struct net_device *dev) | |
1903 | { | |
eea221ce AN |
1904 | struct tc35815_regs __iomem *tr = |
1905 | (struct tc35815_regs __iomem *)dev->base_addr; | |
1da177e4 | 1906 | |
7f225b42 | 1907 | if (dev->flags & IFF_PROMISC) { |
eea221ce AN |
1908 | /* With some (all?) 100MHalf HUB, controller will hang |
1909 | * if we enabled promiscuous mode before linkup... */ | |
ee79b7fb | 1910 | struct tc35815_local *lp = netdev_priv(dev); |
c6686fe3 AN |
1911 | |
1912 | if (!lp->link) | |
eea221ce | 1913 | return; |
1da177e4 LT |
1914 | /* Enable promiscuous mode */ |
1915 | tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl); | |
7f225b42 | 1916 | } else if ((dev->flags & IFF_ALLMULTI) || |
4cd24eaf | 1917 | netdev_mc_count(dev) > CAM_ENTRY_MAX - 3) { |
1da177e4 LT |
1918 | /* CAM 0, 1, 20 are reserved. */ |
1919 | /* Disable promiscuous mode, use normal mode. */ | |
1920 | tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl); | |
4cd24eaf | 1921 | } else if (!netdev_mc_empty(dev)) { |
22bedad3 | 1922 | struct netdev_hw_addr *ha; |
1da177e4 LT |
1923 | int i; |
1924 | int ena_bits = CAM_Ena_Bit(CAM_ENTRY_SOURCE); | |
1925 | ||
1926 | tc_writel(0, &tr->CAM_Ctl); | |
1927 | /* Walk the address list, and load the filter */ | |
567ec874 | 1928 | i = 0; |
22bedad3 | 1929 | netdev_for_each_mc_addr(ha, dev) { |
1da177e4 | 1930 | /* entry 0,1 is reserved. */ |
22bedad3 | 1931 | tc35815_set_cam_entry(dev, i + 2, ha->addr); |
1da177e4 | 1932 | ena_bits |= CAM_Ena_Bit(i + 2); |
567ec874 | 1933 | i++; |
1da177e4 LT |
1934 | } |
1935 | tc_writel(ena_bits, &tr->CAM_Ena); | |
1936 | tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl); | |
7f225b42 | 1937 | } else { |
1da177e4 LT |
1938 | tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena); |
1939 | tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl); | |
1940 | } | |
1941 | } | |
1942 | ||
eea221ce | 1943 | static void tc35815_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
1da177e4 | 1944 | { |
ee79b7fb | 1945 | struct tc35815_local *lp = netdev_priv(dev); |
7826d43f JP |
1946 | |
1947 | strlcpy(info->driver, MODNAME, sizeof(info->driver)); | |
1948 | strlcpy(info->version, DRV_VERSION, sizeof(info->version)); | |
1949 | strlcpy(info->bus_info, pci_name(lp->pci_dev), sizeof(info->bus_info)); | |
eea221ce | 1950 | } |
6aa20a22 | 1951 | |
eea221ce AN |
1952 | static u32 tc35815_get_msglevel(struct net_device *dev) |
1953 | { | |
ee79b7fb | 1954 | struct tc35815_local *lp = netdev_priv(dev); |
eea221ce AN |
1955 | return lp->msg_enable; |
1956 | } | |
1957 | ||
1958 | static void tc35815_set_msglevel(struct net_device *dev, u32 datum) | |
1959 | { | |
ee79b7fb | 1960 | struct tc35815_local *lp = netdev_priv(dev); |
eea221ce AN |
1961 | lp->msg_enable = datum; |
1962 | } | |
1963 | ||
b9f2c044 | 1964 | static int tc35815_get_sset_count(struct net_device *dev, int sset) |
eea221ce | 1965 | { |
ee79b7fb | 1966 | struct tc35815_local *lp = netdev_priv(dev); |
b9f2c044 JG |
1967 | |
1968 | switch (sset) { | |
1969 | case ETH_SS_STATS: | |
1970 | return sizeof(lp->lstats) / sizeof(int); | |
1971 | default: | |
1972 | return -EOPNOTSUPP; | |
1973 | } | |
eea221ce | 1974 | } |
1da177e4 | 1975 | |
eea221ce AN |
1976 | static void tc35815_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data) |
1977 | { | |
ee79b7fb | 1978 | struct tc35815_local *lp = netdev_priv(dev); |
eea221ce AN |
1979 | data[0] = lp->lstats.max_tx_qlen; |
1980 | data[1] = lp->lstats.tx_ints; | |
1981 | data[2] = lp->lstats.rx_ints; | |
1982 | data[3] = lp->lstats.tx_underrun; | |
1983 | } | |
1984 | ||
1985 | static struct { | |
1986 | const char str[ETH_GSTRING_LEN]; | |
1987 | } ethtool_stats_keys[] = { | |
1988 | { "max_tx_qlen" }, | |
1989 | { "tx_ints" }, | |
1990 | { "rx_ints" }, | |
1991 | { "tx_underrun" }, | |
1992 | }; | |
1993 | ||
1994 | static void tc35815_get_strings(struct net_device *dev, u32 stringset, u8 *data) | |
1995 | { | |
1996 | memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys)); | |
1997 | } | |
1998 | ||
1999 | static const struct ethtool_ops tc35815_ethtool_ops = { | |
2000 | .get_drvinfo = tc35815_get_drvinfo, | |
c6686fe3 | 2001 | .get_link = ethtool_op_get_link, |
eea221ce AN |
2002 | .get_msglevel = tc35815_get_msglevel, |
2003 | .set_msglevel = tc35815_set_msglevel, | |
2004 | .get_strings = tc35815_get_strings, | |
b9f2c044 | 2005 | .get_sset_count = tc35815_get_sset_count, |
eea221ce | 2006 | .get_ethtool_stats = tc35815_get_ethtool_stats, |
3a11d9ef PR |
2007 | .get_link_ksettings = phy_ethtool_get_link_ksettings, |
2008 | .set_link_ksettings = phy_ethtool_set_link_ksettings, | |
eea221ce AN |
2009 | }; |
2010 | ||
eea221ce AN |
2011 | static void tc35815_chip_reset(struct net_device *dev) |
2012 | { | |
2013 | struct tc35815_regs __iomem *tr = | |
2014 | (struct tc35815_regs __iomem *)dev->base_addr; | |
2015 | int i; | |
1da177e4 LT |
2016 | /* reset the controller */ |
2017 | tc_writel(MAC_Reset, &tr->MAC_Ctl); | |
eea221ce AN |
2018 | udelay(4); /* 3200ns */ |
2019 | i = 0; | |
2020 | while (tc_readl(&tr->MAC_Ctl) & MAC_Reset) { | |
2021 | if (i++ > 100) { | |
2022 | printk(KERN_ERR "%s: MAC reset failed.\n", dev->name); | |
2023 | break; | |
2024 | } | |
2025 | mdelay(1); | |
2026 | } | |
1da177e4 LT |
2027 | tc_writel(0, &tr->MAC_Ctl); |
2028 | ||
2029 | /* initialize registers to default value */ | |
2030 | tc_writel(0, &tr->DMA_Ctl); | |
2031 | tc_writel(0, &tr->TxThrsh); | |
2032 | tc_writel(0, &tr->TxPollCtr); | |
2033 | tc_writel(0, &tr->RxFragSize); | |
2034 | tc_writel(0, &tr->Int_En); | |
2035 | tc_writel(0, &tr->FDA_Bas); | |
2036 | tc_writel(0, &tr->FDA_Lim); | |
2037 | tc_writel(0xffffffff, &tr->Int_Src); /* Write 1 to clear */ | |
2038 | tc_writel(0, &tr->CAM_Ctl); | |
2039 | tc_writel(0, &tr->Tx_Ctl); | |
2040 | tc_writel(0, &tr->Rx_Ctl); | |
2041 | tc_writel(0, &tr->CAM_Ena); | |
2042 | (void)tc_readl(&tr->Miss_Cnt); /* Read to clear */ | |
2043 | ||
eea221ce AN |
2044 | /* initialize internal SRAM */ |
2045 | tc_writel(DMA_TestMode, &tr->DMA_Ctl); | |
2046 | for (i = 0; i < 0x1000; i += 4) { | |
2047 | tc_writel(i, &tr->CAM_Adr); | |
2048 | tc_writel(0, &tr->CAM_Data); | |
2049 | } | |
2050 | tc_writel(0, &tr->DMA_Ctl); | |
1da177e4 LT |
2051 | } |
2052 | ||
2053 | static void tc35815_chip_init(struct net_device *dev) | |
2054 | { | |
ee79b7fb | 2055 | struct tc35815_local *lp = netdev_priv(dev); |
eea221ce AN |
2056 | struct tc35815_regs __iomem *tr = |
2057 | (struct tc35815_regs __iomem *)dev->base_addr; | |
1da177e4 LT |
2058 | unsigned long txctl = TX_CTL_CMD; |
2059 | ||
1da177e4 | 2060 | /* load station address to CAM */ |
eea221ce | 2061 | tc35815_set_cam_entry(dev, CAM_ENTRY_SOURCE, dev->dev_addr); |
1da177e4 LT |
2062 | |
2063 | /* Enable CAM (broadcast and unicast) */ | |
2064 | tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena); | |
2065 | tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl); | |
2066 | ||
eea221ce AN |
2067 | /* Use DMA_RxAlign_2 to make IP header 4-byte aligned. */ |
2068 | if (HAVE_DMA_RXALIGN(lp)) | |
2069 | tc_writel(DMA_BURST_SIZE | DMA_RxAlign_2, &tr->DMA_Ctl); | |
2070 | else | |
2071 | tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl); | |
1da177e4 LT |
2072 | tc_writel(0, &tr->TxPollCtr); /* Batch mode */ |
2073 | tc_writel(TX_THRESHOLD, &tr->TxThrsh); | |
2074 | tc_writel(INT_EN_CMD, &tr->Int_En); | |
2075 | ||
2076 | /* set queues */ | |
eea221ce | 2077 | tc_writel(fd_virt_to_bus(lp, lp->rfd_base), &tr->FDA_Bas); |
1da177e4 LT |
2078 | tc_writel((unsigned long)lp->rfd_limit - (unsigned long)lp->rfd_base, |
2079 | &tr->FDA_Lim); | |
2080 | /* | |
2081 | * Activation method: | |
eea221ce | 2082 | * First, enable the MAC Transmitter and the DMA Receive circuits. |
1da177e4 LT |
2083 | * Then enable the DMA Transmitter and the MAC Receive circuits. |
2084 | */ | |
eea221ce | 2085 | tc_writel(fd_virt_to_bus(lp, lp->fbl_ptr), &tr->BLFrmPtr); /* start DMA receiver */ |
1da177e4 | 2086 | tc_writel(RX_CTL_CMD, &tr->Rx_Ctl); /* start MAC receiver */ |
eea221ce | 2087 | |
1da177e4 | 2088 | /* start MAC transmitter */ |
eea221ce | 2089 | /* TX4939 does not have EnLCarr */ |
c6686fe3 | 2090 | if (lp->chiptype == TC35815_TX4939) |
eea221ce | 2091 | txctl &= ~Tx_EnLCarr; |
1da177e4 | 2092 | /* WORKAROUND: ignore LostCrS in full duplex operation */ |
a4fc549a | 2093 | if (!dev->phydev || !lp->link || lp->duplex == DUPLEX_FULL) |
eea221ce | 2094 | txctl &= ~Tx_EnLCarr; |
1da177e4 | 2095 | tc_writel(txctl, &tr->Tx_Ctl); |
eea221ce AN |
2096 | } |
2097 | ||
2098 | #ifdef CONFIG_PM | |
2099 | static int tc35815_suspend(struct pci_dev *pdev, pm_message_t state) | |
2100 | { | |
2101 | struct net_device *dev = pci_get_drvdata(pdev); | |
ee79b7fb | 2102 | struct tc35815_local *lp = netdev_priv(dev); |
eea221ce AN |
2103 | unsigned long flags; |
2104 | ||
2105 | pci_save_state(pdev); | |
2106 | if (!netif_running(dev)) | |
2107 | return 0; | |
2108 | netif_device_detach(dev); | |
a4fc549a PR |
2109 | if (dev->phydev) |
2110 | phy_stop(dev->phydev); | |
eea221ce | 2111 | spin_lock_irqsave(&lp->lock, flags); |
eea221ce | 2112 | tc35815_chip_reset(dev); |
1da177e4 | 2113 | spin_unlock_irqrestore(&lp->lock, flags); |
eea221ce AN |
2114 | pci_set_power_state(pdev, PCI_D3hot); |
2115 | return 0; | |
1da177e4 LT |
2116 | } |
2117 | ||
eea221ce AN |
2118 | static int tc35815_resume(struct pci_dev *pdev) |
2119 | { | |
2120 | struct net_device *dev = pci_get_drvdata(pdev); | |
eea221ce AN |
2121 | |
2122 | pci_restore_state(pdev); | |
2123 | if (!netif_running(dev)) | |
2124 | return 0; | |
2125 | pci_set_power_state(pdev, PCI_D0); | |
eea221ce | 2126 | tc35815_restart(dev); |
59524a37 | 2127 | netif_carrier_off(dev); |
a4fc549a PR |
2128 | if (dev->phydev) |
2129 | phy_start(dev->phydev); | |
eea221ce AN |
2130 | netif_device_attach(dev); |
2131 | return 0; | |
2132 | } | |
2133 | #endif /* CONFIG_PM */ | |
2134 | ||
2135 | static struct pci_driver tc35815_pci_driver = { | |
2136 | .name = MODNAME, | |
2137 | .id_table = tc35815_pci_tbl, | |
2138 | .probe = tc35815_init_one, | |
b38d1306 | 2139 | .remove = tc35815_remove_one, |
eea221ce AN |
2140 | #ifdef CONFIG_PM |
2141 | .suspend = tc35815_suspend, | |
2142 | .resume = tc35815_resume, | |
2143 | #endif | |
1da177e4 LT |
2144 | }; |
2145 | ||
eea221ce AN |
2146 | module_param_named(speed, options.speed, int, 0); |
2147 | MODULE_PARM_DESC(speed, "0:auto, 10:10Mbps, 100:100Mbps"); | |
2148 | module_param_named(duplex, options.duplex, int, 0); | |
2149 | MODULE_PARM_DESC(duplex, "0:auto, 1:half, 2:full"); | |
eea221ce | 2150 | |
b6f57210 | 2151 | module_pci_driver(tc35815_pci_driver); |
eea221ce AN |
2152 | MODULE_DESCRIPTION("TOSHIBA TC35815 PCI 10M/100M Ethernet driver"); |
2153 | MODULE_LICENSE("GPL"); |