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0b23fb36 IY |
1 | /* |
2 | * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com> | |
3 | * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org> | |
4 | * (C) Copyright 2008 Armadeus Systems nc | |
5 | * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> | |
6 | * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de> | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
0b23fb36 IY |
9 | */ |
10 | ||
11 | #include <common.h> | |
60752ca8 | 12 | #include <dm.h> |
0b23fb36 | 13 | #include <malloc.h> |
cf92e05c | 14 | #include <memalign.h> |
567173a6 | 15 | #include <miiphy.h> |
0b23fb36 | 16 | #include <net.h> |
84f64c8b | 17 | #include <netdev.h> |
0b23fb36 IY |
18 | #include "fec_mxc.h" |
19 | ||
0b23fb36 | 20 | #include <asm/io.h> |
1221ce45 | 21 | #include <linux/errno.h> |
e2a66e60 | 22 | #include <linux/compiler.h> |
0b23fb36 | 23 | |
567173a6 JT |
24 | #include <asm/arch/clock.h> |
25 | #include <asm/arch/imx-regs.h> | |
552a848e | 26 | #include <asm/mach-imx/sys_proto.h> |
567173a6 | 27 | |
0b23fb36 IY |
28 | DECLARE_GLOBAL_DATA_PTR; |
29 | ||
bc1ce150 MV |
30 | /* |
31 | * Timeout the transfer after 5 mS. This is usually a bit more, since | |
32 | * the code in the tightloops this timeout is used in adds some overhead. | |
33 | */ | |
34 | #define FEC_XFER_TIMEOUT 5000 | |
35 | ||
db5b7f56 FE |
36 | /* |
37 | * The standard 32-byte DMA alignment does not work on mx6solox, which requires | |
38 | * 64-byte alignment in the DMA RX FEC buffer. | |
39 | * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also | |
40 | * satisfies the alignment on other SoCs (32-bytes) | |
41 | */ | |
42 | #define FEC_DMA_RX_MINALIGN 64 | |
43 | ||
0b23fb36 IY |
44 | #ifndef CONFIG_MII |
45 | #error "CONFIG_MII has to be defined!" | |
46 | #endif | |
47 | ||
5c1ad3e6 EN |
48 | #ifndef CONFIG_FEC_XCV_TYPE |
49 | #define CONFIG_FEC_XCV_TYPE MII100 | |
392b8502 MV |
50 | #endif |
51 | ||
be7e87e2 MV |
52 | /* |
53 | * The i.MX28 operates with packets in big endian. We need to swap them before | |
54 | * sending and after receiving. | |
55 | */ | |
5c1ad3e6 EN |
56 | #ifdef CONFIG_MX28 |
57 | #define CONFIG_FEC_MXC_SWAP_PACKET | |
58 | #endif | |
59 | ||
60 | #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd)) | |
61 | ||
62 | /* Check various alignment issues at compile time */ | |
63 | #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0)) | |
64 | #error "ARCH_DMA_MINALIGN must be multiple of 16!" | |
65 | #endif | |
66 | ||
67 | #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \ | |
68 | (PKTALIGN % ARCH_DMA_MINALIGN != 0)) | |
69 | #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!" | |
be7e87e2 MV |
70 | #endif |
71 | ||
0b23fb36 IY |
72 | #undef DEBUG |
73 | ||
5c1ad3e6 | 74 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
be7e87e2 MV |
75 | static void swap_packet(uint32_t *packet, int length) |
76 | { | |
77 | int i; | |
78 | ||
79 | for (i = 0; i < DIV_ROUND_UP(length, 4); i++) | |
80 | packet[i] = __swab32(packet[i]); | |
81 | } | |
82 | #endif | |
83 | ||
567173a6 JT |
84 | /* MII-interface related functions */ |
85 | static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr, | |
86 | uint8_t regaddr) | |
0b23fb36 | 87 | { |
0b23fb36 IY |
88 | uint32_t reg; /* convenient holder for the PHY register */ |
89 | uint32_t phy; /* convenient holder for the PHY */ | |
90 | uint32_t start; | |
13947f43 | 91 | int val; |
0b23fb36 IY |
92 | |
93 | /* | |
94 | * reading from any PHY's register is done by properly | |
95 | * programming the FEC's MII data register. | |
96 | */ | |
d133b881 | 97 | writel(FEC_IEVENT_MII, ð->ievent); |
567173a6 JT |
98 | reg = regaddr << FEC_MII_DATA_RA_SHIFT; |
99 | phy = phyaddr << FEC_MII_DATA_PA_SHIFT; | |
0b23fb36 IY |
100 | |
101 | writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | | |
d133b881 | 102 | phy | reg, ð->mii_data); |
0b23fb36 | 103 | |
567173a6 | 104 | /* wait for the related interrupt */ |
a60d1e5b | 105 | start = get_timer(0); |
d133b881 | 106 | while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { |
0b23fb36 IY |
107 | if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { |
108 | printf("Read MDIO failed...\n"); | |
109 | return -1; | |
110 | } | |
111 | } | |
112 | ||
567173a6 | 113 | /* clear mii interrupt bit */ |
d133b881 | 114 | writel(FEC_IEVENT_MII, ð->ievent); |
0b23fb36 | 115 | |
567173a6 | 116 | /* it's now safe to read the PHY's register */ |
13947f43 | 117 | val = (unsigned short)readl(ð->mii_data); |
567173a6 JT |
118 | debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr, |
119 | regaddr, val); | |
13947f43 | 120 | return val; |
0b23fb36 IY |
121 | } |
122 | ||
575c5cc0 | 123 | static void fec_mii_setspeed(struct ethernet_regs *eth) |
4294b248 SB |
124 | { |
125 | /* | |
126 | * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock | |
127 | * and do not drop the Preamble. | |
843a3e58 MR |
128 | * |
129 | * The i.MX28 and i.MX6 types have another field in the MSCR (aka | |
130 | * MII_SPEED) register that defines the MDIO output hold time. Earlier | |
131 | * versions are RAZ there, so just ignore the difference and write the | |
132 | * register always. | |
133 | * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. | |
134 | * HOLDTIME + 1 is the number of clk cycles the fec is holding the | |
135 | * output. | |
136 | * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). | |
137 | * Given that ceil(clkrate / 5000000) <= 64, the calculation for | |
138 | * holdtime cannot result in a value greater than 3. | |
4294b248 | 139 | */ |
843a3e58 MR |
140 | u32 pclk = imx_get_fecclk(); |
141 | u32 speed = DIV_ROUND_UP(pclk, 5000000); | |
142 | u32 hold = DIV_ROUND_UP(pclk, 100000000) - 1; | |
6ba45cc0 MN |
143 | #ifdef FEC_QUIRK_ENET_MAC |
144 | speed--; | |
145 | #endif | |
843a3e58 | 146 | writel(speed << 1 | hold << 8, ð->mii_speed); |
575c5cc0 | 147 | debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed)); |
4294b248 | 148 | } |
0b23fb36 | 149 | |
567173a6 JT |
150 | static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr, |
151 | uint8_t regaddr, uint16_t data) | |
13947f43 | 152 | { |
0b23fb36 IY |
153 | uint32_t reg; /* convenient holder for the PHY register */ |
154 | uint32_t phy; /* convenient holder for the PHY */ | |
155 | uint32_t start; | |
156 | ||
567173a6 JT |
157 | reg = regaddr << FEC_MII_DATA_RA_SHIFT; |
158 | phy = phyaddr << FEC_MII_DATA_PA_SHIFT; | |
0b23fb36 IY |
159 | |
160 | writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | | |
d133b881 | 161 | FEC_MII_DATA_TA | phy | reg | data, ð->mii_data); |
0b23fb36 | 162 | |
567173a6 | 163 | /* wait for the MII interrupt */ |
a60d1e5b | 164 | start = get_timer(0); |
d133b881 | 165 | while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { |
0b23fb36 IY |
166 | if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { |
167 | printf("Write MDIO failed...\n"); | |
168 | return -1; | |
169 | } | |
170 | } | |
171 | ||
567173a6 | 172 | /* clear MII interrupt bit */ |
d133b881 | 173 | writel(FEC_IEVENT_MII, ð->ievent); |
567173a6 JT |
174 | debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr, |
175 | regaddr, data); | |
0b23fb36 IY |
176 | |
177 | return 0; | |
178 | } | |
179 | ||
567173a6 JT |
180 | static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr, |
181 | int regaddr) | |
13947f43 | 182 | { |
567173a6 | 183 | return fec_mdio_read(bus->priv, phyaddr, regaddr); |
13947f43 TK |
184 | } |
185 | ||
567173a6 JT |
186 | static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr, |
187 | int regaddr, u16 data) | |
13947f43 | 188 | { |
567173a6 | 189 | return fec_mdio_write(bus->priv, phyaddr, regaddr, data); |
13947f43 TK |
190 | } |
191 | ||
192 | #ifndef CONFIG_PHYLIB | |
0b23fb36 IY |
193 | static int miiphy_restart_aneg(struct eth_device *dev) |
194 | { | |
b774fe9d SB |
195 | int ret = 0; |
196 | #if !defined(CONFIG_FEC_MXC_NO_ANEG) | |
9e27e9dc | 197 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
13947f43 | 198 | struct ethernet_regs *eth = fec->bus->priv; |
9e27e9dc | 199 | |
0b23fb36 IY |
200 | /* |
201 | * Wake up from sleep if necessary | |
202 | * Reset PHY, then delay 300ns | |
203 | */ | |
cb17b92d | 204 | #ifdef CONFIG_MX27 |
13947f43 | 205 | fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF); |
cb17b92d | 206 | #endif |
13947f43 | 207 | fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET); |
0b23fb36 IY |
208 | udelay(1000); |
209 | ||
567173a6 | 210 | /* Set the auto-negotiation advertisement register bits */ |
13947f43 | 211 | fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE, |
567173a6 JT |
212 | LPA_100FULL | LPA_100HALF | LPA_10FULL | |
213 | LPA_10HALF | PHY_ANLPAR_PSB_802_3); | |
13947f43 | 214 | fec_mdio_write(eth, fec->phy_id, MII_BMCR, |
567173a6 | 215 | BMCR_ANENABLE | BMCR_ANRESTART); |
2e5f4421 MV |
216 | |
217 | if (fec->mii_postcall) | |
218 | ret = fec->mii_postcall(fec->phy_id); | |
219 | ||
b774fe9d | 220 | #endif |
2e5f4421 | 221 | return ret; |
0b23fb36 IY |
222 | } |
223 | ||
0750701a | 224 | #ifndef CONFIG_FEC_FIXED_SPEED |
0b23fb36 IY |
225 | static int miiphy_wait_aneg(struct eth_device *dev) |
226 | { | |
227 | uint32_t start; | |
13947f43 | 228 | int status; |
9e27e9dc | 229 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
13947f43 | 230 | struct ethernet_regs *eth = fec->bus->priv; |
0b23fb36 | 231 | |
567173a6 | 232 | /* Wait for AN completion */ |
a60d1e5b | 233 | start = get_timer(0); |
0b23fb36 IY |
234 | do { |
235 | if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { | |
236 | printf("%s: Autonegotiation timeout\n", dev->name); | |
237 | return -1; | |
238 | } | |
239 | ||
13947f43 TK |
240 | status = fec_mdio_read(eth, fec->phy_id, MII_BMSR); |
241 | if (status < 0) { | |
242 | printf("%s: Autonegotiation failed. status: %d\n", | |
567173a6 | 243 | dev->name, status); |
0b23fb36 IY |
244 | return -1; |
245 | } | |
8ef583a0 | 246 | } while (!(status & BMSR_LSTATUS)); |
0b23fb36 IY |
247 | |
248 | return 0; | |
249 | } | |
0750701a | 250 | #endif /* CONFIG_FEC_FIXED_SPEED */ |
13947f43 TK |
251 | #endif |
252 | ||
0b23fb36 IY |
253 | static int fec_rx_task_enable(struct fec_priv *fec) |
254 | { | |
c0b5a3bb | 255 | writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active); |
0b23fb36 IY |
256 | return 0; |
257 | } | |
258 | ||
259 | static int fec_rx_task_disable(struct fec_priv *fec) | |
260 | { | |
261 | return 0; | |
262 | } | |
263 | ||
264 | static int fec_tx_task_enable(struct fec_priv *fec) | |
265 | { | |
c0b5a3bb | 266 | writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active); |
0b23fb36 IY |
267 | return 0; |
268 | } | |
269 | ||
270 | static int fec_tx_task_disable(struct fec_priv *fec) | |
271 | { | |
272 | return 0; | |
273 | } | |
274 | ||
275 | /** | |
276 | * Initialize receive task's buffer descriptors | |
277 | * @param[in] fec all we know about the device yet | |
278 | * @param[in] count receive buffer count to be allocated | |
5c1ad3e6 | 279 | * @param[in] dsize desired size of each receive buffer |
0b23fb36 IY |
280 | * @return 0 on success |
281 | * | |
79e5f27b | 282 | * Init all RX descriptors to default values. |
0b23fb36 | 283 | */ |
79e5f27b | 284 | static void fec_rbd_init(struct fec_priv *fec, int count, int dsize) |
0b23fb36 | 285 | { |
5c1ad3e6 | 286 | uint32_t size; |
f24e482a | 287 | ulong data; |
5c1ad3e6 EN |
288 | int i; |
289 | ||
0b23fb36 | 290 | /* |
79e5f27b MV |
291 | * Reload the RX descriptors with default values and wipe |
292 | * the RX buffers. | |
0b23fb36 | 293 | */ |
5c1ad3e6 EN |
294 | size = roundup(dsize, ARCH_DMA_MINALIGN); |
295 | for (i = 0; i < count; i++) { | |
f24e482a YL |
296 | data = fec->rbd_base[i].data_pointer; |
297 | memset((void *)data, 0, dsize); | |
298 | flush_dcache_range(data, data + size); | |
79e5f27b MV |
299 | |
300 | fec->rbd_base[i].status = FEC_RBD_EMPTY; | |
301 | fec->rbd_base[i].data_length = 0; | |
5c1ad3e6 EN |
302 | } |
303 | ||
304 | /* Mark the last RBD to close the ring. */ | |
79e5f27b | 305 | fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; |
0b23fb36 IY |
306 | fec->rbd_index = 0; |
307 | ||
f24e482a YL |
308 | flush_dcache_range((ulong)fec->rbd_base, |
309 | (ulong)fec->rbd_base + size); | |
0b23fb36 IY |
310 | } |
311 | ||
312 | /** | |
313 | * Initialize transmit task's buffer descriptors | |
314 | * @param[in] fec all we know about the device yet | |
315 | * | |
316 | * Transmit buffers are created externally. We only have to init the BDs here.\n | |
317 | * Note: There is a race condition in the hardware. When only one BD is in | |
318 | * use it must be marked with the WRAP bit to use it for every transmitt. | |
319 | * This bit in combination with the READY bit results into double transmit | |
320 | * of each data buffer. It seems the state machine checks READY earlier then | |
321 | * resetting it after the first transfer. | |
322 | * Using two BDs solves this issue. | |
323 | */ | |
324 | static void fec_tbd_init(struct fec_priv *fec) | |
325 | { | |
f24e482a | 326 | ulong addr = (ulong)fec->tbd_base; |
5c1ad3e6 EN |
327 | unsigned size = roundup(2 * sizeof(struct fec_bd), |
328 | ARCH_DMA_MINALIGN); | |
79e5f27b MV |
329 | |
330 | memset(fec->tbd_base, 0, size); | |
331 | fec->tbd_base[0].status = 0; | |
332 | fec->tbd_base[1].status = FEC_TBD_WRAP; | |
0b23fb36 | 333 | fec->tbd_index = 0; |
79e5f27b | 334 | flush_dcache_range(addr, addr + size); |
0b23fb36 IY |
335 | } |
336 | ||
337 | /** | |
338 | * Mark the given read buffer descriptor as free | |
339 | * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0 | |
567173a6 | 340 | * @param[in] prbd buffer descriptor to mark free again |
0b23fb36 | 341 | */ |
567173a6 | 342 | static void fec_rbd_clean(int last, struct fec_bd *prbd) |
0b23fb36 | 343 | { |
5c1ad3e6 | 344 | unsigned short flags = FEC_RBD_EMPTY; |
0b23fb36 | 345 | if (last) |
5c1ad3e6 | 346 | flags |= FEC_RBD_WRAP; |
567173a6 JT |
347 | writew(flags, &prbd->status); |
348 | writew(0, &prbd->data_length); | |
0b23fb36 IY |
349 | } |
350 | ||
f54183e6 | 351 | static int fec_get_hwaddr(int dev_id, unsigned char *mac) |
0b23fb36 | 352 | { |
be252b65 | 353 | imx_get_mac_from_fuse(dev_id, mac); |
0adb5b76 | 354 | return !is_valid_ethaddr(mac); |
0b23fb36 IY |
355 | } |
356 | ||
60752ca8 JT |
357 | #ifdef CONFIG_DM_ETH |
358 | static int fecmxc_set_hwaddr(struct udevice *dev) | |
359 | #else | |
4294b248 | 360 | static int fec_set_hwaddr(struct eth_device *dev) |
60752ca8 | 361 | #endif |
0b23fb36 | 362 | { |
60752ca8 JT |
363 | #ifdef CONFIG_DM_ETH |
364 | struct fec_priv *fec = dev_get_priv(dev); | |
365 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
366 | uchar *mac = pdata->enetaddr; | |
367 | #else | |
4294b248 | 368 | uchar *mac = dev->enetaddr; |
0b23fb36 | 369 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
60752ca8 | 370 | #endif |
0b23fb36 IY |
371 | |
372 | writel(0, &fec->eth->iaddr1); | |
373 | writel(0, &fec->eth->iaddr2); | |
374 | writel(0, &fec->eth->gaddr1); | |
375 | writel(0, &fec->eth->gaddr2); | |
376 | ||
567173a6 | 377 | /* Set physical address */ |
0b23fb36 | 378 | writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], |
567173a6 | 379 | &fec->eth->paddr1); |
0b23fb36 IY |
380 | writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2); |
381 | ||
382 | return 0; | |
383 | } | |
384 | ||
567173a6 | 385 | /* Do initial configuration of the FEC registers */ |
a5990b26 MV |
386 | static void fec_reg_setup(struct fec_priv *fec) |
387 | { | |
388 | uint32_t rcntrl; | |
389 | ||
567173a6 | 390 | /* Set interrupt mask register */ |
a5990b26 MV |
391 | writel(0x00000000, &fec->eth->imask); |
392 | ||
567173a6 | 393 | /* Clear FEC-Lite interrupt event register(IEVENT) */ |
a5990b26 MV |
394 | writel(0xffffffff, &fec->eth->ievent); |
395 | ||
567173a6 | 396 | /* Set FEC-Lite receive control register(R_CNTRL): */ |
a5990b26 MV |
397 | |
398 | /* Start with frame length = 1518, common for all modes. */ | |
399 | rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT; | |
9d2d924a | 400 | if (fec->xcv_type != SEVENWIRE) /* xMII modes */ |
401 | rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE; | |
402 | if (fec->xcv_type == RGMII) | |
a5990b26 MV |
403 | rcntrl |= FEC_RCNTRL_RGMII; |
404 | else if (fec->xcv_type == RMII) | |
405 | rcntrl |= FEC_RCNTRL_RMII; | |
a5990b26 MV |
406 | |
407 | writel(rcntrl, &fec->eth->r_cntrl); | |
408 | } | |
409 | ||
0b23fb36 IY |
410 | /** |
411 | * Start the FEC engine | |
412 | * @param[in] dev Our device to handle | |
413 | */ | |
60752ca8 JT |
414 | #ifdef CONFIG_DM_ETH |
415 | static int fec_open(struct udevice *dev) | |
416 | #else | |
0b23fb36 | 417 | static int fec_open(struct eth_device *edev) |
60752ca8 | 418 | #endif |
0b23fb36 | 419 | { |
60752ca8 JT |
420 | #ifdef CONFIG_DM_ETH |
421 | struct fec_priv *fec = dev_get_priv(dev); | |
422 | #else | |
0b23fb36 | 423 | struct fec_priv *fec = (struct fec_priv *)edev->priv; |
60752ca8 | 424 | #endif |
28774cba | 425 | int speed; |
f24e482a | 426 | ulong addr, size; |
5c1ad3e6 | 427 | int i; |
0b23fb36 IY |
428 | |
429 | debug("fec_open: fec_open(dev)\n"); | |
430 | /* full-duplex, heartbeat disabled */ | |
431 | writel(1 << 2, &fec->eth->x_cntrl); | |
432 | fec->rbd_index = 0; | |
433 | ||
5c1ad3e6 EN |
434 | /* Invalidate all descriptors */ |
435 | for (i = 0; i < FEC_RBD_NUM - 1; i++) | |
436 | fec_rbd_clean(0, &fec->rbd_base[i]); | |
437 | fec_rbd_clean(1, &fec->rbd_base[i]); | |
438 | ||
439 | /* Flush the descriptors into RAM */ | |
440 | size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), | |
441 | ARCH_DMA_MINALIGN); | |
f24e482a | 442 | addr = (ulong)fec->rbd_base; |
5c1ad3e6 EN |
443 | flush_dcache_range(addr, addr + size); |
444 | ||
28774cba | 445 | #ifdef FEC_QUIRK_ENET_MAC |
2ef2b950 JL |
446 | /* Enable ENET HW endian SWAP */ |
447 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP, | |
567173a6 | 448 | &fec->eth->ecntrl); |
2ef2b950 JL |
449 | /* Enable ENET store and forward mode */ |
450 | writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD, | |
567173a6 | 451 | &fec->eth->x_wmrk); |
2ef2b950 | 452 | #endif |
567173a6 | 453 | /* Enable FEC-Lite controller */ |
cb17b92d | 454 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, |
567173a6 JT |
455 | &fec->eth->ecntrl); |
456 | ||
7df51fd8 | 457 | #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) |
740d6ae5 | 458 | udelay(100); |
740d6ae5 | 459 | |
567173a6 | 460 | /* setup the MII gasket for RMII mode */ |
740d6ae5 JR |
461 | /* disable the gasket */ |
462 | writew(0, &fec->eth->miigsk_enr); | |
463 | ||
464 | /* wait for the gasket to be disabled */ | |
465 | while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) | |
466 | udelay(2); | |
467 | ||
468 | /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ | |
469 | writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); | |
470 | ||
471 | /* re-enable the gasket */ | |
472 | writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr); | |
473 | ||
474 | /* wait until MII gasket is ready */ | |
475 | int max_loops = 10; | |
476 | while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) { | |
477 | if (--max_loops <= 0) { | |
478 | printf("WAIT for MII Gasket ready timed out\n"); | |
479 | break; | |
480 | } | |
481 | } | |
482 | #endif | |
0b23fb36 | 483 | |
13947f43 | 484 | #ifdef CONFIG_PHYLIB |
4dc27eed | 485 | { |
13947f43 | 486 | /* Start up the PHY */ |
11af8d65 TT |
487 | int ret = phy_startup(fec->phydev); |
488 | ||
489 | if (ret) { | |
490 | printf("Could not initialize PHY %s\n", | |
491 | fec->phydev->dev->name); | |
492 | return ret; | |
493 | } | |
13947f43 | 494 | speed = fec->phydev->speed; |
13947f43 | 495 | } |
0750701a HS |
496 | #elif CONFIG_FEC_FIXED_SPEED |
497 | speed = CONFIG_FEC_FIXED_SPEED; | |
13947f43 | 498 | #else |
0b23fb36 | 499 | miiphy_wait_aneg(edev); |
28774cba | 500 | speed = miiphy_speed(edev->name, fec->phy_id); |
9e27e9dc | 501 | miiphy_duplex(edev->name, fec->phy_id); |
13947f43 | 502 | #endif |
0b23fb36 | 503 | |
28774cba TK |
504 | #ifdef FEC_QUIRK_ENET_MAC |
505 | { | |
506 | u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED; | |
bcb6e902 | 507 | u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T; |
28774cba TK |
508 | if (speed == _1000BASET) |
509 | ecr |= FEC_ECNTRL_SPEED; | |
510 | else if (speed != _100BASET) | |
511 | rcr |= FEC_RCNTRL_RMII_10T; | |
512 | writel(ecr, &fec->eth->ecntrl); | |
513 | writel(rcr, &fec->eth->r_cntrl); | |
514 | } | |
515 | #endif | |
516 | debug("%s:Speed=%i\n", __func__, speed); | |
517 | ||
567173a6 | 518 | /* Enable SmartDMA receive task */ |
0b23fb36 IY |
519 | fec_rx_task_enable(fec); |
520 | ||
521 | udelay(100000); | |
522 | return 0; | |
523 | } | |
524 | ||
60752ca8 JT |
525 | #ifdef CONFIG_DM_ETH |
526 | static int fecmxc_init(struct udevice *dev) | |
527 | #else | |
567173a6 | 528 | static int fec_init(struct eth_device *dev, bd_t *bd) |
60752ca8 | 529 | #endif |
0b23fb36 | 530 | { |
60752ca8 JT |
531 | #ifdef CONFIG_DM_ETH |
532 | struct fec_priv *fec = dev_get_priv(dev); | |
533 | #else | |
0b23fb36 | 534 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
60752ca8 | 535 | #endif |
f24e482a YL |
536 | u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop; |
537 | u8 *i; | |
538 | ulong addr; | |
0b23fb36 | 539 | |
e9319f11 | 540 | /* Initialize MAC address */ |
60752ca8 JT |
541 | #ifdef CONFIG_DM_ETH |
542 | fecmxc_set_hwaddr(dev); | |
543 | #else | |
e9319f11 | 544 | fec_set_hwaddr(dev); |
60752ca8 | 545 | #endif |
e9319f11 | 546 | |
567173a6 | 547 | /* Setup transmit descriptors, there are two in total. */ |
79e5f27b | 548 | fec_tbd_init(fec); |
0b23fb36 | 549 | |
79e5f27b MV |
550 | /* Setup receive descriptors. */ |
551 | fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE); | |
0b23fb36 | 552 | |
a5990b26 | 553 | fec_reg_setup(fec); |
9eb3770b | 554 | |
f41471e6 | 555 | if (fec->xcv_type != SEVENWIRE) |
575c5cc0 | 556 | fec_mii_setspeed(fec->bus->priv); |
9eb3770b | 557 | |
567173a6 | 558 | /* Set Opcode/Pause Duration Register */ |
0b23fb36 IY |
559 | writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ |
560 | writel(0x2, &fec->eth->x_wmrk); | |
567173a6 JT |
561 | |
562 | /* Set multicast address filter */ | |
0b23fb36 IY |
563 | writel(0x00000000, &fec->eth->gaddr1); |
564 | writel(0x00000000, &fec->eth->gaddr2); | |
565 | ||
238a53c7 PF |
566 | /* Do not access reserved register */ |
567 | if (!is_mx6ul() && !is_mx6ull() && !is_mx8m()) { | |
fbecbaa1 PF |
568 | /* clear MIB RAM */ |
569 | for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) | |
570 | writel(0, i); | |
0b23fb36 | 571 | |
fbecbaa1 PF |
572 | /* FIFO receive start register */ |
573 | writel(0x520, &fec->eth->r_fstart); | |
574 | } | |
0b23fb36 IY |
575 | |
576 | /* size and address of each buffer */ | |
577 | writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr); | |
f24e482a YL |
578 | |
579 | addr = (ulong)fec->tbd_base; | |
580 | writel((uint32_t)addr, &fec->eth->etdsr); | |
581 | ||
582 | addr = (ulong)fec->rbd_base; | |
583 | writel((uint32_t)addr, &fec->eth->erdsr); | |
0b23fb36 | 584 | |
13947f43 | 585 | #ifndef CONFIG_PHYLIB |
0b23fb36 IY |
586 | if (fec->xcv_type != SEVENWIRE) |
587 | miiphy_restart_aneg(dev); | |
13947f43 | 588 | #endif |
0b23fb36 IY |
589 | fec_open(dev); |
590 | return 0; | |
591 | } | |
592 | ||
593 | /** | |
594 | * Halt the FEC engine | |
595 | * @param[in] dev Our device to handle | |
596 | */ | |
60752ca8 JT |
597 | #ifdef CONFIG_DM_ETH |
598 | static void fecmxc_halt(struct udevice *dev) | |
599 | #else | |
0b23fb36 | 600 | static void fec_halt(struct eth_device *dev) |
60752ca8 | 601 | #endif |
0b23fb36 | 602 | { |
60752ca8 JT |
603 | #ifdef CONFIG_DM_ETH |
604 | struct fec_priv *fec = dev_get_priv(dev); | |
605 | #else | |
9e27e9dc | 606 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
60752ca8 | 607 | #endif |
0b23fb36 IY |
608 | int counter = 0xffff; |
609 | ||
567173a6 | 610 | /* issue graceful stop command to the FEC transmitter if necessary */ |
cb17b92d | 611 | writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl), |
567173a6 | 612 | &fec->eth->x_cntrl); |
0b23fb36 IY |
613 | |
614 | debug("eth_halt: wait for stop regs\n"); | |
567173a6 | 615 | /* wait for graceful stop to register */ |
0b23fb36 | 616 | while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA))) |
cb17b92d | 617 | udelay(1); |
0b23fb36 | 618 | |
567173a6 | 619 | /* Disable SmartDMA tasks */ |
0b23fb36 IY |
620 | fec_tx_task_disable(fec); |
621 | fec_rx_task_disable(fec); | |
622 | ||
623 | /* | |
624 | * Disable the Ethernet Controller | |
625 | * Note: this will also reset the BD index counter! | |
626 | */ | |
740d6ae5 | 627 | writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, |
567173a6 | 628 | &fec->eth->ecntrl); |
0b23fb36 IY |
629 | fec->rbd_index = 0; |
630 | fec->tbd_index = 0; | |
0b23fb36 IY |
631 | debug("eth_halt: done\n"); |
632 | } | |
633 | ||
634 | /** | |
635 | * Transmit one frame | |
636 | * @param[in] dev Our ethernet device to handle | |
637 | * @param[in] packet Pointer to the data to be transmitted | |
638 | * @param[in] length Data count in bytes | |
639 | * @return 0 on success | |
640 | */ | |
60752ca8 JT |
641 | #ifdef CONFIG_DM_ETH |
642 | static int fecmxc_send(struct udevice *dev, void *packet, int length) | |
643 | #else | |
442dac4c | 644 | static int fec_send(struct eth_device *dev, void *packet, int length) |
60752ca8 | 645 | #endif |
0b23fb36 IY |
646 | { |
647 | unsigned int status; | |
f24e482a YL |
648 | u32 size; |
649 | ulong addr, end; | |
bc1ce150 MV |
650 | int timeout = FEC_XFER_TIMEOUT; |
651 | int ret = 0; | |
0b23fb36 IY |
652 | |
653 | /* | |
654 | * This routine transmits one frame. This routine only accepts | |
655 | * 6-byte Ethernet addresses. | |
656 | */ | |
60752ca8 JT |
657 | #ifdef CONFIG_DM_ETH |
658 | struct fec_priv *fec = dev_get_priv(dev); | |
659 | #else | |
0b23fb36 | 660 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
60752ca8 | 661 | #endif |
0b23fb36 IY |
662 | |
663 | /* | |
664 | * Check for valid length of data. | |
665 | */ | |
666 | if ((length > 1500) || (length <= 0)) { | |
4294b248 | 667 | printf("Payload (%d) too large\n", length); |
0b23fb36 IY |
668 | return -1; |
669 | } | |
670 | ||
671 | /* | |
5c1ad3e6 EN |
672 | * Setup the transmit buffer. We are always using the first buffer for |
673 | * transmission, the second will be empty and only used to stop the DMA | |
674 | * engine. We also flush the packet to RAM here to avoid cache trouble. | |
0b23fb36 | 675 | */ |
5c1ad3e6 | 676 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
be7e87e2 MV |
677 | swap_packet((uint32_t *)packet, length); |
678 | #endif | |
5c1ad3e6 | 679 | |
f24e482a | 680 | addr = (ulong)packet; |
efe24d2e MV |
681 | end = roundup(addr + length, ARCH_DMA_MINALIGN); |
682 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
683 | flush_dcache_range(addr, end); | |
5c1ad3e6 | 684 | |
0b23fb36 | 685 | writew(length, &fec->tbd_base[fec->tbd_index].data_length); |
f24e482a | 686 | writel((uint32_t)addr, &fec->tbd_base[fec->tbd_index].data_pointer); |
5c1ad3e6 | 687 | |
0b23fb36 IY |
688 | /* |
689 | * update BD's status now | |
690 | * This block: | |
691 | * - is always the last in a chain (means no chain) | |
692 | * - should transmitt the CRC | |
693 | * - might be the last BD in the list, so the address counter should | |
694 | * wrap (-> keep the WRAP flag) | |
695 | */ | |
696 | status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP; | |
697 | status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; | |
698 | writew(status, &fec->tbd_base[fec->tbd_index].status); | |
699 | ||
5c1ad3e6 EN |
700 | /* |
701 | * Flush data cache. This code flushes both TX descriptors to RAM. | |
702 | * After this code, the descriptors will be safely in RAM and we | |
703 | * can start DMA. | |
704 | */ | |
705 | size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
f24e482a | 706 | addr = (ulong)fec->tbd_base; |
5c1ad3e6 EN |
707 | flush_dcache_range(addr, addr + size); |
708 | ||
ab94cd49 MV |
709 | /* |
710 | * Below we read the DMA descriptor's last four bytes back from the | |
711 | * DRAM. This is important in order to make sure that all WRITE | |
712 | * operations on the bus that were triggered by previous cache FLUSH | |
713 | * have completed. | |
714 | * | |
715 | * Otherwise, on MX28, it is possible to observe a corruption of the | |
716 | * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM | |
717 | * for the bus structure of MX28. The scenario is as follows: | |
718 | * | |
719 | * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going | |
720 | * to DRAM due to flush_dcache_range() | |
721 | * 2) ARM core writes the FEC registers via AHB_ARB2 | |
722 | * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3 | |
723 | * | |
724 | * Note that 2) does sometimes finish before 1) due to reordering of | |
725 | * WRITE accesses on the AHB bus, therefore triggering 3) before the | |
726 | * DMA descriptor is fully written into DRAM. This results in occasional | |
727 | * corruption of the DMA descriptor. | |
728 | */ | |
729 | readl(addr + size - 4); | |
730 | ||
567173a6 | 731 | /* Enable SmartDMA transmit task */ |
0b23fb36 IY |
732 | fec_tx_task_enable(fec); |
733 | ||
734 | /* | |
5c1ad3e6 EN |
735 | * Wait until frame is sent. On each turn of the wait cycle, we must |
736 | * invalidate data cache to see what's really in RAM. Also, we need | |
737 | * barrier here. | |
0b23fb36 | 738 | */ |
67449098 | 739 | while (--timeout) { |
c0b5a3bb | 740 | if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR)) |
bc1ce150 | 741 | break; |
0b23fb36 | 742 | } |
5c1ad3e6 | 743 | |
f599288d | 744 | if (!timeout) { |
67449098 | 745 | ret = -EINVAL; |
f599288d FE |
746 | goto out; |
747 | } | |
748 | ||
749 | /* | |
750 | * The TDAR bit is cleared when the descriptors are all out from TX | |
751 | * but on mx6solox we noticed that the READY bit is still not cleared | |
752 | * right after TDAR. | |
753 | * These are two distinct signals, and in IC simulation, we found that | |
754 | * TDAR always gets cleared prior than the READY bit of last BD becomes | |
755 | * cleared. | |
756 | * In mx6solox, we use a later version of FEC IP. It looks like that | |
757 | * this intrinsic behaviour of TDAR bit has changed in this newer FEC | |
758 | * version. | |
759 | * | |
760 | * Fix this by polling the READY bit of BD after the TDAR polling, | |
761 | * which covers the mx6solox case and does not harm the other SoCs. | |
762 | */ | |
763 | timeout = FEC_XFER_TIMEOUT; | |
764 | while (--timeout) { | |
765 | invalidate_dcache_range(addr, addr + size); | |
766 | if (!(readw(&fec->tbd_base[fec->tbd_index].status) & | |
767 | FEC_TBD_READY)) | |
768 | break; | |
769 | } | |
67449098 | 770 | |
f599288d | 771 | if (!timeout) |
67449098 MV |
772 | ret = -EINVAL; |
773 | ||
f599288d | 774 | out: |
67449098 | 775 | debug("fec_send: status 0x%x index %d ret %i\n", |
567173a6 JT |
776 | readw(&fec->tbd_base[fec->tbd_index].status), |
777 | fec->tbd_index, ret); | |
0b23fb36 IY |
778 | /* for next transmission use the other buffer */ |
779 | if (fec->tbd_index) | |
780 | fec->tbd_index = 0; | |
781 | else | |
782 | fec->tbd_index = 1; | |
783 | ||
bc1ce150 | 784 | return ret; |
0b23fb36 IY |
785 | } |
786 | ||
787 | /** | |
788 | * Pull one frame from the card | |
789 | * @param[in] dev Our ethernet device to handle | |
790 | * @return Length of packet read | |
791 | */ | |
60752ca8 JT |
792 | #ifdef CONFIG_DM_ETH |
793 | static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp) | |
794 | #else | |
0b23fb36 | 795 | static int fec_recv(struct eth_device *dev) |
60752ca8 | 796 | #endif |
0b23fb36 | 797 | { |
60752ca8 JT |
798 | #ifdef CONFIG_DM_ETH |
799 | struct fec_priv *fec = dev_get_priv(dev); | |
800 | #else | |
0b23fb36 | 801 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
60752ca8 | 802 | #endif |
0b23fb36 IY |
803 | struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index]; |
804 | unsigned long ievent; | |
805 | int frame_length, len = 0; | |
0b23fb36 | 806 | uint16_t bd_status; |
f24e482a | 807 | ulong addr, size, end; |
5c1ad3e6 | 808 | int i; |
fd37f195 | 809 | ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE); |
0b23fb36 | 810 | |
567173a6 | 811 | /* Check if any critical events have happened */ |
0b23fb36 IY |
812 | ievent = readl(&fec->eth->ievent); |
813 | writel(ievent, &fec->eth->ievent); | |
eda959f3 | 814 | debug("fec_recv: ievent 0x%lx\n", ievent); |
0b23fb36 | 815 | if (ievent & FEC_IEVENT_BABR) { |
60752ca8 JT |
816 | #ifdef CONFIG_DM_ETH |
817 | fecmxc_halt(dev); | |
818 | fecmxc_init(dev); | |
819 | #else | |
0b23fb36 IY |
820 | fec_halt(dev); |
821 | fec_init(dev, fec->bd); | |
60752ca8 | 822 | #endif |
0b23fb36 IY |
823 | printf("some error: 0x%08lx\n", ievent); |
824 | return 0; | |
825 | } | |
826 | if (ievent & FEC_IEVENT_HBERR) { | |
827 | /* Heartbeat error */ | |
828 | writel(0x00000001 | readl(&fec->eth->x_cntrl), | |
567173a6 | 829 | &fec->eth->x_cntrl); |
0b23fb36 IY |
830 | } |
831 | if (ievent & FEC_IEVENT_GRA) { | |
832 | /* Graceful stop complete */ | |
833 | if (readl(&fec->eth->x_cntrl) & 0x00000001) { | |
60752ca8 JT |
834 | #ifdef CONFIG_DM_ETH |
835 | fecmxc_halt(dev); | |
836 | #else | |
0b23fb36 | 837 | fec_halt(dev); |
60752ca8 | 838 | #endif |
0b23fb36 | 839 | writel(~0x00000001 & readl(&fec->eth->x_cntrl), |
567173a6 | 840 | &fec->eth->x_cntrl); |
60752ca8 JT |
841 | #ifdef CONFIG_DM_ETH |
842 | fecmxc_init(dev); | |
843 | #else | |
0b23fb36 | 844 | fec_init(dev, fec->bd); |
60752ca8 | 845 | #endif |
0b23fb36 IY |
846 | } |
847 | } | |
848 | ||
849 | /* | |
5c1ad3e6 EN |
850 | * Read the buffer status. Before the status can be read, the data cache |
851 | * must be invalidated, because the data in RAM might have been changed | |
852 | * by DMA. The descriptors are properly aligned to cachelines so there's | |
853 | * no need to worry they'd overlap. | |
854 | * | |
855 | * WARNING: By invalidating the descriptor here, we also invalidate | |
856 | * the descriptors surrounding this one. Therefore we can NOT change the | |
857 | * contents of this descriptor nor the surrounding ones. The problem is | |
858 | * that in order to mark the descriptor as processed, we need to change | |
859 | * the descriptor. The solution is to mark the whole cache line when all | |
860 | * descriptors in the cache line are processed. | |
0b23fb36 | 861 | */ |
f24e482a | 862 | addr = (ulong)rbd; |
5c1ad3e6 EN |
863 | addr &= ~(ARCH_DMA_MINALIGN - 1); |
864 | size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
865 | invalidate_dcache_range(addr, addr + size); | |
866 | ||
0b23fb36 IY |
867 | bd_status = readw(&rbd->status); |
868 | debug("fec_recv: status 0x%x\n", bd_status); | |
869 | ||
870 | if (!(bd_status & FEC_RBD_EMPTY)) { | |
871 | if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) && | |
567173a6 JT |
872 | ((readw(&rbd->data_length) - 4) > 14)) { |
873 | /* Get buffer address and size */ | |
b189584b | 874 | addr = readl(&rbd->data_pointer); |
0b23fb36 | 875 | frame_length = readw(&rbd->data_length) - 4; |
567173a6 | 876 | /* Invalidate data cache over the buffer */ |
efe24d2e MV |
877 | end = roundup(addr + frame_length, ARCH_DMA_MINALIGN); |
878 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
879 | invalidate_dcache_range(addr, end); | |
5c1ad3e6 | 880 | |
567173a6 | 881 | /* Fill the buffer and pass it to upper layers */ |
5c1ad3e6 | 882 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
b189584b | 883 | swap_packet((uint32_t *)addr, frame_length); |
be7e87e2 | 884 | #endif |
b189584b | 885 | memcpy(buff, (char *)addr, frame_length); |
1fd92db8 | 886 | net_process_received_packet(buff, frame_length); |
0b23fb36 IY |
887 | len = frame_length; |
888 | } else { | |
889 | if (bd_status & FEC_RBD_ERR) | |
f24e482a YL |
890 | debug("error frame: 0x%08lx 0x%08x\n", |
891 | addr, bd_status); | |
0b23fb36 | 892 | } |
5c1ad3e6 | 893 | |
0b23fb36 | 894 | /* |
5c1ad3e6 EN |
895 | * Free the current buffer, restart the engine and move forward |
896 | * to the next buffer. Here we check if the whole cacheline of | |
897 | * descriptors was already processed and if so, we mark it free | |
898 | * as whole. | |
0b23fb36 | 899 | */ |
5c1ad3e6 EN |
900 | size = RXDESC_PER_CACHELINE - 1; |
901 | if ((fec->rbd_index & size) == size) { | |
902 | i = fec->rbd_index - size; | |
f24e482a | 903 | addr = (ulong)&fec->rbd_base[i]; |
5c1ad3e6 EN |
904 | for (; i <= fec->rbd_index ; i++) { |
905 | fec_rbd_clean(i == (FEC_RBD_NUM - 1), | |
906 | &fec->rbd_base[i]); | |
907 | } | |
908 | flush_dcache_range(addr, | |
567173a6 | 909 | addr + ARCH_DMA_MINALIGN); |
5c1ad3e6 EN |
910 | } |
911 | ||
0b23fb36 IY |
912 | fec_rx_task_enable(fec); |
913 | fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM; | |
914 | } | |
915 | debug("fec_recv: stop\n"); | |
916 | ||
917 | return len; | |
918 | } | |
919 | ||
ef8e3a3b TK |
920 | static void fec_set_dev_name(char *dest, int dev_id) |
921 | { | |
922 | sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id); | |
923 | } | |
924 | ||
79e5f27b MV |
925 | static int fec_alloc_descs(struct fec_priv *fec) |
926 | { | |
927 | unsigned int size; | |
928 | int i; | |
929 | uint8_t *data; | |
f24e482a | 930 | ulong addr; |
79e5f27b MV |
931 | |
932 | /* Allocate TX descriptors. */ | |
933 | size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
934 | fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size); | |
935 | if (!fec->tbd_base) | |
936 | goto err_tx; | |
937 | ||
938 | /* Allocate RX descriptors. */ | |
939 | size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
940 | fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size); | |
941 | if (!fec->rbd_base) | |
942 | goto err_rx; | |
943 | ||
944 | memset(fec->rbd_base, 0, size); | |
945 | ||
946 | /* Allocate RX buffers. */ | |
947 | ||
948 | /* Maximum RX buffer size. */ | |
db5b7f56 | 949 | size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN); |
79e5f27b | 950 | for (i = 0; i < FEC_RBD_NUM; i++) { |
db5b7f56 | 951 | data = memalign(FEC_DMA_RX_MINALIGN, size); |
79e5f27b MV |
952 | if (!data) { |
953 | printf("%s: error allocating rxbuf %d\n", __func__, i); | |
954 | goto err_ring; | |
955 | } | |
956 | ||
957 | memset(data, 0, size); | |
958 | ||
f24e482a YL |
959 | addr = (ulong)data; |
960 | fec->rbd_base[i].data_pointer = (uint32_t)addr; | |
79e5f27b MV |
961 | fec->rbd_base[i].status = FEC_RBD_EMPTY; |
962 | fec->rbd_base[i].data_length = 0; | |
963 | /* Flush the buffer to memory. */ | |
f24e482a | 964 | flush_dcache_range(addr, addr + size); |
79e5f27b MV |
965 | } |
966 | ||
967 | /* Mark the last RBD to close the ring. */ | |
968 | fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; | |
969 | ||
970 | fec->rbd_index = 0; | |
971 | fec->tbd_index = 0; | |
972 | ||
973 | return 0; | |
974 | ||
975 | err_ring: | |
f24e482a YL |
976 | for (; i >= 0; i--) { |
977 | addr = fec->rbd_base[i].data_pointer; | |
978 | free((void *)addr); | |
979 | } | |
79e5f27b MV |
980 | free(fec->rbd_base); |
981 | err_rx: | |
982 | free(fec->tbd_base); | |
983 | err_tx: | |
984 | return -ENOMEM; | |
985 | } | |
986 | ||
987 | static void fec_free_descs(struct fec_priv *fec) | |
988 | { | |
989 | int i; | |
f24e482a | 990 | ulong addr; |
79e5f27b | 991 | |
f24e482a YL |
992 | for (i = 0; i < FEC_RBD_NUM; i++) { |
993 | addr = fec->rbd_base[i].data_pointer; | |
994 | free((void *)addr); | |
995 | } | |
79e5f27b MV |
996 | free(fec->rbd_base); |
997 | free(fec->tbd_base); | |
998 | } | |
999 | ||
cb5761f7 LW |
1000 | #ifdef CONFIG_DM_ETH |
1001 | struct mii_dev *fec_get_miibus(struct udevice *dev, int dev_id) | |
1002 | #else | |
60752ca8 | 1003 | struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id) |
cb5761f7 | 1004 | #endif |
60752ca8 | 1005 | { |
cb5761f7 LW |
1006 | #ifdef CONFIG_DM_ETH |
1007 | struct fec_priv *priv = dev_get_priv(dev); | |
1008 | struct ethernet_regs *eth = priv->eth; | |
1009 | #else | |
f24e482a | 1010 | struct ethernet_regs *eth = (struct ethernet_regs *)(ulong)base_addr; |
cb5761f7 | 1011 | #endif |
60752ca8 JT |
1012 | struct mii_dev *bus; |
1013 | int ret; | |
1014 | ||
1015 | bus = mdio_alloc(); | |
1016 | if (!bus) { | |
1017 | printf("mdio_alloc failed\n"); | |
1018 | return NULL; | |
1019 | } | |
1020 | bus->read = fec_phy_read; | |
1021 | bus->write = fec_phy_write; | |
1022 | bus->priv = eth; | |
1023 | fec_set_dev_name(bus->name, dev_id); | |
1024 | ||
1025 | ret = mdio_register(bus); | |
1026 | if (ret) { | |
1027 | printf("mdio_register failed\n"); | |
1028 | free(bus); | |
1029 | return NULL; | |
1030 | } | |
1031 | fec_mii_setspeed(eth); | |
1032 | return bus; | |
1033 | } | |
1034 | ||
1035 | #ifndef CONFIG_DM_ETH | |
fe428b90 TK |
1036 | #ifdef CONFIG_PHYLIB |
1037 | int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, | |
1038 | struct mii_dev *bus, struct phy_device *phydev) | |
1039 | #else | |
1040 | static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, | |
1041 | struct mii_dev *bus, int phy_id) | |
1042 | #endif | |
0b23fb36 | 1043 | { |
0b23fb36 | 1044 | struct eth_device *edev; |
9e27e9dc | 1045 | struct fec_priv *fec; |
0b23fb36 | 1046 | unsigned char ethaddr[6]; |
979a5893 | 1047 | char mac[16]; |
e382fb48 MV |
1048 | uint32_t start; |
1049 | int ret = 0; | |
0b23fb36 IY |
1050 | |
1051 | /* create and fill edev struct */ | |
1052 | edev = (struct eth_device *)malloc(sizeof(struct eth_device)); | |
1053 | if (!edev) { | |
9e27e9dc | 1054 | puts("fec_mxc: not enough malloc memory for eth_device\n"); |
e382fb48 MV |
1055 | ret = -ENOMEM; |
1056 | goto err1; | |
9e27e9dc MV |
1057 | } |
1058 | ||
1059 | fec = (struct fec_priv *)malloc(sizeof(struct fec_priv)); | |
1060 | if (!fec) { | |
1061 | puts("fec_mxc: not enough malloc memory for fec_priv\n"); | |
e382fb48 MV |
1062 | ret = -ENOMEM; |
1063 | goto err2; | |
0b23fb36 | 1064 | } |
9e27e9dc | 1065 | |
de0b9576 | 1066 | memset(edev, 0, sizeof(*edev)); |
9e27e9dc MV |
1067 | memset(fec, 0, sizeof(*fec)); |
1068 | ||
79e5f27b MV |
1069 | ret = fec_alloc_descs(fec); |
1070 | if (ret) | |
1071 | goto err3; | |
1072 | ||
0b23fb36 IY |
1073 | edev->priv = fec; |
1074 | edev->init = fec_init; | |
1075 | edev->send = fec_send; | |
1076 | edev->recv = fec_recv; | |
1077 | edev->halt = fec_halt; | |
fb57ec97 | 1078 | edev->write_hwaddr = fec_set_hwaddr; |
0b23fb36 | 1079 | |
f24e482a | 1080 | fec->eth = (struct ethernet_regs *)(ulong)base_addr; |
0b23fb36 IY |
1081 | fec->bd = bd; |
1082 | ||
392b8502 | 1083 | fec->xcv_type = CONFIG_FEC_XCV_TYPE; |
0b23fb36 IY |
1084 | |
1085 | /* Reset chip. */ | |
cb17b92d | 1086 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl); |
e382fb48 MV |
1087 | start = get_timer(0); |
1088 | while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) { | |
1089 | if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { | |
3450a859 | 1090 | printf("FEC MXC: Timeout resetting chip\n"); |
79e5f27b | 1091 | goto err4; |
e382fb48 | 1092 | } |
0b23fb36 | 1093 | udelay(10); |
e382fb48 | 1094 | } |
0b23fb36 | 1095 | |
a5990b26 | 1096 | fec_reg_setup(fec); |
ef8e3a3b TK |
1097 | fec_set_dev_name(edev->name, dev_id); |
1098 | fec->dev_id = (dev_id == -1) ? 0 : dev_id; | |
fe428b90 TK |
1099 | fec->bus = bus; |
1100 | fec_mii_setspeed(bus->priv); | |
1101 | #ifdef CONFIG_PHYLIB | |
1102 | fec->phydev = phydev; | |
1103 | phy_connect_dev(phydev, edev); | |
1104 | /* Configure phy */ | |
1105 | phy_config(phydev); | |
1106 | #else | |
9e27e9dc | 1107 | fec->phy_id = phy_id; |
fe428b90 TK |
1108 | #endif |
1109 | eth_register(edev); | |
979a5893 AD |
1110 | /* only support one eth device, the index number pointed by dev_id */ |
1111 | edev->index = fec->dev_id; | |
fe428b90 | 1112 | |
f01e4e1e AD |
1113 | if (fec_get_hwaddr(fec->dev_id, ethaddr) == 0) { |
1114 | debug("got MAC%d address from fuse: %pM\n", fec->dev_id, ethaddr); | |
fe428b90 | 1115 | memcpy(edev->enetaddr, ethaddr, 6); |
979a5893 AD |
1116 | if (fec->dev_id) |
1117 | sprintf(mac, "eth%daddr", fec->dev_id); | |
1118 | else | |
1119 | strcpy(mac, "ethaddr"); | |
00caae6d | 1120 | if (!env_get(mac)) |
fd1e959e | 1121 | eth_env_set_enetaddr(mac, ethaddr); |
fe428b90 TK |
1122 | } |
1123 | return ret; | |
79e5f27b MV |
1124 | err4: |
1125 | fec_free_descs(fec); | |
fe428b90 TK |
1126 | err3: |
1127 | free(fec); | |
1128 | err2: | |
1129 | free(edev); | |
1130 | err1: | |
1131 | return ret; | |
1132 | } | |
1133 | ||
fe428b90 TK |
1134 | int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) |
1135 | { | |
1136 | uint32_t base_mii; | |
1137 | struct mii_dev *bus = NULL; | |
1138 | #ifdef CONFIG_PHYLIB | |
1139 | struct phy_device *phydev = NULL; | |
1140 | #endif | |
1141 | int ret; | |
1142 | ||
5c1ad3e6 | 1143 | #ifdef CONFIG_MX28 |
13947f43 TK |
1144 | /* |
1145 | * The i.MX28 has two ethernet interfaces, but they are not equal. | |
1146 | * Only the first one can access the MDIO bus. | |
1147 | */ | |
fe428b90 | 1148 | base_mii = MXS_ENET0_BASE; |
13947f43 | 1149 | #else |
fe428b90 | 1150 | base_mii = addr; |
13947f43 | 1151 | #endif |
fe428b90 TK |
1152 | debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr); |
1153 | bus = fec_get_miibus(base_mii, dev_id); | |
1154 | if (!bus) | |
1155 | return -ENOMEM; | |
4dc27eed | 1156 | #ifdef CONFIG_PHYLIB |
fe428b90 | 1157 | phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII); |
4dc27eed | 1158 | if (!phydev) { |
845a57b4 | 1159 | mdio_unregister(bus); |
4dc27eed | 1160 | free(bus); |
fe428b90 | 1161 | return -ENOMEM; |
4dc27eed | 1162 | } |
fe428b90 TK |
1163 | ret = fec_probe(bd, dev_id, addr, bus, phydev); |
1164 | #else | |
1165 | ret = fec_probe(bd, dev_id, addr, bus, phy_id); | |
4dc27eed | 1166 | #endif |
fe428b90 TK |
1167 | if (ret) { |
1168 | #ifdef CONFIG_PHYLIB | |
1169 | free(phydev); | |
1170 | #endif | |
845a57b4 | 1171 | mdio_unregister(bus); |
fe428b90 TK |
1172 | free(bus); |
1173 | } | |
e382fb48 | 1174 | return ret; |
eef24480 | 1175 | } |
0b23fb36 | 1176 | |
eef24480 TK |
1177 | #ifdef CONFIG_FEC_MXC_PHYADDR |
1178 | int fecmxc_initialize(bd_t *bd) | |
1179 | { | |
1180 | return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR, | |
1181 | IMX_FEC_BASE); | |
0b23fb36 | 1182 | } |
eef24480 | 1183 | #endif |
2e5f4421 | 1184 | |
13947f43 | 1185 | #ifndef CONFIG_PHYLIB |
2e5f4421 MV |
1186 | int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)) |
1187 | { | |
1188 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
1189 | fec->mii_postcall = cb; | |
1190 | return 0; | |
1191 | } | |
13947f43 | 1192 | #endif |
60752ca8 JT |
1193 | |
1194 | #else | |
1195 | ||
1ed2570f JT |
1196 | static int fecmxc_read_rom_hwaddr(struct udevice *dev) |
1197 | { | |
1198 | struct fec_priv *priv = dev_get_priv(dev); | |
1199 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
1200 | ||
1201 | return fec_get_hwaddr(priv->dev_id, pdata->enetaddr); | |
1202 | } | |
1203 | ||
60752ca8 JT |
1204 | static const struct eth_ops fecmxc_ops = { |
1205 | .start = fecmxc_init, | |
1206 | .send = fecmxc_send, | |
1207 | .recv = fecmxc_recv, | |
1208 | .stop = fecmxc_halt, | |
1209 | .write_hwaddr = fecmxc_set_hwaddr, | |
1ed2570f | 1210 | .read_rom_hwaddr = fecmxc_read_rom_hwaddr, |
60752ca8 JT |
1211 | }; |
1212 | ||
1213 | static int fec_phy_init(struct fec_priv *priv, struct udevice *dev) | |
1214 | { | |
1215 | struct phy_device *phydev; | |
1216 | int mask = 0xffffffff; | |
1217 | ||
1218 | #ifdef CONFIG_PHYLIB | |
1219 | mask = 1 << CONFIG_FEC_MXC_PHYADDR; | |
1220 | #endif | |
1221 | ||
1222 | phydev = phy_find_by_mask(priv->bus, mask, priv->interface); | |
1223 | if (!phydev) | |
1224 | return -ENODEV; | |
1225 | ||
1226 | phy_connect_dev(phydev, dev); | |
1227 | ||
1228 | priv->phydev = phydev; | |
1229 | phy_config(phydev); | |
1230 | ||
1231 | return 0; | |
1232 | } | |
1233 | ||
1234 | static int fecmxc_probe(struct udevice *dev) | |
1235 | { | |
1236 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
1237 | struct fec_priv *priv = dev_get_priv(dev); | |
1238 | struct mii_dev *bus = NULL; | |
1239 | int dev_id = -1; | |
60752ca8 JT |
1240 | uint32_t start; |
1241 | int ret; | |
1242 | ||
1243 | ret = fec_alloc_descs(priv); | |
1244 | if (ret) | |
1245 | return ret; | |
1246 | ||
60752ca8 | 1247 | /* Reset chip. */ |
567173a6 JT |
1248 | writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET, |
1249 | &priv->eth->ecntrl); | |
60752ca8 JT |
1250 | start = get_timer(0); |
1251 | while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) { | |
1252 | if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { | |
1253 | printf("FEC MXC: Timeout reseting chip\n"); | |
1254 | goto err_timeout; | |
1255 | } | |
1256 | udelay(10); | |
1257 | } | |
1258 | ||
1259 | fec_reg_setup(priv); | |
60752ca8 JT |
1260 | priv->dev_id = (dev_id == -1) ? 0 : dev_id; |
1261 | ||
306dd7da LW |
1262 | bus = fec_get_miibus(dev, dev_id); |
1263 | if (!bus) { | |
1264 | ret = -ENOMEM; | |
1265 | goto err_mii; | |
1266 | } | |
1267 | ||
1268 | priv->bus = bus; | |
1269 | priv->xcv_type = CONFIG_FEC_XCV_TYPE; | |
1270 | priv->interface = pdata->phy_interface; | |
1271 | ret = fec_phy_init(priv, dev); | |
1272 | if (ret) | |
1273 | goto err_phy; | |
1274 | ||
60752ca8 JT |
1275 | return 0; |
1276 | ||
1277 | err_timeout: | |
1278 | free(priv->phydev); | |
1279 | err_phy: | |
1280 | mdio_unregister(bus); | |
1281 | free(bus); | |
1282 | err_mii: | |
1283 | fec_free_descs(priv); | |
1284 | return ret; | |
1285 | } | |
1286 | ||
1287 | static int fecmxc_remove(struct udevice *dev) | |
1288 | { | |
1289 | struct fec_priv *priv = dev_get_priv(dev); | |
1290 | ||
1291 | free(priv->phydev); | |
1292 | fec_free_descs(priv); | |
1293 | mdio_unregister(priv->bus); | |
1294 | mdio_free(priv->bus); | |
1295 | ||
1296 | return 0; | |
1297 | } | |
1298 | ||
1299 | static int fecmxc_ofdata_to_platdata(struct udevice *dev) | |
1300 | { | |
1301 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
1302 | struct fec_priv *priv = dev_get_priv(dev); | |
1303 | const char *phy_mode; | |
1304 | ||
a821c4af | 1305 | pdata->iobase = (phys_addr_t)devfdt_get_addr(dev); |
60752ca8 JT |
1306 | priv->eth = (struct ethernet_regs *)pdata->iobase; |
1307 | ||
1308 | pdata->phy_interface = -1; | |
e160f7d4 SG |
1309 | phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", |
1310 | NULL); | |
60752ca8 JT |
1311 | if (phy_mode) |
1312 | pdata->phy_interface = phy_get_interface_by_name(phy_mode); | |
1313 | if (pdata->phy_interface == -1) { | |
1314 | debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); | |
1315 | return -EINVAL; | |
1316 | } | |
1317 | ||
1318 | /* TODO | |
1319 | * Need to get the reset-gpio and related properties from DT | |
1320 | * and implemet the enet reset code on .probe call | |
1321 | */ | |
1322 | ||
1323 | return 0; | |
1324 | } | |
1325 | ||
1326 | static const struct udevice_id fecmxc_ids[] = { | |
1327 | { .compatible = "fsl,imx6q-fec" }, | |
1328 | { } | |
1329 | }; | |
1330 | ||
1331 | U_BOOT_DRIVER(fecmxc_gem) = { | |
1332 | .name = "fecmxc", | |
1333 | .id = UCLASS_ETH, | |
1334 | .of_match = fecmxc_ids, | |
1335 | .ofdata_to_platdata = fecmxc_ofdata_to_platdata, | |
1336 | .probe = fecmxc_probe, | |
1337 | .remove = fecmxc_remove, | |
1338 | .ops = &fecmxc_ops, | |
1339 | .priv_auto_alloc_size = sizeof(struct fec_priv), | |
1340 | .platdata_auto_alloc_size = sizeof(struct eth_pdata), | |
1341 | }; | |
1342 | #endif |