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0b23fb36 IY |
1 | /* |
2 | * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com> | |
3 | * (C) Copyright 2008 Armadeus Systems, nc | |
4 | * (C) Copyright 2008 Eric Jarrige <eric.jarrige@armadeus.org> | |
5 | * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> | |
6 | * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de> | |
7 | * | |
8 | * (C) Copyright 2003 | |
9 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
10 | * | |
11 | * This file is based on mpc4200fec.h | |
12 | * (C) Copyright Motorola, Inc., 2000 | |
13 | * | |
1a459660 | 14 | * SPDX-License-Identifier: GPL-2.0+ |
0b23fb36 IY |
15 | */ |
16 | ||
0b23fb36 IY |
17 | #ifndef __FEC_MXC_H |
18 | #define __FEC_MXC_H | |
19 | ||
567173a6 | 20 | /* Layout description of the FEC */ |
0b23fb36 | 21 | struct ethernet_regs { |
567173a6 | 22 | /* [10:2]addr = 00 */ |
0b23fb36 | 23 | |
567173a6 | 24 | /* Control and status Registers (offset 000-1FF) */ |
0b23fb36 IY |
25 | uint32_t res0[1]; /* MBAR_ETH + 0x000 */ |
26 | uint32_t ievent; /* MBAR_ETH + 0x004 */ | |
27 | uint32_t imask; /* MBAR_ETH + 0x008 */ | |
28 | ||
29 | uint32_t res1[1]; /* MBAR_ETH + 0x00C */ | |
30 | uint32_t r_des_active; /* MBAR_ETH + 0x010 */ | |
31 | uint32_t x_des_active; /* MBAR_ETH + 0x014 */ | |
32 | uint32_t res2[3]; /* MBAR_ETH + 0x018-20 */ | |
33 | uint32_t ecntrl; /* MBAR_ETH + 0x024 */ | |
34 | ||
35 | uint32_t res3[6]; /* MBAR_ETH + 0x028-03C */ | |
36 | uint32_t mii_data; /* MBAR_ETH + 0x040 */ | |
37 | uint32_t mii_speed; /* MBAR_ETH + 0x044 */ | |
38 | uint32_t res4[7]; /* MBAR_ETH + 0x048-60 */ | |
39 | uint32_t mib_control; /* MBAR_ETH + 0x064 */ | |
40 | ||
41 | uint32_t res5[7]; /* MBAR_ETH + 0x068-80 */ | |
42 | uint32_t r_cntrl; /* MBAR_ETH + 0x084 */ | |
43 | uint32_t res6[15]; /* MBAR_ETH + 0x088-C0 */ | |
44 | uint32_t x_cntrl; /* MBAR_ETH + 0x0C4 */ | |
45 | uint32_t res7[7]; /* MBAR_ETH + 0x0C8-E0 */ | |
46 | uint32_t paddr1; /* MBAR_ETH + 0x0E4 */ | |
47 | uint32_t paddr2; /* MBAR_ETH + 0x0E8 */ | |
48 | uint32_t op_pause; /* MBAR_ETH + 0x0EC */ | |
49 | ||
50 | uint32_t res8[10]; /* MBAR_ETH + 0x0F0-114 */ | |
51 | uint32_t iaddr1; /* MBAR_ETH + 0x118 */ | |
52 | uint32_t iaddr2; /* MBAR_ETH + 0x11C */ | |
53 | uint32_t gaddr1; /* MBAR_ETH + 0x120 */ | |
54 | uint32_t gaddr2; /* MBAR_ETH + 0x124 */ | |
55 | uint32_t res9[7]; /* MBAR_ETH + 0x128-140 */ | |
56 | ||
57 | uint32_t x_wmrk; /* MBAR_ETH + 0x144 */ | |
58 | uint32_t res10[1]; /* MBAR_ETH + 0x148 */ | |
59 | uint32_t r_bound; /* MBAR_ETH + 0x14C */ | |
60 | uint32_t r_fstart; /* MBAR_ETH + 0x150 */ | |
61 | uint32_t res11[11]; /* MBAR_ETH + 0x154-17C */ | |
62 | uint32_t erdsr; /* MBAR_ETH + 0x180 */ | |
63 | uint32_t etdsr; /* MBAR_ETH + 0x184 */ | |
64 | uint32_t emrbr; /* MBAR_ETH + 0x188 */ | |
65 | uint32_t res12[29]; /* MBAR_ETH + 0x18C-1FC */ | |
66 | ||
567173a6 | 67 | /* MIB COUNTERS (Offset 200-2FF) */ |
0b23fb36 IY |
68 | uint32_t rmon_t_drop; /* MBAR_ETH + 0x200 */ |
69 | uint32_t rmon_t_packets; /* MBAR_ETH + 0x204 */ | |
70 | uint32_t rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */ | |
71 | uint32_t rmon_t_mc_pkt; /* MBAR_ETH + 0x20C */ | |
72 | uint32_t rmon_t_crc_align; /* MBAR_ETH + 0x210 */ | |
73 | uint32_t rmon_t_undersize; /* MBAR_ETH + 0x214 */ | |
74 | uint32_t rmon_t_oversize; /* MBAR_ETH + 0x218 */ | |
75 | uint32_t rmon_t_frag; /* MBAR_ETH + 0x21C */ | |
76 | uint32_t rmon_t_jab; /* MBAR_ETH + 0x220 */ | |
77 | uint32_t rmon_t_col; /* MBAR_ETH + 0x224 */ | |
78 | uint32_t rmon_t_p64; /* MBAR_ETH + 0x228 */ | |
79 | uint32_t rmon_t_p65to127; /* MBAR_ETH + 0x22C */ | |
80 | uint32_t rmon_t_p128to255; /* MBAR_ETH + 0x230 */ | |
81 | uint32_t rmon_t_p256to511; /* MBAR_ETH + 0x234 */ | |
82 | uint32_t rmon_t_p512to1023; /* MBAR_ETH + 0x238 */ | |
83 | uint32_t rmon_t_p1024to2047; /* MBAR_ETH + 0x23C */ | |
84 | uint32_t rmon_t_p_gte2048; /* MBAR_ETH + 0x240 */ | |
85 | uint32_t rmon_t_octets; /* MBAR_ETH + 0x244 */ | |
86 | uint32_t ieee_t_drop; /* MBAR_ETH + 0x248 */ | |
87 | uint32_t ieee_t_frame_ok; /* MBAR_ETH + 0x24C */ | |
88 | uint32_t ieee_t_1col; /* MBAR_ETH + 0x250 */ | |
89 | uint32_t ieee_t_mcol; /* MBAR_ETH + 0x254 */ | |
90 | uint32_t ieee_t_def; /* MBAR_ETH + 0x258 */ | |
91 | uint32_t ieee_t_lcol; /* MBAR_ETH + 0x25C */ | |
92 | uint32_t ieee_t_excol; /* MBAR_ETH + 0x260 */ | |
93 | uint32_t ieee_t_macerr; /* MBAR_ETH + 0x264 */ | |
94 | uint32_t ieee_t_cserr; /* MBAR_ETH + 0x268 */ | |
95 | uint32_t ieee_t_sqe; /* MBAR_ETH + 0x26C */ | |
96 | uint32_t t_fdxfc; /* MBAR_ETH + 0x270 */ | |
97 | uint32_t ieee_t_octets_ok; /* MBAR_ETH + 0x274 */ | |
98 | ||
99 | uint32_t res13[2]; /* MBAR_ETH + 0x278-27C */ | |
100 | uint32_t rmon_r_drop; /* MBAR_ETH + 0x280 */ | |
101 | uint32_t rmon_r_packets; /* MBAR_ETH + 0x284 */ | |
102 | uint32_t rmon_r_bc_pkt; /* MBAR_ETH + 0x288 */ | |
103 | uint32_t rmon_r_mc_pkt; /* MBAR_ETH + 0x28C */ | |
104 | uint32_t rmon_r_crc_align; /* MBAR_ETH + 0x290 */ | |
105 | uint32_t rmon_r_undersize; /* MBAR_ETH + 0x294 */ | |
106 | uint32_t rmon_r_oversize; /* MBAR_ETH + 0x298 */ | |
107 | uint32_t rmon_r_frag; /* MBAR_ETH + 0x29C */ | |
108 | uint32_t rmon_r_jab; /* MBAR_ETH + 0x2A0 */ | |
109 | ||
110 | uint32_t rmon_r_resvd_0; /* MBAR_ETH + 0x2A4 */ | |
111 | ||
112 | uint32_t rmon_r_p64; /* MBAR_ETH + 0x2A8 */ | |
113 | uint32_t rmon_r_p65to127; /* MBAR_ETH + 0x2AC */ | |
114 | uint32_t rmon_r_p128to255; /* MBAR_ETH + 0x2B0 */ | |
115 | uint32_t rmon_r_p256to511; /* MBAR_ETH + 0x2B4 */ | |
116 | uint32_t rmon_r_p512to1023; /* MBAR_ETH + 0x2B8 */ | |
117 | uint32_t rmon_r_p1024to2047; /* MBAR_ETH + 0x2BC */ | |
118 | uint32_t rmon_r_p_gte2048; /* MBAR_ETH + 0x2C0 */ | |
119 | uint32_t rmon_r_octets; /* MBAR_ETH + 0x2C4 */ | |
120 | uint32_t ieee_r_drop; /* MBAR_ETH + 0x2C8 */ | |
121 | uint32_t ieee_r_frame_ok; /* MBAR_ETH + 0x2CC */ | |
122 | uint32_t ieee_r_crc; /* MBAR_ETH + 0x2D0 */ | |
123 | uint32_t ieee_r_align; /* MBAR_ETH + 0x2D4 */ | |
124 | uint32_t r_macerr; /* MBAR_ETH + 0x2D8 */ | |
125 | uint32_t r_fdxfc; /* MBAR_ETH + 0x2DC */ | |
126 | uint32_t ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */ | |
127 | ||
740d6ae5 JR |
128 | uint32_t res14[7]; /* MBAR_ETH + 0x2E4-2FC */ |
129 | ||
7df51fd8 | 130 | #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) |
740d6ae5 JR |
131 | uint16_t miigsk_cfgr; /* MBAR_ETH + 0x300 */ |
132 | uint16_t res15[3]; /* MBAR_ETH + 0x302-306 */ | |
133 | uint16_t miigsk_enr; /* MBAR_ETH + 0x308 */ | |
134 | uint16_t res16[3]; /* MBAR_ETH + 0x30a-30e */ | |
135 | uint32_t res17[60]; /* MBAR_ETH + 0x300-3FF */ | |
136 | #else | |
0b23fb36 | 137 | uint32_t res15[64]; /* MBAR_ETH + 0x300-3FF */ |
740d6ae5 | 138 | #endif |
0b23fb36 IY |
139 | }; |
140 | ||
141 | #define FEC_IEVENT_HBERR 0x80000000 | |
142 | #define FEC_IEVENT_BABR 0x40000000 | |
143 | #define FEC_IEVENT_BABT 0x20000000 | |
144 | #define FEC_IEVENT_GRA 0x10000000 | |
145 | #define FEC_IEVENT_TXF 0x08000000 | |
146 | #define FEC_IEVENT_TXB 0x04000000 | |
147 | #define FEC_IEVENT_RXF 0x02000000 | |
148 | #define FEC_IEVENT_RXB 0x01000000 | |
149 | #define FEC_IEVENT_MII 0x00800000 | |
150 | #define FEC_IEVENT_EBERR 0x00400000 | |
151 | #define FEC_IEVENT_LC 0x00200000 | |
152 | #define FEC_IEVENT_RL 0x00100000 | |
153 | #define FEC_IEVENT_UN 0x00080000 | |
154 | ||
155 | #define FEC_IMASK_HBERR 0x80000000 | |
156 | #define FEC_IMASK_BABR 0x40000000 | |
157 | #define FEC_IMASKT_BABT 0x20000000 | |
158 | #define FEC_IMASK_GRA 0x10000000 | |
159 | #define FEC_IMASKT_TXF 0x08000000 | |
160 | #define FEC_IMASK_TXB 0x04000000 | |
161 | #define FEC_IMASKT_RXF 0x02000000 | |
162 | #define FEC_IMASK_RXB 0x01000000 | |
163 | #define FEC_IMASK_MII 0x00800000 | |
164 | #define FEC_IMASK_EBERR 0x00400000 | |
165 | #define FEC_IMASK_LC 0x00200000 | |
166 | #define FEC_IMASKT_RL 0x00100000 | |
167 | #define FEC_IMASK_UN 0x00080000 | |
168 | ||
0b23fb36 IY |
169 | #define FEC_RCNTRL_MAX_FL_SHIFT 16 |
170 | #define FEC_RCNTRL_LOOP 0x00000001 | |
171 | #define FEC_RCNTRL_DRT 0x00000002 | |
172 | #define FEC_RCNTRL_MII_MODE 0x00000004 | |
173 | #define FEC_RCNTRL_PROM 0x00000008 | |
174 | #define FEC_RCNTRL_BC_REJ 0x00000010 | |
175 | #define FEC_RCNTRL_FCE 0x00000020 | |
2ef2b950 | 176 | #define FEC_RCNTRL_RGMII 0x00000040 |
a50a90c9 | 177 | #define FEC_RCNTRL_RMII 0x00000100 |
28774cba | 178 | #define FEC_RCNTRL_RMII_10T 0x00000200 |
0b23fb36 IY |
179 | |
180 | #define FEC_TCNTRL_GTS 0x00000001 | |
181 | #define FEC_TCNTRL_HBC 0x00000002 | |
182 | #define FEC_TCNTRL_FDEN 0x00000004 | |
183 | #define FEC_TCNTRL_TFC_PAUSE 0x00000008 | |
184 | #define FEC_TCNTRL_RFC_PAUSE 0x00000010 | |
185 | ||
186 | #define FEC_ECNTRL_RESET 0x00000001 /* reset the FEC */ | |
187 | #define FEC_ECNTRL_ETHER_EN 0x00000002 /* enable the FEC */ | |
28774cba | 188 | #define FEC_ECNTRL_SPEED 0x00000020 |
2ef2b950 JL |
189 | #define FEC_ECNTRL_DBSWAP 0x00000100 |
190 | ||
191 | #define FEC_X_WMRK_STRFWD 0x00000100 | |
0b23fb36 | 192 | |
c0b5a3bb MV |
193 | #define FEC_X_DES_ACTIVE_TDAR 0x01000000 |
194 | #define FEC_R_DES_ACTIVE_RDAR 0x01000000 | |
195 | ||
7df51fd8 | 196 | #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) |
740d6ae5 JR |
197 | /* defines for MIIGSK */ |
198 | /* RMII frequency control: 0=50MHz, 1=5MHz */ | |
199 | #define MIIGSK_CFGR_FRCONT (1 << 6) | |
200 | /* loopback mode */ | |
201 | #define MIIGSK_CFGR_LBMODE (1 << 4) | |
202 | /* echo mode */ | |
203 | #define MIIGSK_CFGR_EMODE (1 << 3) | |
204 | /* MII gasket mode field */ | |
205 | #define MIIGSK_CFGR_IF_MODE_MASK (3 << 0) | |
206 | /* MMI/7-Wire mode */ | |
207 | #define MIIGSK_CFGR_IF_MODE_MII (0 << 0) | |
208 | /* RMII mode */ | |
209 | #define MIIGSK_CFGR_IF_MODE_RMII (1 << 0) | |
210 | /* reflects MIIGSK Enable bit (RO) */ | |
211 | #define MIIGSK_ENR_READY (1 << 2) | |
212 | /* enable MIGSK (set by default) */ | |
213 | #define MIIGSK_ENR_EN (1 << 1) | |
214 | #endif | |
215 | ||
0b23fb36 IY |
216 | /** |
217 | * @brief Receive & Transmit Buffer Descriptor definitions | |
218 | * | |
219 | * Note: The first BD must be aligned (see DB_ALIGNMENT) | |
220 | */ | |
221 | struct fec_bd { | |
222 | uint16_t data_length; /* payload's length in bytes */ | |
223 | uint16_t status; /* BD's staus (see datasheet) */ | |
224 | uint32_t data_pointer; /* payload's buffer address */ | |
225 | }; | |
226 | ||
567173a6 | 227 | /* Supported phy types on this platform */ |
0b23fb36 IY |
228 | enum xceiver_type { |
229 | SEVENWIRE, /* 7-wire */ | |
230 | MII10, /* MII 10Mbps */ | |
a50a90c9 | 231 | MII100, /* MII 100Mbps */ |
2ef2b950 JL |
232 | RMII, /* RMII */ |
233 | RGMII, /* RGMII */ | |
0b23fb36 IY |
234 | }; |
235 | ||
567173a6 | 236 | /* @brief i.MX27-FEC private structure */ |
0b23fb36 IY |
237 | struct fec_priv { |
238 | struct ethernet_regs *eth; /* pointer to register'S base */ | |
239 | enum xceiver_type xcv_type; /* transceiver type */ | |
240 | struct fec_bd *rbd_base; /* RBD ring */ | |
241 | int rbd_index; /* next receive BD to read */ | |
242 | struct fec_bd *tbd_base; /* TBD ring */ | |
243 | int tbd_index; /* next transmit BD to write */ | |
244 | bd_t *bd; | |
5c1ad3e6 | 245 | uint8_t *tdb_ptr; |
9e27e9dc | 246 | int dev_id; |
13947f43 TK |
247 | struct mii_dev *bus; |
248 | #ifdef CONFIG_PHYLIB | |
249 | struct phy_device *phydev; | |
250 | #else | |
fe428b90 | 251 | int phy_id; |
2e5f4421 | 252 | int (*mii_postcall)(int); |
13947f43 | 253 | #endif |
60752ca8 JT |
254 | |
255 | #ifdef CONFIG_DM_ETH | |
256 | u32 interface; | |
257 | #endif | |
0b23fb36 IY |
258 | }; |
259 | ||
567173a6 JT |
260 | void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); |
261 | ||
0b23fb36 IY |
262 | /** |
263 | * @brief Numbers of buffer descriptors for receiving | |
264 | * | |
265 | * The number defines the stocked memory buffers for the receiving task. | |
266 | * Larger values makes no sense in this limited environment. | |
267 | */ | |
268 | #define FEC_RBD_NUM 64 | |
269 | ||
270 | /** | |
271 | * @brief Define the ethernet packet size limit in memory | |
272 | * | |
273 | * Note: Do not shrink this number. This will force the FEC to spread larger | |
274 | * frames in more than one BD. This is nothing to worry about, but the current | |
275 | * driver can't handle it. | |
276 | */ | |
277 | #define FEC_MAX_PKT_SIZE 1536 | |
278 | ||
279 | /* Receive BD status bits */ | |
280 | #define FEC_RBD_EMPTY 0x8000 /* Receive BD status: Buffer is empty */ | |
281 | #define FEC_RBD_WRAP 0x2000 /* Receive BD status: Last BD in ring */ | |
282 | /* Receive BD status: Buffer is last in frame (useless here!) */ | |
283 | #define FEC_RBD_LAST 0x0800 | |
284 | #define FEC_RBD_MISS 0x0100 /* Receive BD status: Miss bit for prom mode */ | |
285 | /* Receive BD status: The received frame is broadcast frame */ | |
286 | #define FEC_RBD_BC 0x0080 | |
287 | /* Receive BD status: The received frame is multicast frame */ | |
288 | #define FEC_RBD_MC 0x0040 | |
289 | #define FEC_RBD_LG 0x0020 /* Receive BD status: Frame length violation */ | |
290 | #define FEC_RBD_NO 0x0010 /* Receive BD status: Nonoctet align frame */ | |
291 | #define FEC_RBD_CR 0x0004 /* Receive BD status: CRC error */ | |
292 | #define FEC_RBD_OV 0x0002 /* Receive BD status: Receive FIFO overrun */ | |
293 | #define FEC_RBD_TR 0x0001 /* Receive BD status: Frame is truncated */ | |
294 | #define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \ | |
295 | FEC_RBD_OV | FEC_RBD_TR) | |
296 | ||
297 | /* Transmit BD status bits */ | |
298 | #define FEC_TBD_READY 0x8000 /* Tansmit BD status: Buffer is ready */ | |
299 | #define FEC_TBD_WRAP 0x2000 /* Tansmit BD status: Mark as last BD in ring */ | |
300 | #define FEC_TBD_LAST 0x0800 /* Tansmit BD status: Buffer is last in frame */ | |
301 | #define FEC_TBD_TC 0x0400 /* Tansmit BD status: Transmit the CRC */ | |
302 | #define FEC_TBD_ABC 0x0200 /* Tansmit BD status: Append bad CRC */ | |
303 | ||
304 | /* MII-related definitios */ | |
305 | #define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */ | |
306 | #define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */ | |
307 | #define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */ | |
308 | #define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */ | |
309 | #define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */ | |
310 | #define FEC_MII_DATA_TA 0x00020000 /* Turnaround */ | |
311 | #define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */ | |
312 | ||
313 | #define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */ | |
314 | #define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */ | |
315 | ||
316 | #endif /* __FEC_MXC_H */ |