[people/ms/u-boot.git] / drivers / net / fm / memac.c

/*
 * Copyright 2012 Freescale Semiconductor, Inc.
 *	Roy Zang <tie-fei.zang@freescale.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/* MAXFRM - maximum frame length */
#define MAXFRM_MASK	0x0000ffff

#include <common.h>
#include <phy.h>
#include <asm/types.h>
#include <asm/io.h>
#include <fsl_memac.h>

#include "fm.h"

static void memac_init_mac(struct fsl_enet_mac *mac)
{
	struct memac *regs = mac->base;

	/* mask all interrupt */
	out_be32(&regs->imask, IMASK_MASK_ALL);

	/* clear all events */
	out_be32(&regs->ievent, IEVENT_CLEAR_ALL);

	/* set the max receive length */
	out_be32(&regs->maxfrm, mac->max_rx_len & MAXFRM_MASK);

	/* multicast frame reception for the hash entry disable */
	out_be32(&regs->hashtable_ctrl, 0);
}

static void memac_enable_mac(struct fsl_enet_mac *mac)
{
	struct memac *regs = mac->base;

	setbits_be32(&regs->command_config,
		     MEMAC_CMD_CFG_RXTX_EN | MEMAC_CMD_CFG_NO_LEN_CHK);
}

static void memac_disable_mac(struct fsl_enet_mac *mac)
{
	struct memac *regs = mac->base;

	clrbits_be32(&regs->command_config, MEMAC_CMD_CFG_RXTX_EN);
}

static void memac_set_mac_addr(struct fsl_enet_mac *mac, u8 *mac_addr)
{
	struct memac *regs = mac->base;
	u32 mac_addr0, mac_addr1;

	/*
	 * if a station address of 0x12345678ABCD, perform a write to
	 * MAC_ADDR0 of 0x78563412, MAC_ADDR1 of 0x0000CDAB
	 */
	mac_addr0 = (mac_addr[3] << 24) | (mac_addr[2] << 16) | \
			(mac_addr[1] << 8)  | (mac_addr[0]);
	out_be32(&regs->mac_addr_0, mac_addr0);

	mac_addr1 = ((mac_addr[5] << 8) | mac_addr[4]) & 0x0000ffff;
	out_be32(&regs->mac_addr_1, mac_addr1);
}

static void memac_set_interface_mode(struct fsl_enet_mac *mac,
					phy_interface_t type, int speed)
{
	/* Roy need more work here */

	struct memac *regs = mac->base;
	u32 if_mode, if_status;

	/* clear all bits relative with interface mode */
	if_mode = in_be32(&regs->if_mode);
	if_status = in_be32(&regs->if_status);

	/* set interface mode */
	switch (type) {
	case PHY_INTERFACE_MODE_GMII:
		if_mode &= ~IF_MODE_MASK;
		if_mode |= IF_MODE_GMII;
		break;
	case PHY_INTERFACE_MODE_RGMII:
		if_mode |= (IF_MODE_GMII | IF_MODE_RG);
		break;
	case PHY_INTERFACE_MODE_RMII:
		if_mode |= (IF_MODE_GMII | IF_MODE_RM);
		break;
	case PHY_INTERFACE_MODE_SGMII:
	case PHY_INTERFACE_MODE_QSGMII:
		if_mode &= ~IF_MODE_MASK;
		if_mode |= (IF_MODE_GMII);
		break;
	case PHY_INTERFACE_MODE_XGMII:
		if_mode &= ~IF_MODE_MASK;
		if_mode |= IF_MODE_XGMII;
		break;
	default:
		break;
	}
	/* Enable automatic speed selection for Non-XGMII */
	if (type != PHY_INTERFACE_MODE_XGMII)
		if_mode |= IF_MODE_EN_AUTO;

	if (type == PHY_INTERFACE_MODE_RGMII) {
		if_mode &= ~IF_MODE_EN_AUTO;
		if_mode &= ~IF_MODE_SETSP_MASK;
		switch (speed) {
		case SPEED_1000:
			if_mode |= IF_MODE_SETSP_1000M;
			break;
		case SPEED_100:
			if_mode |= IF_MODE_SETSP_100M;
			break;
		case SPEED_10:
			if_mode |= IF_MODE_SETSP_10M;
		default:
			break;
		}
	}

	debug(" %s, if_mode = %x\n", __func__,  if_mode);
	debug(" %s, if_status = %x\n", __func__,  if_status);
	out_be32(&regs->if_mode, if_mode);
	return;
}

void init_memac(struct fsl_enet_mac *mac, void *base,
		void *phyregs, int max_rx_len)
{
	mac->base = base;
	mac->phyregs = phyregs;
	mac->max_rx_len = max_rx_len;
	mac->init_mac = memac_init_mac;
	mac->enable_mac = memac_enable_mac;
	mac->disable_mac = memac_disable_mac;
	mac->set_mac_addr = memac_set_mac_addr;
	mac->set_if_mode = memac_set_interface_mode;
}
Commit	Line	Data
111fd19e RZ	1	/*
	2	* Copyright 2012 Freescale Semiconductor, Inc.
	3	* Roy Zang <tie-fei.zang@freescale.com>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
111fd19e RZ	6	*/
	7
	8	/* MAXFRM - maximum frame length */
	9	#define MAXFRM_MASK 0x0000ffff
	10
	11	#include <common.h>
	12	#include <phy.h>
	13	#include <asm/types.h>
	14	#include <asm/io.h>
cd348efa	15	#include <fsl_memac.h>
111fd19e RZ	16
	17	#include "fm.h"
	18
	19	static void memac_init_mac(struct fsl_enet_mac *mac)
	20	{
	21	struct memac *regs = mac->base;
	22
	23	/* mask all interrupt */
	24	out_be32(&regs->imask, IMASK_MASK_ALL);
	25
	26	/* clear all events */
	27	out_be32(&regs->ievent, IEVENT_CLEAR_ALL);
	28
	29	/* set the max receive length */
	30	out_be32(&regs->maxfrm, mac->max_rx_len & MAXFRM_MASK);
	31
	32	/* multicast frame reception for the hash entry disable */
	33	out_be32(&regs->hashtable_ctrl, 0);
	34	}
	35
	36	static void memac_enable_mac(struct fsl_enet_mac *mac)
	37	{
	38	struct memac *regs = mac->base;
	39
ff5fb2a3 SX	40	setbits_be32(&regs->command_config,
ff5fb2a3 SX	41	MEMAC_CMD_CFG_RXTX_EN \| MEMAC_CMD_CFG_NO_LEN_CHK);
111fd19e RZ	42	}
	43
	44	static void memac_disable_mac(struct fsl_enet_mac *mac)
	45	{
	46	struct memac *regs = mac->base;
	47
	48	clrbits_be32(&regs->command_config, MEMAC_CMD_CFG_RXTX_EN);
	49	}
	50
	51	static void memac_set_mac_addr(struct fsl_enet_mac mac, u8 mac_addr)
	52	{
	53	struct memac *regs = mac->base;
	54	u32 mac_addr0, mac_addr1;
	55
	56	/*
	57	* if a station address of 0x12345678ABCD, perform a write to
	58	* MAC_ADDR0 of 0x78563412, MAC_ADDR1 of 0x0000CDAB
	59	*/
	60	mac_addr0 = (mac_addr[3] << 24) \| (mac_addr[2] << 16) \| \
	61	(mac_addr[1] << 8) \| (mac_addr[0]);
	62	out_be32(&regs->mac_addr_0, mac_addr0);
	63
	64	mac_addr1 = ((mac_addr[5] << 8) \| mac_addr[4]) & 0x0000ffff;
	65	out_be32(&regs->mac_addr_1, mac_addr1);
	66	}
	67
	68	static void memac_set_interface_mode(struct fsl_enet_mac *mac,
	69	phy_interface_t type, int speed)
	70	{
	71	/* Roy need more work here */
	72
	73	struct memac *regs = mac->base;
	74	u32 if_mode, if_status;
	75
	76	/* clear all bits relative with interface mode */
	77	if_mode = in_be32(&regs->if_mode);
	78	if_status = in_be32(&regs->if_status);
	79
	80	/* set interface mode */
	81	switch (type) {
	82	case PHY_INTERFACE_MODE_GMII:
	83	if_mode &= ~IF_MODE_MASK;
	84	if_mode \|= IF_MODE_GMII;
	85	break;
	86	case PHY_INTERFACE_MODE_RGMII:
	87	if_mode \|= (IF_MODE_GMII \| IF_MODE_RG);
	88	break;
	89	case PHY_INTERFACE_MODE_RMII:
	90	if_mode \|= (IF_MODE_GMII \| IF_MODE_RM);
	91	break;
	92	case PHY_INTERFACE_MODE_SGMII:
1c68d01e	93	case PHY_INTERFACE_MODE_QSGMII:
111fd19e RZ	94	if_mode &= ~IF_MODE_MASK;
	95	if_mode \|= (IF_MODE_GMII);
	96	break;
ff5fb2a3 SX	97	case PHY_INTERFACE_MODE_XGMII:
	98	if_mode &= ~IF_MODE_MASK;
	99	if_mode \|= IF_MODE_XGMII;
	100	break;
111fd19e RZ	101	default:
	102	break;
	103	}
ff5fb2a3 SX	104	/* Enable automatic speed selection for Non-XGMII */
	105	if (type != PHY_INTERFACE_MODE_XGMII)
	106	if_mode \|= IF_MODE_EN_AUTO;
111fd19e	107
c5729f0b ZRR	108	if (type == PHY_INTERFACE_MODE_RGMII) {
	109	if_mode &= ~IF_MODE_EN_AUTO;
	110	if_mode &= ~IF_MODE_SETSP_MASK;
	111	switch (speed) {
	112	case SPEED_1000:
	113	if_mode \|= IF_MODE_SETSP_1000M;
	114	break;
	115	case SPEED_100:
	116	if_mode \|= IF_MODE_SETSP_100M;
	117	break;
	118	case SPEED_10:
	119	if_mode \|= IF_MODE_SETSP_10M;
	120	default:
	121	break;
	122	}
	123	}
	124
111fd19e RZ	125	debug(" %s, if_mode = %x\n", __func__, if_mode);
	126	debug(" %s, if_status = %x\n", __func__, if_status);
	127	out_be32(&regs->if_mode, if_mode);
	128	return;
	129	}
	130
	131	void init_memac(struct fsl_enet_mac mac, void base,
	132	void *phyregs, int max_rx_len)
	133	{
	134	mac->base = base;
	135	mac->phyregs = phyregs;
	136	mac->max_rx_len = max_rx_len;
	137	mac->init_mac = memac_init_mac;
	138	mac->enable_mac = memac_enable_mac;
	139	mac->disable_mac = memac_disable_mac;
	140	mac->set_mac_addr = memac_set_mac_addr;
	141	mac->set_if_mode = memac_set_interface_mode;
	142	}