projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| c916d7c9 KG |
1 | /* |
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
| 3 | * | |
| 1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| c916d7c9 KG |
5 | */ |
| 6 | #include <common.h> | |
| 7 | #include <phy.h> | |
| 8 | #include <fm_eth.h> | |
| 9 | #include <asm/io.h> | |
| 10 | #include <asm/immap_85xx.h> | |
| 11 | #include <asm/fsl_serdes.h> | |
| 12 | ||
| 960d70c6 | 13 | static u32 port_to_devdisr[] = { |
| c916d7c9 KG |
14 | [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, |
| 15 | [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, | |
| 16 | [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, | |
| 17 | [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, | |
| 18 | [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1, | |
| 19 | [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1, | |
| 20 | [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2, | |
| 21 | [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3, | |
| 22 | [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4, | |
| 23 | [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2, | |
| 24 | }; | |
| 25 | ||
| 26 | static int is_device_disabled(enum fm_port port) | |
| 27 | { | |
| 28 | ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); | |
| 29 | u32 devdisr2 = in_be32(&gur->devdisr2); | |
| 30 | ||
| 31 | return port_to_devdisr[port] & devdisr2; | |
| 32 | } | |
| 33 | ||
| 69a85242 KG |
34 | void fman_disable_port(enum fm_port port) |
| 35 | { | |
| 36 | ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); | |
| f5b9e736 KG |
37 | |
| 38 | /* don't allow disabling of DTSEC1 as its needed for MDIO */ | |
| 39 | if (port == FM1_DTSEC1) | |
| 40 | return; | |
| 41 | ||
| 69a85242 KG |
42 | setbits_be32(&gur->devdisr2, port_to_devdisr[port]); |
| 43 | } | |
| 44 | ||
| c916d7c9 KG |
45 | phy_interface_t fman_port_enet_if(enum fm_port port) |
| 46 | { | |
| 47 | ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); | |
| 48 | u32 rcwsr11 = in_be32(&gur->rcwsr[11]); | |
| 49 | ||
| 50 | if (is_device_disabled(port)) | |
| 51 | return PHY_INTERFACE_MODE_NONE; | |
| 52 | ||
| 53 | if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1))) | |
| 54 | return PHY_INTERFACE_MODE_XGMII; | |
| 55 | ||
| 56 | if ((port == FM2_10GEC1) && (is_serdes_configured(XAUI_FM2))) | |
| 57 | return PHY_INTERFACE_MODE_XGMII; | |
| 58 | ||
| 59 | /* handle RGMII first */ | |
| 60 | if ((port == FM1_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == | |
| 61 | FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1)) | |
| 62 | return PHY_INTERFACE_MODE_RGMII; | |
| 63 | ||
| 64 | if ((port == FM1_DTSEC2) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == | |
| 65 | FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2)) | |
| 66 | return PHY_INTERFACE_MODE_RGMII; | |
| 67 | ||
| 68 | if ((port == FM2_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == | |
| 69 | FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1)) | |
| 70 | return PHY_INTERFACE_MODE_RGMII; | |
| 71 | ||
| 72 | switch (port) { | |
| 73 | case FM1_DTSEC1: | |
| 74 | case FM1_DTSEC2: | |
| 75 | case FM1_DTSEC3: | |
| 76 | case FM1_DTSEC4: | |
| 77 | if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) | |
| 78 | return PHY_INTERFACE_MODE_SGMII; | |
| 79 | break; | |
| 80 | case FM2_DTSEC1: | |
| 81 | case FM2_DTSEC2: | |
| 82 | case FM2_DTSEC3: | |
| 83 | case FM2_DTSEC4: | |
| 84 | if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1)) | |
| 85 | return PHY_INTERFACE_MODE_SGMII; | |
| 86 | break; | |
| 87 | default: | |
| 88 | return PHY_INTERFACE_MODE_NONE; | |
| 89 | } | |
| 90 | ||
| 91 | return PHY_INTERFACE_MODE_NONE; | |
| 92 | } |