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c916d7c9 KG |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
c916d7c9 KG |
5 | */ |
6 | #include <common.h> | |
7 | #include <phy.h> | |
8 | #include <fm_eth.h> | |
9 | #include <asm/io.h> | |
10 | #include <asm/immap_85xx.h> | |
11 | #include <asm/fsl_serdes.h> | |
12 | ||
960d70c6 | 13 | static u32 port_to_devdisr[] = { |
c916d7c9 KG |
14 | [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, |
15 | [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, | |
16 | [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, | |
17 | [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, | |
18 | [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5, | |
19 | [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1, | |
20 | }; | |
21 | ||
22 | static int is_device_disabled(enum fm_port port) | |
23 | { | |
24 | ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); | |
25 | u32 devdisr2 = in_be32(&gur->devdisr2); | |
26 | ||
27 | return port_to_devdisr[port] & devdisr2; | |
28 | } | |
29 | ||
69a85242 KG |
30 | void fman_disable_port(enum fm_port port) |
31 | { | |
32 | ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); | |
f5b9e736 KG |
33 | |
34 | /* don't allow disabling of DTSEC1 as its needed for MDIO */ | |
35 | if (port == FM1_DTSEC1) | |
36 | return; | |
37 | ||
69a85242 KG |
38 | setbits_be32(&gur->devdisr2, port_to_devdisr[port]); |
39 | } | |
40 | ||
f51d3b71 VL |
41 | void fman_enable_port(enum fm_port port) |
42 | { | |
43 | ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); | |
44 | ||
45 | clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); | |
46 | } | |
47 | ||
c916d7c9 KG |
48 | phy_interface_t fman_port_enet_if(enum fm_port port) |
49 | { | |
50 | ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); | |
51 | u32 rcwsr11 = in_be32(&gur->rcwsr[11]); | |
52 | ||
53 | if (is_device_disabled(port)) | |
54 | return PHY_INTERFACE_MODE_NONE; | |
55 | ||
56 | if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1))) | |
57 | return PHY_INTERFACE_MODE_XGMII; | |
58 | ||
59 | /* handle RGMII first */ | |
60 | if ((port == FM1_DTSEC4) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == | |
61 | FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII)) | |
62 | return PHY_INTERFACE_MODE_RGMII; | |
63 | ||
64 | if ((port == FM1_DTSEC4) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == | |
65 | FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII)) | |
66 | return PHY_INTERFACE_MODE_MII; | |
67 | ||
68 | if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == | |
69 | FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII)) | |
70 | return PHY_INTERFACE_MODE_RGMII; | |
71 | ||
72 | if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == | |
73 | FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII)) | |
74 | return PHY_INTERFACE_MODE_MII; | |
75 | ||
76 | switch (port) { | |
77 | case FM1_DTSEC1: | |
78 | case FM1_DTSEC2: | |
79 | case FM1_DTSEC3: | |
80 | case FM1_DTSEC4: | |
81 | case FM1_DTSEC5: | |
82 | if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) | |
83 | return PHY_INTERFACE_MODE_SGMII; | |
84 | break; | |
85 | default: | |
86 | return PHY_INTERFACE_MODE_NONE; | |
87 | } | |
88 | ||
89 | return PHY_INTERFACE_MODE_NONE; | |
90 | } |