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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
7d436078 PK |
2 | /* |
3 | * Copyright 2013 Freescale Semiconductor, Inc. | |
7d436078 PK |
4 | */ |
5 | #include <common.h> | |
6 | #include <phy.h> | |
7 | #include <fm_eth.h> | |
8 | #include <asm/io.h> | |
9 | #include <asm/immap_85xx.h> | |
10 | #include <asm/fsl_serdes.h> | |
11 | ||
12 | phy_interface_t fman_port_enet_if(enum fm_port port) | |
13 | { | |
5b7672fc PK |
14 | ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
15 | u32 rcwsr13 = in_be32(&gur->rcwsr[13]); | |
16 | ||
17 | /* handle RGMII first */ | |
18 | if ((port == FM1_DTSEC2) && | |
19 | ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) == | |
20 | FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT)) { | |
21 | if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == | |
22 | FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII) | |
23 | return PHY_INTERFACE_MODE_RGMII; | |
24 | else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == | |
25 | FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII) | |
26 | return PHY_INTERFACE_MODE_MII; | |
5b7672fc PK |
27 | } |
28 | ||
29 | if ((port == FM1_DTSEC4) && | |
30 | ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) == | |
31 | FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH)) { | |
32 | if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == | |
33 | FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII) | |
34 | return PHY_INTERFACE_MODE_RGMII; | |
35 | else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == | |
36 | FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII) | |
37 | return PHY_INTERFACE_MODE_MII; | |
5b7672fc PK |
38 | } |
39 | ||
40 | if (port == FM1_DTSEC5) { | |
41 | if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == | |
42 | FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII) | |
43 | return PHY_INTERFACE_MODE_RGMII; | |
44 | else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == | |
45 | FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII) | |
46 | return PHY_INTERFACE_MODE_MII; | |
5b7672fc PK |
47 | } |
48 | ||
49 | switch (port) { | |
50 | case FM1_DTSEC1: | |
51 | case FM1_DTSEC2: | |
27b57569 CC |
52 | if (is_serdes_configured(QSGMII_SW1_A + port - FM1_DTSEC1) || |
53 | is_serdes_configured(SGMII_SW1_MAC1 + port - FM1_DTSEC1)) | |
5b7672fc PK |
54 | return PHY_INTERFACE_MODE_QSGMII; |
55 | case FM1_DTSEC3: | |
56 | case FM1_DTSEC4: | |
57 | case FM1_DTSEC5: | |
58 | if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) | |
59 | return PHY_INTERFACE_MODE_SGMII; | |
60 | break; | |
61 | default: | |
62 | return PHY_INTERFACE_MODE_NONE; | |
63 | } | |
64 | ||
7d436078 PK |
65 | return PHY_INTERFACE_MODE_NONE; |
66 | } |