[thirdparty/u-boot.git] / drivers / net / greth.c

/* Gaisler.com GRETH 10/100/1000 Ethernet MAC driver
 *
 * Driver use polling mode (no Interrupt)
 *
 * (C) Copyright 2007
 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/* #define DEBUG */

#include <common.h>
#include <command.h>
#include <errno.h>
#include <net.h>
#include <netdev.h>
#include <malloc.h>
#include <asm/processor.h>
#include <ambapp.h>
#include <asm/leon.h>

#include "greth.h"

/* Default to 3s timeout on autonegotiation */
#ifndef GRETH_PHY_TIMEOUT_MS
#define GRETH_PHY_TIMEOUT_MS 3000
#endif

/* Default to PHY adrress 0 not not specified */
#ifdef CONFIG_SYS_GRLIB_GRETH_PHYADDR
#define GRETH_PHY_ADR_DEFAULT CONFIG_SYS_GRLIB_GRETH_PHYADDR
#else
#define GRETH_PHY_ADR_DEFAULT 0
#endif

/* ByPass Cache when reading regs */
#define GRETH_REGLOAD(addr)		SPARC_NOCACHE_READ(addr)
/* Write-through cache ==> no bypassing needed on writes */
#define GRETH_REGSAVE(addr,data) (*(volatile unsigned int *)(addr) = (data))
#define GRETH_REGORIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)|data)
#define GRETH_REGANDIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)&data)

#define GRETH_RXBD_CNT 4
#define GRETH_TXBD_CNT 1

#define GRETH_RXBUF_SIZE 1540
#define GRETH_BUF_ALIGN 4
#define GRETH_RXBUF_EFF_SIZE \
	( (GRETH_RXBUF_SIZE&~(GRETH_BUF_ALIGN-1))+GRETH_BUF_ALIGN )

typedef struct {
	greth_regs *regs;
	int irq;
	struct eth_device *dev;

	/* Hardware info */
	unsigned char phyaddr;
	int gbit_mac;

	/* Current operating Mode */
	int gb;			/* GigaBit */
	int fd;			/* Full Duplex */
	int sp;			/* 10/100Mbps speed (1=100,0=10) */
	int auto_neg;		/* Auto negotiate done */

	unsigned char hwaddr[6];	/* MAC Address */

	/* Descriptors */
	greth_bd *rxbd_base, *rxbd_max;
	greth_bd *txbd_base, *txbd_max;

	greth_bd *rxbd_curr;

	/* rx buffers in rx descriptors */
	void *rxbuf_base;	/* (GRETH_RXBUF_SIZE+ALIGNBYTES) * GRETH_RXBD_CNT */

	/* unused for gbit_mac, temp buffer for sending packets with unligned
	 * start.
	 * Pointer to packet allocated with malloc.
	 */
	void *txbuf;

	struct {
		/* rx status */
		unsigned int rx_packets,
		    rx_crc_errors, rx_frame_errors, rx_length_errors, rx_errors;

		/* tx stats */
		unsigned int tx_packets,
		    tx_latecol_errors,
		    tx_underrun_errors, tx_limit_errors, tx_errors;
	} stats;
} greth_priv;

/* Read MII register 'addr' from core 'regs' */
static int read_mii(int phyaddr, int regaddr, volatile greth_regs * regs)
{
	while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {
	}

	GRETH_REGSAVE(&regs->mdio, ((phyaddr & 0x1F) << 11) | ((regaddr & 0x1F) << 6) | 2);

	while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {
	}

	if (!(GRETH_REGLOAD(&regs->mdio) & GRETH_MII_NVALID)) {
		return (GRETH_REGLOAD(&regs->mdio) >> 16) & 0xFFFF;
	} else {
		return -1;
	}
}

static void write_mii(int phyaddr, int regaddr, int data, volatile greth_regs * regs)
{
	while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {
	}

	GRETH_REGSAVE(&regs->mdio,
		      ((data & 0xFFFF) << 16) | ((phyaddr & 0x1F) << 11) |
		      ((regaddr & 0x1F) << 6) | 1);

	while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {
	}

}

/* init/start hardware and allocate descriptor buffers for rx side
 *
 */
int greth_init(struct eth_device *dev, bd_t * bis)
{
	int i;

	greth_priv *greth = dev->priv;
	greth_regs *regs = greth->regs;

	debug("greth_init\n");

	/* Reset core */
	GRETH_REGSAVE(&regs->control, (GRETH_RESET | (greth->gb << 8) |
		(greth->sp << 7) | (greth->fd << 4)));

	/* Wait for Reset to complete */
	while ( GRETH_REGLOAD(&regs->control) & GRETH_RESET) ;

	GRETH_REGSAVE(&regs->control,
		((greth->gb << 8) | (greth->sp << 7) | (greth->fd << 4)));

	if (!greth->rxbd_base) {

		/* allocate descriptors */
		greth->rxbd_base = (greth_bd *)
		    memalign(0x1000, GRETH_RXBD_CNT * sizeof(greth_bd));
		greth->txbd_base = (greth_bd *)
		    memalign(0x1000, GRETH_TXBD_CNT * sizeof(greth_bd));

		/* allocate buffers to all descriptors  */
		greth->rxbuf_base =
		    malloc(GRETH_RXBUF_EFF_SIZE * GRETH_RXBD_CNT);
	}

	/* initate rx decriptors */
	for (i = 0; i < GRETH_RXBD_CNT; i++) {
		greth->rxbd_base[i].addr = (unsigned int)
		    greth->rxbuf_base + (GRETH_RXBUF_EFF_SIZE * i);
		/* enable desciptor & set wrap bit if last descriptor */
		if (i >= (GRETH_RXBD_CNT - 1)) {
			greth->rxbd_base[i].stat = GRETH_BD_EN | GRETH_BD_WR;
		} else {
			greth->rxbd_base[i].stat = GRETH_BD_EN;
		}
	}

	/* initiate indexes */
	greth->rxbd_curr = greth->rxbd_base;
	greth->rxbd_max = greth->rxbd_base + (GRETH_RXBD_CNT - 1);
	greth->txbd_max = greth->txbd_base + (GRETH_TXBD_CNT - 1);
	/*
	 * greth->txbd_base->addr = 0;
	 * greth->txbd_base->stat = GRETH_BD_WR;
	 */

	/* initate tx decriptors */
	for (i = 0; i < GRETH_TXBD_CNT; i++) {
		greth->txbd_base[i].addr = 0;
		/* enable desciptor & set wrap bit if last descriptor */
		if (i >= (GRETH_TXBD_CNT - 1)) {
			greth->txbd_base[i].stat = GRETH_BD_WR;
		} else {
			greth->txbd_base[i].stat = 0;
		}
	}

	/**** SET HARDWARE REGS ****/

	/* Set pointer to tx/rx descriptor areas */
	GRETH_REGSAVE(&regs->rx_desc_p, (unsigned int)&greth->rxbd_base[0]);
	GRETH_REGSAVE(&regs->tx_desc_p, (unsigned int)&greth->txbd_base[0]);

	/* Enable Transmitter, GRETH will now scan descriptors for packets
	 * to transmitt */
	debug("greth_init: enabling receiver\n");
	GRETH_REGORIN(&regs->control, GRETH_RXEN);

	return 0;
}

/* Initiate PHY to a relevant speed
 * return:
 *  - 0 = success
 *  - 1 = timeout/fail
 */
int greth_init_phy(greth_priv * dev, bd_t * bis)
{
	greth_regs *regs = dev->regs;
	int tmp, tmp1, tmp2, i;
	unsigned int start, timeout;
	int phyaddr = GRETH_PHY_ADR_DEFAULT;

#ifndef CONFIG_SYS_GRLIB_GRETH_PHYADDR
	/* If BSP doesn't provide a hardcoded PHY address the driver will
	 * try to autodetect PHY address by stopping the search on the first
	 * PHY address which has REG0 implemented.
	 */
	for (i=0; i<32; i++) {
		tmp = read_mii(i, 0, regs);
		if ( (tmp != 0) && (tmp != 0xffff) ) {
			phyaddr = i;
			break;
		}
	}
#endif

	/* Save PHY Address */
	dev->phyaddr = phyaddr;

	debug("GRETH PHY ADDRESS: %d\n", phyaddr);

	/* X msecs to ticks */
	timeout = usec2ticks(GRETH_PHY_TIMEOUT_MS * 1000);

	/* Get system timer0 current value
	 * Total timeout is 5s
	 */
	start = get_timer(0);

	/* get phy control register default values */

	while ((tmp = read_mii(phyaddr, 0, regs)) & 0x8000) {
		if (get_timer(start) > timeout) {
			debug("greth_init_phy: PHY read 1 failed\n");
			return 1;	/* Fail */
		}
	}

	/* reset PHY and wait for completion */
	write_mii(phyaddr, 0, 0x8000 | tmp, regs);

	while (((tmp = read_mii(phyaddr, 0, regs))) & 0x8000) {
		if (get_timer(start) > timeout) {
			debug("greth_init_phy: PHY read 2 failed\n");
			return 1;	/* Fail */
		}
	}

	/* Check if PHY is autoneg capable and then determine operating
	 * mode, otherwise force it to 10 Mbit halfduplex
	 */
	dev->gb = 0;
	dev->fd = 0;
	dev->sp = 0;
	dev->auto_neg = 0;
	if (!((tmp >> 12) & 1)) {
		write_mii(phyaddr, 0, 0, regs);
	} else {
		/* wait for auto negotiation to complete and then check operating mode */
		dev->auto_neg = 1;
		i = 0;
		while (!(((tmp = read_mii(phyaddr, 1, regs)) >> 5) & 1)) {
			if (get_timer(start) > timeout) {
				printf("Auto negotiation timed out. "
				       "Selecting default config\n");
				tmp = read_mii(phyaddr, 0, regs);
				dev->gb = ((tmp >> 6) & 1)
				    && !((tmp >> 13) & 1);
				dev->sp = !((tmp >> 6) & 1)
				    && ((tmp >> 13) & 1);
				dev->fd = (tmp >> 8) & 1;
				goto auto_neg_done;
			}
		}
		if ((tmp >> 8) & 1) {
			tmp1 = read_mii(phyaddr, 9, regs);
			tmp2 = read_mii(phyaddr, 10, regs);
			if ((tmp1 & GRETH_MII_EXTADV_1000FD) &&
			    (tmp2 & GRETH_MII_EXTPRT_1000FD)) {
				dev->gb = 1;
				dev->fd = 1;
			}
			if ((tmp1 & GRETH_MII_EXTADV_1000HD) &&
			    (tmp2 & GRETH_MII_EXTPRT_1000HD)) {
				dev->gb = 1;
				dev->fd = 0;
			}
		}
		if ((dev->gb == 0) || ((dev->gb == 1) && (dev->gbit_mac == 0))) {
			tmp1 = read_mii(phyaddr, 4, regs);
			tmp2 = read_mii(phyaddr, 5, regs);
			if ((tmp1 & GRETH_MII_100TXFD) &&
			    (tmp2 & GRETH_MII_100TXFD)) {
				dev->sp = 1;
				dev->fd = 1;
			}
			if ((tmp1 & GRETH_MII_100TXHD) &&
			    (tmp2 & GRETH_MII_100TXHD)) {
				dev->sp = 1;
				dev->fd = 0;
			}
			if ((tmp1 & GRETH_MII_10FD) && (tmp2 & GRETH_MII_10FD)) {
				dev->fd = 1;
			}
			if ((dev->gb == 1) && (dev->gbit_mac == 0)) {
				dev->gb = 0;
				dev->fd = 0;
				write_mii(phyaddr, 0, dev->sp << 13, regs);
			}
		}

	}
      auto_neg_done:
	debug("%s GRETH Ethermac at [0x%x] irq %d. Running \
		%d Mbps %s duplex\n", dev->gbit_mac ? "10/100/1000" : "10/100", (unsigned int)(regs), (unsigned int)(dev->irq), dev->gb ? 1000 : (dev->sp ? 100 : 10), dev->fd ? "full" : "half");
	/* Read out PHY info if extended registers are available */
	if (tmp & 1) {
		tmp1 = read_mii(phyaddr, 2, regs);
		tmp2 = read_mii(phyaddr, 3, regs);
		tmp1 = (tmp1 << 6) | ((tmp2 >> 10) & 0x3F);
		tmp = tmp2 & 0xF;

		tmp2 = (tmp2 >> 4) & 0x3F;
		debug("PHY: Vendor %x   Device %x    Revision %d\n", tmp1,
		       tmp2, tmp);
	} else {
		printf("PHY info not available\n");
	}

	/* set speed and duplex bits in control register */
	GRETH_REGORIN(&regs->control,
		      (dev->gb << 8) | (dev->sp << 7) | (dev->fd << 4));

	return 0;
}

void greth_halt(struct eth_device *dev)
{
	greth_priv *greth;
	greth_regs *regs;
	int i;

	debug("greth_halt\n");

	if (!dev || !dev->priv)
		return;

	greth = dev->priv;
	regs = greth->regs;

	if (!regs)
		return;

	/* disable receiver/transmitter by clearing the enable bits */
	GRETH_REGANDIN(&regs->control, ~(GRETH_RXEN | GRETH_TXEN));

	/* reset rx/tx descriptors */
	if (greth->rxbd_base) {
		for (i = 0; i < GRETH_RXBD_CNT; i++) {
			greth->rxbd_base[i].stat =
			    (i >= (GRETH_RXBD_CNT - 1)) ? GRETH_BD_WR : 0;
		}
	}

	if (greth->txbd_base) {
		for (i = 0; i < GRETH_TXBD_CNT; i++) {
			greth->txbd_base[i].stat =
			    (i >= (GRETH_TXBD_CNT - 1)) ? GRETH_BD_WR : 0;
		}
	}
}

int greth_send(struct eth_device *dev, void *eth_data, int data_length)
{
	greth_priv *greth = dev->priv;
	greth_regs *regs = greth->regs;
	greth_bd *txbd;
	void *txbuf;
	unsigned int status;

	debug("greth_send\n");

	/* send data, wait for data to be sent, then return */
	if (((unsigned int)eth_data & (GRETH_BUF_ALIGN - 1))
	    && !greth->gbit_mac) {
		/* data not aligned as needed by GRETH 10/100, solve this by allocating 4 byte aligned buffer
		 * and copy data to before giving it to GRETH.
		 */
		if (!greth->txbuf) {
			greth->txbuf = malloc(GRETH_RXBUF_SIZE);
		}

		txbuf = greth->txbuf;

		/* copy data info buffer */
		memcpy((char *)txbuf, (char *)eth_data, data_length);

		/* keep buffer to next time */
	} else {
		txbuf = (void *)eth_data;
	}
	/* get descriptor to use, only 1 supported... hehe easy */
	txbd = greth->txbd_base;

	/* setup descriptor to wrap around to it self */
	txbd->addr = (unsigned int)txbuf;
	txbd->stat = GRETH_BD_EN | GRETH_BD_WR | data_length;

	/* Remind Core which descriptor to use when sending */
	GRETH_REGSAVE(&regs->tx_desc_p, (unsigned int)txbd);

	/* initate send by enabling transmitter */
	GRETH_REGORIN(&regs->control, GRETH_TXEN);

	/* Wait for data to be sent */
	while ((status = GRETH_REGLOAD(&txbd->stat)) & GRETH_BD_EN) {
		;
	}

	/* was the packet transmitted succesfully? */
	if (status & GRETH_TXBD_ERR_AL) {
		greth->stats.tx_limit_errors++;
	}

	if (status & GRETH_TXBD_ERR_UE) {
		greth->stats.tx_underrun_errors++;
	}

	if (status & GRETH_TXBD_ERR_LC) {
		greth->stats.tx_latecol_errors++;
	}

	if (status &
	    (GRETH_TXBD_ERR_LC | GRETH_TXBD_ERR_UE | GRETH_TXBD_ERR_AL)) {
		/* any error */
		greth->stats.tx_errors++;
		return -1;
	}

	/* bump tx packet counter */
	greth->stats.tx_packets++;

	/* return succefully */
	return 0;
}

int greth_recv(struct eth_device *dev)
{
	greth_priv *greth = dev->priv;
	greth_regs *regs = greth->regs;
	greth_bd *rxbd;
	unsigned int status, len = 0, bad;
	char *d;
	int enable = 0;
	int i;

	/* Receive One packet only, but clear as many error packets as there are
	 * available.
	 */
	{
		/* current receive descriptor */
		rxbd = greth->rxbd_curr;

		/* get status of next received packet */
		status = GRETH_REGLOAD(&rxbd->stat);

		bad = 0;

		/* stop if no more packets received */
		if (status & GRETH_BD_EN) {
			goto done;
		}

		debug("greth_recv: packet 0x%x, 0x%x, len: %d\n",
		       (unsigned int)rxbd, status, status & GRETH_BD_LEN);

		/* Check status for errors.
		 */
		if (status & GRETH_RXBD_ERR_FT) {
			greth->stats.rx_length_errors++;
			bad = 1;
		}
		if (status & (GRETH_RXBD_ERR_AE | GRETH_RXBD_ERR_OE)) {
			greth->stats.rx_frame_errors++;
			bad = 1;
		}
		if (status & GRETH_RXBD_ERR_CRC) {
			greth->stats.rx_crc_errors++;
			bad = 1;
		}
		if (bad) {
			greth->stats.rx_errors++;
			printf
			    ("greth_recv: Bad packet (%d, %d, %d, 0x%08x, %d)\n",
			     greth->stats.rx_length_errors,
			     greth->stats.rx_frame_errors,
			     greth->stats.rx_crc_errors, status,
			     greth->stats.rx_packets);
			/* print all rx descriptors */
			for (i = 0; i < GRETH_RXBD_CNT; i++) {
				printf("[%d]: Stat=0x%lx, Addr=0x%lx\n", i,
				       GRETH_REGLOAD(&greth->rxbd_base[i].stat),
				       GRETH_REGLOAD(&greth->rxbd_base[i].addr));
			}
		} else {
			/* Process the incoming packet. */
			len = status & GRETH_BD_LEN;
			d = (char *)rxbd->addr;

			debug
			    ("greth_recv: new packet, length: %d. data: %x %x %x %x %x %x %x %x\n",
			     len, d[0], d[1], d[2], d[3], d[4], d[5], d[6],
			     d[7]);

			/* flush all data cache to make sure we're not reading old packet data */
			sparc_dcache_flush_all();

			/* pass packet on to network subsystem */
			net_process_received_packet((void *)d, len);

			/* bump stats counters */
			greth->stats.rx_packets++;

			/* bad is now 0 ==> will stop loop */
		}

		/* reenable descriptor to receive more packet with this descriptor, wrap around if needed */
		rxbd->stat =
		    GRETH_BD_EN |
		    (((unsigned int)greth->rxbd_curr >=
		      (unsigned int)greth->rxbd_max) ? GRETH_BD_WR : 0);
		enable = 1;

		/* increase index */
		greth->rxbd_curr =
		    ((unsigned int)greth->rxbd_curr >=
		     (unsigned int)greth->rxbd_max) ? greth->
		    rxbd_base : (greth->rxbd_curr + 1);

	}

	if (enable) {
		GRETH_REGORIN(&regs->control, GRETH_RXEN);
	}
      done:
	/* return positive length of packet or 0 if non received */
	return len;
}

void greth_set_hwaddr(greth_priv * greth, unsigned char *mac)
{
	/* save new MAC address */
	greth->dev->enetaddr[0] = greth->hwaddr[0] = mac[0];
	greth->dev->enetaddr[1] = greth->hwaddr[1] = mac[1];
	greth->dev->enetaddr[2] = greth->hwaddr[2] = mac[2];
	greth->dev->enetaddr[3] = greth->hwaddr[3] = mac[3];
	greth->dev->enetaddr[4] = greth->hwaddr[4] = mac[4];
	greth->dev->enetaddr[5] = greth->hwaddr[5] = mac[5];
	greth->regs->esa_msb = (mac[0] << 8) | mac[1];
	greth->regs->esa_lsb =
	    (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5];

	debug("GRETH: New MAC address: %02x:%02x:%02x:%02x:%02x:%02x\n",
	       mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
}

int greth_initialize(bd_t * bis)
{
	greth_priv *greth;
	ambapp_apbdev apbdev;
	struct eth_device *dev;
	int i;
	char *addr_str, *end;
	unsigned char addr[6];

	debug("Scanning for GRETH\n");

	/* Find Device & IRQ via AMBA Plug&Play information */
	if (ambapp_apb_first(VENDOR_GAISLER, GAISLER_ETHMAC, &apbdev) != 1) {
		return -1;	/* GRETH not found */
	}

	greth = (greth_priv *) malloc(sizeof(greth_priv));
	dev = (struct eth_device *)malloc(sizeof(struct eth_device));
	memset(dev, 0, sizeof(struct eth_device));
	memset(greth, 0, sizeof(greth_priv));

	greth->regs = (greth_regs *) apbdev.address;
	greth->irq = apbdev.irq;
	debug("Found GRETH at %p, irq %d\n", greth->regs, greth->irq);
	dev->priv = (void *)greth;
	dev->iobase = (unsigned int)greth->regs;
	dev->init = greth_init;
	dev->halt = greth_halt;
	dev->send = greth_send;
	dev->recv = greth_recv;
	greth->dev = dev;

	/* Reset Core */
	GRETH_REGSAVE(&greth->regs->control, GRETH_RESET);

	/* Wait for core to finish reset cycle */
	while (GRETH_REGLOAD(&greth->regs->control) & GRETH_RESET) ;

	/* Get the phy address which assumed to have been set
	   correctly with the reset value in hardware */
	greth->phyaddr = (GRETH_REGLOAD(&greth->regs->mdio) >> 11) & 0x1F;

	/* Check if mac is gigabit capable */
	greth->gbit_mac = (GRETH_REGLOAD(&greth->regs->control) >> 27) & 1;

	/* Make descriptor string */
	if (greth->gbit_mac) {
		sprintf(dev->name, "GRETH_10/100/GB");
	} else {
		sprintf(dev->name, "GRETH_10/100");
	}

	/* initiate PHY, select speed/duplex depending on connected PHY */
	if (greth_init_phy(greth, bis)) {
		/* Failed to init PHY (timedout) */
		debug("GRETH[%p]: Failed to init PHY\n", greth->regs);
		return -1;
	}

	/* Register Device to EtherNet subsystem  */
	eth_register(dev);

	/* Get MAC address */
	if ((addr_str = getenv("ethaddr")) != NULL) {
		for (i = 0; i < 6; i++) {
			addr[i] =
			    addr_str ? simple_strtoul(addr_str, &end, 16) : 0;
			if (addr_str) {
				addr_str = (*end) ? end + 1 : end;
			}
		}
	} else {
		/* No ethaddr set */
		return -EINVAL;
	}

	/* set and remember MAC address */
	greth_set_hwaddr(greth, addr);

	debug("GRETH[%p]: Initialized successfully\n", greth->regs);
	return 0;
}
Commit	Line	Data
c2b7da55 DH	1	/* Gaisler.com GRETH 10/100/1000 Ethernet MAC driver
	2	*
	3	* Driver use polling mode (no Interrupt)
	4	*
	5	* (C) Copyright 2007
	6	* Daniel Hellstrom, Gaisler Research, daniel@gaisler.com
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
c2b7da55 DH	9	*/
c2b7da55 DH	10
6644c195 DH	11	/* #define DEBUG */
6644c195 DH	12
c2b7da55 DH	13	#include <common.h>
c2b7da55 DH	14	#include <command.h>
92ac5208	15	#include <errno.h>
c2b7da55	16	#include <net.h>
89973f8a	17	#include <netdev.h>
c2b7da55 DH	18	#include <malloc.h>
	19	#include <asm/processor.h>
	20	#include <ambapp.h>
	21	#include <asm/leon.h>
	22
c2b7da55 DH	23	#include "greth.h"
	24
	25	/* Default to 3s timeout on autonegotiation */
	26	#ifndef GRETH_PHY_TIMEOUT_MS
	27	#define GRETH_PHY_TIMEOUT_MS 3000
	28	#endif
	29
e780d82b DH	30	/* Default to PHY adrress 0 not not specified */
	31	#ifdef CONFIG_SYS_GRLIB_GRETH_PHYADDR
	32	#define GRETH_PHY_ADR_DEFAULT CONFIG_SYS_GRLIB_GRETH_PHYADDR
	33	#else
	34	#define GRETH_PHY_ADR_DEFAULT 0
	35	#endif
	36
c2b7da55 DH	37	/* ByPass Cache when reading regs */
	38	#define GRETH_REGLOAD(addr) SPARC_NOCACHE_READ(addr)
	39	/* Write-through cache ==> no bypassing needed on writes */
e3ce686c	40	#define GRETH_REGSAVE(addr,data) ((volatile unsigned int )(addr) = (data))
c2b7da55 DH	41	#define GRETH_REGORIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)\|data)
	42	#define GRETH_REGANDIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)&data)
	43
	44	#define GRETH_RXBD_CNT 4
	45	#define GRETH_TXBD_CNT 1
	46
	47	#define GRETH_RXBUF_SIZE 1540
	48	#define GRETH_BUF_ALIGN 4
	49	#define GRETH_RXBUF_EFF_SIZE \
	50	( (GRETH_RXBUF_SIZE&~(GRETH_BUF_ALIGN-1))+GRETH_BUF_ALIGN )
	51
	52	typedef struct {
	53	greth_regs *regs;
	54	int irq;
	55	struct eth_device *dev;
	56
	57	/* Hardware info */
	58	unsigned char phyaddr;
	59	int gbit_mac;
	60
	61	/* Current operating Mode */
	62	int gb; /* GigaBit */
	63	int fd; /* Full Duplex */
	64	int sp; /* 10/100Mbps speed (1=100,0=10) */
	65	int auto_neg; /* Auto negotiate done */
	66
	67	unsigned char hwaddr[6]; /* MAC Address */
	68
	69	/* Descriptors */
	70	greth_bd rxbd_base, rxbd_max;
	71	greth_bd txbd_base, txbd_max;
	72
	73	greth_bd *rxbd_curr;
	74
	75	/* rx buffers in rx descriptors */
	76	void rxbuf_base; / (GRETH_RXBUF_SIZE+ALIGNBYTES) * GRETH_RXBD_CNT */
	77
	78	/* unused for gbit_mac, temp buffer for sending packets with unligned
	79	* start.
	80	* Pointer to packet allocated with malloc.
	81	*/
	82	void *txbuf;
	83
	84	struct {
	85	/* rx status */
	86	unsigned int rx_packets,
	87	rx_crc_errors, rx_frame_errors, rx_length_errors, rx_errors;
	88
	89	/* tx stats */
	90	unsigned int tx_packets,
	91	tx_latecol_errors,
	92	tx_underrun_errors, tx_limit_errors, tx_errors;
	93	} stats;
	94	} greth_priv;
	95
	96	/* Read MII register 'addr' from core 'regs' */
e780d82b	97	static int read_mii(int phyaddr, int regaddr, volatile greth_regs * regs)
c2b7da55 DH	98	{
	99	while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {
	100	}
	101
e780d82b	102	GRETH_REGSAVE(&regs->mdio, ((phyaddr & 0x1F) << 11) \| ((regaddr & 0x1F) << 6) \| 2);
c2b7da55 DH	103
	104	while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {
	105	}
	106
	107	if (!(GRETH_REGLOAD(&regs->mdio) & GRETH_MII_NVALID)) {
	108	return (GRETH_REGLOAD(&regs->mdio) >> 16) & 0xFFFF;
	109	} else {
	110	return -1;
	111	}
	112	}
	113
e780d82b	114	static void write_mii(int phyaddr, int regaddr, int data, volatile greth_regs * regs)
c2b7da55 DH	115	{
	116	while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {
	117	}
	118
	119	GRETH_REGSAVE(&regs->mdio,
e780d82b DH	120	((data & 0xFFFF) << 16) \| ((phyaddr & 0x1F) << 11) \|
e780d82b DH	121	((regaddr & 0x1F) << 6) \| 1);
c2b7da55 DH	122
	123	while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {
	124	}
	125
	126	}
	127
	128	/* init/start hardware and allocate descriptor buffers for rx side
	129	*
	130	*/
	131	int greth_init(struct eth_device dev, bd_t bis)
	132	{
	133	int i;
	134
	135	greth_priv *greth = dev->priv;
	136	greth_regs *regs = greth->regs;
6644c195 DH	137
6644c195 DH	138	debug("greth_init\n");
c2b7da55	139
533b67d4 DH	140	/* Reset core */
	141	GRETH_REGSAVE(&regs->control, (GRETH_RESET \| (greth->gb << 8) \|
	142	(greth->sp << 7) \| (greth->fd << 4)));
	143
	144	/* Wait for Reset to complete */
	145	while ( GRETH_REGLOAD(&regs->control) & GRETH_RESET) ;
	146
	147	GRETH_REGSAVE(&regs->control,
	148	((greth->gb << 8) \| (greth->sp << 7) \| (greth->fd << 4)));
	149
c2b7da55 DH	150	if (!greth->rxbd_base) {
	151
	152	/* allocate descriptors */
	153	greth->rxbd_base = (greth_bd *)
	154	memalign(0x1000, GRETH_RXBD_CNT * sizeof(greth_bd));
	155	greth->txbd_base = (greth_bd *)
ed52d121	156	memalign(0x1000, GRETH_TXBD_CNT * sizeof(greth_bd));
c2b7da55 DH	157
	158	/* allocate buffers to all descriptors */
	159	greth->rxbuf_base =
	160	malloc(GRETH_RXBUF_EFF_SIZE * GRETH_RXBD_CNT);
	161	}
	162
	163	/* initate rx decriptors */
	164	for (i = 0; i < GRETH_RXBD_CNT; i++) {
	165	greth->rxbd_base[i].addr = (unsigned int)
	166	greth->rxbuf_base + (GRETH_RXBUF_EFF_SIZE * i);
	167	/* enable desciptor & set wrap bit if last descriptor */
	168	if (i >= (GRETH_RXBD_CNT - 1)) {
	169	greth->rxbd_base[i].stat = GRETH_BD_EN \| GRETH_BD_WR;
	170	} else {
	171	greth->rxbd_base[i].stat = GRETH_BD_EN;
	172	}
	173	}
	174
	175	/* initiate indexes */
	176	greth->rxbd_curr = greth->rxbd_base;
	177	greth->rxbd_max = greth->rxbd_base + (GRETH_RXBD_CNT - 1);
	178	greth->txbd_max = greth->txbd_base + (GRETH_TXBD_CNT - 1);
	179	/*
	180	* greth->txbd_base->addr = 0;
	181	* greth->txbd_base->stat = GRETH_BD_WR;
	182	*/
	183
	184	/* initate tx decriptors */
	185	for (i = 0; i < GRETH_TXBD_CNT; i++) {
	186	greth->txbd_base[i].addr = 0;
	187	/* enable desciptor & set wrap bit if last descriptor */
ed52d121	188	if (i >= (GRETH_TXBD_CNT - 1)) {
c2b7da55 DH	189	greth->txbd_base[i].stat = GRETH_BD_WR;
	190	} else {
	191	greth->txbd_base[i].stat = 0;
	192	}
	193	}
	194
	195	/** SET HARDWARE REGS **/
	196
	197	/* Set pointer to tx/rx descriptor areas */
	198	GRETH_REGSAVE(&regs->rx_desc_p, (unsigned int)&greth->rxbd_base[0]);
	199	GRETH_REGSAVE(&regs->tx_desc_p, (unsigned int)&greth->txbd_base[0]);
	200
	201	/* Enable Transmitter, GRETH will now scan descriptors for packets
	202	* to transmitt */
6644c195	203	debug("greth_init: enabling receiver\n");
c2b7da55 DH	204	GRETH_REGORIN(&regs->control, GRETH_RXEN);
	205
	206	return 0;
	207	}
	208
	209	/* Initiate PHY to a relevant speed
	210	* return:
	211	* - 0 = success
	212	* - 1 = timeout/fail
	213	*/
	214	int greth_init_phy(greth_priv * dev, bd_t * bis)
	215	{
	216	greth_regs *regs = dev->regs;
	217	int tmp, tmp1, tmp2, i;
	218	unsigned int start, timeout;
e780d82b DH	219	int phyaddr = GRETH_PHY_ADR_DEFAULT;
	220
	221	#ifndef CONFIG_SYS_GRLIB_GRETH_PHYADDR
	222	/* If BSP doesn't provide a hardcoded PHY address the driver will
	223	* try to autodetect PHY address by stopping the search on the first
	224	* PHY address which has REG0 implemented.
	225	*/
	226	for (i=0; i<32; i++) {
	227	tmp = read_mii(i, 0, regs);
	228	if ( (tmp != 0) && (tmp != 0xffff) ) {
	229	phyaddr = i;
	230	break;
	231	}
	232	}
	233	#endif
	234
	235	/* Save PHY Address */
	236	dev->phyaddr = phyaddr;
	237
	238	debug("GRETH PHY ADDRESS: %d\n", phyaddr);
c2b7da55 DH	239
	240	/* X msecs to ticks */
	241	timeout = usec2ticks(GRETH_PHY_TIMEOUT_MS * 1000);
	242
	243	/* Get system timer0 current value
	244	* Total timeout is 5s
	245	*/
	246	start = get_timer(0);
	247
	248	/* get phy control register default values */
	249
e780d82b DH	250	while ((tmp = read_mii(phyaddr, 0, regs)) & 0x8000) {
	251	if (get_timer(start) > timeout) {
	252	debug("greth_init_phy: PHY read 1 failed\n");
c2b7da55	253	return 1; /* Fail */
e780d82b	254	}
c2b7da55 DH	255	}
	256
	257	/* reset PHY and wait for completion */
e780d82b	258	write_mii(phyaddr, 0, 0x8000 \| tmp, regs);
c2b7da55	259
e780d82b DH	260	while (((tmp = read_mii(phyaddr, 0, regs))) & 0x8000) {
	261	if (get_timer(start) > timeout) {
	262	debug("greth_init_phy: PHY read 2 failed\n");
c2b7da55	263	return 1; /* Fail */
e780d82b	264	}
c2b7da55 DH	265	}
	266
	267	/* Check if PHY is autoneg capable and then determine operating
	268	* mode, otherwise force it to 10 Mbit halfduplex
	269	*/
	270	dev->gb = 0;
	271	dev->fd = 0;
	272	dev->sp = 0;
	273	dev->auto_neg = 0;
	274	if (!((tmp >> 12) & 1)) {
e780d82b	275	write_mii(phyaddr, 0, 0, regs);
c2b7da55 DH	276	} else {
	277	/* wait for auto negotiation to complete and then check operating mode */
	278	dev->auto_neg = 1;
	279	i = 0;
e780d82b	280	while (!(((tmp = read_mii(phyaddr, 1, regs)) >> 5) & 1)) {
c2b7da55 DH	281	if (get_timer(start) > timeout) {
	282	printf("Auto negotiation timed out. "
	283	"Selecting default config\n");
e780d82b	284	tmp = read_mii(phyaddr, 0, regs);
c2b7da55 DH	285	dev->gb = ((tmp >> 6) & 1)
	286	&& !((tmp >> 13) & 1);
	287	dev->sp = !((tmp >> 6) & 1)
	288	&& ((tmp >> 13) & 1);
	289	dev->fd = (tmp >> 8) & 1;
	290	goto auto_neg_done;
	291	}
	292	}
	293	if ((tmp >> 8) & 1) {
e780d82b DH	294	tmp1 = read_mii(phyaddr, 9, regs);
e780d82b DH	295	tmp2 = read_mii(phyaddr, 10, regs);
c2b7da55 DH	296	if ((tmp1 & GRETH_MII_EXTADV_1000FD) &&
	297	(tmp2 & GRETH_MII_EXTPRT_1000FD)) {
	298	dev->gb = 1;
	299	dev->fd = 1;
	300	}
	301	if ((tmp1 & GRETH_MII_EXTADV_1000HD) &&
	302	(tmp2 & GRETH_MII_EXTPRT_1000HD)) {
	303	dev->gb = 1;
	304	dev->fd = 0;
	305	}
	306	}
	307	if ((dev->gb == 0) \|\| ((dev->gb == 1) && (dev->gbit_mac == 0))) {
e780d82b DH	308	tmp1 = read_mii(phyaddr, 4, regs);
e780d82b DH	309	tmp2 = read_mii(phyaddr, 5, regs);
c2b7da55 DH	310	if ((tmp1 & GRETH_MII_100TXFD) &&
	311	(tmp2 & GRETH_MII_100TXFD)) {
	312	dev->sp = 1;
	313	dev->fd = 1;
	314	}
	315	if ((tmp1 & GRETH_MII_100TXHD) &&
	316	(tmp2 & GRETH_MII_100TXHD)) {
	317	dev->sp = 1;
	318	dev->fd = 0;
	319	}
	320	if ((tmp1 & GRETH_MII_10FD) && (tmp2 & GRETH_MII_10FD)) {
	321	dev->fd = 1;
	322	}
	323	if ((dev->gb == 1) && (dev->gbit_mac == 0)) {
	324	dev->gb = 0;
	325	dev->fd = 0;
e780d82b	326	write_mii(phyaddr, 0, dev->sp << 13, regs);
c2b7da55 DH	327	}
	328	}
	329
	330	}
	331	auto_neg_done:
6644c195	332	debug("%s GRETH Ethermac at [0x%x] irq %d. Running \
c2b7da55	333	%d Mbps %s duplex\n", dev->gbit_mac ? "10/100/1000" : "10/100", (unsigned int)(regs), (unsigned int)(dev->irq), dev->gb ? 1000 : (dev->sp ? 100 : 10), dev->fd ? "full" : "half");
c2b7da55 DH	334	/* Read out PHY info if extended registers are available */
c2b7da55 DH	335	if (tmp & 1) {
e780d82b DH	336	tmp1 = read_mii(phyaddr, 2, regs);
e780d82b DH	337	tmp2 = read_mii(phyaddr, 3, regs);
c2b7da55 DH	338	tmp1 = (tmp1 << 6) \| ((tmp2 >> 10) & 0x3F);
	339	tmp = tmp2 & 0xF;
	340
	341	tmp2 = (tmp2 >> 4) & 0x3F;
6644c195	342	debug("PHY: Vendor %x Device %x Revision %d\n", tmp1,
c2b7da55	343	tmp2, tmp);
c2b7da55 DH	344	} else {
	345	printf("PHY info not available\n");
	346	}
	347
	348	/* set speed and duplex bits in control register */
	349	GRETH_REGORIN(&regs->control,
	350	(dev->gb << 8) \| (dev->sp << 7) \| (dev->fd << 4));
	351
	352	return 0;
	353	}
	354
	355	void greth_halt(struct eth_device *dev)
	356	{
	357	greth_priv *greth;
	358	greth_regs *regs;
	359	int i;
6644c195 DH	360
	361	debug("greth_halt\n");
	362
c2b7da55 DH	363	if (!dev \|\| !dev->priv)
	364	return;
	365
	366	greth = dev->priv;
	367	regs = greth->regs;
	368
	369	if (!regs)
	370	return;
	371
	372	/* disable receiver/transmitter by clearing the enable bits */
	373	GRETH_REGANDIN(&regs->control, ~(GRETH_RXEN \| GRETH_TXEN));
	374
	375	/* reset rx/tx descriptors */
	376	if (greth->rxbd_base) {
	377	for (i = 0; i < GRETH_RXBD_CNT; i++) {
	378	greth->rxbd_base[i].stat =
	379	(i >= (GRETH_RXBD_CNT - 1)) ? GRETH_BD_WR : 0;
	380	}
	381	}
	382
	383	if (greth->txbd_base) {
	384	for (i = 0; i < GRETH_TXBD_CNT; i++) {
	385	greth->txbd_base[i].stat =
	386	(i >= (GRETH_TXBD_CNT - 1)) ? GRETH_BD_WR : 0;
	387	}
	388	}
	389	}
	390
10cbe3b6	391	int greth_send(struct eth_device dev, void eth_data, int data_length)
c2b7da55 DH	392	{
	393	greth_priv *greth = dev->priv;
	394	greth_regs *regs = greth->regs;
	395	greth_bd *txbd;
	396	void *txbuf;
	397	unsigned int status;
6644c195 DH	398
	399	debug("greth_send\n");
	400
c2b7da55 DH	401	/* send data, wait for data to be sent, then return */
	402	if (((unsigned int)eth_data & (GRETH_BUF_ALIGN - 1))
	403	&& !greth->gbit_mac) {
	404	/* data not aligned as needed by GRETH 10/100, solve this by allocating 4 byte aligned buffer
	405	* and copy data to before giving it to GRETH.
	406	*/
	407	if (!greth->txbuf) {
	408	greth->txbuf = malloc(GRETH_RXBUF_SIZE);
c2b7da55 DH	409	}
	410
	411	txbuf = greth->txbuf;
	412
	413	/* copy data info buffer */
	414	memcpy((char )txbuf, (char )eth_data, data_length);
	415
	416	/* keep buffer to next time */
	417	} else {
	418	txbuf = (void *)eth_data;
	419	}
	420	/* get descriptor to use, only 1 supported... hehe easy */
	421	txbd = greth->txbd_base;
	422
	423	/* setup descriptor to wrap around to it self */
	424	txbd->addr = (unsigned int)txbuf;
	425	txbd->stat = GRETH_BD_EN \| GRETH_BD_WR \| data_length;
	426
	427	/* Remind Core which descriptor to use when sending */
	428	GRETH_REGSAVE(&regs->tx_desc_p, (unsigned int)txbd);
	429
	430	/* initate send by enabling transmitter */
	431	GRETH_REGORIN(&regs->control, GRETH_TXEN);
	432
	433	/* Wait for data to be sent */
	434	while ((status = GRETH_REGLOAD(&txbd->stat)) & GRETH_BD_EN) {
	435	;
	436	}
	437
	438	/* was the packet transmitted succesfully? */
	439	if (status & GRETH_TXBD_ERR_AL) {
	440	greth->stats.tx_limit_errors++;
	441	}
	442
	443	if (status & GRETH_TXBD_ERR_UE) {
	444	greth->stats.tx_underrun_errors++;
	445	}
	446
	447	if (status & GRETH_TXBD_ERR_LC) {
	448	greth->stats.tx_latecol_errors++;
	449	}
	450
	451	if (status &
	452	(GRETH_TXBD_ERR_LC \| GRETH_TXBD_ERR_UE \| GRETH_TXBD_ERR_AL)) {
	453	/* any error */
	454	greth->stats.tx_errors++;
	455	return -1;
	456	}
	457
	458	/* bump tx packet counter */
	459	greth->stats.tx_packets++;
	460
	461	/* return succefully */
	462	return 0;
	463	}
	464
	465	int greth_recv(struct eth_device *dev)
	466	{
	467	greth_priv *greth = dev->priv;
	468	greth_regs *regs = greth->regs;
	469	greth_bd *rxbd;
	470	unsigned int status, len = 0, bad;
fa2afe02	471	char *d;
c2b7da55 DH	472	int enable = 0;
c2b7da55 DH	473	int i;
6644c195	474
c2b7da55 DH	475	/* Receive One packet only, but clear as many error packets as there are
	476	* available.
	477	*/
	478	{
	479	/* current receive descriptor */
	480	rxbd = greth->rxbd_curr;
	481
	482	/* get status of next received packet */
	483	status = GRETH_REGLOAD(&rxbd->stat);
	484
	485	bad = 0;
	486
	487	/* stop if no more packets received */
	488	if (status & GRETH_BD_EN) {
	489	goto done;
	490	}
6644c195	491
fa2afe02	492	debug("greth_recv: packet 0x%x, 0x%x, len: %d\n",
c2b7da55	493	(unsigned int)rxbd, status, status & GRETH_BD_LEN);
c2b7da55 DH	494
	495	/* Check status for errors.
	496	*/
	497	if (status & GRETH_RXBD_ERR_FT) {
	498	greth->stats.rx_length_errors++;
	499	bad = 1;
	500	}
	501	if (status & (GRETH_RXBD_ERR_AE \| GRETH_RXBD_ERR_OE)) {
	502	greth->stats.rx_frame_errors++;
	503	bad = 1;
	504	}
	505	if (status & GRETH_RXBD_ERR_CRC) {
	506	greth->stats.rx_crc_errors++;
	507	bad = 1;
	508	}
	509	if (bad) {
	510	greth->stats.rx_errors++;
	511	printf
	512	("greth_recv: Bad packet (%d, %d, %d, 0x%08x, %d)\n",
	513	greth->stats.rx_length_errors,
	514	greth->stats.rx_frame_errors,
	515	greth->stats.rx_crc_errors, status,
	516	greth->stats.rx_packets);
	517	/* print all rx descriptors */
	518	for (i = 0; i < GRETH_RXBD_CNT; i++) {
	519	printf("[%d]: Stat=0x%lx, Addr=0x%lx\n", i,
	520	GRETH_REGLOAD(&greth->rxbd_base[i].stat),
e780d82b	521	GRETH_REGLOAD(&greth->rxbd_base[i].addr));
c2b7da55 DH	522	}
	523	} else {
	524	/* Process the incoming packet. */
	525	len = status & GRETH_BD_LEN;
	526	d = (char *)rxbd->addr;
6644c195 DH	527
6644c195 DH	528	debug
c2b7da55 DH	529	("greth_recv: new packet, length: %d. data: %x %x %x %x %x %x %x %x\n",
	530	len, d[0], d[1], d[2], d[3], d[4], d[5], d[6],
	531	d[7]);
6644c195	532
c2b7da55 DH	533	/* flush all data cache to make sure we're not reading old packet data */
	534	sparc_dcache_flush_all();
	535
	536	/* pass packet on to network subsystem */
1fd92db8	537	net_process_received_packet((void *)d, len);
c2b7da55 DH	538
	539	/* bump stats counters */
	540	greth->stats.rx_packets++;
	541
	542	/* bad is now 0 ==> will stop loop */
	543	}
	544
	545	/* reenable descriptor to receive more packet with this descriptor, wrap around if needed */
	546	rxbd->stat =
	547	GRETH_BD_EN \|
	548	(((unsigned int)greth->rxbd_curr >=
	549	(unsigned int)greth->rxbd_max) ? GRETH_BD_WR : 0);
	550	enable = 1;
	551
	552	/* increase index */
	553	greth->rxbd_curr =
	554	((unsigned int)greth->rxbd_curr >=
	555	(unsigned int)greth->rxbd_max) ? greth->
	556	rxbd_base : (greth->rxbd_curr + 1);
	557
e780d82b	558	}
c2b7da55 DH	559
	560	if (enable) {
	561	GRETH_REGORIN(&regs->control, GRETH_RXEN);
	562	}
	563	done:
16263087	564	/* return positive length of packet or 0 if non received */
c2b7da55 DH	565	return len;
	566	}
	567
	568	void greth_set_hwaddr(greth_priv * greth, unsigned char *mac)
	569	{
	570	/* save new MAC address */
	571	greth->dev->enetaddr[0] = greth->hwaddr[0] = mac[0];
	572	greth->dev->enetaddr[1] = greth->hwaddr[1] = mac[1];
	573	greth->dev->enetaddr[2] = greth->hwaddr[2] = mac[2];
	574	greth->dev->enetaddr[3] = greth->hwaddr[3] = mac[3];
	575	greth->dev->enetaddr[4] = greth->hwaddr[4] = mac[4];
	576	greth->dev->enetaddr[5] = greth->hwaddr[5] = mac[5];
	577	greth->regs->esa_msb = (mac[0] << 8) \| mac[1];
	578	greth->regs->esa_lsb =
	579	(mac[2] << 24) \| (mac[3] << 16) \| (mac[4] << 8) \| mac[5];
6644c195 DH	580
6644c195 DH	581	debug("GRETH: New MAC address: %02x:%02x:%02x:%02x:%02x:%02x\n",
c2b7da55	582	mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
c2b7da55 DH	583	}
	584
	585	int greth_initialize(bd_t * bis)
	586	{
	587	greth_priv *greth;
	588	ambapp_apbdev apbdev;
	589	struct eth_device *dev;
	590	int i;
	591	char addr_str, end;
	592	unsigned char addr[6];
6644c195 DH	593
	594	debug("Scanning for GRETH\n");
	595
c2b7da55 DH	596	/* Find Device & IRQ via AMBA Plug&Play information */
	597	if (ambapp_apb_first(VENDOR_GAISLER, GAISLER_ETHMAC, &apbdev) != 1) {
	598	return -1; /* GRETH not found */
	599	}
	600
	601	greth = (greth_priv *) malloc(sizeof(greth_priv));
	602	dev = (struct eth_device *)malloc(sizeof(struct eth_device));
	603	memset(dev, 0, sizeof(struct eth_device));
	604	memset(greth, 0, sizeof(greth_priv));
	605
	606	greth->regs = (greth_regs *) apbdev.address;
	607	greth->irq = apbdev.irq;
fa2afe02	608	debug("Found GRETH at %p, irq %d\n", greth->regs, greth->irq);
c2b7da55 DH	609	dev->priv = (void *)greth;
	610	dev->iobase = (unsigned int)greth->regs;
	611	dev->init = greth_init;
	612	dev->halt = greth_halt;
	613	dev->send = greth_send;
	614	dev->recv = greth_recv;
	615	greth->dev = dev;
	616
	617	/* Reset Core */
	618	GRETH_REGSAVE(&greth->regs->control, GRETH_RESET);
	619
	620	/* Wait for core to finish reset cycle */
	621	while (GRETH_REGLOAD(&greth->regs->control) & GRETH_RESET) ;
	622
	623	/* Get the phy address which assumed to have been set
	624	correctly with the reset value in hardware */
	625	greth->phyaddr = (GRETH_REGLOAD(&greth->regs->mdio) >> 11) & 0x1F;
	626
	627	/* Check if mac is gigabit capable */
	628	greth->gbit_mac = (GRETH_REGLOAD(&greth->regs->control) >> 27) & 1;
	629
	630	/* Make descriptor string */
	631	if (greth->gbit_mac) {
64394660	632	sprintf(dev->name, "GRETH_10/100/GB");
c2b7da55	633	} else {
64394660	634	sprintf(dev->name, "GRETH_10/100");
c2b7da55 DH	635	}
	636
	637	/* initiate PHY, select speed/duplex depending on connected PHY */
	638	if (greth_init_phy(greth, bis)) {
	639	/* Failed to init PHY (timedout) */
fa2afe02	640	debug("GRETH[%p]: Failed to init PHY\n", greth->regs);
c2b7da55 DH	641	return -1;
	642	}
	643
	644	/* Register Device to EtherNet subsystem */
	645	eth_register(dev);
	646
	647	/* Get MAC address */
	648	if ((addr_str = getenv("ethaddr")) != NULL) {
	649	for (i = 0; i < 6; i++) {
	650	addr[i] =
	651	addr_str ? simple_strtoul(addr_str, &end, 16) : 0;
	652	if (addr_str) {
	653	addr_str = (*end) ? end + 1 : end;
	654	}
	655	}
	656	} else {
92ac5208 JH	657	/* No ethaddr set */
92ac5208 JH	658	return -EINVAL;
c2b7da55 DH	659	}
	660
	661	/* set and remember MAC address */
	662	greth_set_hwaddr(greth, addr);
	663
fa2afe02	664	debug("GRETH[%p]: Initialized successfully\n", greth->regs);
fc363ce3	665	return 0;
c2b7da55	666	}