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1 | /* Gaisler.com GRETH 10/100/1000 Ethernet MAC driver |
2 | * | |
3 | * Driver use polling mode (no Interrupt) | |
4 | * | |
5 | * (C) Copyright 2007 | |
6 | * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | #include <common.h> | |
28 | #include <command.h> | |
29 | #include <net.h> | |
30 | #include <malloc.h> | |
31 | #include <asm/processor.h> | |
32 | #include <ambapp.h> | |
33 | #include <asm/leon.h> | |
34 | ||
35 | /* #define DEBUG */ | |
36 | ||
37 | #include "greth.h" | |
38 | ||
39 | /* Default to 3s timeout on autonegotiation */ | |
40 | #ifndef GRETH_PHY_TIMEOUT_MS | |
41 | #define GRETH_PHY_TIMEOUT_MS 3000 | |
42 | #endif | |
43 | ||
44 | /* ByPass Cache when reading regs */ | |
45 | #define GRETH_REGLOAD(addr) SPARC_NOCACHE_READ(addr) | |
46 | /* Write-through cache ==> no bypassing needed on writes */ | |
47 | #define GRETH_REGSAVE(addr,data) (*(unsigned int *)(addr) = (data)) | |
48 | #define GRETH_REGORIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)|data) | |
49 | #define GRETH_REGANDIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)&data) | |
50 | ||
51 | #define GRETH_RXBD_CNT 4 | |
52 | #define GRETH_TXBD_CNT 1 | |
53 | ||
54 | #define GRETH_RXBUF_SIZE 1540 | |
55 | #define GRETH_BUF_ALIGN 4 | |
56 | #define GRETH_RXBUF_EFF_SIZE \ | |
57 | ( (GRETH_RXBUF_SIZE&~(GRETH_BUF_ALIGN-1))+GRETH_BUF_ALIGN ) | |
58 | ||
59 | typedef struct { | |
60 | greth_regs *regs; | |
61 | int irq; | |
62 | struct eth_device *dev; | |
63 | ||
64 | /* Hardware info */ | |
65 | unsigned char phyaddr; | |
66 | int gbit_mac; | |
67 | ||
68 | /* Current operating Mode */ | |
69 | int gb; /* GigaBit */ | |
70 | int fd; /* Full Duplex */ | |
71 | int sp; /* 10/100Mbps speed (1=100,0=10) */ | |
72 | int auto_neg; /* Auto negotiate done */ | |
73 | ||
74 | unsigned char hwaddr[6]; /* MAC Address */ | |
75 | ||
76 | /* Descriptors */ | |
77 | greth_bd *rxbd_base, *rxbd_max; | |
78 | greth_bd *txbd_base, *txbd_max; | |
79 | ||
80 | greth_bd *rxbd_curr; | |
81 | ||
82 | /* rx buffers in rx descriptors */ | |
83 | void *rxbuf_base; /* (GRETH_RXBUF_SIZE+ALIGNBYTES) * GRETH_RXBD_CNT */ | |
84 | ||
85 | /* unused for gbit_mac, temp buffer for sending packets with unligned | |
86 | * start. | |
87 | * Pointer to packet allocated with malloc. | |
88 | */ | |
89 | void *txbuf; | |
90 | ||
91 | struct { | |
92 | /* rx status */ | |
93 | unsigned int rx_packets, | |
94 | rx_crc_errors, rx_frame_errors, rx_length_errors, rx_errors; | |
95 | ||
96 | /* tx stats */ | |
97 | unsigned int tx_packets, | |
98 | tx_latecol_errors, | |
99 | tx_underrun_errors, tx_limit_errors, tx_errors; | |
100 | } stats; | |
101 | } greth_priv; | |
102 | ||
103 | /* Read MII register 'addr' from core 'regs' */ | |
104 | static int read_mii(int addr, volatile greth_regs * regs) | |
105 | { | |
106 | while (GRETH_REGLOAD(®s->mdio) & GRETH_MII_BUSY) { | |
107 | } | |
108 | ||
109 | GRETH_REGSAVE(®s->mdio, (0 << 11) | ((addr & 0x1F) << 6) | 2); | |
110 | ||
111 | while (GRETH_REGLOAD(®s->mdio) & GRETH_MII_BUSY) { | |
112 | } | |
113 | ||
114 | if (!(GRETH_REGLOAD(®s->mdio) & GRETH_MII_NVALID)) { | |
115 | return (GRETH_REGLOAD(®s->mdio) >> 16) & 0xFFFF; | |
116 | } else { | |
117 | return -1; | |
118 | } | |
119 | } | |
120 | ||
121 | static void write_mii(int addr, int data, volatile greth_regs * regs) | |
122 | { | |
123 | while (GRETH_REGLOAD(®s->mdio) & GRETH_MII_BUSY) { | |
124 | } | |
125 | ||
126 | GRETH_REGSAVE(®s->mdio, | |
127 | ((data & 0xFFFF) << 16) | (0 << 11) | ((addr & 0x1F) << 6) | |
128 | | 1); | |
129 | ||
130 | while (GRETH_REGLOAD(®s->mdio) & GRETH_MII_BUSY) { | |
131 | } | |
132 | ||
133 | } | |
134 | ||
135 | /* init/start hardware and allocate descriptor buffers for rx side | |
136 | * | |
137 | */ | |
138 | int greth_init(struct eth_device *dev, bd_t * bis) | |
139 | { | |
140 | int i; | |
141 | ||
142 | greth_priv *greth = dev->priv; | |
143 | greth_regs *regs = greth->regs; | |
144 | #ifdef DEBUG | |
145 | printf("greth_init\n"); | |
146 | #endif | |
147 | ||
148 | GRETH_REGSAVE(®s->control, 0); | |
149 | ||
150 | if (!greth->rxbd_base) { | |
151 | ||
152 | /* allocate descriptors */ | |
153 | greth->rxbd_base = (greth_bd *) | |
154 | memalign(0x1000, GRETH_RXBD_CNT * sizeof(greth_bd)); | |
155 | greth->txbd_base = (greth_bd *) | |
156 | memalign(0x1000, GRETH_RXBD_CNT * sizeof(greth_bd)); | |
157 | ||
158 | /* allocate buffers to all descriptors */ | |
159 | greth->rxbuf_base = | |
160 | malloc(GRETH_RXBUF_EFF_SIZE * GRETH_RXBD_CNT); | |
161 | } | |
162 | ||
163 | /* initate rx decriptors */ | |
164 | for (i = 0; i < GRETH_RXBD_CNT; i++) { | |
165 | greth->rxbd_base[i].addr = (unsigned int) | |
166 | greth->rxbuf_base + (GRETH_RXBUF_EFF_SIZE * i); | |
167 | /* enable desciptor & set wrap bit if last descriptor */ | |
168 | if (i >= (GRETH_RXBD_CNT - 1)) { | |
169 | greth->rxbd_base[i].stat = GRETH_BD_EN | GRETH_BD_WR; | |
170 | } else { | |
171 | greth->rxbd_base[i].stat = GRETH_BD_EN; | |
172 | } | |
173 | } | |
174 | ||
175 | /* initiate indexes */ | |
176 | greth->rxbd_curr = greth->rxbd_base; | |
177 | greth->rxbd_max = greth->rxbd_base + (GRETH_RXBD_CNT - 1); | |
178 | greth->txbd_max = greth->txbd_base + (GRETH_TXBD_CNT - 1); | |
179 | /* | |
180 | * greth->txbd_base->addr = 0; | |
181 | * greth->txbd_base->stat = GRETH_BD_WR; | |
182 | */ | |
183 | ||
184 | /* initate tx decriptors */ | |
185 | for (i = 0; i < GRETH_TXBD_CNT; i++) { | |
186 | greth->txbd_base[i].addr = 0; | |
187 | /* enable desciptor & set wrap bit if last descriptor */ | |
188 | if (i >= (GRETH_RXBD_CNT - 1)) { | |
189 | greth->txbd_base[i].stat = GRETH_BD_WR; | |
190 | } else { | |
191 | greth->txbd_base[i].stat = 0; | |
192 | } | |
193 | } | |
194 | ||
195 | /**** SET HARDWARE REGS ****/ | |
196 | ||
197 | /* Set pointer to tx/rx descriptor areas */ | |
198 | GRETH_REGSAVE(®s->rx_desc_p, (unsigned int)&greth->rxbd_base[0]); | |
199 | GRETH_REGSAVE(®s->tx_desc_p, (unsigned int)&greth->txbd_base[0]); | |
200 | ||
201 | /* Enable Transmitter, GRETH will now scan descriptors for packets | |
202 | * to transmitt */ | |
203 | #ifdef DEBUG | |
204 | printf("greth_init: enabling receiver\n"); | |
205 | #endif | |
206 | GRETH_REGORIN(®s->control, GRETH_RXEN); | |
207 | ||
208 | return 0; | |
209 | } | |
210 | ||
211 | /* Initiate PHY to a relevant speed | |
212 | * return: | |
213 | * - 0 = success | |
214 | * - 1 = timeout/fail | |
215 | */ | |
216 | int greth_init_phy(greth_priv * dev, bd_t * bis) | |
217 | { | |
218 | greth_regs *regs = dev->regs; | |
219 | int tmp, tmp1, tmp2, i; | |
220 | unsigned int start, timeout; | |
221 | ||
222 | /* X msecs to ticks */ | |
223 | timeout = usec2ticks(GRETH_PHY_TIMEOUT_MS * 1000); | |
224 | ||
225 | /* Get system timer0 current value | |
226 | * Total timeout is 5s | |
227 | */ | |
228 | start = get_timer(0); | |
229 | ||
230 | /* get phy control register default values */ | |
231 | ||
232 | while ((tmp = read_mii(0, regs)) & 0x8000) { | |
233 | if (get_timer(start) > timeout) | |
234 | return 1; /* Fail */ | |
235 | } | |
236 | ||
237 | /* reset PHY and wait for completion */ | |
238 | write_mii(0, 0x8000 | tmp, regs); | |
239 | ||
240 | while (((tmp = read_mii(0, regs))) & 0x8000) { | |
241 | if (get_timer(start) > timeout) | |
242 | return 1; /* Fail */ | |
243 | } | |
244 | ||
245 | /* Check if PHY is autoneg capable and then determine operating | |
246 | * mode, otherwise force it to 10 Mbit halfduplex | |
247 | */ | |
248 | dev->gb = 0; | |
249 | dev->fd = 0; | |
250 | dev->sp = 0; | |
251 | dev->auto_neg = 0; | |
252 | if (!((tmp >> 12) & 1)) { | |
253 | write_mii(0, 0, regs); | |
254 | } else { | |
255 | /* wait for auto negotiation to complete and then check operating mode */ | |
256 | dev->auto_neg = 1; | |
257 | i = 0; | |
258 | while (!(((tmp = read_mii(1, regs)) >> 5) & 1)) { | |
259 | if (get_timer(start) > timeout) { | |
260 | printf("Auto negotiation timed out. " | |
261 | "Selecting default config\n"); | |
262 | tmp = read_mii(0, regs); | |
263 | dev->gb = ((tmp >> 6) & 1) | |
264 | && !((tmp >> 13) & 1); | |
265 | dev->sp = !((tmp >> 6) & 1) | |
266 | && ((tmp >> 13) & 1); | |
267 | dev->fd = (tmp >> 8) & 1; | |
268 | goto auto_neg_done; | |
269 | } | |
270 | } | |
271 | if ((tmp >> 8) & 1) { | |
272 | tmp1 = read_mii(9, regs); | |
273 | tmp2 = read_mii(10, regs); | |
274 | if ((tmp1 & GRETH_MII_EXTADV_1000FD) && | |
275 | (tmp2 & GRETH_MII_EXTPRT_1000FD)) { | |
276 | dev->gb = 1; | |
277 | dev->fd = 1; | |
278 | } | |
279 | if ((tmp1 & GRETH_MII_EXTADV_1000HD) && | |
280 | (tmp2 & GRETH_MII_EXTPRT_1000HD)) { | |
281 | dev->gb = 1; | |
282 | dev->fd = 0; | |
283 | } | |
284 | } | |
285 | if ((dev->gb == 0) || ((dev->gb == 1) && (dev->gbit_mac == 0))) { | |
286 | tmp1 = read_mii(4, regs); | |
287 | tmp2 = read_mii(5, regs); | |
288 | if ((tmp1 & GRETH_MII_100TXFD) && | |
289 | (tmp2 & GRETH_MII_100TXFD)) { | |
290 | dev->sp = 1; | |
291 | dev->fd = 1; | |
292 | } | |
293 | if ((tmp1 & GRETH_MII_100TXHD) && | |
294 | (tmp2 & GRETH_MII_100TXHD)) { | |
295 | dev->sp = 1; | |
296 | dev->fd = 0; | |
297 | } | |
298 | if ((tmp1 & GRETH_MII_10FD) && (tmp2 & GRETH_MII_10FD)) { | |
299 | dev->fd = 1; | |
300 | } | |
301 | if ((dev->gb == 1) && (dev->gbit_mac == 0)) { | |
302 | dev->gb = 0; | |
303 | dev->fd = 0; | |
304 | write_mii(0, dev->sp << 13, regs); | |
305 | } | |
306 | } | |
307 | ||
308 | } | |
309 | auto_neg_done: | |
310 | #ifdef DEBUG | |
311 | printf("%s GRETH Ethermac at [0x%x] irq %d. Running \ | |
312 | %d Mbps %s duplex\n", dev->gbit_mac ? "10/100/1000" : "10/100", (unsigned int)(regs), (unsigned int)(dev->irq), dev->gb ? 1000 : (dev->sp ? 100 : 10), dev->fd ? "full" : "half"); | |
313 | #endif | |
314 | /* Read out PHY info if extended registers are available */ | |
315 | if (tmp & 1) { | |
316 | tmp1 = read_mii(2, regs); | |
317 | tmp2 = read_mii(3, regs); | |
318 | tmp1 = (tmp1 << 6) | ((tmp2 >> 10) & 0x3F); | |
319 | tmp = tmp2 & 0xF; | |
320 | ||
321 | tmp2 = (tmp2 >> 4) & 0x3F; | |
322 | #ifdef DEBUG | |
323 | printf("PHY: Vendor %x Device %x Revision %d\n", tmp1, | |
324 | tmp2, tmp); | |
325 | #endif | |
326 | } else { | |
327 | printf("PHY info not available\n"); | |
328 | } | |
329 | ||
330 | /* set speed and duplex bits in control register */ | |
331 | GRETH_REGORIN(®s->control, | |
332 | (dev->gb << 8) | (dev->sp << 7) | (dev->fd << 4)); | |
333 | ||
334 | return 0; | |
335 | } | |
336 | ||
337 | void greth_halt(struct eth_device *dev) | |
338 | { | |
339 | greth_priv *greth; | |
340 | greth_regs *regs; | |
341 | int i; | |
342 | #ifdef DEBUG | |
343 | printf("greth_halt\n"); | |
344 | #endif | |
345 | if (!dev || !dev->priv) | |
346 | return; | |
347 | ||
348 | greth = dev->priv; | |
349 | regs = greth->regs; | |
350 | ||
351 | if (!regs) | |
352 | return; | |
353 | ||
354 | /* disable receiver/transmitter by clearing the enable bits */ | |
355 | GRETH_REGANDIN(®s->control, ~(GRETH_RXEN | GRETH_TXEN)); | |
356 | ||
357 | /* reset rx/tx descriptors */ | |
358 | if (greth->rxbd_base) { | |
359 | for (i = 0; i < GRETH_RXBD_CNT; i++) { | |
360 | greth->rxbd_base[i].stat = | |
361 | (i >= (GRETH_RXBD_CNT - 1)) ? GRETH_BD_WR : 0; | |
362 | } | |
363 | } | |
364 | ||
365 | if (greth->txbd_base) { | |
366 | for (i = 0; i < GRETH_TXBD_CNT; i++) { | |
367 | greth->txbd_base[i].stat = | |
368 | (i >= (GRETH_TXBD_CNT - 1)) ? GRETH_BD_WR : 0; | |
369 | } | |
370 | } | |
371 | } | |
372 | ||
373 | int greth_send(struct eth_device *dev, volatile void *eth_data, int data_length) | |
374 | { | |
375 | greth_priv *greth = dev->priv; | |
376 | greth_regs *regs = greth->regs; | |
377 | greth_bd *txbd; | |
378 | void *txbuf; | |
379 | unsigned int status; | |
380 | #ifdef DEBUG | |
381 | printf("greth_send\n"); | |
382 | #endif | |
383 | /* send data, wait for data to be sent, then return */ | |
384 | if (((unsigned int)eth_data & (GRETH_BUF_ALIGN - 1)) | |
385 | && !greth->gbit_mac) { | |
386 | /* data not aligned as needed by GRETH 10/100, solve this by allocating 4 byte aligned buffer | |
387 | * and copy data to before giving it to GRETH. | |
388 | */ | |
389 | if (!greth->txbuf) { | |
390 | greth->txbuf = malloc(GRETH_RXBUF_SIZE); | |
391 | #ifdef DEBUG | |
392 | printf("GRETH: allocated aligned tx-buf\n"); | |
393 | #endif | |
394 | } | |
395 | ||
396 | txbuf = greth->txbuf; | |
397 | ||
398 | /* copy data info buffer */ | |
399 | memcpy((char *)txbuf, (char *)eth_data, data_length); | |
400 | ||
401 | /* keep buffer to next time */ | |
402 | } else { | |
403 | txbuf = (void *)eth_data; | |
404 | } | |
405 | /* get descriptor to use, only 1 supported... hehe easy */ | |
406 | txbd = greth->txbd_base; | |
407 | ||
408 | /* setup descriptor to wrap around to it self */ | |
409 | txbd->addr = (unsigned int)txbuf; | |
410 | txbd->stat = GRETH_BD_EN | GRETH_BD_WR | data_length; | |
411 | ||
412 | /* Remind Core which descriptor to use when sending */ | |
413 | GRETH_REGSAVE(®s->tx_desc_p, (unsigned int)txbd); | |
414 | ||
415 | /* initate send by enabling transmitter */ | |
416 | GRETH_REGORIN(®s->control, GRETH_TXEN); | |
417 | ||
418 | /* Wait for data to be sent */ | |
419 | while ((status = GRETH_REGLOAD(&txbd->stat)) & GRETH_BD_EN) { | |
420 | ; | |
421 | } | |
422 | ||
423 | /* was the packet transmitted succesfully? */ | |
424 | if (status & GRETH_TXBD_ERR_AL) { | |
425 | greth->stats.tx_limit_errors++; | |
426 | } | |
427 | ||
428 | if (status & GRETH_TXBD_ERR_UE) { | |
429 | greth->stats.tx_underrun_errors++; | |
430 | } | |
431 | ||
432 | if (status & GRETH_TXBD_ERR_LC) { | |
433 | greth->stats.tx_latecol_errors++; | |
434 | } | |
435 | ||
436 | if (status & | |
437 | (GRETH_TXBD_ERR_LC | GRETH_TXBD_ERR_UE | GRETH_TXBD_ERR_AL)) { | |
438 | /* any error */ | |
439 | greth->stats.tx_errors++; | |
440 | return -1; | |
441 | } | |
442 | ||
443 | /* bump tx packet counter */ | |
444 | greth->stats.tx_packets++; | |
445 | ||
446 | /* return succefully */ | |
447 | return 0; | |
448 | } | |
449 | ||
450 | int greth_recv(struct eth_device *dev) | |
451 | { | |
452 | greth_priv *greth = dev->priv; | |
453 | greth_regs *regs = greth->regs; | |
454 | greth_bd *rxbd; | |
455 | unsigned int status, len = 0, bad; | |
456 | unsigned char *d; | |
457 | int enable = 0; | |
458 | int i; | |
459 | #ifdef DEBUG | |
460 | /* printf("greth_recv\n"); */ | |
461 | #endif | |
462 | /* Receive One packet only, but clear as many error packets as there are | |
463 | * available. | |
464 | */ | |
465 | { | |
466 | /* current receive descriptor */ | |
467 | rxbd = greth->rxbd_curr; | |
468 | ||
469 | /* get status of next received packet */ | |
470 | status = GRETH_REGLOAD(&rxbd->stat); | |
471 | ||
472 | bad = 0; | |
473 | ||
474 | /* stop if no more packets received */ | |
475 | if (status & GRETH_BD_EN) { | |
476 | goto done; | |
477 | } | |
478 | #ifdef DEBUG | |
479 | printf("greth_recv: packet 0x%lx, 0x%lx, len: %d\n", | |
480 | (unsigned int)rxbd, status, status & GRETH_BD_LEN); | |
481 | #endif | |
482 | ||
483 | /* Check status for errors. | |
484 | */ | |
485 | if (status & GRETH_RXBD_ERR_FT) { | |
486 | greth->stats.rx_length_errors++; | |
487 | bad = 1; | |
488 | } | |
489 | if (status & (GRETH_RXBD_ERR_AE | GRETH_RXBD_ERR_OE)) { | |
490 | greth->stats.rx_frame_errors++; | |
491 | bad = 1; | |
492 | } | |
493 | if (status & GRETH_RXBD_ERR_CRC) { | |
494 | greth->stats.rx_crc_errors++; | |
495 | bad = 1; | |
496 | } | |
497 | if (bad) { | |
498 | greth->stats.rx_errors++; | |
499 | printf | |
500 | ("greth_recv: Bad packet (%d, %d, %d, 0x%08x, %d)\n", | |
501 | greth->stats.rx_length_errors, | |
502 | greth->stats.rx_frame_errors, | |
503 | greth->stats.rx_crc_errors, status, | |
504 | greth->stats.rx_packets); | |
505 | /* print all rx descriptors */ | |
506 | for (i = 0; i < GRETH_RXBD_CNT; i++) { | |
507 | printf("[%d]: Stat=0x%lx, Addr=0x%lx\n", i, | |
508 | GRETH_REGLOAD(&greth->rxbd_base[i].stat), | |
509 | GRETH_REGLOAD(&greth->rxbd_base[i]. | |
510 | addr)); | |
511 | } | |
512 | } else { | |
513 | /* Process the incoming packet. */ | |
514 | len = status & GRETH_BD_LEN; | |
515 | d = (char *)rxbd->addr; | |
516 | #ifdef DEBUG | |
517 | printf | |
518 | ("greth_recv: new packet, length: %d. data: %x %x %x %x %x %x %x %x\n", | |
519 | len, d[0], d[1], d[2], d[3], d[4], d[5], d[6], | |
520 | d[7]); | |
521 | #endif | |
522 | /* flush all data cache to make sure we're not reading old packet data */ | |
523 | sparc_dcache_flush_all(); | |
524 | ||
525 | /* pass packet on to network subsystem */ | |
526 | NetReceive((void *)d, len); | |
527 | ||
528 | /* bump stats counters */ | |
529 | greth->stats.rx_packets++; | |
530 | ||
531 | /* bad is now 0 ==> will stop loop */ | |
532 | } | |
533 | ||
534 | /* reenable descriptor to receive more packet with this descriptor, wrap around if needed */ | |
535 | rxbd->stat = | |
536 | GRETH_BD_EN | | |
537 | (((unsigned int)greth->rxbd_curr >= | |
538 | (unsigned int)greth->rxbd_max) ? GRETH_BD_WR : 0); | |
539 | enable = 1; | |
540 | ||
541 | /* increase index */ | |
542 | greth->rxbd_curr = | |
543 | ((unsigned int)greth->rxbd_curr >= | |
544 | (unsigned int)greth->rxbd_max) ? greth-> | |
545 | rxbd_base : (greth->rxbd_curr + 1); | |
546 | ||
547 | }; | |
548 | ||
549 | if (enable) { | |
550 | GRETH_REGORIN(®s->control, GRETH_RXEN); | |
551 | } | |
552 | done: | |
553 | /* return positive length of packet or 0 if non recieved */ | |
554 | return len; | |
555 | } | |
556 | ||
557 | void greth_set_hwaddr(greth_priv * greth, unsigned char *mac) | |
558 | { | |
559 | /* save new MAC address */ | |
560 | greth->dev->enetaddr[0] = greth->hwaddr[0] = mac[0]; | |
561 | greth->dev->enetaddr[1] = greth->hwaddr[1] = mac[1]; | |
562 | greth->dev->enetaddr[2] = greth->hwaddr[2] = mac[2]; | |
563 | greth->dev->enetaddr[3] = greth->hwaddr[3] = mac[3]; | |
564 | greth->dev->enetaddr[4] = greth->hwaddr[4] = mac[4]; | |
565 | greth->dev->enetaddr[5] = greth->hwaddr[5] = mac[5]; | |
566 | greth->regs->esa_msb = (mac[0] << 8) | mac[1]; | |
567 | greth->regs->esa_lsb = | |
568 | (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5]; | |
569 | #ifdef DEBUG | |
570 | printf("GRETH: New MAC address: %02x:%02x:%02x:%02x:%02x:%02x\n", | |
571 | mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); | |
572 | #endif | |
573 | } | |
574 | ||
575 | int greth_initialize(bd_t * bis) | |
576 | { | |
577 | greth_priv *greth; | |
578 | ambapp_apbdev apbdev; | |
579 | struct eth_device *dev; | |
580 | int i; | |
581 | char *addr_str, *end; | |
582 | unsigned char addr[6]; | |
583 | #ifdef DEBUG | |
584 | printf("Scanning for GRETH\n"); | |
585 | #endif | |
586 | /* Find Device & IRQ via AMBA Plug&Play information */ | |
587 | if (ambapp_apb_first(VENDOR_GAISLER, GAISLER_ETHMAC, &apbdev) != 1) { | |
588 | return -1; /* GRETH not found */ | |
589 | } | |
590 | ||
591 | greth = (greth_priv *) malloc(sizeof(greth_priv)); | |
592 | dev = (struct eth_device *)malloc(sizeof(struct eth_device)); | |
593 | memset(dev, 0, sizeof(struct eth_device)); | |
594 | memset(greth, 0, sizeof(greth_priv)); | |
595 | ||
596 | greth->regs = (greth_regs *) apbdev.address; | |
597 | greth->irq = apbdev.irq; | |
598 | #ifdef DEBUG | |
599 | printf("Found GRETH at 0x%lx, irq %d\n", greth->regs, greth->irq); | |
600 | #endif | |
601 | dev->priv = (void *)greth; | |
602 | dev->iobase = (unsigned int)greth->regs; | |
603 | dev->init = greth_init; | |
604 | dev->halt = greth_halt; | |
605 | dev->send = greth_send; | |
606 | dev->recv = greth_recv; | |
607 | greth->dev = dev; | |
608 | ||
609 | /* Reset Core */ | |
610 | GRETH_REGSAVE(&greth->regs->control, GRETH_RESET); | |
611 | ||
612 | /* Wait for core to finish reset cycle */ | |
613 | while (GRETH_REGLOAD(&greth->regs->control) & GRETH_RESET) ; | |
614 | ||
615 | /* Get the phy address which assumed to have been set | |
616 | correctly with the reset value in hardware */ | |
617 | greth->phyaddr = (GRETH_REGLOAD(&greth->regs->mdio) >> 11) & 0x1F; | |
618 | ||
619 | /* Check if mac is gigabit capable */ | |
620 | greth->gbit_mac = (GRETH_REGLOAD(&greth->regs->control) >> 27) & 1; | |
621 | ||
622 | /* Make descriptor string */ | |
623 | if (greth->gbit_mac) { | |
624 | sprintf(dev->name, "GRETH 10/100/GB"); | |
625 | } else { | |
626 | sprintf(dev->name, "GRETH 10/100"); | |
627 | } | |
628 | ||
629 | /* initiate PHY, select speed/duplex depending on connected PHY */ | |
630 | if (greth_init_phy(greth, bis)) { | |
631 | /* Failed to init PHY (timedout) */ | |
632 | return -1; | |
633 | } | |
634 | ||
635 | /* Register Device to EtherNet subsystem */ | |
636 | eth_register(dev); | |
637 | ||
638 | /* Get MAC address */ | |
639 | if ((addr_str = getenv("ethaddr")) != NULL) { | |
640 | for (i = 0; i < 6; i++) { | |
641 | addr[i] = | |
642 | addr_str ? simple_strtoul(addr_str, &end, 16) : 0; | |
643 | if (addr_str) { | |
644 | addr_str = (*end) ? end + 1 : end; | |
645 | } | |
646 | } | |
647 | } else { | |
648 | /* HW Address not found in environment, Set default HW address */ | |
649 | addr[0] = GRETH_HWADDR_0; /* MSB */ | |
650 | addr[1] = GRETH_HWADDR_1; | |
651 | addr[2] = GRETH_HWADDR_2; | |
652 | addr[3] = GRETH_HWADDR_3; | |
653 | addr[4] = GRETH_HWADDR_4; | |
654 | addr[5] = GRETH_HWADDR_5; /* LSB */ | |
655 | } | |
656 | ||
657 | /* set and remember MAC address */ | |
658 | greth_set_hwaddr(greth, addr); | |
659 | ||
660 | return 1; | |
661 | } |