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Commit | Line | Data |
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ac6dbb85 WD |
1 | /* |
2 | * INCA-IP internal switch ethernet driver. | |
3 | * | |
f8d813e3 | 4 | * (C) Copyright 2003-2004 |
ac6dbb85 WD |
5 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
ac6dbb85 WD |
8 | */ |
9 | ||
10 | ||
11 | #include <common.h> | |
12 | ||
ac6dbb85 WD |
13 | #include <malloc.h> |
14 | #include <net.h> | |
8218bd2a | 15 | #include <netdev.h> |
ac6dbb85 WD |
16 | #include <asm/inca-ip.h> |
17 | #include <asm/addrspace.h> | |
18 | ||
19 | ||
20 | #define NUM_RX_DESC PKTBUFSRX | |
21 | #define NUM_TX_DESC 3 | |
22 | #define TOUT_LOOP 1000000 | |
23 | ||
24 | ||
25 | #define DELAY udelay(10000) | |
356a0d9f WD |
26 | /* Sometimes the store word instruction hangs while writing to one |
27 | * of the Switch registers. Moving the instruction into a separate | |
28 | * function somehow makes the problem go away. | |
29 | */ | |
30 | static void SWORD(volatile u32 * reg, u32 value) | |
31 | { | |
32 | *reg = value; | |
33 | } | |
ac6dbb85 WD |
34 | |
35 | #define DMA_WRITE_REG(reg, value) *((volatile u32 *)reg) = (u32)value; | |
36 | #define DMA_READ_REG(reg, value) value = (u32)*((volatile u32*)reg) | |
37 | #define SW_WRITE_REG(reg, value) \ | |
356a0d9f | 38 | SWORD(reg, value);\ |
79d696fc | 39 | DELAY;\ |
356a0d9f | 40 | SWORD(reg, value); |
ac6dbb85 | 41 | |
79d696fc WD |
42 | #define SW_READ_REG(reg, value) \ |
43 | value = (u32)*((volatile u32*)reg);\ | |
44 | DELAY;\ | |
45 | value = (u32)*((volatile u32*)reg); | |
ac6dbb85 | 46 | |
79d696fc WD |
47 | #define INCA_DMA_TX_POLLING_TIME 0x07 |
48 | #define INCA_DMA_RX_POLLING_TIME 0x07 | |
ac6dbb85 | 49 | |
79d696fc WD |
50 | #define INCA_DMA_TX_HOLD 0x80000000 |
51 | #define INCA_DMA_TX_EOP 0x40000000 | |
52 | #define INCA_DMA_TX_SOP 0x20000000 | |
53 | #define INCA_DMA_TX_ICPT 0x10000000 | |
54 | #define INCA_DMA_TX_IEOP 0x08000000 | |
ac6dbb85 | 55 | |
79d696fc WD |
56 | #define INCA_DMA_RX_C 0x80000000 |
57 | #define INCA_DMA_RX_SOP 0x40000000 | |
58 | #define INCA_DMA_RX_EOP 0x20000000 | |
ac6dbb85 | 59 | |
f8d813e3 WD |
60 | #define INCA_SWITCH_PHY_SPEED_10H 0x1 |
61 | #define INCA_SWITCH_PHY_SPEED_10F 0x5 | |
62 | #define INCA_SWITCH_PHY_SPEED_100H 0x2 | |
63 | #define INCA_SWITCH_PHY_SPEED_100F 0x6 | |
64 | ||
cf56e110 | 65 | /************************ Auto MDIX settings ************************/ |
79d696fc WD |
66 | #define INCA_IP_AUTO_MDIX_LAN_PORTS_DIR INCA_IP_Ports_P1_DIR |
67 | #define INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL INCA_IP_Ports_P1_ALTSEL | |
68 | #define INCA_IP_AUTO_MDIX_LAN_PORTS_OUT INCA_IP_Ports_P1_OUT | |
69 | #define INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX 16 | |
70 | ||
71 | #define WAIT_SIGNAL_RETRIES 100 | |
72 | #define WAIT_LINK_RETRIES 100 | |
73 | #define LINK_RETRY_DELAY 2000 /* ms */ | |
cf56e110 | 74 | /********************************************************************/ |
ac6dbb85 WD |
75 | |
76 | typedef struct | |
77 | { | |
e0ac62d7 WD |
78 | union { |
79 | struct { | |
79d696fc WD |
80 | volatile u32 HOLD :1; |
81 | volatile u32 ICpt :1; | |
82 | volatile u32 IEop :1; | |
83 | volatile u32 offset :3; | |
84 | volatile u32 reserved0 :4; | |
85 | volatile u32 NFB :22; | |
ac6dbb85 WD |
86 | }field; |
87 | ||
88 | volatile u32 word; | |
89 | }params; | |
90 | ||
91 | volatile u32 nextRxDescPtr; | |
92 | ||
93 | volatile u32 RxDataPtr; | |
94 | ||
e0ac62d7 WD |
95 | union { |
96 | struct { | |
79d696fc WD |
97 | volatile u32 C :1; |
98 | volatile u32 Sop :1; | |
99 | volatile u32 Eop :1; | |
100 | volatile u32 reserved3 :12; | |
101 | volatile u32 NBT :17; | |
ac6dbb85 WD |
102 | }field; |
103 | ||
104 | volatile u32 word; | |
105 | }status; | |
106 | ||
107 | } inca_rx_descriptor_t; | |
108 | ||
109 | ||
110 | typedef struct | |
111 | { | |
e0ac62d7 WD |
112 | union { |
113 | struct { | |
79d696fc WD |
114 | volatile u32 HOLD :1; |
115 | volatile u32 Eop :1; | |
116 | volatile u32 Sop :1; | |
117 | volatile u32 ICpt :1; | |
118 | volatile u32 IEop :1; | |
119 | volatile u32 reserved0 :5; | |
120 | volatile u32 NBA :22; | |
ac6dbb85 WD |
121 | }field; |
122 | ||
123 | volatile u32 word; | |
124 | }params; | |
125 | ||
126 | volatile u32 nextTxDescPtr; | |
127 | ||
128 | volatile u32 TxDataPtr; | |
129 | ||
79d696fc WD |
130 | volatile u32 C :1; |
131 | volatile u32 reserved3 :31; | |
ac6dbb85 WD |
132 | |
133 | } inca_tx_descriptor_t; | |
134 | ||
135 | ||
136 | static inca_rx_descriptor_t rx_ring[NUM_RX_DESC] __attribute__ ((aligned(16))); | |
137 | static inca_tx_descriptor_t tx_ring[NUM_TX_DESC] __attribute__ ((aligned(16))); | |
138 | ||
139 | static int tx_new, rx_new, tx_hold, rx_hold; | |
140 | static int tx_old_hold = -1; | |
79d696fc | 141 | static int initialized = 0; |
ac6dbb85 WD |
142 | |
143 | ||
144 | static int inca_switch_init(struct eth_device *dev, bd_t * bis); | |
10cbe3b6 | 145 | static int inca_switch_send(struct eth_device *dev, void *packet, int length); |
ac6dbb85 WD |
146 | static int inca_switch_recv(struct eth_device *dev); |
147 | static void inca_switch_halt(struct eth_device *dev); | |
148 | static void inca_init_switch_chip(void); | |
149 | static void inca_dma_init(void); | |
cf56e110 | 150 | static int inca_amdix(void); |
ac6dbb85 WD |
151 | |
152 | ||
ac6dbb85 WD |
153 | int inca_switch_initialize(bd_t * bis) |
154 | { | |
155 | struct eth_device *dev; | |
156 | ||
157 | #if 0 | |
158 | printf("Entered inca_switch_initialize()\n"); | |
159 | #endif | |
160 | ||
e0ac62d7 | 161 | if (!(dev = (struct eth_device *) malloc (sizeof *dev))) { |
ac6dbb85 WD |
162 | printf("Failed to allocate memory\n"); |
163 | return 0; | |
164 | } | |
165 | memset(dev, 0, sizeof(*dev)); | |
166 | ||
167 | inca_dma_init(); | |
168 | ||
169 | inca_init_switch_chip(); | |
3c74e32a | 170 | |
0c852a28 | 171 | #if defined(CONFIG_INCA_IP_SWITCH_AMDIX) |
cf56e110 | 172 | inca_amdix(); |
0c852a28 | 173 | #endif |
ac6dbb85 WD |
174 | |
175 | sprintf(dev->name, "INCA-IP Switch"); | |
176 | dev->init = inca_switch_init; | |
177 | dev->halt = inca_switch_halt; | |
178 | dev->send = inca_switch_send; | |
179 | dev->recv = inca_switch_recv; | |
180 | ||
181 | eth_register(dev); | |
182 | ||
183 | #if 0 | |
184 | printf("Leaving inca_switch_initialize()\n"); | |
185 | #endif | |
186 | ||
8218bd2a | 187 | return 0; |
ac6dbb85 WD |
188 | } |
189 | ||
190 | ||
191 | static int inca_switch_init(struct eth_device *dev, bd_t * bis) | |
192 | { | |
193 | int i; | |
194 | u32 v, regValue; | |
195 | u16 wTmp; | |
196 | ||
197 | #if 0 | |
198 | printf("Entering inca_switch_init()\n"); | |
199 | #endif | |
200 | ||
e0ac62d7 WD |
201 | /* Set MAC address. |
202 | */ | |
ac6dbb85 WD |
203 | wTmp = (u16)dev->enetaddr[0]; |
204 | regValue = (wTmp << 8) | dev->enetaddr[1]; | |
205 | ||
206 | SW_WRITE_REG(INCA_IP_Switch_PMAC_SA1, regValue); | |
207 | ||
208 | wTmp = (u16)dev->enetaddr[2]; | |
209 | regValue = (wTmp << 8) | dev->enetaddr[3]; | |
210 | regValue = regValue << 16; | |
211 | wTmp = (u16)dev->enetaddr[4]; | |
212 | regValue |= (wTmp<<8) | dev->enetaddr[5]; | |
213 | ||
214 | SW_WRITE_REG(INCA_IP_Switch_PMAC_SA2, regValue); | |
215 | ||
e0ac62d7 WD |
216 | /* Initialize the descriptor rings. |
217 | */ | |
f8d813e3 | 218 | for (i = 0; i < NUM_RX_DESC; i++) { |
7daf2ebe | 219 | inca_rx_descriptor_t * rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[i]); |
ac6dbb85 WD |
220 | memset(rx_desc, 0, sizeof(rx_ring[i])); |
221 | ||
e0ac62d7 WD |
222 | /* Set maximum size of receive buffer. |
223 | */ | |
ac6dbb85 WD |
224 | rx_desc->params.field.NFB = PKTSIZE_ALIGN; |
225 | ||
e0ac62d7 WD |
226 | /* Set the offset of the receive buffer. Zero means |
227 | * that the offset mechanism is not used. | |
228 | */ | |
ac6dbb85 WD |
229 | rx_desc->params.field.offset = 0; |
230 | ||
231 | /* Check if it is the last descriptor. | |
232 | */ | |
e0ac62d7 WD |
233 | if (i == (NUM_RX_DESC - 1)) { |
234 | /* Let the last descriptor point to the first | |
235 | * one. | |
236 | */ | |
7daf2ebe | 237 | rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(rx_ring); |
e0ac62d7 WD |
238 | } else { |
239 | /* Set the address of the next descriptor. | |
240 | */ | |
7daf2ebe | 241 | rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(&rx_ring[i+1]); |
ac6dbb85 WD |
242 | } |
243 | ||
7daf2ebe | 244 | rx_desc->RxDataPtr = (u32)CKSEG1ADDR(NetRxPackets[i]); |
ac6dbb85 WD |
245 | } |
246 | ||
247 | #if 0 | |
248 | printf("rx_ring = 0x%08X 0x%08X\n", (u32)rx_ring, (u32)&rx_ring[0]); | |
249 | printf("tx_ring = 0x%08X 0x%08X\n", (u32)tx_ring, (u32)&tx_ring[0]); | |
250 | #endif | |
251 | ||
e0ac62d7 | 252 | for (i = 0; i < NUM_TX_DESC; i++) { |
7daf2ebe | 253 | inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[i]); |
ac6dbb85 WD |
254 | |
255 | memset(tx_desc, 0, sizeof(tx_ring[i])); | |
256 | ||
79d696fc | 257 | tx_desc->params.word = 0; |
ac6dbb85 | 258 | tx_desc->params.field.HOLD = 1; |
79d696fc | 259 | tx_desc->C = 1; |
ac6dbb85 WD |
260 | |
261 | /* Check if it is the last descriptor. | |
262 | */ | |
e0ac62d7 | 263 | if (i == (NUM_TX_DESC - 1)) { |
ac6dbb85 WD |
264 | /* Let the last descriptor point to the |
265 | * first one. | |
266 | */ | |
7daf2ebe | 267 | tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(tx_ring); |
e0ac62d7 | 268 | } else { |
ac6dbb85 WD |
269 | /* Set the address of the next descriptor. |
270 | */ | |
7daf2ebe | 271 | tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(&tx_ring[i+1]); |
ac6dbb85 WD |
272 | } |
273 | } | |
274 | ||
e0ac62d7 WD |
275 | /* Initialize RxDMA. |
276 | */ | |
ac6dbb85 | 277 | DMA_READ_REG(INCA_IP_DMA_DMA_RXISR, v); |
d82a27bc | 278 | debug("RX status = 0x%08X\n", v); |
ac6dbb85 | 279 | |
e0ac62d7 WD |
280 | /* Writing to the FRDA of CHANNEL. |
281 | */ | |
ac6dbb85 WD |
282 | DMA_WRITE_REG(INCA_IP_DMA_DMA_RXFRDA0, (u32)rx_ring); |
283 | ||
e0ac62d7 WD |
284 | /* Writing to the COMMAND REG. |
285 | */ | |
79d696fc | 286 | DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_INIT); |
ac6dbb85 | 287 | |
e0ac62d7 WD |
288 | /* Initialize TxDMA. |
289 | */ | |
ac6dbb85 | 290 | DMA_READ_REG(INCA_IP_DMA_DMA_TXISR, v); |
d82a27bc | 291 | debug("TX status = 0x%08X\n", v); |
ac6dbb85 | 292 | |
e0ac62d7 WD |
293 | /* Writing to the FRDA of CHANNEL. |
294 | */ | |
ac6dbb85 WD |
295 | DMA_WRITE_REG(INCA_IP_DMA_DMA_TXFRDA0, (u32)tx_ring); |
296 | ||
297 | tx_new = rx_new = 0; | |
298 | ||
299 | tx_hold = NUM_TX_DESC - 1; | |
300 | rx_hold = NUM_RX_DESC - 1; | |
301 | ||
302 | #if 0 | |
303 | rx_ring[rx_hold].params.field.HOLD = 1; | |
304 | #endif | |
e0ac62d7 WD |
305 | /* enable spanning tree forwarding, enable the CPU port */ |
306 | /* ST_PT: | |
79d696fc WD |
307 | * CPS (CPU port status) 0x3 (forwarding) |
308 | * LPS (LAN port status) 0x3 (forwarding) | |
309 | * PPS (PC port status) 0x3 (forwarding) | |
e0ac62d7 | 310 | */ |
ac6dbb85 WD |
311 | SW_WRITE_REG(INCA_IP_Switch_ST_PT,0x3f); |
312 | ||
313 | #if 0 | |
314 | printf("Leaving inca_switch_init()\n"); | |
315 | #endif | |
316 | ||
317 | return 0; | |
318 | } | |
319 | ||
320 | ||
10cbe3b6 | 321 | static int inca_switch_send(struct eth_device *dev, void *packet, int length) |
ac6dbb85 | 322 | { |
79d696fc WD |
323 | int i; |
324 | int res = -1; | |
325 | u32 command; | |
326 | u32 regValue; | |
7daf2ebe | 327 | inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_new]); |
ac6dbb85 WD |
328 | |
329 | #if 0 | |
330 | printf("Entered inca_switch_send()\n"); | |
331 | #endif | |
332 | ||
e0ac62d7 | 333 | if (length <= 0) { |
ac6dbb85 WD |
334 | printf ("%s: bad packet size: %d\n", dev->name, length); |
335 | goto Done; | |
336 | } | |
8bde7f77 | 337 | |
e0ac62d7 WD |
338 | for(i = 0; tx_desc->C == 0; i++) { |
339 | if (i >= TOUT_LOOP) { | |
ac6dbb85 WD |
340 | printf("%s: tx error buffer not ready\n", dev->name); |
341 | goto Done; | |
342 | } | |
343 | } | |
344 | ||
e0ac62d7 | 345 | if (tx_old_hold >= 0) { |
7daf2ebe | 346 | ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_old_hold]))->params.field.HOLD = 1; |
ac6dbb85 WD |
347 | } |
348 | tx_old_hold = tx_hold; | |
349 | ||
350 | tx_desc->params.word = | |
8bde7f77 | 351 | (INCA_DMA_TX_SOP | INCA_DMA_TX_EOP | INCA_DMA_TX_HOLD); |
ac6dbb85 WD |
352 | |
353 | tx_desc->C = 0; | |
354 | tx_desc->TxDataPtr = (u32)packet; | |
355 | tx_desc->params.field.NBA = length; | |
356 | ||
7daf2ebe | 357 | ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->params.field.HOLD = 0; |
ac6dbb85 WD |
358 | |
359 | tx_hold = tx_new; | |
79d696fc | 360 | tx_new = (tx_new + 1) % NUM_TX_DESC; |
ac6dbb85 WD |
361 | |
362 | ||
e0ac62d7 | 363 | if (! initialized) { |
ac6dbb85 WD |
364 | command = INCA_IP_DMA_DMA_TXCCR0_INIT; |
365 | initialized = 1; | |
e0ac62d7 | 366 | } else { |
ac6dbb85 WD |
367 | command = INCA_IP_DMA_DMA_TXCCR0_HR; |
368 | } | |
8bde7f77 | 369 | |
ac6dbb85 WD |
370 | DMA_READ_REG(INCA_IP_DMA_DMA_TXCCR0, regValue); |
371 | regValue |= command; | |
372 | #if 0 | |
373 | printf("regValue = 0x%x\n", regValue); | |
374 | #endif | |
375 | DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, regValue); | |
376 | ||
377 | #if 1 | |
7daf2ebe | 378 | for(i = 0; ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->C == 0; i++) { |
e0ac62d7 | 379 | if (i >= TOUT_LOOP) { |
ac6dbb85 WD |
380 | printf("%s: tx buffer not ready\n", dev->name); |
381 | goto Done; | |
382 | } | |
383 | } | |
384 | #endif | |
385 | res = length; | |
386 | Done: | |
387 | #if 0 | |
388 | printf("Leaving inca_switch_send()\n"); | |
389 | #endif | |
390 | return res; | |
391 | } | |
392 | ||
393 | ||
394 | static int inca_switch_recv(struct eth_device *dev) | |
395 | { | |
79d696fc | 396 | int length = 0; |
ac6dbb85 WD |
397 | inca_rx_descriptor_t * rx_desc; |
398 | ||
399 | #if 0 | |
400 | printf("Entered inca_switch_recv()\n"); | |
401 | #endif | |
402 | ||
e0ac62d7 | 403 | for (;;) { |
7daf2ebe | 404 | rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_new]); |
ac6dbb85 | 405 | |
e0ac62d7 | 406 | if (rx_desc->status.field.C == 0) { |
ac6dbb85 WD |
407 | break; |
408 | } | |
409 | ||
410 | #if 0 | |
411 | rx_ring[rx_new].params.field.HOLD = 1; | |
412 | #endif | |
413 | ||
e0ac62d7 | 414 | if (! rx_desc->status.field.Eop) { |
ac6dbb85 WD |
415 | printf("Partly received packet!!!\n"); |
416 | break; | |
417 | } | |
418 | ||
419 | length = rx_desc->status.field.NBT; | |
420 | rx_desc->status.word &= | |
8bde7f77 | 421 | ~(INCA_DMA_RX_EOP | INCA_DMA_RX_SOP | INCA_DMA_RX_C); |
ac6dbb85 WD |
422 | #if 0 |
423 | { | |
424 | int i; | |
425 | for (i=0;i<length - 4;i++) { | |
426 | if (i % 16 == 0) printf("\n%04x: ", i); | |
427 | printf("%02X ", NetRxPackets[rx_new][i]); | |
428 | } | |
429 | printf("\n"); | |
430 | } | |
431 | #endif | |
432 | ||
e0ac62d7 | 433 | if (length) { |
ac6dbb85 WD |
434 | #if 0 |
435 | printf("Received %d bytes\n", length); | |
436 | #endif | |
7daf2ebe | 437 | NetReceive((void*)CKSEG1ADDR(NetRxPackets[rx_new]), length - 4); |
e0ac62d7 | 438 | } else { |
ac6dbb85 WD |
439 | #if 1 |
440 | printf("Zero length!!!\n"); | |
441 | #endif | |
442 | } | |
443 | ||
444 | ||
7daf2ebe | 445 | ((inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_hold]))->params.field.HOLD = 0; |
ac6dbb85 WD |
446 | |
447 | rx_hold = rx_new; | |
448 | ||
449 | rx_new = (rx_new + 1) % NUM_RX_DESC; | |
450 | } | |
451 | ||
452 | #if 0 | |
453 | printf("Leaving inca_switch_recv()\n"); | |
454 | #endif | |
455 | ||
456 | return length; | |
457 | } | |
458 | ||
459 | ||
460 | static void inca_switch_halt(struct eth_device *dev) | |
461 | { | |
462 | #if 0 | |
463 | printf("Entered inca_switch_halt()\n"); | |
464 | #endif | |
465 | ||
466 | #if 1 | |
467 | initialized = 0; | |
468 | #endif | |
469 | #if 1 | |
e0ac62d7 WD |
470 | /* Disable forwarding to the CPU port. |
471 | */ | |
ac6dbb85 WD |
472 | SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf); |
473 | ||
e0ac62d7 WD |
474 | /* Close RxDMA channel. |
475 | */ | |
ac6dbb85 WD |
476 | DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF); |
477 | ||
e0ac62d7 WD |
478 | /* Close TxDMA channel. |
479 | */ | |
ac6dbb85 WD |
480 | DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_TXCCR0_OFF); |
481 | ||
482 | ||
483 | #endif | |
484 | #if 0 | |
485 | printf("Leaving inca_switch_halt()\n"); | |
486 | #endif | |
487 | } | |
488 | ||
489 | ||
490 | static void inca_init_switch_chip(void) | |
491 | { | |
492 | u32 regValue; | |
493 | ||
e0ac62d7 WD |
494 | /* To workaround a problem with collision counter |
495 | * (see Errata sheet). | |
496 | */ | |
ac6dbb85 WD |
497 | SW_WRITE_REG(INCA_IP_Switch_PC_TX_CTL, 0x00000001); |
498 | SW_WRITE_REG(INCA_IP_Switch_LAN_TX_CTL, 0x00000001); | |
499 | ||
500 | #if 1 | |
e0ac62d7 | 501 | /* init MDIO configuration: |
79d696fc WD |
502 | * MDS (Poll speed): 0x01 (4ms) |
503 | * PHY_LAN_ADDR: 0x06 | |
504 | * PHY_PC_ADDR: 0x05 | |
e0ac62d7 | 505 | * UEP (Use External PHY): 0x00 (Internal PHY is used) |
79d696fc WD |
506 | * PS (Port Select): 0x00 (PT/UMM for LAN) |
507 | * PT (PHY Test): 0x00 (no test mode) | |
508 | * UMM (Use MDIO Mode): 0x00 (state machine is disabled) | |
e0ac62d7 | 509 | */ |
ac6dbb85 WD |
510 | SW_WRITE_REG(INCA_IP_Switch_MDIO_CFG, 0x4c50); |
511 | ||
e0ac62d7 WD |
512 | /* init PHY: |
513 | * SL (Auto Neg. Speed for LAN) | |
514 | * SP (Auto Neg. Speed for PC) | |
515 | * LL (Link Status for LAN) | |
516 | * LP (Link Status for PC) | |
517 | * DL (Duplex Status for LAN) | |
518 | * DP (Duplex Status for PC) | |
519 | * PL (Auto Neg. Pause Status for LAN) | |
520 | * PP (Auto Neg. Pause Status for PC) | |
521 | */ | |
ac6dbb85 WD |
522 | SW_WRITE_REG (INCA_IP_Switch_EPHY, 0xff); |
523 | ||
e0ac62d7 WD |
524 | /* MDIO_ACC: |
525 | * RA (Request/Ack) 0x01 (Request) | |
79d696fc WD |
526 | * RW (Read/Write) 0x01 (Write) |
527 | * PHY_ADDR 0x05 (PC) | |
528 | * REG_ADDR 0x00 (PHY_BCR: basic control register) | |
529 | * PHY_DATA 0x8000 | |
530 | * Reset - software reset | |
531 | * LB (loop back) - normal | |
532 | * SS (speed select) - 10 Mbit/s | |
e0ac62d7 | 533 | * ANE (auto neg. enable) - enable |
79d696fc WD |
534 | * PD (power down) - normal |
535 | * ISO (isolate) - normal | |
e0ac62d7 | 536 | * RAN (restart auto neg.) - normal |
79d696fc | 537 | * DM (duplex mode) - half duplex |
e0ac62d7 WD |
538 | * CT (collision test) - enable |
539 | */ | |
540 | SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0a09000); | |
541 | ||
542 | /* MDIO_ACC: | |
543 | * RA (Request/Ack) 0x01 (Request) | |
79d696fc WD |
544 | * RW (Read/Write) 0x01 (Write) |
545 | * PHY_ADDR 0x06 (LAN) | |
546 | * REG_ADDR 0x00 (PHY_BCR: basic control register) | |
547 | * PHY_DATA 0x8000 | |
548 | * Reset - software reset | |
549 | * LB (loop back) - normal | |
550 | * SS (speed select) - 10 Mbit/s | |
e0ac62d7 | 551 | * ANE (auto neg. enable) - enable |
79d696fc WD |
552 | * PD (power down) - normal |
553 | * ISO (isolate) - normal | |
e0ac62d7 | 554 | * RAN (restart auto neg.) - normal |
79d696fc | 555 | * DM (duplex mode) - half duplex |
e0ac62d7 WD |
556 | * CT (collision test) - enable |
557 | */ | |
79d696fc | 558 | SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0c09000); |
e0ac62d7 | 559 | |
ac6dbb85 WD |
560 | #endif |
561 | ||
e0ac62d7 WD |
562 | /* Make sure the CPU port is disabled for now. We |
563 | * don't want packets to get stacked for us until | |
564 | * we enable DMA and are prepared to receive them. | |
565 | */ | |
ac6dbb85 WD |
566 | SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf); |
567 | ||
568 | SW_READ_REG(INCA_IP_Switch_ARL_CTL, regValue); | |
569 | ||
e0ac62d7 WD |
570 | /* CRC GEN is enabled. |
571 | */ | |
ac6dbb85 WD |
572 | regValue |= 0x00000200; |
573 | SW_WRITE_REG(INCA_IP_Switch_ARL_CTL, regValue); | |
574 | ||
e0ac62d7 WD |
575 | /* ADD TAG is disabled. |
576 | */ | |
ac6dbb85 WD |
577 | SW_READ_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue); |
578 | regValue &= ~0x00000002; | |
579 | SW_WRITE_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue); | |
580 | } | |
581 | ||
582 | ||
583 | static void inca_dma_init(void) | |
584 | { | |
e0ac62d7 WD |
585 | /* Switch off all DMA channels. |
586 | */ | |
ac6dbb85 WD |
587 | DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF); |
588 | DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR1, INCA_IP_DMA_DMA_RXCCR1_OFF); | |
589 | ||
590 | DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF); | |
591 | DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR1, INCA_IP_DMA_DMA_TXCCR1_OFF); | |
592 | DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR2, INCA_IP_DMA_DMA_TXCCR2_OFF); | |
593 | ||
e0ac62d7 WD |
594 | /* Setup TX channel polling time. |
595 | */ | |
ac6dbb85 WD |
596 | DMA_WRITE_REG(INCA_IP_DMA_DMA_TXPOLL, INCA_DMA_TX_POLLING_TIME); |
597 | ||
e0ac62d7 WD |
598 | /* Setup RX channel polling time. |
599 | */ | |
ac6dbb85 WD |
600 | DMA_WRITE_REG(INCA_IP_DMA_DMA_RXPOLL, INCA_DMA_RX_POLLING_TIME); |
601 | ||
e0ac62d7 WD |
602 | /* ERRATA: write reset value into the DMA RX IMR register. |
603 | */ | |
ac6dbb85 WD |
604 | DMA_WRITE_REG(INCA_IP_DMA_DMA_RXIMR, 0xFFFFFFFF); |
605 | ||
e0ac62d7 WD |
606 | /* Just in case: disable all transmit interrupts also. |
607 | */ | |
ac6dbb85 WD |
608 | DMA_WRITE_REG(INCA_IP_DMA_DMA_TXIMR, 0xFFFFFFFF); |
609 | ||
610 | DMA_WRITE_REG(INCA_IP_DMA_DMA_TXISR, 0xFFFFFFFF); | |
611 | DMA_WRITE_REG(INCA_IP_DMA_DMA_RXISR, 0xFFFFFFFF); | |
612 | } | |
613 | ||
0c852a28 | 614 | #if defined(CONFIG_INCA_IP_SWITCH_AMDIX) |
cf56e110 WD |
615 | static int inca_amdix(void) |
616 | { | |
f8d813e3 WD |
617 | u32 phyReg1 = 0; |
618 | u32 phyReg4 = 0; | |
619 | u32 phyReg5 = 0; | |
620 | u32 phyReg6 = 0; | |
621 | u32 phyReg31 = 0; | |
622 | u32 regEphy = 0; | |
cf56e110 WD |
623 | int mdi_flag; |
624 | int retries; | |
625 | ||
626 | /* Setup GPIO pins. | |
627 | */ | |
628 | *INCA_IP_AUTO_MDIX_LAN_PORTS_DIR |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); | |
629 | *INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); | |
630 | ||
f8d813e3 | 631 | #if 0 |
cf56e110 WD |
632 | /* Wait for signal. |
633 | */ | |
634 | retries = WAIT_SIGNAL_RETRIES; | |
f8d813e3 | 635 | while (--retries) { |
cf56e110 WD |
636 | SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, |
637 | (0x1 << 31) | /* RA */ | |
638 | (0x0 << 30) | /* Read */ | |
639 | (0x6 << 21) | /* LAN */ | |
640 | (17 << 16)); /* PHY_MCSR */ | |
f8d813e3 WD |
641 | do { |
642 | SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1); | |
643 | } while (phyReg1 & (1 << 31)); | |
cf56e110 | 644 | |
f8d813e3 | 645 | if (phyReg1 & (1 << 1)) { |
cf56e110 WD |
646 | /* Signal detected */ |
647 | break; | |
648 | } | |
649 | } | |
650 | ||
651 | if (!retries) | |
f8d813e3 WD |
652 | goto Fail; |
653 | #endif | |
cf56e110 WD |
654 | |
655 | /* Set MDI mode. | |
656 | */ | |
657 | *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); | |
658 | mdi_flag = 1; | |
659 | ||
660 | /* Wait for link. | |
661 | */ | |
662 | retries = WAIT_LINK_RETRIES; | |
f8d813e3 | 663 | while (--retries) { |
cf56e110 WD |
664 | udelay(LINK_RETRY_DELAY * 1000); |
665 | SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, | |
666 | (0x1 << 31) | /* RA */ | |
667 | (0x0 << 30) | /* Read */ | |
668 | (0x6 << 21) | /* LAN */ | |
669 | (1 << 16)); /* PHY_BSR */ | |
f8d813e3 WD |
670 | do { |
671 | SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1); | |
672 | } while (phyReg1 & (1 << 31)); | |
cf56e110 | 673 | |
f8d813e3 | 674 | if (phyReg1 & (1 << 2)) { |
cf56e110 WD |
675 | /* Link is up */ |
676 | break; | |
f8d813e3 | 677 | } else if (mdi_flag) { |
cf56e110 WD |
678 | /* Set MDIX mode */ |
679 | *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); | |
680 | mdi_flag = 0; | |
f8d813e3 | 681 | } else { |
cf56e110 WD |
682 | /* Set MDI mode */ |
683 | *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); | |
684 | mdi_flag = 1; | |
685 | } | |
686 | } | |
687 | ||
f8d813e3 WD |
688 | if (!retries) { |
689 | goto Fail; | |
690 | } else { | |
691 | SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, | |
692 | (0x1 << 31) | /* RA */ | |
693 | (0x0 << 30) | /* Read */ | |
694 | (0x6 << 21) | /* LAN */ | |
695 | (1 << 16)); /* PHY_BSR */ | |
696 | do { | |
697 | SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1); | |
698 | } while (phyReg1 & (1 << 31)); | |
699 | ||
700 | /* Auto-negotiation / Parallel detection complete | |
701 | */ | |
702 | if (phyReg1 & (1 << 5)) { | |
703 | SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, | |
704 | (0x1 << 31) | /* RA */ | |
705 | (0x0 << 30) | /* Read */ | |
706 | (0x6 << 21) | /* LAN */ | |
707 | (31 << 16)); /* PHY_SCSR */ | |
708 | do { | |
79d696fc | 709 | SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg31); |
f8d813e3 WD |
710 | } while (phyReg31 & (1 << 31)); |
711 | ||
712 | switch ((phyReg31 >> 2) & 0x7) { | |
713 | case INCA_SWITCH_PHY_SPEED_10H: | |
714 | /* 10Base-T Half-duplex */ | |
715 | regEphy = 0; | |
716 | break; | |
717 | case INCA_SWITCH_PHY_SPEED_10F: | |
718 | /* 10Base-T Full-duplex */ | |
719 | regEphy = INCA_IP_Switch_EPHY_DL; | |
720 | break; | |
721 | case INCA_SWITCH_PHY_SPEED_100H: | |
722 | /* 100Base-TX Half-duplex */ | |
723 | regEphy = INCA_IP_Switch_EPHY_SL; | |
724 | break; | |
725 | case INCA_SWITCH_PHY_SPEED_100F: | |
726 | /* 100Base-TX Full-duplex */ | |
727 | regEphy = INCA_IP_Switch_EPHY_SL | INCA_IP_Switch_EPHY_DL; | |
728 | break; | |
729 | } | |
730 | ||
731 | /* In case of Auto-negotiation, | |
732 | * update the negotiated PAUSE support status | |
733 | */ | |
734 | if (phyReg1 & (1 << 3)) { | |
735 | SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, | |
736 | (0x1 << 31) | /* RA */ | |
737 | (0x0 << 30) | /* Read */ | |
738 | (0x6 << 21) | /* LAN */ | |
8ef583a0 | 739 | (6 << 16)); /* MII_EXPANSION */ |
f8d813e3 | 740 | do { |
79d696fc | 741 | SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg6); |
f8d813e3 WD |
742 | } while (phyReg6 & (1 << 31)); |
743 | ||
744 | /* We are Autoneg-able. | |
745 | * Is Link partner also able to autoneg? | |
746 | */ | |
747 | if (phyReg6 & (1 << 0)) { | |
748 | SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, | |
749 | (0x1 << 31) | /* RA */ | |
750 | (0x0 << 30) | /* Read */ | |
751 | (0x6 << 21) | /* LAN */ | |
8ef583a0 | 752 | (4 << 16)); /* MII_ADVERTISE */ |
f8d813e3 | 753 | do { |
79d696fc | 754 | SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg4); |
f8d813e3 WD |
755 | } while (phyReg4 & (1 << 31)); |
756 | ||
757 | /* We advertise PAUSE capab. | |
758 | * Does link partner also advertise it? | |
759 | */ | |
760 | if (phyReg4 & (1 << 10)) { | |
761 | SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, | |
762 | (0x1 << 31) | /* RA */ | |
763 | (0x0 << 30) | /* Read */ | |
764 | (0x6 << 21) | /* LAN */ | |
8ef583a0 | 765 | (5 << 16)); /* MII_LPA */ |
f8d813e3 | 766 | do { |
79d696fc | 767 | SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg5); |
f8d813e3 WD |
768 | } while (phyReg5 & (1 << 31)); |
769 | ||
770 | /* Link partner is PAUSE capab. | |
771 | */ | |
772 | if (phyReg5 & (1 << 10)) { | |
773 | regEphy |= INCA_IP_Switch_EPHY_PL; | |
774 | } | |
775 | } | |
776 | } | |
777 | ||
778 | } | |
779 | ||
780 | /* Link is up */ | |
781 | regEphy |= INCA_IP_Switch_EPHY_LL; | |
782 | ||
783 | SW_WRITE_REG(INCA_IP_Switch_EPHY, regEphy); | |
784 | } | |
785 | } | |
cf56e110 WD |
786 | |
787 | return 0; | |
f8d813e3 WD |
788 | |
789 | Fail: | |
790 | printf("No Link on LAN port\n"); | |
791 | return -1; | |
cf56e110 | 792 | } |
0c852a28 | 793 | #endif /* CONFIG_INCA_IP_SWITCH_AMDIX */ |