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d3a2ae6d YZ |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
8c47eaa7 | 4 | Copyright(c) 1999 - 2010 Intel Corporation. |
d3a2ae6d YZ |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | ||
29 | #include "ixgbe.h" | |
6ee16520 YZ |
30 | #ifdef CONFIG_IXGBE_DCB |
31 | #include "ixgbe_dcb_82599.h" | |
32 | #endif /* CONFIG_IXGBE_DCB */ | |
d3a2ae6d | 33 | #include <linux/if_ether.h> |
5a0e3ad6 | 34 | #include <linux/gfp.h> |
d3a2ae6d YZ |
35 | #include <scsi/scsi_cmnd.h> |
36 | #include <scsi/scsi_device.h> | |
37 | #include <scsi/fc/fc_fs.h> | |
38 | #include <scsi/fc/fc_fcoe.h> | |
39 | #include <scsi/libfc.h> | |
40 | #include <scsi/libfcoe.h> | |
41 | ||
d0ed8937 YZ |
42 | /** |
43 | * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type | |
44 | * @rx_desc: advanced rx descriptor | |
45 | * | |
46 | * Returns : true if it is FCoE pkt | |
47 | */ | |
48 | static inline bool ixgbe_rx_is_fcoe(union ixgbe_adv_rx_desc *rx_desc) | |
49 | { | |
50 | u16 p; | |
51 | ||
52 | p = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info); | |
53 | if (p & IXGBE_RXDADV_PKTTYPE_ETQF) { | |
54 | p &= IXGBE_RXDADV_PKTTYPE_ETQF_MASK; | |
55 | p >>= IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT; | |
56 | return p == IXGBE_ETQF_FILTER_FCOE; | |
57 | } | |
58 | return false; | |
59 | } | |
60 | ||
61 | /** | |
62 | * ixgbe_fcoe_clear_ddp - clear the given ddp context | |
63 | * @ddp - ptr to the ixgbe_fcoe_ddp | |
64 | * | |
65 | * Returns : none | |
66 | * | |
67 | */ | |
68 | static inline void ixgbe_fcoe_clear_ddp(struct ixgbe_fcoe_ddp *ddp) | |
69 | { | |
70 | ddp->len = 0; | |
71 | ddp->err = 0; | |
72 | ddp->udl = NULL; | |
73 | ddp->udp = 0UL; | |
74 | ddp->sgl = NULL; | |
75 | ddp->sgc = 0; | |
76 | } | |
77 | ||
78 | /** | |
79 | * ixgbe_fcoe_ddp_put - free the ddp context for a given xid | |
80 | * @netdev: the corresponding net_device | |
81 | * @xid: the xid that corresponding ddp will be freed | |
82 | * | |
83 | * This is the implementation of net_device_ops.ndo_fcoe_ddp_done | |
84 | * and it is expected to be called by ULD, i.e., FCP layer of libfc | |
85 | * to release the corresponding ddp context when the I/O is done. | |
86 | * | |
87 | * Returns : data length already ddp-ed in bytes | |
88 | */ | |
89 | int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid) | |
90 | { | |
91 | int len = 0; | |
92 | struct ixgbe_fcoe *fcoe; | |
93 | struct ixgbe_adapter *adapter; | |
94 | struct ixgbe_fcoe_ddp *ddp; | |
95 | ||
96 | if (!netdev) | |
97 | goto out_ddp_put; | |
98 | ||
99 | if (xid >= IXGBE_FCOE_DDP_MAX) | |
100 | goto out_ddp_put; | |
101 | ||
102 | adapter = netdev_priv(netdev); | |
103 | fcoe = &adapter->fcoe; | |
104 | ddp = &fcoe->ddp[xid]; | |
105 | if (!ddp->udl) | |
106 | goto out_ddp_put; | |
107 | ||
108 | len = ddp->len; | |
109 | /* if there an error, force to invalidate ddp context */ | |
110 | if (ddp->err) { | |
111 | spin_lock_bh(&fcoe->lock); | |
112 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCFLT, 0); | |
113 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCFLTRW, | |
114 | (xid | IXGBE_FCFLTRW_WE)); | |
115 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCBUFF, 0); | |
116 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCDMARW, | |
117 | (xid | IXGBE_FCDMARW_WE)); | |
118 | spin_unlock_bh(&fcoe->lock); | |
119 | } | |
120 | if (ddp->sgl) | |
121 | pci_unmap_sg(adapter->pdev, ddp->sgl, ddp->sgc, | |
122 | DMA_FROM_DEVICE); | |
123 | pci_pool_free(fcoe->pool, ddp->udl, ddp->udp); | |
124 | ixgbe_fcoe_clear_ddp(ddp); | |
125 | ||
126 | out_ddp_put: | |
127 | return len; | |
128 | } | |
129 | ||
130 | /** | |
131 | * ixgbe_fcoe_ddp_get - called to set up ddp context | |
132 | * @netdev: the corresponding net_device | |
133 | * @xid: the exchange id requesting ddp | |
134 | * @sgl: the scatter-gather list for this request | |
135 | * @sgc: the number of scatter-gather items | |
136 | * | |
137 | * This is the implementation of net_device_ops.ndo_fcoe_ddp_setup | |
138 | * and is expected to be called from ULD, e.g., FCP layer of libfc | |
139 | * to set up ddp for the corresponding xid of the given sglist for | |
140 | * the corresponding I/O. | |
141 | * | |
142 | * Returns : 1 for success and 0 for no ddp | |
143 | */ | |
144 | int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, | |
145 | struct scatterlist *sgl, unsigned int sgc) | |
146 | { | |
147 | struct ixgbe_adapter *adapter; | |
148 | struct ixgbe_hw *hw; | |
149 | struct ixgbe_fcoe *fcoe; | |
150 | struct ixgbe_fcoe_ddp *ddp; | |
151 | struct scatterlist *sg; | |
152 | unsigned int i, j, dmacount; | |
153 | unsigned int len; | |
154 | static const unsigned int bufflen = 4096; | |
155 | unsigned int firstoff = 0; | |
156 | unsigned int lastsize; | |
157 | unsigned int thisoff = 0; | |
158 | unsigned int thislen = 0; | |
159 | u32 fcbuff, fcdmarw, fcfltrw; | |
160 | dma_addr_t addr; | |
161 | ||
162 | if (!netdev || !sgl) | |
163 | return 0; | |
164 | ||
165 | adapter = netdev_priv(netdev); | |
166 | if (xid >= IXGBE_FCOE_DDP_MAX) { | |
167 | DPRINTK(DRV, WARNING, "xid=0x%x out-of-range\n", xid); | |
168 | return 0; | |
169 | } | |
170 | ||
171 | fcoe = &adapter->fcoe; | |
172 | if (!fcoe->pool) { | |
173 | DPRINTK(DRV, WARNING, "xid=0x%x no ddp pool for fcoe\n", xid); | |
174 | return 0; | |
175 | } | |
176 | ||
177 | ddp = &fcoe->ddp[xid]; | |
178 | if (ddp->sgl) { | |
179 | DPRINTK(DRV, ERR, "xid 0x%x w/ non-null sgl=%p nents=%d\n", | |
180 | xid, ddp->sgl, ddp->sgc); | |
181 | return 0; | |
182 | } | |
183 | ixgbe_fcoe_clear_ddp(ddp); | |
184 | ||
185 | /* setup dma from scsi command sgl */ | |
186 | dmacount = pci_map_sg(adapter->pdev, sgl, sgc, DMA_FROM_DEVICE); | |
187 | if (dmacount == 0) { | |
188 | DPRINTK(DRV, ERR, "xid 0x%x DMA map error\n", xid); | |
189 | return 0; | |
190 | } | |
191 | ||
192 | /* alloc the udl from our ddp pool */ | |
193 | ddp->udl = pci_pool_alloc(fcoe->pool, GFP_KERNEL, &ddp->udp); | |
194 | if (!ddp->udl) { | |
195 | DPRINTK(DRV, ERR, "failed allocated ddp context\n"); | |
196 | goto out_noddp_unmap; | |
197 | } | |
198 | ddp->sgl = sgl; | |
199 | ddp->sgc = sgc; | |
200 | ||
201 | j = 0; | |
202 | for_each_sg(sgl, sg, dmacount, i) { | |
203 | addr = sg_dma_address(sg); | |
204 | len = sg_dma_len(sg); | |
205 | while (len) { | |
a7551b75 RL |
206 | /* max number of buffers allowed in one DDP context */ |
207 | if (j >= IXGBE_BUFFCNT_MAX) { | |
208 | netif_err(adapter, drv, adapter->netdev, | |
209 | "xid=%x:%d,%d,%d:addr=%llx " | |
210 | "not enough descriptors\n", | |
211 | xid, i, j, dmacount, (u64)addr); | |
212 | goto out_noddp_free; | |
213 | } | |
214 | ||
d0ed8937 YZ |
215 | /* get the offset of length of current buffer */ |
216 | thisoff = addr & ((dma_addr_t)bufflen - 1); | |
217 | thislen = min((bufflen - thisoff), len); | |
218 | /* | |
219 | * all but the 1st buffer (j == 0) | |
220 | * must be aligned on bufflen | |
221 | */ | |
222 | if ((j != 0) && (thisoff)) | |
223 | goto out_noddp_free; | |
224 | /* | |
225 | * all but the last buffer | |
226 | * ((i == (dmacount - 1)) && (thislen == len)) | |
227 | * must end at bufflen | |
228 | */ | |
229 | if (((i != (dmacount - 1)) || (thislen != len)) | |
230 | && ((thislen + thisoff) != bufflen)) | |
231 | goto out_noddp_free; | |
232 | ||
233 | ddp->udl[j] = (u64)(addr - thisoff); | |
234 | /* only the first buffer may have none-zero offset */ | |
235 | if (j == 0) | |
236 | firstoff = thisoff; | |
237 | len -= thislen; | |
238 | addr += thislen; | |
239 | j++; | |
d0ed8937 YZ |
240 | } |
241 | } | |
242 | /* only the last buffer may have non-full bufflen */ | |
243 | lastsize = thisoff + thislen; | |
244 | ||
245 | fcbuff = (IXGBE_FCBUFF_4KB << IXGBE_FCBUFF_BUFFSIZE_SHIFT); | |
a7551b75 | 246 | fcbuff |= ((j & 0xff) << IXGBE_FCBUFF_BUFFCNT_SHIFT); |
d0ed8937 YZ |
247 | fcbuff |= (firstoff << IXGBE_FCBUFF_OFFSET_SHIFT); |
248 | fcbuff |= (IXGBE_FCBUFF_VALID); | |
249 | ||
250 | fcdmarw = xid; | |
251 | fcdmarw |= IXGBE_FCDMARW_WE; | |
252 | fcdmarw |= (lastsize << IXGBE_FCDMARW_LASTSIZE_SHIFT); | |
253 | ||
254 | fcfltrw = xid; | |
255 | fcfltrw |= IXGBE_FCFLTRW_WE; | |
256 | ||
257 | /* program DMA context */ | |
258 | hw = &adapter->hw; | |
259 | spin_lock_bh(&fcoe->lock); | |
8e20ce94 | 260 | IXGBE_WRITE_REG(hw, IXGBE_FCPTRL, ddp->udp & DMA_BIT_MASK(32)); |
d0ed8937 YZ |
261 | IXGBE_WRITE_REG(hw, IXGBE_FCPTRH, (u64)ddp->udp >> 32); |
262 | IXGBE_WRITE_REG(hw, IXGBE_FCBUFF, fcbuff); | |
263 | IXGBE_WRITE_REG(hw, IXGBE_FCDMARW, fcdmarw); | |
264 | /* program filter context */ | |
265 | IXGBE_WRITE_REG(hw, IXGBE_FCPARAM, 0); | |
266 | IXGBE_WRITE_REG(hw, IXGBE_FCFLT, IXGBE_FCFLT_VALID); | |
267 | IXGBE_WRITE_REG(hw, IXGBE_FCFLTRW, fcfltrw); | |
268 | spin_unlock_bh(&fcoe->lock); | |
269 | ||
270 | return 1; | |
271 | ||
272 | out_noddp_free: | |
273 | pci_pool_free(fcoe->pool, ddp->udl, ddp->udp); | |
274 | ixgbe_fcoe_clear_ddp(ddp); | |
275 | ||
276 | out_noddp_unmap: | |
277 | pci_unmap_sg(adapter->pdev, sgl, sgc, DMA_FROM_DEVICE); | |
278 | return 0; | |
279 | } | |
280 | ||
281 | /** | |
282 | * ixgbe_fcoe_ddp - check ddp status and mark it done | |
283 | * @adapter: ixgbe adapter | |
284 | * @rx_desc: advanced rx descriptor | |
285 | * @skb: the skb holding the received data | |
286 | * | |
287 | * This checks ddp status. | |
288 | * | |
3d8fd385 YZ |
289 | * Returns : < 0 indicates an error or not a FCiE ddp, 0 indicates |
290 | * not passing the skb to ULD, > 0 indicates is the length of data | |
291 | * being ddped. | |
d0ed8937 YZ |
292 | */ |
293 | int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, | |
294 | union ixgbe_adv_rx_desc *rx_desc, | |
295 | struct sk_buff *skb) | |
296 | { | |
297 | u16 xid; | |
d4ab8819 | 298 | u32 fctl; |
d0ed8937 YZ |
299 | u32 sterr, fceofe, fcerr, fcstat; |
300 | int rc = -EINVAL; | |
301 | struct ixgbe_fcoe *fcoe; | |
302 | struct ixgbe_fcoe_ddp *ddp; | |
303 | struct fc_frame_header *fh; | |
304 | ||
305 | if (!ixgbe_rx_is_fcoe(rx_desc)) | |
306 | goto ddp_out; | |
307 | ||
308 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
309 | sterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
310 | fcerr = (sterr & IXGBE_RXDADV_ERR_FCERR); | |
311 | fceofe = (sterr & IXGBE_RXDADV_ERR_FCEOFE); | |
312 | if (fcerr == IXGBE_FCERR_BADCRC) | |
313 | skb->ip_summed = CHECKSUM_NONE; | |
314 | ||
315 | skb_reset_network_header(skb); | |
316 | skb_set_transport_header(skb, skb_network_offset(skb) + | |
317 | sizeof(struct fcoe_hdr)); | |
318 | fh = (struct fc_frame_header *)skb_transport_header(skb); | |
d4ab8819 YZ |
319 | fctl = ntoh24(fh->fh_f_ctl); |
320 | if (fctl & FC_FC_EX_CTX) | |
321 | xid = be16_to_cpu(fh->fh_ox_id); | |
322 | else | |
323 | xid = be16_to_cpu(fh->fh_rx_id); | |
324 | ||
d0ed8937 YZ |
325 | if (xid >= IXGBE_FCOE_DDP_MAX) |
326 | goto ddp_out; | |
327 | ||
328 | fcoe = &adapter->fcoe; | |
329 | ddp = &fcoe->ddp[xid]; | |
330 | if (!ddp->udl) | |
331 | goto ddp_out; | |
332 | ||
333 | ddp->err = (fcerr | fceofe); | |
334 | if (ddp->err) | |
335 | goto ddp_out; | |
336 | ||
337 | fcstat = (sterr & IXGBE_RXDADV_STAT_FCSTAT); | |
338 | if (fcstat) { | |
339 | /* update length of DDPed data */ | |
340 | ddp->len = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss); | |
341 | /* unmap the sg list when FCP_RSP is received */ | |
342 | if (fcstat == IXGBE_RXDADV_STAT_FCSTAT_FCPRSP) { | |
343 | pci_unmap_sg(adapter->pdev, ddp->sgl, | |
344 | ddp->sgc, DMA_FROM_DEVICE); | |
345 | ddp->sgl = NULL; | |
346 | ddp->sgc = 0; | |
347 | } | |
348 | /* return 0 to bypass going to ULD for DDPed data */ | |
349 | if (fcstat == IXGBE_RXDADV_STAT_FCSTAT_DDP) | |
350 | rc = 0; | |
17e78b06 | 351 | else if (ddp->len) |
3d8fd385 | 352 | rc = ddp->len; |
d0ed8937 YZ |
353 | } |
354 | ||
355 | ddp_out: | |
356 | return rc; | |
357 | } | |
358 | ||
bc079228 YZ |
359 | /** |
360 | * ixgbe_fso - ixgbe FCoE Sequence Offload (FSO) | |
361 | * @adapter: ixgbe adapter | |
362 | * @tx_ring: tx desc ring | |
363 | * @skb: associated skb | |
364 | * @tx_flags: tx flags | |
365 | * @hdr_len: hdr_len to be returned | |
366 | * | |
367 | * This sets up large send offload for FCoE | |
368 | * | |
369 | * Returns : 0 indicates no FSO, > 0 for FSO, < 0 for error | |
370 | */ | |
371 | int ixgbe_fso(struct ixgbe_adapter *adapter, | |
372 | struct ixgbe_ring *tx_ring, struct sk_buff *skb, | |
373 | u32 tx_flags, u8 *hdr_len) | |
374 | { | |
375 | u8 sof, eof; | |
376 | u32 vlan_macip_lens; | |
377 | u32 fcoe_sof_eof; | |
378 | u32 type_tucmd; | |
379 | u32 mss_l4len_idx; | |
380 | int mss = 0; | |
381 | unsigned int i; | |
382 | struct ixgbe_tx_buffer *tx_buffer_info; | |
383 | struct ixgbe_adv_tx_context_desc *context_desc; | |
384 | struct fc_frame_header *fh; | |
385 | ||
386 | if (skb_is_gso(skb) && (skb_shinfo(skb)->gso_type != SKB_GSO_FCOE)) { | |
387 | DPRINTK(DRV, ERR, "Wrong gso type %d:expecting SKB_GSO_FCOE\n", | |
388 | skb_shinfo(skb)->gso_type); | |
389 | return -EINVAL; | |
390 | } | |
391 | ||
392 | /* resets the header to point fcoe/fc */ | |
393 | skb_set_network_header(skb, skb->mac_len); | |
394 | skb_set_transport_header(skb, skb->mac_len + | |
395 | sizeof(struct fcoe_hdr)); | |
396 | ||
397 | /* sets up SOF and ORIS */ | |
398 | fcoe_sof_eof = 0; | |
399 | sof = ((struct fcoe_hdr *)skb_network_header(skb))->fcoe_sof; | |
400 | switch (sof) { | |
401 | case FC_SOF_I2: | |
402 | fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_ORIS; | |
403 | break; | |
404 | case FC_SOF_I3: | |
405 | fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_SOF; | |
406 | fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_ORIS; | |
407 | break; | |
408 | case FC_SOF_N2: | |
409 | break; | |
410 | case FC_SOF_N3: | |
411 | fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_SOF; | |
412 | break; | |
413 | default: | |
414 | DPRINTK(DRV, WARNING, "unknown sof = 0x%x\n", sof); | |
415 | return -EINVAL; | |
416 | } | |
417 | ||
418 | /* the first byte of the last dword is EOF */ | |
419 | skb_copy_bits(skb, skb->len - 4, &eof, 1); | |
420 | /* sets up EOF and ORIE */ | |
421 | switch (eof) { | |
422 | case FC_EOF_N: | |
423 | fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_N; | |
424 | break; | |
425 | case FC_EOF_T: | |
426 | /* lso needs ORIE */ | |
427 | if (skb_is_gso(skb)) { | |
428 | fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_N; | |
429 | fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_ORIE; | |
430 | } else { | |
431 | fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_T; | |
432 | } | |
433 | break; | |
434 | case FC_EOF_NI: | |
435 | fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_NI; | |
436 | break; | |
437 | case FC_EOF_A: | |
438 | fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_A; | |
439 | break; | |
440 | default: | |
441 | DPRINTK(DRV, WARNING, "unknown eof = 0x%x\n", eof); | |
442 | return -EINVAL; | |
443 | } | |
444 | ||
445 | /* sets up PARINC indicating data offset */ | |
446 | fh = (struct fc_frame_header *)skb_transport_header(skb); | |
447 | if (fh->fh_f_ctl[2] & FC_FC_REL_OFF) | |
448 | fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_PARINC; | |
449 | ||
450 | /* hdr_len includes fc_hdr if FCoE lso is enabled */ | |
451 | *hdr_len = sizeof(struct fcoe_crc_eof); | |
452 | if (skb_is_gso(skb)) | |
453 | *hdr_len += (skb_transport_offset(skb) + | |
454 | sizeof(struct fc_frame_header)); | |
455 | /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ | |
456 | vlan_macip_lens = (skb_transport_offset(skb) + | |
457 | sizeof(struct fc_frame_header)); | |
458 | vlan_macip_lens |= ((skb_transport_offset(skb) - 4) | |
459 | << IXGBE_ADVTXD_MACLEN_SHIFT); | |
460 | vlan_macip_lens |= (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
461 | ||
462 | /* type_tycmd and mss: set TUCMD.FCoE to enable offload */ | |
463 | type_tucmd = IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT | | |
464 | IXGBE_ADVTXT_TUCMD_FCOE; | |
465 | if (skb_is_gso(skb)) | |
466 | mss = skb_shinfo(skb)->gso_size; | |
467 | /* mss_l4len_id: use 1 for FSO as TSO, no need for L4LEN */ | |
468 | mss_l4len_idx = (mss << IXGBE_ADVTXD_MSS_SHIFT) | | |
469 | (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
470 | ||
471 | /* write context desc */ | |
472 | i = tx_ring->next_to_use; | |
473 | context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); | |
474 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
475 | context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof); | |
476 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); | |
477 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); | |
478 | ||
479 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
480 | tx_buffer_info->time_stamp = jiffies; | |
481 | tx_buffer_info->next_to_watch = i; | |
482 | ||
483 | i++; | |
484 | if (i == tx_ring->count) | |
485 | i = 0; | |
486 | tx_ring->next_to_use = i; | |
487 | ||
488 | return skb_is_gso(skb); | |
489 | } | |
490 | ||
d3a2ae6d YZ |
491 | /** |
492 | * ixgbe_configure_fcoe - configures registers for fcoe at start | |
493 | * @adapter: ptr to ixgbe adapter | |
494 | * | |
495 | * This sets up FCoE related registers | |
496 | * | |
497 | * Returns : none | |
498 | */ | |
499 | void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter) | |
500 | { | |
29ebf6f8 | 501 | int i, fcoe_q, fcoe_i; |
d3a2ae6d | 502 | struct ixgbe_hw *hw = &adapter->hw; |
d0ed8937 | 503 | struct ixgbe_fcoe *fcoe = &adapter->fcoe; |
29ebf6f8 | 504 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; |
61a0f421 YZ |
505 | #ifdef CONFIG_IXGBE_DCB |
506 | u8 tc; | |
507 | u32 up2tc; | |
508 | #endif | |
d0ed8937 YZ |
509 | |
510 | /* create the pool for ddp if not created yet */ | |
511 | if (!fcoe->pool) { | |
512 | /* allocate ddp pool */ | |
513 | fcoe->pool = pci_pool_create("ixgbe_fcoe_ddp", | |
514 | adapter->pdev, IXGBE_FCPTR_MAX, | |
515 | IXGBE_FCPTR_ALIGN, PAGE_SIZE); | |
516 | if (!fcoe->pool) | |
517 | DPRINTK(DRV, ERR, | |
518 | "failed to allocated FCoE DDP pool\n"); | |
d3a2ae6d | 519 | |
d0ed8937 YZ |
520 | spin_lock_init(&fcoe->lock); |
521 | } | |
29ebf6f8 YZ |
522 | |
523 | /* Enable L2 eth type filter for FCoE */ | |
d3a2ae6d YZ |
524 | IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FCOE), |
525 | (ETH_P_FCOE | IXGBE_ETQF_FCOE | IXGBE_ETQF_FILTER_EN)); | |
af06393b CL |
526 | /* Enable L2 eth type filter for FIP */ |
527 | IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FIP), | |
528 | (ETH_P_FIP | IXGBE_ETQF_FILTER_EN)); | |
29ebf6f8 YZ |
529 | if (adapter->ring_feature[RING_F_FCOE].indices) { |
530 | /* Use multiple rx queues for FCoE by redirection table */ | |
531 | for (i = 0; i < IXGBE_FCRETA_SIZE; i++) { | |
532 | fcoe_i = f->mask + i % f->indices; | |
533 | fcoe_i &= IXGBE_FCRETA_ENTRY_MASK; | |
4a0b9ca0 | 534 | fcoe_q = adapter->rx_ring[fcoe_i]->reg_idx; |
29ebf6f8 YZ |
535 | IXGBE_WRITE_REG(hw, IXGBE_FCRETA(i), fcoe_q); |
536 | } | |
537 | IXGBE_WRITE_REG(hw, IXGBE_FCRECTL, IXGBE_FCRECTL_ENA); | |
538 | IXGBE_WRITE_REG(hw, IXGBE_ETQS(IXGBE_ETQF_FILTER_FCOE), 0); | |
af06393b CL |
539 | fcoe_i = f->mask; |
540 | fcoe_i &= IXGBE_FCRETA_ENTRY_MASK; | |
541 | fcoe_q = adapter->rx_ring[fcoe_i]->reg_idx; | |
542 | IXGBE_WRITE_REG(hw, IXGBE_ETQS(IXGBE_ETQF_FILTER_FIP), | |
543 | IXGBE_ETQS_QUEUE_EN | | |
544 | (fcoe_q << IXGBE_ETQS_RX_QUEUE_SHIFT)); | |
29ebf6f8 YZ |
545 | } else { |
546 | /* Use single rx queue for FCoE */ | |
547 | fcoe_i = f->mask; | |
4a0b9ca0 | 548 | fcoe_q = adapter->rx_ring[fcoe_i]->reg_idx; |
29ebf6f8 YZ |
549 | IXGBE_WRITE_REG(hw, IXGBE_FCRECTL, 0); |
550 | IXGBE_WRITE_REG(hw, IXGBE_ETQS(IXGBE_ETQF_FILTER_FCOE), | |
551 | IXGBE_ETQS_QUEUE_EN | | |
552 | (fcoe_q << IXGBE_ETQS_RX_QUEUE_SHIFT)); | |
553 | } | |
af06393b CL |
554 | /* send FIP frames to the first FCoE queue */ |
555 | fcoe_i = f->mask; | |
556 | fcoe_q = adapter->rx_ring[fcoe_i]->reg_idx; | |
557 | IXGBE_WRITE_REG(hw, IXGBE_ETQS(IXGBE_ETQF_FILTER_FIP), | |
558 | IXGBE_ETQS_QUEUE_EN | | |
559 | (fcoe_q << IXGBE_ETQS_RX_QUEUE_SHIFT)); | |
29ebf6f8 | 560 | |
d3a2ae6d YZ |
561 | IXGBE_WRITE_REG(hw, IXGBE_FCRXCTRL, |
562 | IXGBE_FCRXCTRL_FCOELLI | | |
563 | IXGBE_FCRXCTRL_FCCRCBO | | |
564 | (FC_FCOE_VER << IXGBE_FCRXCTRL_FCOEVER_SHIFT)); | |
61a0f421 YZ |
565 | #ifdef CONFIG_IXGBE_DCB |
566 | up2tc = IXGBE_READ_REG(&adapter->hw, IXGBE_RTTUP2TC); | |
567 | for (i = 0; i < MAX_USER_PRIORITY; i++) { | |
568 | tc = (u8)(up2tc >> (i * IXGBE_RTTUP2TC_UP_SHIFT)); | |
569 | tc &= (MAX_TRAFFIC_CLASS - 1); | |
570 | if (fcoe->tc == tc) { | |
571 | fcoe->up = i; | |
572 | break; | |
573 | } | |
574 | } | |
575 | #endif | |
d3a2ae6d | 576 | } |
d0ed8937 YZ |
577 | |
578 | /** | |
579 | * ixgbe_cleanup_fcoe - release all fcoe ddp context resources | |
580 | * @adapter : ixgbe adapter | |
581 | * | |
582 | * Cleans up outstanding ddp context resources | |
583 | * | |
584 | * Returns : none | |
585 | */ | |
586 | void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter) | |
587 | { | |
588 | int i; | |
589 | struct ixgbe_fcoe *fcoe = &adapter->fcoe; | |
590 | ||
591 | /* release ddp resource */ | |
592 | if (fcoe->pool) { | |
593 | for (i = 0; i < IXGBE_FCOE_DDP_MAX; i++) | |
594 | ixgbe_fcoe_ddp_put(adapter->netdev, i); | |
595 | pci_pool_destroy(fcoe->pool); | |
596 | fcoe->pool = NULL; | |
597 | } | |
598 | } | |
8450ff8c YZ |
599 | |
600 | /** | |
601 | * ixgbe_fcoe_enable - turn on FCoE offload feature | |
602 | * @netdev: the corresponding netdev | |
603 | * | |
604 | * Turns on FCoE offload feature in 82599. | |
605 | * | |
606 | * Returns : 0 indicates success or -EINVAL on failure | |
607 | */ | |
608 | int ixgbe_fcoe_enable(struct net_device *netdev) | |
609 | { | |
610 | int rc = -EINVAL; | |
611 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
612 | ||
613 | ||
614 | if (!(adapter->flags & IXGBE_FLAG_FCOE_CAPABLE)) | |
615 | goto out_enable; | |
616 | ||
617 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
618 | goto out_enable; | |
619 | ||
620 | DPRINTK(DRV, INFO, "Enabling FCoE offload features.\n"); | |
621 | if (netif_running(netdev)) | |
622 | netdev->netdev_ops->ndo_stop(netdev); | |
623 | ||
624 | ixgbe_clear_interrupt_scheme(adapter); | |
625 | ||
626 | adapter->flags |= IXGBE_FLAG_FCOE_ENABLED; | |
627 | adapter->ring_feature[RING_F_FCOE].indices = IXGBE_FCRETA_SIZE; | |
628 | netdev->features |= NETIF_F_FCOE_CRC; | |
629 | netdev->features |= NETIF_F_FSO; | |
630 | netdev->features |= NETIF_F_FCOE_MTU; | |
631 | netdev->vlan_features |= NETIF_F_FCOE_CRC; | |
632 | netdev->vlan_features |= NETIF_F_FSO; | |
633 | netdev->vlan_features |= NETIF_F_FCOE_MTU; | |
634 | netdev->fcoe_ddp_xid = IXGBE_FCOE_DDP_MAX - 1; | |
8450ff8c YZ |
635 | |
636 | ixgbe_init_interrupt_scheme(adapter); | |
936332b8 | 637 | netdev_features_change(netdev); |
8450ff8c YZ |
638 | |
639 | if (netif_running(netdev)) | |
640 | netdev->netdev_ops->ndo_open(netdev); | |
641 | rc = 0; | |
642 | ||
643 | out_enable: | |
644 | return rc; | |
645 | } | |
646 | ||
647 | /** | |
648 | * ixgbe_fcoe_disable - turn off FCoE offload feature | |
649 | * @netdev: the corresponding netdev | |
650 | * | |
651 | * Turns off FCoE offload feature in 82599. | |
652 | * | |
653 | * Returns : 0 indicates success or -EINVAL on failure | |
654 | */ | |
655 | int ixgbe_fcoe_disable(struct net_device *netdev) | |
656 | { | |
657 | int rc = -EINVAL; | |
658 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
659 | ||
660 | if (!(adapter->flags & IXGBE_FLAG_FCOE_CAPABLE)) | |
661 | goto out_disable; | |
662 | ||
663 | if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) | |
664 | goto out_disable; | |
665 | ||
666 | DPRINTK(DRV, INFO, "Disabling FCoE offload features.\n"); | |
667 | if (netif_running(netdev)) | |
668 | netdev->netdev_ops->ndo_stop(netdev); | |
669 | ||
670 | ixgbe_clear_interrupt_scheme(adapter); | |
671 | ||
672 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | |
673 | adapter->ring_feature[RING_F_FCOE].indices = 0; | |
674 | netdev->features &= ~NETIF_F_FCOE_CRC; | |
675 | netdev->features &= ~NETIF_F_FSO; | |
676 | netdev->features &= ~NETIF_F_FCOE_MTU; | |
677 | netdev->vlan_features &= ~NETIF_F_FCOE_CRC; | |
678 | netdev->vlan_features &= ~NETIF_F_FSO; | |
679 | netdev->vlan_features &= ~NETIF_F_FCOE_MTU; | |
680 | netdev->fcoe_ddp_xid = 0; | |
8450ff8c YZ |
681 | |
682 | ixgbe_cleanup_fcoe(adapter); | |
8450ff8c | 683 | ixgbe_init_interrupt_scheme(adapter); |
936332b8 VD |
684 | netdev_features_change(netdev); |
685 | ||
8450ff8c YZ |
686 | if (netif_running(netdev)) |
687 | netdev->netdev_ops->ndo_open(netdev); | |
688 | rc = 0; | |
689 | ||
690 | out_disable: | |
691 | return rc; | |
692 | } | |
6ee16520 YZ |
693 | |
694 | #ifdef CONFIG_IXGBE_DCB | |
695 | /** | |
696 | * ixgbe_fcoe_getapp - retrieves current user priority bitmap for FCoE | |
697 | * @adapter : ixgbe adapter | |
698 | * | |
699 | * Finds out the corresponding user priority bitmap from the current | |
700 | * traffic class that FCoE belongs to. Returns 0 as the invalid user | |
701 | * priority bitmap to indicate an error. | |
702 | * | |
703 | * Returns : 802.1p user priority bitmap for FCoE | |
704 | */ | |
705 | u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter) | |
706 | { | |
61a0f421 | 707 | return 1 << adapter->fcoe.up; |
6ee16520 YZ |
708 | } |
709 | ||
710 | /** | |
711 | * ixgbe_fcoe_setapp - sets the user priority bitmap for FCoE | |
712 | * @adapter : ixgbe adapter | |
713 | * @up : 802.1p user priority bitmap | |
714 | * | |
715 | * Finds out the traffic class from the input user priority | |
716 | * bitmap for FCoE. | |
717 | * | |
718 | * Returns : 0 on success otherwise returns 1 on error | |
719 | */ | |
720 | u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up) | |
721 | { | |
722 | int i; | |
723 | u32 up2tc; | |
724 | ||
725 | /* valid user priority bitmap must not be 0 */ | |
726 | if (up) { | |
727 | /* from user priority to the corresponding traffic class */ | |
728 | up2tc = IXGBE_READ_REG(&adapter->hw, IXGBE_RTTUP2TC); | |
729 | for (i = 0; i < MAX_USER_PRIORITY; i++) { | |
730 | if (up & (1 << i)) { | |
731 | up2tc >>= (i * IXGBE_RTTUP2TC_UP_SHIFT); | |
732 | up2tc &= (MAX_TRAFFIC_CLASS - 1); | |
733 | adapter->fcoe.tc = (u8)up2tc; | |
61a0f421 | 734 | adapter->fcoe.up = i; |
6ee16520 YZ |
735 | return 0; |
736 | } | |
737 | } | |
738 | } | |
739 | ||
740 | return 1; | |
741 | } | |
742 | #endif /* CONFIG_IXGBE_DCB */ | |
61a1fa10 YZ |
743 | |
744 | /** | |
745 | * ixgbe_fcoe_get_wwn - get world wide name for the node or the port | |
746 | * @netdev : ixgbe adapter | |
747 | * @wwn : the world wide name | |
748 | * @type: the type of world wide name | |
749 | * | |
750 | * Returns the node or port world wide name if both the prefix and the san | |
751 | * mac address are valid, then the wwn is formed based on the NAA-2 for | |
752 | * IEEE Extended name identifier (ref. to T10 FC-LS Spec., Sec. 15.3). | |
753 | * | |
754 | * Returns : 0 on success | |
755 | */ | |
756 | int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type) | |
757 | { | |
758 | int rc = -EINVAL; | |
759 | u16 prefix = 0xffff; | |
760 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
761 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
762 | ||
763 | switch (type) { | |
764 | case NETDEV_FCOE_WWNN: | |
765 | prefix = mac->wwnn_prefix; | |
766 | break; | |
767 | case NETDEV_FCOE_WWPN: | |
768 | prefix = mac->wwpn_prefix; | |
769 | break; | |
770 | default: | |
771 | break; | |
772 | } | |
773 | ||
774 | if ((prefix != 0xffff) && | |
775 | is_valid_ether_addr(mac->san_addr)) { | |
776 | *wwn = ((u64) prefix << 48) | | |
777 | ((u64) mac->san_addr[0] << 40) | | |
778 | ((u64) mac->san_addr[1] << 32) | | |
779 | ((u64) mac->san_addr[2] << 24) | | |
780 | ((u64) mac->san_addr[3] << 16) | | |
781 | ((u64) mac->san_addr[4] << 8) | | |
782 | ((u64) mac->san_addr[5]); | |
783 | rc = 0; | |
784 | } | |
785 | return rc; | |
786 | } | |
787 | ||
788 |