[people/ms/u-boot.git] / drivers / net / keystone_net.c

/*
 * Ethernet driver for TI K2HK EVM.
 *
 * (C) Copyright 2012-2014
 *     Texas Instruments Incorporated, <www.ti.com>
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */
#include <common.h>
#include <command.h>
#include <console.h>

#include <net.h>
#include <phy.h>
#include <errno.h>
#include <miiphy.h>
#include <malloc.h>
#include <asm/ti-common/keystone_nav.h>
#include <asm/ti-common/keystone_net.h>
#include <asm/ti-common/keystone_serdes.h>

unsigned int emac_open;
static struct mii_dev *mdio_bus;
static unsigned int sys_has_mdio = 1;

#ifdef KEYSTONE2_EMAC_GIG_ENABLE
#define emac_gigabit_enable(x)	keystone2_eth_gigabit_enable(x)
#else
#define emac_gigabit_enable(x)	/* no gigabit to enable */
#endif

#define RX_BUFF_NUMS	24
#define RX_BUFF_LEN	1520
#define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
#define SGMII_ANEG_TIMEOUT		4000

static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);

struct rx_buff_desc net_rx_buffs = {
	.buff_ptr	= rx_buffs,
	.num_buffs	= RX_BUFF_NUMS,
	.buff_len	= RX_BUFF_LEN,
	.rx_flow	= 22,
};

#ifndef CONFIG_SOC_K2G
static void keystone2_net_serdes_setup(void);
#endif

int keystone2_eth_read_mac_addr(struct eth_device *dev)
{
	struct eth_priv_t *eth_priv;
	u32 maca = 0;
	u32 macb = 0;

	eth_priv = (struct eth_priv_t *)dev->priv;

	/* Read the e-fuse mac address */
	if (eth_priv->slave_port == 1) {
		maca = __raw_readl(MAC_ID_BASE_ADDR);
		macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
	}

	dev->enetaddr[0] = (macb >>  8) & 0xff;
	dev->enetaddr[1] = (macb >>  0) & 0xff;
	dev->enetaddr[2] = (maca >> 24) & 0xff;
	dev->enetaddr[3] = (maca >> 16) & 0xff;
	dev->enetaddr[4] = (maca >>  8) & 0xff;
	dev->enetaddr[5] = (maca >>  0) & 0xff;

	return 0;
}

/* MDIO */

static int keystone2_mdio_reset(struct mii_dev *bus)
{
	u_int32_t clkdiv;
	struct mdio_regs *adap_mdio = bus->priv;

	clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;

	writel((clkdiv & 0xffff) | MDIO_CONTROL_ENABLE |
	       MDIO_CONTROL_FAULT | MDIO_CONTROL_FAULT_ENABLE,
	       &adap_mdio->control);

	while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE)
		;

	return 0;
}

/**
 * keystone2_mdio_read - read a PHY register via MDIO interface.
 * Blocks until operation is complete.
 */
static int keystone2_mdio_read(struct mii_dev *bus,
			       int addr, int devad, int reg)
{
	int tmp;
	struct mdio_regs *adap_mdio = bus->priv;

	while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
		;

	writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_READ |
	       ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16),
	       &adap_mdio->useraccess0);

	/* Wait for command to complete */
	while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO)
		;

	if (tmp & MDIO_USERACCESS0_ACK)
		return tmp & 0xffff;

	return -1;
}

/**
 * keystone2_mdio_write - write to a PHY register via MDIO interface.
 * Blocks until operation is complete.
 */
static int keystone2_mdio_write(struct mii_dev *bus,
				int addr, int devad, int reg, u16 val)
{
	struct mdio_regs *adap_mdio = bus->priv;

	while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
		;

	writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_WRITE |
	       ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16) |
	       (val & 0xffff), &adap_mdio->useraccess0);

	/* Wait for command to complete */
	while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
		;

	return 0;
}

static void  __attribute__((unused))
	keystone2_eth_gigabit_enable(struct eth_device *dev)
{
	u_int16_t data;
	struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;

	if (sys_has_mdio) {
		data = keystone2_mdio_read(mdio_bus, eth_priv->phy_addr,
					   MDIO_DEVAD_NONE, 0);
		/* speed selection MSB */
		if (!(data & (1 << 6)))
			return;
	}

	/*
	 * Check if link detected is giga-bit
	 * If Gigabit mode detected, enable gigbit in MAC
	 */
	writel(readl(DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) +
		     CPGMACSL_REG_CTL) |
	       EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
	       DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL);
}

#ifdef CONFIG_SOC_K2G
int keystone_rgmii_config(struct phy_device *phy_dev)
{
	unsigned int i, status;

	i = 0;
	do {
		if (i > SGMII_ANEG_TIMEOUT) {
			puts(" TIMEOUT !\n");
			phy_dev->link = 0;
			return 0;
		}

		if (ctrlc()) {
			puts("user interrupt!\n");
			phy_dev->link = 0;
			return -EINTR;
		}

		if ((i++ % 500) == 0)
			printf(".");

		udelay(1000);   /* 1 ms */
		status = readl(RGMII_STATUS_REG);
	} while (!(status & RGMII_REG_STATUS_LINK));

	puts(" done\n");

	return 0;
}
#else
int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface)
{
	unsigned int i, status, mask;
	unsigned int mr_adv_ability, control;

	switch (interface) {
	case SGMII_LINK_MAC_MAC_AUTONEG:
		mr_adv_ability	= (SGMII_REG_MR_ADV_ENABLE |
				   SGMII_REG_MR_ADV_LINK |
				   SGMII_REG_MR_ADV_FULL_DUPLEX |
				   SGMII_REG_MR_ADV_GIG_MODE);
		control		= (SGMII_REG_CONTROL_MASTER |
				   SGMII_REG_CONTROL_AUTONEG);

		break;
	case SGMII_LINK_MAC_PHY:
	case SGMII_LINK_MAC_PHY_FORCED:
		mr_adv_ability	= SGMII_REG_MR_ADV_ENABLE;
		control		= SGMII_REG_CONTROL_AUTONEG;

		break;
	case SGMII_LINK_MAC_MAC_FORCED:
		mr_adv_ability	= (SGMII_REG_MR_ADV_ENABLE |
				   SGMII_REG_MR_ADV_LINK |
				   SGMII_REG_MR_ADV_FULL_DUPLEX |
				   SGMII_REG_MR_ADV_GIG_MODE);
		control		= SGMII_REG_CONTROL_MASTER;

		break;
	case SGMII_LINK_MAC_FIBER:
		mr_adv_ability	= 0x20;
		control		= SGMII_REG_CONTROL_AUTONEG;

		break;
	default:
		mr_adv_ability	= SGMII_REG_MR_ADV_ENABLE;
		control		= SGMII_REG_CONTROL_AUTONEG;
	}

	__raw_writel(0, SGMII_CTL_REG(port));

	/*
	 * Wait for the SerDes pll to lock,
	 * but don't trap if lock is never read
	 */
	for (i = 0; i < 1000; i++)  {
		udelay(2000);
		status = __raw_readl(SGMII_STATUS_REG(port));
		if ((status & SGMII_REG_STATUS_LOCK) != 0)
			break;
	}

	__raw_writel(mr_adv_ability, SGMII_MRADV_REG(port));
	__raw_writel(control, SGMII_CTL_REG(port));


	mask = SGMII_REG_STATUS_LINK;

	if (control & SGMII_REG_CONTROL_AUTONEG)
		mask |= SGMII_REG_STATUS_AUTONEG;

	status = __raw_readl(SGMII_STATUS_REG(port));
	if ((status & mask) == mask)
		return 0;

	printf("\n%s Waiting for SGMII auto negotiation to complete",
	       phy_dev->dev->name);
	while ((status & mask) != mask) {
		/*
		 * Timeout reached ?
		 */
		if (i > SGMII_ANEG_TIMEOUT) {
			puts(" TIMEOUT !\n");
			phy_dev->link = 0;
			return 0;
		}

		if (ctrlc()) {
			puts("user interrupt!\n");
			phy_dev->link = 0;
			return -EINTR;
		}

		if ((i++ % 500) == 0)
			printf(".");

		udelay(1000);   /* 1 ms */
		status = __raw_readl(SGMII_STATUS_REG(port));
	}
	puts(" done\n");

	return 0;
}
#endif

int mac_sl_reset(u32 port)
{
	u32 i, v;

	if (port >= DEVICE_N_GMACSL_PORTS)
		return GMACSL_RET_INVALID_PORT;

	/* Set the soft reset bit */
	writel(CPGMAC_REG_RESET_VAL_RESET,
	       DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);

	/* Wait for the bit to clear */
	for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
		v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
		if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
		    CPGMAC_REG_RESET_VAL_RESET)
			return GMACSL_RET_OK;
	}

	/* Timeout on the reset */
	return GMACSL_RET_WARN_RESET_INCOMPLETE;
}

int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
{
	u32 v, i;
	int ret = GMACSL_RET_OK;

	if (port >= DEVICE_N_GMACSL_PORTS)
		return GMACSL_RET_INVALID_PORT;

	if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) {
		cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN;
		ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG;
	}

	/* Must wait if the device is undergoing reset */
	for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
		v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
		if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
		    CPGMAC_REG_RESET_VAL_RESET)
			break;
	}

	if (i == DEVICE_EMACSL_RESET_POLL_COUNT)
		return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE;

	writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
	writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);

#ifndef CONFIG_SOC_K2HK
	/* Map RX packet flow priority to 0 */
	writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP);
#endif

	return ret;
}

int ethss_config(u32 ctl, u32 max_pkt_size)
{
	u32 i;

	/* Max length register */
	writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN);

	/* Control register */
	writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL);

	/* All statistics enabled by default */
	writel(CPSW_REG_VAL_STAT_ENABLE_ALL,
	       DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN);

	/* Reset and enable the ALE */
	writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE |
	       CPSW_REG_VAL_ALE_CTL_BYPASS,
	       DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL);

	/* All ports put into forward mode */
	for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++)
		writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE,
		       DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i));

	return 0;
}

int ethss_start(void)
{
	int i;
	struct mac_sl_cfg cfg;

	cfg.max_rx_len	= MAX_SIZE_STREAM_BUFFER;
	cfg.ctl		= GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL;

	for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) {
		mac_sl_reset(i);
		mac_sl_config(i, &cfg);
	}

	return 0;
}

int ethss_stop(void)
{
	int i;

	for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++)
		mac_sl_reset(i);

	return 0;
}

int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num)
{
	if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE)
		num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE;

	return ksnav_send(&netcp_pktdma, buffer,
			  num_bytes, (slave_port_num) << 16);
}

/* Eth device open */
static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
{
	struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
	struct phy_device *phy_dev = eth_priv->phy_dev;

	debug("+ emac_open\n");

	net_rx_buffs.rx_flow	= eth_priv->rx_flow;

	sys_has_mdio =
		(eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0;

	if (sys_has_mdio)
		keystone2_mdio_reset(mdio_bus);

#ifdef CONFIG_SOC_K2G
	keystone_rgmii_config(phy_dev);
#else
	keystone_sgmii_config(phy_dev, eth_priv->slave_port - 1,
			      eth_priv->sgmii_link_type);
#endif

	udelay(10000);

	/* On chip switch configuration */
	ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);

	/* TODO: add error handling code */
	if (qm_init()) {
		printf("ERROR: qm_init()\n");
		return -1;
	}
	if (ksnav_init(&netcp_pktdma, &net_rx_buffs)) {
		qm_close();
		printf("ERROR: netcp_init()\n");
		return -1;
	}

	/*
	 * Streaming switch configuration. If not present this
	 * statement is defined to void in target.h.
	 * If present this is usually defined to a series of register writes
	 */
	hw_config_streaming_switch();

	if (sys_has_mdio) {
		keystone2_mdio_reset(mdio_bus);

		phy_startup(phy_dev);
		if (phy_dev->link == 0) {
			ksnav_close(&netcp_pktdma);
			qm_close();
			return -1;
		}
	}

	emac_gigabit_enable(dev);

	ethss_start();

	debug("- emac_open\n");

	emac_open = 1;

	return 0;
}

/* Eth device close */
void keystone2_eth_close(struct eth_device *dev)
{
	struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
	struct phy_device *phy_dev = eth_priv->phy_dev;

	debug("+ emac_close\n");

	if (!emac_open)
		return;

	ethss_stop();

	ksnav_close(&netcp_pktdma);
	qm_close();
	phy_shutdown(phy_dev);

	emac_open = 0;

	debug("- emac_close\n");
}

/*
 * This function sends a single packet on the network and returns
 * positive number (number of bytes transmitted) or negative for error
 */
static int keystone2_eth_send_packet(struct eth_device *dev,
					void *packet, int length)
{
	int ret_status = -1;
	struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
	struct phy_device *phy_dev = eth_priv->phy_dev;

	genphy_update_link(phy_dev);
	if (phy_dev->link == 0)
		return -1;

	if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0)
		return ret_status;

	return length;
}

/*
 * This function handles receipt of a packet from the network
 */
static int keystone2_eth_rcv_packet(struct eth_device *dev)
{
	void *hd;
	int  pkt_size;
	u32  *pkt;

	hd = ksnav_recv(&netcp_pktdma, &pkt, &pkt_size);
	if (hd == NULL)
		return 0;

	net_process_received_packet((uchar *)pkt, pkt_size);

	ksnav_release_rxhd(&netcp_pktdma, hd);

	return pkt_size;
}

#ifdef CONFIG_MCAST_TFTP
static int keystone2_eth_bcast_addr(struct eth_device *dev, u32 ip, u8 set)
{
	return 0;
}
#endif

/*
 * This function initializes the EMAC hardware.
 */
int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
{
	int res;
	struct eth_device *dev;
	struct phy_device *phy_dev;

	dev = malloc(sizeof(struct eth_device));
	if (dev == NULL)
		return -1;

	memset(dev, 0, sizeof(struct eth_device));

	strcpy(dev->name, eth_priv->int_name);
	dev->priv = eth_priv;

	keystone2_eth_read_mac_addr(dev);

	dev->iobase		= 0;
	dev->init		= keystone2_eth_open;
	dev->halt		= keystone2_eth_close;
	dev->send		= keystone2_eth_send_packet;
	dev->recv		= keystone2_eth_rcv_packet;
#ifdef CONFIG_MCAST_TFTP
	dev->mcast		= keystone2_eth_bcast_addr;
#endif

	eth_register(dev);

	/* Register MDIO bus if it's not registered yet */
	if (!mdio_bus) {
		mdio_bus	= mdio_alloc();
		mdio_bus->read	= keystone2_mdio_read;
		mdio_bus->write	= keystone2_mdio_write;
		mdio_bus->reset	= keystone2_mdio_reset;
		mdio_bus->priv	= (void *)EMAC_MDIO_BASE_ADDR;
		sprintf(mdio_bus->name, "ethernet-mdio");

		res = mdio_register(mdio_bus);
		if (res)
			return res;
	}

#ifndef CONFIG_SOC_K2G
	keystone2_net_serdes_setup();
#endif

	/* Create phy device and bind it with driver */
#ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
	phy_dev = phy_connect(mdio_bus, eth_priv->phy_addr,
			      dev, eth_priv->phy_if);
	phy_config(phy_dev);
#else
	phy_dev = phy_find_by_mask(mdio_bus, 1 << eth_priv->phy_addr,
				   eth_priv->phy_if);
	phy_dev->dev = dev;
#endif
	eth_priv->phy_dev = phy_dev;

	return 0;
}

struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
	.clk = SERDES_CLOCK_156P25M,
	.rate = SERDES_RATE_5G,
	.rate_mode = SERDES_QUARTER_RATE,
	.intf = SERDES_PHY_SGMII,
	.loopback = 0,
};

#ifndef CONFIG_SOC_K2G
static void keystone2_net_serdes_setup(void)
{
	ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
			&ks2_serdes_sgmii_156p25mhz,
			CONFIG_KSNET_SERDES_LANES_PER_SGMII);

#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
	ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE,
			&ks2_serdes_sgmii_156p25mhz,
			CONFIG_KSNET_SERDES_LANES_PER_SGMII);
#endif

	/* wait till setup */
	udelay(5000);
}
#endif
Commit	Line	Data
fc9a8e8d KM	1	/*
	2	* Ethernet driver for TI K2HK EVM.
	3	*
	4	* (C) Copyright 2012-2014
	5	* Texas Instruments Incorporated, <www.ti.com>
	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9	#include <common.h>
	10	#include <command.h>
24b852a7	11	#include <console.h>
fc9a8e8d KM	12
fc9a8e8d KM	13	#include <net.h>
3fe93623	14	#include <phy.h>
c05d05e7	15	#include <errno.h>
fc9a8e8d KM	16	#include <miiphy.h>
fc9a8e8d KM	17	#include <malloc.h>
ef454717	18	#include <asm/ti-common/keystone_nav.h>
0935cac6	19	#include <asm/ti-common/keystone_net.h>
a43febde	20	#include <asm/ti-common/keystone_serdes.h>
fc9a8e8d	21
fc9a8e8d	22	unsigned int emac_open;
550c5ce6	23	static struct mii_dev *mdio_bus;
fc9a8e8d KM	24	static unsigned int sys_has_mdio = 1;
	25
	26	#ifdef KEYSTONE2_EMAC_GIG_ENABLE
	27	#define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x)
	28	#else
	29	#define emac_gigabit_enable(x) /* no gigabit to enable */
	30	#endif
	31
	32	#define RX_BUFF_NUMS 24
	33	#define RX_BUFF_LEN 1520
	34	#define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
c05d05e7	35	#define SGMII_ANEG_TIMEOUT 4000
fc9a8e8d KM	36
	37	static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);
	38
	39	struct rx_buff_desc net_rx_buffs = {
	40	.buff_ptr = rx_buffs,
	41	.num_buffs = RX_BUFF_NUMS,
	42	.buff_len = RX_BUFF_LEN,
	43	.rx_flow = 22,
	44	};
	45
4657a2d4	46	#ifndef CONFIG_SOC_K2G
a43febde	47	static void keystone2_net_serdes_setup(void);
4657a2d4	48	#endif
fc9a8e8d	49
fc9a8e8d KM	50	int keystone2_eth_read_mac_addr(struct eth_device *dev)
	51	{
	52	struct eth_priv_t *eth_priv;
	53	u32 maca = 0;
	54	u32 macb = 0;
	55
	56	eth_priv = (struct eth_priv_t *)dev->priv;
	57
	58	/* Read the e-fuse mac address */
	59	if (eth_priv->slave_port == 1) {
	60	maca = __raw_readl(MAC_ID_BASE_ADDR);
	61	macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
	62	}
	63
	64	dev->enetaddr[0] = (macb >> 8) & 0xff;
	65	dev->enetaddr[1] = (macb >> 0) & 0xff;
	66	dev->enetaddr[2] = (maca >> 24) & 0xff;
	67	dev->enetaddr[3] = (maca >> 16) & 0xff;
	68	dev->enetaddr[4] = (maca >> 8) & 0xff;
	69	dev->enetaddr[5] = (maca >> 0) & 0xff;
	70
	71	return 0;
	72	}
	73
550c5ce6 KI	74	/* MDIO */
	75
	76	static int keystone2_mdio_reset(struct mii_dev *bus)
fc9a8e8d	77	{
550c5ce6 KI	78	u_int32_t clkdiv;
550c5ce6 KI	79	struct mdio_regs *adap_mdio = bus->priv;
fc9a8e8d KM	80
	81	clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
	82
550c5ce6 KI	83	writel((clkdiv & 0xffff) \| MDIO_CONTROL_ENABLE \|
550c5ce6 KI	84	MDIO_CONTROL_FAULT \| MDIO_CONTROL_FAULT_ENABLE,
fc9a8e8d KM	85	&adap_mdio->control);
	86
	87	while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE)
	88	;
550c5ce6 KI	89
550c5ce6 KI	90	return 0;
fc9a8e8d KM	91	}
fc9a8e8d KM	92
550c5ce6 KI	93	/**
	94	* keystone2_mdio_read - read a PHY register via MDIO interface.
	95	* Blocks until operation is complete.
	96	*/
	97	static int keystone2_mdio_read(struct mii_dev *bus,
	98	int addr, int devad, int reg)
fc9a8e8d	99	{
550c5ce6 KI	100	int tmp;
550c5ce6 KI	101	struct mdio_regs *adap_mdio = bus->priv;
fc9a8e8d KM	102
	103	while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
	104	;
	105
550c5ce6 KI	106	writel(MDIO_USERACCESS0_GO \| MDIO_USERACCESS0_WRITE_READ \|
550c5ce6 KI	107	((reg & 0x1f) << 21) \| ((addr & 0x1f) << 16),
fc9a8e8d KM	108	&adap_mdio->useraccess0);
	109
	110	/* Wait for command to complete */
	111	while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO)
	112	;
	113
550c5ce6 KI	114	if (tmp & MDIO_USERACCESS0_ACK)
550c5ce6 KI	115	return tmp & 0xffff;
fc9a8e8d	116
fc9a8e8d KM	117	return -1;
	118	}
	119
550c5ce6 KI	120	/**
550c5ce6 KI	121	* keystone2_mdio_write - write to a PHY register via MDIO interface.
fc9a8e8d KM	122	* Blocks until operation is complete.
fc9a8e8d KM	123	*/
550c5ce6 KI	124	static int keystone2_mdio_write(struct mii_dev *bus,
550c5ce6 KI	125	int addr, int devad, int reg, u16 val)
fc9a8e8d	126	{
550c5ce6 KI	127	struct mdio_regs *adap_mdio = bus->priv;
550c5ce6 KI	128
fc9a8e8d KM	129	while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
	130	;
	131
550c5ce6 KI	132	writel(MDIO_USERACCESS0_GO \| MDIO_USERACCESS0_WRITE_WRITE \|
	133	((reg & 0x1f) << 21) \| ((addr & 0x1f) << 16) \|
	134	(val & 0xffff), &adap_mdio->useraccess0);
fc9a8e8d KM	135
	136	/* Wait for command to complete */
	137	while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
	138	;
	139
	140	return 0;
	141	}
	142
fc9a8e8d KM	143	static void __attribute__((unused))
	144	keystone2_eth_gigabit_enable(struct eth_device *dev)
	145	{
	146	u_int16_t data;
	147	struct eth_priv_t eth_priv = (struct eth_priv_t )dev->priv;
	148
	149	if (sys_has_mdio) {
550c5ce6 KI	150	data = keystone2_mdio_read(mdio_bus, eth_priv->phy_addr,
	151	MDIO_DEVAD_NONE, 0);
	152	/* speed selection MSB */
	153	if (!(data & (1 << 6)))
fc9a8e8d KM	154	return;
	155	}
	156
	157	/*
	158	* Check if link detected is giga-bit
	159	* If Gigabit mode detected, enable gigbit in MAC
	160	*/
b2cfe322 HZ	161	writel(readl(DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) +
b2cfe322 HZ	162	CPGMACSL_REG_CTL) \|
fc9a8e8d	163	EMAC_MACCONTROL_GIGFORCE \| EMAC_MACCONTROL_GIGABIT_ENABLE,
b2cfe322	164	DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL);
fc9a8e8d KM	165	}
fc9a8e8d KM	166
4657a2d4 VA	167	#ifdef CONFIG_SOC_K2G
	168	int keystone_rgmii_config(struct phy_device *phy_dev)
	169	{
	170	unsigned int i, status;
	171
	172	i = 0;
	173	do {
	174	if (i > SGMII_ANEG_TIMEOUT) {
	175	puts(" TIMEOUT !\n");
	176	phy_dev->link = 0;
	177	return 0;
	178	}
	179
	180	if (ctrlc()) {
	181	puts("user interrupt!\n");
	182	phy_dev->link = 0;
	183	return -EINTR;
	184	}
	185
	186	if ((i++ % 500) == 0)
	187	printf(".");
	188
	189	udelay(1000); /* 1 ms */
	190	status = readl(RGMII_STATUS_REG);
	191	} while (!(status & RGMII_REG_STATUS_LINK));
	192
	193	puts(" done\n");
	194
	195	return 0;
	196	}
	197	#else
c05d05e7	198	int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface)
fc9a8e8d KM	199	{
	200	unsigned int i, status, mask;
	201	unsigned int mr_adv_ability, control;
	202
	203	switch (interface) {
	204	case SGMII_LINK_MAC_MAC_AUTONEG:
	205	mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE \|
	206	SGMII_REG_MR_ADV_LINK \|
	207	SGMII_REG_MR_ADV_FULL_DUPLEX \|
	208	SGMII_REG_MR_ADV_GIG_MODE);
	209	control = (SGMII_REG_CONTROL_MASTER \|
	210	SGMII_REG_CONTROL_AUTONEG);
	211
	212	break;
	213	case SGMII_LINK_MAC_PHY:
	214	case SGMII_LINK_MAC_PHY_FORCED:
	215	mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
	216	control = SGMII_REG_CONTROL_AUTONEG;
	217
	218	break;
	219	case SGMII_LINK_MAC_MAC_FORCED:
	220	mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE \|
	221	SGMII_REG_MR_ADV_LINK \|
	222	SGMII_REG_MR_ADV_FULL_DUPLEX \|
	223	SGMII_REG_MR_ADV_GIG_MODE);
	224	control = SGMII_REG_CONTROL_MASTER;
	225
	226	break;
	227	case SGMII_LINK_MAC_FIBER:
	228	mr_adv_ability = 0x20;
	229	control = SGMII_REG_CONTROL_AUTONEG;
	230
	231	break;
	232	default:
	233	mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
	234	control = SGMII_REG_CONTROL_AUTONEG;
	235	}
	236
	237	__raw_writel(0, SGMII_CTL_REG(port));
	238
	239	/*
	240	* Wait for the SerDes pll to lock,
	241	* but don't trap if lock is never read
	242	*/
	243	for (i = 0; i < 1000; i++) {
	244	udelay(2000);
	245	status = __raw_readl(SGMII_STATUS_REG(port));
	246	if ((status & SGMII_REG_STATUS_LOCK) != 0)
	247	break;
	248	}
	249
	250	__raw_writel(mr_adv_ability, SGMII_MRADV_REG(port));
	251	__raw_writel(control, SGMII_CTL_REG(port));
	252
	253
	254	mask = SGMII_REG_STATUS_LINK;
	255
	256	if (control & SGMII_REG_CONTROL_AUTONEG)
	257	mask \|= SGMII_REG_STATUS_AUTONEG;
	258
c05d05e7 KI	259	status = __raw_readl(SGMII_STATUS_REG(port));
	260	if ((status & mask) == mask)
	261	return 0;
	262
	263	printf("\n%s Waiting for SGMII auto negotiation to complete",
	264	phy_dev->dev->name);
	265	while ((status & mask) != mask) {
	266	/*
	267	* Timeout reached ?
	268	*/
	269	if (i > SGMII_ANEG_TIMEOUT) {
	270	puts(" TIMEOUT !\n");
	271	phy_dev->link = 0;
	272	return 0;
	273	}
	274
	275	if (ctrlc()) {
	276	puts("user interrupt!\n");
	277	phy_dev->link = 0;
	278	return -EINTR;
	279	}
	280
	281	if ((i++ % 500) == 0)
	282	printf(".");
	283
	284	udelay(1000); /* 1 ms */
fc9a8e8d	285	status = __raw_readl(SGMII_STATUS_REG(port));
fc9a8e8d	286	}
c05d05e7	287	puts(" done\n");
fc9a8e8d KM	288
	289	return 0;
	290	}
4657a2d4	291	#endif
fc9a8e8d KM	292
	293	int mac_sl_reset(u32 port)
	294	{
	295	u32 i, v;
	296
	297	if (port >= DEVICE_N_GMACSL_PORTS)
	298	return GMACSL_RET_INVALID_PORT;
	299
	300	/* Set the soft reset bit */
e6c9428a KI	301	writel(CPGMAC_REG_RESET_VAL_RESET,
e6c9428a KI	302	DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
fc9a8e8d KM	303
	304	/* Wait for the bit to clear */
	305	for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
e6c9428a	306	v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
fc9a8e8d KM	307	if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
	308	CPGMAC_REG_RESET_VAL_RESET)
	309	return GMACSL_RET_OK;
	310	}
	311
	312	/* Timeout on the reset */
	313	return GMACSL_RET_WARN_RESET_INCOMPLETE;
	314	}
	315
	316	int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
	317	{
	318	u32 v, i;
	319	int ret = GMACSL_RET_OK;
	320
	321	if (port >= DEVICE_N_GMACSL_PORTS)
	322	return GMACSL_RET_INVALID_PORT;
	323
	324	if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) {
	325	cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN;
	326	ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG;
	327	}
	328
	329	/* Must wait if the device is undergoing reset */
	330	for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
e6c9428a	331	v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
fc9a8e8d KM	332	if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
	333	CPGMAC_REG_RESET_VAL_RESET)
	334	break;
	335	}
	336
	337	if (i == DEVICE_EMACSL_RESET_POLL_COUNT)
	338	return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE;
	339
e6c9428a KI	340	writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
e6c9428a KI	341	writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
fc9a8e8d	342
4657a2d4	343	#ifndef CONFIG_SOC_K2HK
ff11c769 KI	344	/* Map RX packet flow priority to 0 */
	345	writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP);
	346	#endif
	347
fc9a8e8d KM	348	return ret;
	349	}
	350
	351	int ethss_config(u32 ctl, u32 max_pkt_size)
	352	{
	353	u32 i;
	354
	355	/* Max length register */
e6c9428a	356	writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN);
fc9a8e8d KM	357
fc9a8e8d KM	358	/* Control register */
e6c9428a	359	writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL);
fc9a8e8d KM	360
fc9a8e8d KM	361	/* All statistics enabled by default */
e6c9428a KI	362	writel(CPSW_REG_VAL_STAT_ENABLE_ALL,
e6c9428a KI	363	DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN);
fc9a8e8d KM	364
fc9a8e8d KM	365	/* Reset and enable the ALE */
e6c9428a KI	366	writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE \|
	367	CPSW_REG_VAL_ALE_CTL_BYPASS,
	368	DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL);
fc9a8e8d KM	369
	370	/* All ports put into forward mode */
	371	for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++)
e6c9428a KI	372	writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE,
e6c9428a KI	373	DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i));
fc9a8e8d KM	374
	375	return 0;
	376	}
	377
	378	int ethss_start(void)
	379	{
	380	int i;
	381	struct mac_sl_cfg cfg;
	382
	383	cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER;
	384	cfg.ctl = GMACSL_ENABLE \| GMACSL_RX_ENABLE_EXT_CTL;
	385
	386	for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) {
	387	mac_sl_reset(i);
	388	mac_sl_config(i, &cfg);
	389	}
	390
	391	return 0;
	392	}
	393
	394	int ethss_stop(void)
	395	{
	396	int i;
	397
	398	for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++)
	399	mac_sl_reset(i);
	400
	401	return 0;
	402	}
	403
	404	int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num)
	405	{
	406	if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE)
	407	num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE;
	408
9ea9021a KI	409	return ksnav_send(&netcp_pktdma, buffer,
9ea9021a KI	410	num_bytes, (slave_port_num) << 16);
fc9a8e8d KM	411	}
	412
	413	/* Eth device open */
	414	static int keystone2_eth_open(struct eth_device dev, bd_t bis)
	415	{
fc9a8e8d	416	struct eth_priv_t eth_priv = (struct eth_priv_t )dev->priv;
3fe93623	417	struct phy_device *phy_dev = eth_priv->phy_dev;
fc9a8e8d KM	418
	419	debug("+ emac_open\n");
	420
	421	net_rx_buffs.rx_flow = eth_priv->rx_flow;
	422
	423	sys_has_mdio =
	424	(eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0;
	425
6c0fb41a KI	426	if (sys_has_mdio)
	427	keystone2_mdio_reset(mdio_bus);
	428
4657a2d4 VA	429	#ifdef CONFIG_SOC_K2G
	430	keystone_rgmii_config(phy_dev);
	431	#else
c05d05e7	432	keystone_sgmii_config(phy_dev, eth_priv->slave_port - 1,
fc9a8e8d	433	eth_priv->sgmii_link_type);
4657a2d4	434	#endif
fc9a8e8d KM	435
	436	udelay(10000);
	437
	438	/* On chip switch configuration */
	439	ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);
	440
	441	/* TODO: add error handling code */
	442	if (qm_init()) {
	443	printf("ERROR: qm_init()\n");
	444	return -1;
	445	}
9ea9021a	446	if (ksnav_init(&netcp_pktdma, &net_rx_buffs)) {
fc9a8e8d KM	447	qm_close();
	448	printf("ERROR: netcp_init()\n");
	449	return -1;
	450	}
	451
	452	/*
	453	* Streaming switch configuration. If not present this
	454	* statement is defined to void in target.h.
	455	* If present this is usually defined to a series of register writes
	456	*/
	457	hw_config_streaming_switch();
	458
	459	if (sys_has_mdio) {
550c5ce6	460	keystone2_mdio_reset(mdio_bus);
fc9a8e8d	461
3fe93623 KI	462	phy_startup(phy_dev);
3fe93623 KI	463	if (phy_dev->link == 0) {
9ea9021a	464	ksnav_close(&netcp_pktdma);
fc9a8e8d KM	465	qm_close();
	466	return -1;
	467	}
	468	}
	469
	470	emac_gigabit_enable(dev);
	471
	472	ethss_start();
	473
	474	debug("- emac_open\n");
	475
	476	emac_open = 1;
	477
	478	return 0;
	479	}
	480
	481	/* Eth device close */
	482	void keystone2_eth_close(struct eth_device *dev)
	483	{
3fe93623 KI	484	struct eth_priv_t eth_priv = (struct eth_priv_t )dev->priv;
	485	struct phy_device *phy_dev = eth_priv->phy_dev;
	486
fc9a8e8d KM	487	debug("+ emac_close\n");
	488
	489	if (!emac_open)
	490	return;
	491
	492	ethss_stop();
	493
9ea9021a	494	ksnav_close(&netcp_pktdma);
fc9a8e8d	495	qm_close();
3fe93623	496	phy_shutdown(phy_dev);
fc9a8e8d KM	497
	498	emac_open = 0;
	499
	500	debug("- emac_close\n");
	501	}
	502
fc9a8e8d KM	503	/*
	504	* This function sends a single packet on the network and returns
	505	* positive number (number of bytes transmitted) or negative for error
	506	*/
	507	static int keystone2_eth_send_packet(struct eth_device *dev,
	508	void *packet, int length)
	509	{
	510	int ret_status = -1;
	511	struct eth_priv_t eth_priv = (struct eth_priv_t )dev->priv;
a4d2adee	512	struct phy_device *phy_dev = eth_priv->phy_dev;
fc9a8e8d	513
a4d2adee KI	514	genphy_update_link(phy_dev);
a4d2adee KI	515	if (phy_dev->link == 0)
fc9a8e8d KM	516	return -1;
fc9a8e8d KM	517
fc9a8e8d KM	518	if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0)
	519	return ret_status;
	520
fc9a8e8d KM	521	return length;
	522	}
	523
	524	/*
	525	* This function handles receipt of a packet from the network
	526	*/
	527	static int keystone2_eth_rcv_packet(struct eth_device *dev)
	528	{
	529	void *hd;
	530	int pkt_size;
	531	u32 *pkt;
	532
9ea9021a	533	hd = ksnav_recv(&netcp_pktdma, &pkt, &pkt_size);
fc9a8e8d KM	534	if (hd == NULL)
	535	return 0;
	536
1fd92db8	537	net_process_received_packet((uchar *)pkt, pkt_size);
fc9a8e8d	538
9ea9021a	539	ksnav_release_rxhd(&netcp_pktdma, hd);
fc9a8e8d KM	540
	541	return pkt_size;
	542	}
	543
5031ca59 VA	544	#ifdef CONFIG_MCAST_TFTP
	545	static int keystone2_eth_bcast_addr(struct eth_device *dev, u32 ip, u8 set)
	546	{
	547	return 0;
	548	}
	549	#endif
	550
fc9a8e8d KM	551	/*
	552	* This function initializes the EMAC hardware.
	553	*/
	554	int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
	555	{
550c5ce6	556	int res;
fc9a8e8d	557	struct eth_device *dev;
3fe93623	558	struct phy_device *phy_dev;
fc9a8e8d KM	559
	560	dev = malloc(sizeof(struct eth_device));
	561	if (dev == NULL)
	562	return -1;
	563
	564	memset(dev, 0, sizeof(struct eth_device));
	565
	566	strcpy(dev->name, eth_priv->int_name);
	567	dev->priv = eth_priv;
	568
	569	keystone2_eth_read_mac_addr(dev);
	570
	571	dev->iobase = 0;
	572	dev->init = keystone2_eth_open;
	573	dev->halt = keystone2_eth_close;
	574	dev->send = keystone2_eth_send_packet;
	575	dev->recv = keystone2_eth_rcv_packet;
5031ca59 VA	576	#ifdef CONFIG_MCAST_TFTP
	577	dev->mcast = keystone2_eth_bcast_addr;
	578	#endif
fc9a8e8d KM	579
	580	eth_register(dev);
	581
550c5ce6 KI	582	/* Register MDIO bus if it's not registered yet */
	583	if (!mdio_bus) {
	584	mdio_bus = mdio_alloc();
	585	mdio_bus->read = keystone2_mdio_read;
	586	mdio_bus->write = keystone2_mdio_write;
	587	mdio_bus->reset = keystone2_mdio_reset;
	588	mdio_bus->priv = (void *)EMAC_MDIO_BASE_ADDR;
	589	sprintf(mdio_bus->name, "ethernet-mdio");
	590
	591	res = mdio_register(mdio_bus);
	592	if (res)
	593	return res;
	594	}
	595
4657a2d4	596	#ifndef CONFIG_SOC_K2G
312aca4e	597	keystone2_net_serdes_setup();
4657a2d4	598	#endif
312aca4e	599
3fe93623 KI	600	/* Create phy device and bind it with driver */
	601	#ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
	602	phy_dev = phy_connect(mdio_bus, eth_priv->phy_addr,
bf7bd4e7	603	dev, eth_priv->phy_if);
3fe93623 KI	604	phy_config(phy_dev);
	605	#else
	606	phy_dev = phy_find_by_mask(mdio_bus, 1 << eth_priv->phy_addr,
bf7bd4e7	607	eth_priv->phy_if);
3fe93623 KI	608	phy_dev->dev = dev;
	609	#endif
	610	eth_priv->phy_dev = phy_dev;
	611
fc9a8e8d KM	612	return 0;
	613	}
	614
92a16c81 HZ	615	struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
	616	.clk = SERDES_CLOCK_156P25M,
	617	.rate = SERDES_RATE_5G,
	618	.rate_mode = SERDES_QUARTER_RATE,
	619	.intf = SERDES_PHY_SGMII,
	620	.loopback = 0,
	621	};
	622
4657a2d4	623	#ifndef CONFIG_SOC_K2G
a43febde	624	static void keystone2_net_serdes_setup(void)
fc9a8e8d	625	{
92a16c81 HZ	626	ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
	627	&ks2_serdes_sgmii_156p25mhz,
	628	CONFIG_KSNET_SERDES_LANES_PER_SGMII);
	629
87ac27bd	630	#if defined(CONFIG_SOC_K2E) \|\| defined(CONFIG_SOC_K2L)
3c61502a KI	631	ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE,
	632	&ks2_serdes_sgmii_156p25mhz,
	633	CONFIG_KSNET_SERDES_LANES_PER_SGMII);
	634	#endif
	635
92a16c81 HZ	636	/* wait till setup */
92a16c81 HZ	637	udelay(5000);
fc9a8e8d	638	}
4657a2d4	639	#endif