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e60476a0 PK |
1 | /* |
2 | * Copyright 2015 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | #include <common.h> | |
7 | #include <phy.h> | |
8 | #include <fsl-mc/ldpaa_wriop.h> | |
9 | #include <asm/io.h> | |
e60476a0 | 10 | #include <asm/arch/fsl_serdes.h> |
e60476a0 PK |
11 | |
12 | u32 dpmac_to_devdisr[] = { | |
13 | [WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1, | |
14 | [WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2, | |
15 | [WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3, | |
16 | [WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4, | |
17 | [WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5, | |
18 | [WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6, | |
19 | [WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7, | |
20 | [WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8, | |
21 | [WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9, | |
22 | [WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10, | |
23 | [WRIOP1_DPMAC11] = FSL_CHASSIS3_DEVDISR2_DPMAC11, | |
24 | [WRIOP1_DPMAC12] = FSL_CHASSIS3_DEVDISR2_DPMAC12, | |
25 | [WRIOP1_DPMAC13] = FSL_CHASSIS3_DEVDISR2_DPMAC13, | |
26 | [WRIOP1_DPMAC14] = FSL_CHASSIS3_DEVDISR2_DPMAC14, | |
27 | [WRIOP1_DPMAC15] = FSL_CHASSIS3_DEVDISR2_DPMAC15, | |
28 | [WRIOP1_DPMAC16] = FSL_CHASSIS3_DEVDISR2_DPMAC16, | |
29 | [WRIOP1_DPMAC17] = FSL_CHASSIS3_DEVDISR2_DPMAC17, | |
30 | [WRIOP1_DPMAC18] = FSL_CHASSIS3_DEVDISR2_DPMAC18, | |
31 | [WRIOP1_DPMAC19] = FSL_CHASSIS3_DEVDISR2_DPMAC19, | |
32 | [WRIOP1_DPMAC20] = FSL_CHASSIS3_DEVDISR2_DPMAC20, | |
33 | [WRIOP1_DPMAC21] = FSL_CHASSIS3_DEVDISR2_DPMAC21, | |
34 | [WRIOP1_DPMAC22] = FSL_CHASSIS3_DEVDISR2_DPMAC22, | |
35 | [WRIOP1_DPMAC23] = FSL_CHASSIS3_DEVDISR2_DPMAC23, | |
36 | [WRIOP1_DPMAC24] = FSL_CHASSIS3_DEVDISR2_DPMAC24, | |
37 | }; | |
38 | ||
39 | static int is_device_disabled(int dpmac_id) | |
40 | { | |
41 | struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; | |
42 | u32 devdisr2 = in_le32(&gur->devdisr2); | |
43 | ||
44 | return dpmac_to_devdisr[dpmac_id] & devdisr2; | |
45 | } | |
46 | ||
47 | void wriop_dpmac_disable(int dpmac_id) | |
48 | { | |
49 | struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; | |
50 | ||
51 | setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]); | |
52 | } | |
53 | ||
54 | void wriop_dpmac_enable(int dpmac_id) | |
55 | { | |
56 | struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; | |
57 | ||
58 | clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]); | |
59 | } | |
60 | ||
61 | phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl) | |
62 | { | |
63 | enum srds_prtcl; | |
64 | ||
65 | if (is_device_disabled(dpmac_id + 1)) | |
66 | return PHY_INTERFACE_MODE_NONE; | |
67 | ||
68 | if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII16) | |
69 | return PHY_INTERFACE_MODE_SGMII; | |
70 | ||
71 | if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8) | |
72 | return PHY_INTERFACE_MODE_XGMII; | |
73 | ||
74 | if (lane_prtcl >= XAUI1 && lane_prtcl <= XAUI2) | |
75 | return PHY_INTERFACE_MODE_XGMII; | |
76 | ||
77 | if (lane_prtcl >= QSGMII_A && lane_prtcl <= QSGMII_D) | |
78 | return PHY_INTERFACE_MODE_QSGMII; | |
79 | ||
80 | return PHY_INTERFACE_MODE_NONE; | |
81 | } | |
1b7dba99 PK |
82 | |
83 | void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl) | |
84 | { | |
85 | switch (lane_prtcl) { | |
86 | case QSGMII_A: | |
87 | wriop_init_dpmac(sd, 5, (int)lane_prtcl); | |
88 | wriop_init_dpmac(sd, 6, (int)lane_prtcl); | |
89 | wriop_init_dpmac(sd, 7, (int)lane_prtcl); | |
90 | wriop_init_dpmac(sd, 8, (int)lane_prtcl); | |
91 | break; | |
92 | case QSGMII_B: | |
93 | wriop_init_dpmac(sd, 1, (int)lane_prtcl); | |
94 | wriop_init_dpmac(sd, 2, (int)lane_prtcl); | |
95 | wriop_init_dpmac(sd, 3, (int)lane_prtcl); | |
96 | wriop_init_dpmac(sd, 4, (int)lane_prtcl); | |
97 | break; | |
98 | case QSGMII_C: | |
99 | wriop_init_dpmac(sd, 13, (int)lane_prtcl); | |
100 | wriop_init_dpmac(sd, 14, (int)lane_prtcl); | |
101 | wriop_init_dpmac(sd, 15, (int)lane_prtcl); | |
102 | wriop_init_dpmac(sd, 16, (int)lane_prtcl); | |
103 | break; | |
104 | case QSGMII_D: | |
105 | wriop_init_dpmac(sd, 9, (int)lane_prtcl); | |
106 | wriop_init_dpmac(sd, 10, (int)lane_prtcl); | |
107 | wriop_init_dpmac(sd, 11, (int)lane_prtcl); | |
108 | wriop_init_dpmac(sd, 12, (int)lane_prtcl); | |
109 | break; | |
110 | } | |
111 | } |