[people/ms/u-boot.git] / drivers / net / lpc32xx_eth.c

/*
 * LPC32xx Ethernet MAC interface driver
 *
 * (C) Copyright 2014  DENX Software Engineering GmbH
 * Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <net.h>
#include <malloc.h>
#include <miiphy.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/types.h>
#include <asm/system.h>
#include <asm/byteorder.h>
#include <asm/arch/cpu.h>
#include <asm/arch/config.h>

/*
 * Notes:
 *
 * 1. Unless specified otherwise, all references to tables or paragraphs
 *    are to UM10326, "LPC32x0 and LPC32x0/01 User manual".
 *
 * 2. Only bitfield masks/values which are actually used by the driver
 *    are defined.
 */

/* a single RX descriptor. The controller has an array of these */
struct lpc32xx_eth_rxdesc {
	u32 packet;		/* Receive packet pointer */
	u32 control;		/* Descriptor command status */
};

#define LPC32XX_ETH_RX_DESC_SIZE (sizeof(struct lpc32xx_eth_rxdesc))

/* RX control bitfields/masks (see Table 330) */
#define LPC32XX_ETH_RX_CTRL_SIZE_MASK 0x000007FF
#define LPC32XX_ETH_RX_CTRL_UNUSED    0x7FFFF800
#define LPC32XX_ETH_RX_CTRL_INTERRUPT 0x80000000

/* a single RX status. The controller has an array of these */
struct lpc32xx_eth_rxstat {
	u32 statusinfo;		/* Transmit Descriptor status */
	u32 statushashcrc;	/* Transmit Descriptor CRCs */
};

#define LPC32XX_ETH_RX_STAT_SIZE (sizeof(struct lpc32xx_eth_rxstat))

/* RX statusinfo bitfields/masks (see Table 333) */
#define RX_STAT_RXSIZE 0x000007FF
/* Helper: OR of all errors except RANGE */
#define RX_STAT_ERRORS 0x1B800000

/* a single TX descriptor. The controller has an array of these */
struct lpc32xx_eth_txdesc {
	u32 packet;		/* Transmit packet pointer */
	u32 control;		/* Descriptor control */
};

#define LPC32XX_ETH_TX_DESC_SIZE (sizeof(struct lpc32xx_eth_txdesc))

/* TX control bitfields/masks (see Table 335) */
#define TX_CTRL_TXSIZE    0x000007FF
#define TX_CTRL_LAST      0x40000000

/* a single TX status. The controller has an array of these */
struct lpc32xx_eth_txstat {
	u32 statusinfo;		/* Transmit Descriptor status */
};

#define LPC32XX_ETH_TX_STAT_SIZE (sizeof(struct lpc32xx_eth_txstat))

/* Ethernet MAC interface registers (see Table 283) */
struct lpc32xx_eth_registers {
	/* MAC registers - 0x3106_0000 to 0x3106_01FC */
	u32 mac1;		/* MAC configuration register 1 */
	u32 mac2;		/* MAC configuration register 2 */
	u32 ipgt;		/* Back-to-back Inter-Packet Gap reg. */
	u32 ipgr;		/* Non-back-to-back IPG register */
	u32 clrt;		/* Collision Window / Retry register */
	u32 maxf;		/* Maximum Frame register */
	u32 supp;		/* Phy Support register */
	u32 test;
	u32 mcfg;		/* MII management configuration reg. */
	u32 mcmd;		/* MII management command register */
	u32 madr;		/* MII management address register */
	u32 mwtd;		/* MII management wite data register */
	u32 mrdd;		/* MII management read data register */
	u32 mind;		/* MII management indicators register */
	u32 reserved1[2];
	u32 sa0;		/* Station address register 0 */
	u32 sa1;		/* Station address register 1 */
	u32 sa2;		/* Station address register 2 */
	u32 reserved2[45];
	/* Control registers */
	u32 command;
	u32 status;
	u32 rxdescriptor;
	u32 rxstatus;
	u32 rxdescriptornumber;	/* actually, number MINUS ONE */
	u32 rxproduceindex;	/* head of rx desc fifo */
	u32 rxconsumeindex;	/* tail of rx desc fifo */
	u32 txdescriptor;
	u32 txstatus;
	u32 txdescriptornumber;	/* actually, number MINUS ONE */
	u32 txproduceindex;	/* head of rx desc fifo */
	u32 txconsumeindex;	/* tail of rx desc fifo */
	u32 reserved3[10];
	u32 tsv0;		/* Transmit status vector register 0 */
	u32 tsv1;		/* Transmit status vector register 1 */
	u32 rsv;		/* Receive status vector register */
	u32 reserved4[3];
	u32 flowcontrolcounter;
	u32 flowcontrolstatus;
	u32 reserved5[34];
	/* RX filter registers - 0x3106_0200 to 0x3106_0FDC */
	u32 rxfilterctrl;
	u32 rxfilterwolstatus;
	u32 rxfilterwolclear;
	u32 reserved6;
	u32 hashfilterl;
	u32 hashfilterh;
	u32 reserved7[882];
	/* Module control registers - 0x3106_0FE0 to 0x3106_0FF8 */
	u32 intstatus;		/* Interrupt status register */
	u32 intenable;
	u32 intclear;
	u32 intset;
	u32 reserved8;
	u32 powerdown;
	u32 reserved9;
};

/* MAC1 register bitfields/masks and offsets (see Table 283) */
#define MAC1_RECV_ENABLE        0x00000001
#define MAC1_PASS_ALL_RX_FRAMES 0x00000002
#define MAC1_SOFT_RESET         0x00008000
/* Helper: general reset */
#define MAC1_RESETS             0x0000CF00

/* MAC2 register bitfields/masks and offsets (see Table 284) */
#define MAC2_FULL_DUPLEX    0x00000001
#define MAC2_CRC_ENABLE     0x00000010
#define MAC2_PAD_CRC_ENABLE 0x00000020

/* SUPP register bitfields/masks and offsets (see Table 290) */
#define SUPP_SPEED 0x00000100

/* MCFG register bitfields/masks and offsets (see Table 292) */
#define MCFG_CLOCK_SELECT_MASK  0x0000001C
/* divide clock by 28 (see Table 293) */
#define MCFG_CLOCK_SELECT_DIV28 0x0000001C

/* MADR register bitfields/masks and offsets (see Table 295) */
#define MADR_REG_MASK   0x0000001F
#define MADR_PHY_MASK   0x00001F00
#define MADR_REG_OFFSET 0
#define MADR_PHY_OFFSET 8

/* MIND register bitfields/masks (see Table 298) */
#define MIND_BUSY      0x00000001

/* COMMAND register bitfields/masks and offsets (see Table 283) */
#define COMMAND_RXENABLE      0x00000001
#define COMMAND_TXENABLE      0x00000002
#define COMMAND_PASSRUNTFRAME 0x00000040
#define COMMAND_FULL_DUPLEX   0x00000400
/* Helper: general reset */
#define COMMAND_RESETS        0x00000038

/* STATUS register bitfields/masks and offsets (see Table 283) */
#define STATUS_RXSTATUS 0x00000001
#define STATUS_TXSTATUS 0x00000002

/* RXFILTERCTRL register bitfields/masks (see Table 319) */
#define RXFILTERCTRL_ACCEPTBROADCAST 0x00000002
#define RXFILTERCTRL_ACCEPTPERFECT   0x00000020

/* Buffers and descriptors */

#define ATTRS(n) __aligned(n)

#define TX_BUF_COUNT 4
#define RX_BUF_COUNT 4

struct lpc32xx_eth_buffers {
	ATTRS(4) struct lpc32xx_eth_txdesc tx_desc[TX_BUF_COUNT];
	ATTRS(4) struct lpc32xx_eth_txstat tx_stat[TX_BUF_COUNT];
	ATTRS(PKTALIGN) u8 tx_buf[TX_BUF_COUNT*PKTSIZE_ALIGN];
	ATTRS(4) struct lpc32xx_eth_rxdesc rx_desc[RX_BUF_COUNT];
	ATTRS(8) struct lpc32xx_eth_rxstat rx_stat[RX_BUF_COUNT];
	ATTRS(PKTALIGN) u8 rx_buf[RX_BUF_COUNT*PKTSIZE_ALIGN];
};

/* port device data struct */
struct lpc32xx_eth_device {
	struct eth_device dev;
	struct lpc32xx_eth_registers *regs;
	struct lpc32xx_eth_buffers *bufs;
};

#define LPC32XX_ETH_DEVICE_SIZE (sizeof(struct lpc32xx_eth_device))

/* generic macros */
#define to_lpc32xx_eth(_d) container_of(_d, struct lpc32xx_eth_device, dev)

/* timeout for MII polling */
#define MII_TIMEOUT 10000000

/* limits for PHY and register addresses */
#define MII_MAX_REG (MADR_REG_MASK >> MADR_REG_OFFSET)

#define MII_MAX_PHY (MADR_PHY_MASK >> MADR_PHY_OFFSET)

DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
/*
 * mii_reg_read - miiphy_read callback function.
 *
 * Returns 16bit phy register value, or 0xffff on error
 */
static int mii_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 *data)
{
	struct eth_device *dev = eth_get_dev_by_name(devname);
	struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev);
	struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs;
	u32 mind_reg;
	u32 timeout;

	/* check parameters */
	if (phy_adr > MII_MAX_PHY) {
		printf("%s:%u: Invalid PHY address %d\n",
		       __func__, __LINE__, phy_adr);
		return -EFAULT;
	}
	if (reg_ofs > MII_MAX_REG) {
		printf("%s:%u: Invalid register offset %d\n",
		       __func__, __LINE__, reg_ofs);
		return -EFAULT;
	}

	/* write the phy and reg addressse into the MII address reg */
	writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET),
	       &regs->madr);

	/* write 1 to the MII command register to cause a read */
	writel(1, &regs->mcmd);

	/* wait till the MII is not busy */
	timeout = MII_TIMEOUT;
	do {
		/* read MII indicators register */
		mind_reg = readl(&regs->mind);
		if (--timeout == 0)
			break;
	} while (mind_reg & MIND_BUSY);

	/* write 0 to the MII command register to finish the read */
	writel(0, &regs->mcmd);

	if (timeout == 0) {
		printf("%s:%u: MII busy timeout\n", __func__, __LINE__);
		return -EFAULT;
	}

	*data = (u16) readl(&regs->mrdd);

	debug("%s:(adr %d, off %d) => %04x\n", __func__, phy_adr,
	      reg_ofs, *data);

	return 0;
}

/*
 * mii_reg_write - imiiphy_write callback function.
 *
 * Returns 0 if write succeed, -EINVAL on bad parameters
 * -ETIME on timeout
 */
static int mii_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
{
	struct eth_device *dev = eth_get_dev_by_name(devname);
	struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev);
	struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs;
	u32 mind_reg;
	u32 timeout;

	/* check parameters */
	if (phy_adr > MII_MAX_PHY) {
		printf("%s:%u: Invalid PHY address %d\n",
		       __func__, __LINE__, phy_adr);
		return -EFAULT;
	}
	if (reg_ofs > MII_MAX_REG) {
		printf("%s:%u: Invalid register offset %d\n",
		       __func__, __LINE__, reg_ofs);
		return -EFAULT;
	}

	/* wait till the MII is not busy */
	timeout = MII_TIMEOUT;
	do {
		/* read MII indicators register */
		mind_reg = readl(&regs->mind);
		if (--timeout == 0)
			break;
	} while (mind_reg & MIND_BUSY);

	if (timeout == 0) {
		printf("%s:%u: MII busy timeout\n", __func__,
		       __LINE__);
		return -EFAULT;
	}

	/* write the phy and reg addressse into the MII address reg */
	writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET),
	       &regs->madr);

	/* write data to the MII write register */
	writel(data, &regs->mwtd);

	/*debug("%s:(adr %d, off %d) <= %04x\n", __func__, phy_adr,
		reg_ofs, data);*/

	return 0;
}
#endif

#if defined(CONFIG_PHYLIB)
int lpc32xx_eth_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr,
	int reg_addr)
{
	u16 data;
	int ret;
	ret = mii_reg_read(bus->name, phy_addr, reg_addr, &data);
	if (ret)
		return ret;
	return data;
}

int lpc32xx_eth_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr,
	int reg_addr, u16 data)
{
	return mii_reg_write(bus->name, phy_addr, reg_addr, data);
}
#endif

/*
 * Locate buffers in SRAM at 0x00001000 to avoid cache issues and
 * maximize throughput.
 */

#define LPC32XX_ETH_BUFS 0x00001000

static struct lpc32xx_eth_device lpc32xx_eth = {
	.regs = (struct lpc32xx_eth_registers *)LPC32XX_ETH_BASE,
	.bufs = (struct lpc32xx_eth_buffers *)LPC32XX_ETH_BUFS
};

#define TX_TIMEOUT 10000

static int lpc32xx_eth_send(struct eth_device *dev, void *dataptr, int datasize)
{
	struct lpc32xx_eth_device *lpc32xx_eth_device =
		container_of(dev, struct lpc32xx_eth_device, dev);
	struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
	struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
	int timeout, tx_index;

	/* time out if transmit descriptor array remains full too long */
	timeout = TX_TIMEOUT;
	while ((readl(&regs->status) & STATUS_TXSTATUS) &&
	       (readl(&regs->txconsumeindex)
	       == readl(&regs->txproduceindex))) {
		if (timeout-- == 0)
			return -1;
	}

	/* determine next transmit packet index to use */
	tx_index = readl(&regs->txproduceindex);

	/* set up transmit packet */
	writel((u32)dataptr, &bufs->tx_desc[tx_index].packet);
	writel(TX_CTRL_LAST | ((datasize - 1) & TX_CTRL_TXSIZE),
	       &bufs->tx_desc[tx_index].control);
	writel(0, &bufs->tx_stat[tx_index].statusinfo);

	/* pass transmit packet to DMA engine */
	tx_index = (tx_index + 1) % TX_BUF_COUNT;
	writel(tx_index, &regs->txproduceindex);

	/* transmission succeeded */
	return 0;
}

#define RX_TIMEOUT 1000000

static int lpc32xx_eth_recv(struct eth_device *dev)
{
	struct lpc32xx_eth_device *lpc32xx_eth_device =
		container_of(dev, struct lpc32xx_eth_device, dev);
	struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
	struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
	int timeout, rx_index;

	/* time out if receive descriptor array remains empty too long */
	timeout = RX_TIMEOUT;
	while (readl(&regs->rxproduceindex) == readl(&regs->rxconsumeindex)) {
		if (timeout-- == 0)
			return -1;
	}

	/* determine next receive packet index to use */
	rx_index = readl(&regs->rxconsumeindex);

	/* if data was valid, pass it on */
	if (!(bufs->rx_stat[rx_index].statusinfo & RX_STAT_ERRORS)) {
		net_process_received_packet(
			&(bufs->rx_buf[rx_index * PKTSIZE_ALIGN]),
			(bufs->rx_stat[rx_index].statusinfo
			 & RX_STAT_RXSIZE) + 1);
	}

	/* pass receive slot back to DMA engine */
	rx_index = (rx_index + 1) % RX_BUF_COUNT;
	writel(rx_index, &regs->rxconsumeindex);

	/* reception successful */
	return 0;
}

static int lpc32xx_eth_write_hwaddr(struct eth_device *dev)
{
	struct lpc32xx_eth_device *lpc32xx_eth_device =
		container_of(dev, struct lpc32xx_eth_device, dev);
	struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;

	/* Save station address */
	writel((unsigned long) (dev->enetaddr[0] |
		(dev->enetaddr[1] << 8)), &regs->sa2);
	writel((unsigned long) (dev->enetaddr[2] |
		(dev->enetaddr[3] << 8)), &regs->sa1);
	writel((unsigned long) (dev->enetaddr[4] |
		(dev->enetaddr[5] << 8)), &regs->sa0);

	return 0;
}

static int lpc32xx_eth_init(struct eth_device *dev)
{
	struct lpc32xx_eth_device *lpc32xx_eth_device =
		container_of(dev, struct lpc32xx_eth_device, dev);
	struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
	struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
	int index;

	/* Release SOFT reset to let MII talk to PHY */
	clrbits_le32(&regs->mac1, MAC1_SOFT_RESET);

	/* Configure Full/Half Duplex mode */
	if (miiphy_duplex(dev->name, CONFIG_PHY_ADDR) == FULL) {
		setbits_le32(&regs->mac2, MAC2_FULL_DUPLEX);
		setbits_le32(&regs->command, COMMAND_FULL_DUPLEX);
		writel(0x15, &regs->ipgt);
	} else {
		writel(0x12, &regs->ipgt);
	}

	/* Configure 100MBit/10MBit mode */
	if (miiphy_speed(dev->name, CONFIG_PHY_ADDR) == _100BASET)
		writel(SUPP_SPEED, &regs->supp);
	else
		writel(0, &regs->supp);

	/* Initial MAC initialization */
	writel(MAC1_PASS_ALL_RX_FRAMES, &regs->mac1);
	writel(MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE, &regs->mac2);
	writel(PKTSIZE_ALIGN, &regs->maxf);

	/* Retries: 15 (0xF). Collision window: 57 (0x37). */
	writel(0x370F, &regs->clrt);

	/* Set IP gap pt 2 to default 0x12 but pt 1 to non-default 0 */
	writel(0x0012, &regs->ipgr);

	/* pass runt (smaller than 64 bytes) frames */
	writel(COMMAND_PASSRUNTFRAME, &regs->command);

	/* Save station address */
	writel((unsigned long) (dev->enetaddr[0] |
		(dev->enetaddr[1] << 8)), &regs->sa2);
	writel((unsigned long) (dev->enetaddr[2] |
		(dev->enetaddr[3] << 8)), &regs->sa1);
	writel((unsigned long) (dev->enetaddr[4] |
		(dev->enetaddr[5] << 8)), &regs->sa0);

	/* set up transmit buffers */
	for (index = 0; index < TX_BUF_COUNT; index++) {
		bufs->tx_desc[index].control = 0;
		bufs->tx_stat[index].statusinfo = 0;
	}
	writel((u32)(&bufs->tx_desc), (u32 *)&regs->txdescriptor);
	writel((u32)(&bufs->tx_stat), &regs->txstatus);
	writel(TX_BUF_COUNT-1, &regs->txdescriptornumber);

	/* set up receive buffers */
	for (index = 0; index < RX_BUF_COUNT; index++) {
		bufs->rx_desc[index].packet =
			(u32) (bufs->rx_buf+index*PKTSIZE_ALIGN);
		bufs->rx_desc[index].control = PKTSIZE_ALIGN - 1;
		bufs->rx_stat[index].statusinfo = 0;
		bufs->rx_stat[index].statushashcrc = 0;
	}
	writel((u32)(&bufs->rx_desc), &regs->rxdescriptor);
	writel((u32)(&bufs->rx_stat), &regs->rxstatus);
	writel(RX_BUF_COUNT-1, &regs->rxdescriptornumber);

	/* Enable broadcast and matching address packets */
	writel(RXFILTERCTRL_ACCEPTBROADCAST |
		RXFILTERCTRL_ACCEPTPERFECT, &regs->rxfilterctrl);

	/* Clear and disable interrupts */
	writel(0xFFFF, &regs->intclear);
	writel(0, &regs->intenable);

	/* Enable receive and transmit mode of MAC ethernet core */
	setbits_le32(&regs->command, COMMAND_RXENABLE | COMMAND_TXENABLE);
	setbits_le32(&regs->mac1, MAC1_RECV_ENABLE);

	/*
	 * Perform a 'dummy' first send to work around Ethernet.1
	 * erratum (see ES_LPC3250 rev. 9 dated 1 June 2011).
	 * Use zeroed "index" variable as the dummy.
	 */

	index = 0;
	lpc32xx_eth_send(dev, &index, 4);

	return 0;
}

static int lpc32xx_eth_halt(struct eth_device *dev)
{
	struct lpc32xx_eth_device *lpc32xx_eth_device =
		container_of(dev, struct lpc32xx_eth_device, dev);
	struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;

	/* Reset all MAC logic */
	writel(MAC1_RESETS, &regs->mac1);
	writel(COMMAND_RESETS, &regs->command);
	/* Let reset condition settle */
	udelay(2000);

	return 0;
}

#if defined(CONFIG_PHYLIB)
int lpc32xx_eth_phylib_init(struct eth_device *dev, int phyid)
{
	struct mii_dev *bus;
	struct phy_device *phydev;
	int ret;

	bus = mdio_alloc();
	if (!bus) {
		printf("mdio_alloc failed\n");
		return -ENOMEM;
	}
	bus->read = lpc32xx_eth_phy_read;
	bus->write = lpc32xx_eth_phy_write;
	sprintf(bus->name, dev->name);

	ret = mdio_register(bus);
	if (ret) {
		printf("mdio_register failed\n");
		free(bus);
		return -ENOMEM;
	}

	phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_MII);
	if (!phydev) {
		printf("phy_connect failed\n");
		return -ENODEV;
	}

	phy_config(phydev);
	phy_startup(phydev);

	return 0;
}
#endif

int lpc32xx_eth_initialize(bd_t *bis)
{
	struct eth_device *dev = &lpc32xx_eth.dev;
	struct lpc32xx_eth_registers *regs = lpc32xx_eth.regs;

	/*
	 * Set RMII management clock rate. With HCLK at 104 MHz and
	 * a divider of 28, this will be 3.72 MHz.
	 */

	writel(MCFG_CLOCK_SELECT_DIV28, &regs->mcfg);

	/* Reset all MAC logic */
	writel(MAC1_RESETS, &regs->mac1);
	writel(COMMAND_RESETS, &regs->command);

	/* wait 10 ms for the whole I/F to reset */
	udelay(10000);

	/* must be less than sizeof(dev->name) */
	strcpy(dev->name, "eth0");

	dev->init = (void *)lpc32xx_eth_init;
	dev->halt = (void *)lpc32xx_eth_halt;
	dev->send = (void *)lpc32xx_eth_send;
	dev->recv = (void *)lpc32xx_eth_recv;
	dev->write_hwaddr = (void *)lpc32xx_eth_write_hwaddr;

	/* Release SOFT reset to let MII talk to PHY */
	clrbits_le32(&regs->mac1, MAC1_SOFT_RESET);

	/* register driver before talking to phy */
	eth_register(dev);

#if defined(CONFIG_PHYLIB)
	lpc32xx_eth_phylib_init(dev, 0);
#elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
	miiphy_register(dev->name, mii_reg_read, mii_reg_write);
#endif

	return 0;
}
Commit	Line	Data
ac2916a2 AA	1	/*
	2	* LPC32xx Ethernet MAC interface driver
	3	*
	4	* (C) Copyright 2014 DENX Software Engineering GmbH
	5	* Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr>
	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9
	10	#include <common.h>
	11	#include <net.h>
	12	#include <malloc.h>
	13	#include <miiphy.h>
	14	#include <asm/io.h>
	15	#include <asm/errno.h>
	16	#include <asm/types.h>
	17	#include <asm/system.h>
	18	#include <asm/byteorder.h>
	19	#include <asm/arch/cpu.h>
	20	#include <asm/arch/config.h>
	21
	22	/*
	23	* Notes:
	24	*
	25	* 1. Unless specified otherwise, all references to tables or paragraphs
	26	* are to UM10326, "LPC32x0 and LPC32x0/01 User manual".
	27	*
	28	* 2. Only bitfield masks/values which are actually used by the driver
	29	* are defined.
	30	*/
	31
	32	/* a single RX descriptor. The controller has an array of these */
	33	struct lpc32xx_eth_rxdesc {
	34	u32 packet; /* Receive packet pointer */
	35	u32 control; /* Descriptor command status */
	36	};
	37
	38	#define LPC32XX_ETH_RX_DESC_SIZE (sizeof(struct lpc32xx_eth_rxdesc))
	39
	40	/* RX control bitfields/masks (see Table 330) */
	41	#define LPC32XX_ETH_RX_CTRL_SIZE_MASK 0x000007FF
	42	#define LPC32XX_ETH_RX_CTRL_UNUSED 0x7FFFF800
	43	#define LPC32XX_ETH_RX_CTRL_INTERRUPT 0x80000000
	44
	45	/* a single RX status. The controller has an array of these */
	46	struct lpc32xx_eth_rxstat {
	47	u32 statusinfo; /* Transmit Descriptor status */
	48	u32 statushashcrc; /* Transmit Descriptor CRCs */
	49	};
	50
	51	#define LPC32XX_ETH_RX_STAT_SIZE (sizeof(struct lpc32xx_eth_rxstat))
	52
	53	/* RX statusinfo bitfields/masks (see Table 333) */
	54	#define RX_STAT_RXSIZE 0x000007FF
	55	/* Helper: OR of all errors except RANGE */
	56	#define RX_STAT_ERRORS 0x1B800000
	57
	58	/* a single TX descriptor. The controller has an array of these */
	59	struct lpc32xx_eth_txdesc {
	60	u32 packet; /* Transmit packet pointer */
	61	u32 control; /* Descriptor control */
	62	};
	63
	64	#define LPC32XX_ETH_TX_DESC_SIZE (sizeof(struct lpc32xx_eth_txdesc))
65
66	/* TX control bitfields/masks (see Table 335) */
67	#define TX_CTRL_TXSIZE 0x000007FF
68	#define TX_CTRL_LAST 0x40000000
69
70	/* a single TX status. The controller has an array of these */
71	struct lpc32xx_eth_txstat {
72	u32 statusinfo; /* Transmit Descriptor status */
73	};
74
75	#define LPC32XX_ETH_TX_STAT_SIZE (sizeof(struct lpc32xx_eth_txstat))
76
77	/* Ethernet MAC interface registers (see Table 283) */
78	struct lpc32xx_eth_registers {
79	/* MAC registers - 0x3106_0000 to 0x3106_01FC */
80	u32 mac1; /* MAC configuration register 1 */
81	u32 mac2; /* MAC configuration register 2 */
82	u32 ipgt; /* Back-to-back Inter-Packet Gap reg. */
83	u32 ipgr; /* Non-back-to-back IPG register */
84	u32 clrt; /* Collision Window / Retry register */
85	u32 maxf; /* Maximum Frame register */
86	u32 supp; /* Phy Support register */
87	u32 test;
88	u32 mcfg; /* MII management configuration reg. */
89	u32 mcmd; /* MII management command register */
90	u32 madr; /* MII management address register */
91	u32 mwtd; /* MII management wite data register */
92	u32 mrdd; /* MII management read data register */
93	u32 mind; /* MII management indicators register */
94	u32 reserved1[2];
95	u32 sa0; /* Station address register 0 */
96	u32 sa1; /* Station address register 1 */
97	u32 sa2; /* Station address register 2 */
98	u32 reserved2[45];
99	/* Control registers */
100	u32 command;
101	u32 status;
102	u32 rxdescriptor;
103	u32 rxstatus;
104	u32 rxdescriptornumber; /* actually, number MINUS ONE */
105	u32 rxproduceindex; /* head of rx desc fifo */
106	u32 rxconsumeindex; /* tail of rx desc fifo */
107	u32 txdescriptor;
108	u32 txstatus;
109	u32 txdescriptornumber; /* actually, number MINUS ONE */
110	u32 txproduceindex; /* head of rx desc fifo */
111	u32 txconsumeindex; /* tail of rx desc fifo */
112	u32 reserved3[10];
113	u32 tsv0; /* Transmit status vector register 0 */
114	u32 tsv1; /* Transmit status vector register 1 */
115	u32 rsv; /* Receive status vector register */
116	u32 reserved4[3];
117	u32 flowcontrolcounter;
118	u32 flowcontrolstatus;
119	u32 reserved5[34];
120	/* RX filter registers - 0x3106_0200 to 0x3106_0FDC */
121	u32 rxfilterctrl;
122	u32 rxfilterwolstatus;
123	u32 rxfilterwolclear;
124	u32 reserved6;
125	u32 hashfilterl;
126	u32 hashfilterh;
127	u32 reserved7[882];
128	/* Module control registers - 0x3106_0FE0 to 0x3106_0FF8 */
129	u32 intstatus; /* Interrupt status register */
130	u32 intenable;
131	u32 intclear;
132	u32 intset;
133	u32 reserved8;
134	u32 powerdown;
135	u32 reserved9;
136	};
137
138	/* MAC1 register bitfields/masks and offsets (see Table 283) */
139	#define MAC1_RECV_ENABLE 0x00000001
140	#define MAC1_PASS_ALL_RX_FRAMES 0x00000002
141	#define MAC1_SOFT_RESET 0x00008000
142	/* Helper: general reset */
143	#define MAC1_RESETS 0x0000CF00
144
145	/* MAC2 register bitfields/masks and offsets (see Table 284) */
146	#define MAC2_FULL_DUPLEX 0x00000001
147	#define MAC2_CRC_ENABLE 0x00000010
148	#define MAC2_PAD_CRC_ENABLE 0x00000020
149
150	/* SUPP register bitfields/masks and offsets (see Table 290) */
151	#define SUPP_SPEED 0x00000100
152
153	/* MCFG register bitfields/masks and offsets (see Table 292) */
154	#define MCFG_CLOCK_SELECT_MASK 0x0000001C
155	/* divide clock by 28 (see Table 293) */
156	#define MCFG_CLOCK_SELECT_DIV28 0x0000001C
157
158	/* MADR register bitfields/masks and offsets (see Table 295) */
159	#define MADR_REG_MASK 0x0000001F
160	#define MADR_PHY_MASK 0x00001F00
161	#define MADR_REG_OFFSET 0
162	#define MADR_PHY_OFFSET 8
163
164	/* MIND register bitfields/masks (see Table 298) */
165	#define MIND_BUSY 0x00000001
166
167	/* COMMAND register bitfields/masks and offsets (see Table 283) */
168	#define COMMAND_RXENABLE 0x00000001
169	#define COMMAND_TXENABLE 0x00000002
170	#define COMMAND_PASSRUNTFRAME 0x00000040
171	#define COMMAND_FULL_DUPLEX 0x00000400
172	/* Helper: general reset */
6e039b4c	173	#define COMMAND_RESETS 0x00000038
ac2916a2 AA	174
	175	/* STATUS register bitfields/masks and offsets (see Table 283) */
	176	#define STATUS_RXSTATUS 0x00000001
	177	#define STATUS_TXSTATUS 0x00000002
	178
	179	/* RXFILTERCTRL register bitfields/masks (see Table 319) */
	180	#define RXFILTERCTRL_ACCEPTBROADCAST 0x00000002
	181	#define RXFILTERCTRL_ACCEPTPERFECT 0x00000020
	182
	183	/* Buffers and descriptors */
	184
	185	#define ATTRS(n) __aligned(n)
	186
	187	#define TX_BUF_COUNT 4
	188	#define RX_BUF_COUNT 4
	189
	190	struct lpc32xx_eth_buffers {
	191	ATTRS(4) struct lpc32xx_eth_txdesc tx_desc[TX_BUF_COUNT];
	192	ATTRS(4) struct lpc32xx_eth_txstat tx_stat[TX_BUF_COUNT];
	193	ATTRS(PKTALIGN) u8 tx_buf[TX_BUF_COUNT*PKTSIZE_ALIGN];
	194	ATTRS(4) struct lpc32xx_eth_rxdesc rx_desc[RX_BUF_COUNT];
	195	ATTRS(8) struct lpc32xx_eth_rxstat rx_stat[RX_BUF_COUNT];
	196	ATTRS(PKTALIGN) u8 rx_buf[RX_BUF_COUNT*PKTSIZE_ALIGN];
	197	};
	198
	199	/* port device data struct */
	200	struct lpc32xx_eth_device {
	201	struct eth_device dev;
	202	struct lpc32xx_eth_registers *regs;
	203	struct lpc32xx_eth_buffers *bufs;
	204	};
	205
	206	#define LPC32XX_ETH_DEVICE_SIZE (sizeof(struct lpc32xx_eth_device))
	207
	208	/* generic macros */
	209	#define to_lpc32xx_eth(_d) container_of(_d, struct lpc32xx_eth_device, dev)
	210
	211	/* timeout for MII polling */
	212	#define MII_TIMEOUT 10000000
	213
	214	/* limits for PHY and register addresses */
	215	#define MII_MAX_REG (MADR_REG_MASK >> MADR_REG_OFFSET)
	216
	217	#define MII_MAX_PHY (MADR_PHY_MASK >> MADR_PHY_OFFSET)
	218
	219	DECLARE_GLOBAL_DATA_PTR;
	220
	221	#if defined(CONFIG_PHYLIB) \|\| defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII)
	222	/*
	223	* mii_reg_read - miiphy_read callback function.
	224	*
	225	* Returns 16bit phy register value, or 0xffff on error
	226	*/
	227	static int mii_reg_read(const char devname, u8 phy_adr, u8 reg_ofs, u16 data)
	228	{
	229	struct eth_device *dev = eth_get_dev_by_name(devname);
	230	struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev);
	231	struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs;
	232	u32 mind_reg;
	233	u32 timeout;
	234
	235	/* check parameters */
	236	if (phy_adr > MII_MAX_PHY) {
	237	printf("%s:%u: Invalid PHY address %d\n",
238	__func__, __LINE__, phy_adr);
239	return -EFAULT;
240	}
241	if (reg_ofs > MII_MAX_REG) {
242	printf("%s:%u: Invalid register offset %d\n",
243	__func__, __LINE__, reg_ofs);
244	return -EFAULT;
245	}
246
247	/* write the phy and reg addressse into the MII address reg */
248	writel((phy_adr << MADR_PHY_OFFSET) \| (reg_ofs << MADR_REG_OFFSET),
249	&regs->madr);
250
251	/* write 1 to the MII command register to cause a read */
252	writel(1, &regs->mcmd);
253
254	/* wait till the MII is not busy */
255	timeout = MII_TIMEOUT;
256	do {
257	/* read MII indicators register */
258	mind_reg = readl(&regs->mind);
259	if (--timeout == 0)
260	break;
261	} while (mind_reg & MIND_BUSY);
262
263	/* write 0 to the MII command register to finish the read */
264	writel(0, &regs->mcmd);
265
266	if (timeout == 0) {
267	printf("%s:%u: MII busy timeout\n", __func__, __LINE__);
268	return -EFAULT;
269	}
270
271	*data = (u16) readl(&regs->mrdd);
272
273	debug("%s:(adr %d, off %d) => %04x\n", __func__, phy_adr,
274	reg_ofs, *data);
275
276	return 0;
277	}
278
279	/*
280	* mii_reg_write - imiiphy_write callback function.
281	*
282	* Returns 0 if write succeed, -EINVAL on bad parameters
283	* -ETIME on timeout
284	*/
285	static int mii_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
286	{
287	struct eth_device *dev = eth_get_dev_by_name(devname);
288	struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev);
289	struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs;
290	u32 mind_reg;
291	u32 timeout;
292
293	/* check parameters */
294	if (phy_adr > MII_MAX_PHY) {
295	printf("%s:%u: Invalid PHY address %d\n",
296	__func__, __LINE__, phy_adr);
297	return -EFAULT;
298	}
299	if (reg_ofs > MII_MAX_REG) {
300	printf("%s:%u: Invalid register offset %d\n",
301	__func__, __LINE__, reg_ofs);
302	return -EFAULT;
303	}
304
305	/* wait till the MII is not busy */
306	timeout = MII_TIMEOUT;
307	do {
308	/* read MII indicators register */
309	mind_reg = readl(&regs->mind);
310	if (--timeout == 0)
311	break;
312	} while (mind_reg & MIND_BUSY);
313
314	if (timeout == 0) {
315	printf("%s:%u: MII busy timeout\n", __func__,
316	__LINE__);
317	return -EFAULT;
318	}
319
320	/* write the phy and reg addressse into the MII address reg */
321	writel((phy_adr << MADR_PHY_OFFSET) \| (reg_ofs << MADR_REG_OFFSET),
322	&regs->madr);
323
324	/* write data to the MII write register */
325	writel(data, &regs->mwtd);
326
327	/*debug("%s:(adr %d, off %d) <= %04x\n", __func__, phy_adr,
328	reg_ofs, data);*/
329
330	return 0;
331	}
332	#endif
333
334	#if defined(CONFIG_PHYLIB)
335	int lpc32xx_eth_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr,
336	int reg_addr)
337	{
338	u16 data;
339	int ret;
340	ret = mii_reg_read(bus->name, phy_addr, reg_addr, &data);
341	if (ret)
342	return ret;
343	return data;
344	}
345
346	int lpc32xx_eth_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr,
347	int reg_addr, u16 data)
348	{
349	return mii_reg_write(bus->name, phy_addr, reg_addr, data);
350	}
351	#endif
352
353	/*
354	* Locate buffers in SRAM at 0x00001000 to avoid cache issues and
355	* maximize throughput.
356	*/
357
358	#define LPC32XX_ETH_BUFS 0x00001000
359
360	static struct lpc32xx_eth_device lpc32xx_eth = {
361	.regs = (struct lpc32xx_eth_registers *)LPC32XX_ETH_BASE,
362	.bufs = (struct lpc32xx_eth_buffers *)LPC32XX_ETH_BUFS
363	};
364
365	#define TX_TIMEOUT 10000
366
367	static int lpc32xx_eth_send(struct eth_device dev, void dataptr, int datasize)
368	{
369	struct lpc32xx_eth_device *lpc32xx_eth_device =
370	container_of(dev, struct lpc32xx_eth_device, dev);
371	struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
372	struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
373	int timeout, tx_index;
374
375	/* time out if transmit descriptor array remains full too long */
376	timeout = TX_TIMEOUT;
377	while ((readl(&regs->status) & STATUS_TXSTATUS) &&
378	(readl(&regs->txconsumeindex)
379	== readl(&regs->txproduceindex))) {
380	if (timeout-- == 0)
381	return -1;
382	}
383
384	/* determine next transmit packet index to use */
385	tx_index = readl(&regs->txproduceindex);
386
387	/* set up transmit packet */
388	writel((u32)dataptr, &bufs->tx_desc[tx_index].packet);
389	writel(TX_CTRL_LAST \| ((datasize - 1) & TX_CTRL_TXSIZE),
390	&bufs->tx_desc[tx_index].control);
391	writel(0, &bufs->tx_stat[tx_index].statusinfo);
392
393	/* pass transmit packet to DMA engine */
394	tx_index = (tx_index + 1) % TX_BUF_COUNT;
395	writel(tx_index, &regs->txproduceindex);
396
397	/* transmission succeeded */
398	return 0;
399	}
400
401	#define RX_TIMEOUT 1000000
402
403	static int lpc32xx_eth_recv(struct eth_device *dev)
404	{
405	struct lpc32xx_eth_device *lpc32xx_eth_device =
406	container_of(dev, struct lpc32xx_eth_device, dev);
407	struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
408	struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
409	int timeout, rx_index;
410
411	/* time out if receive descriptor array remains empty too long */
412	timeout = RX_TIMEOUT;
413	while (readl(&regs->rxproduceindex) == readl(&regs->rxconsumeindex)) {
414	if (timeout-- == 0)
415	return -1;
416	}
417
418	/* determine next receive packet index to use */
419	rx_index = readl(&regs->rxconsumeindex);
420
421	/* if data was valid, pass it on */
1fd92db8 JH	422	if (!(bufs->rx_stat[rx_index].statusinfo & RX_STAT_ERRORS)) {
	423	net_process_received_packet(
	424	&(bufs->rx_buf[rx_index * PKTSIZE_ALIGN]),
	425	(bufs->rx_stat[rx_index].statusinfo
	426	& RX_STAT_RXSIZE) + 1);
	427	}
ac2916a2 AA	428
	429	/* pass receive slot back to DMA engine */
	430	rx_index = (rx_index + 1) % RX_BUF_COUNT;
	431	writel(rx_index, &regs->rxconsumeindex);
	432
	433	/* reception successful */
	434	return 0;
	435	}
	436
	437	static int lpc32xx_eth_write_hwaddr(struct eth_device *dev)
	438	{
	439	struct lpc32xx_eth_device *lpc32xx_eth_device =
	440	container_of(dev, struct lpc32xx_eth_device, dev);
	441	struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
	442
	443	/* Save station address */
	444	writel((unsigned long) (dev->enetaddr[0] \|
	445	(dev->enetaddr[1] << 8)), &regs->sa2);
	446	writel((unsigned long) (dev->enetaddr[2] \|
	447	(dev->enetaddr[3] << 8)), &regs->sa1);
	448	writel((unsigned long) (dev->enetaddr[4] \|
	449	(dev->enetaddr[5] << 8)), &regs->sa0);
	450
	451	return 0;
	452	}
	453
	454	static int lpc32xx_eth_init(struct eth_device *dev)
	455	{
	456	struct lpc32xx_eth_device *lpc32xx_eth_device =
	457	container_of(dev, struct lpc32xx_eth_device, dev);
	458	struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
	459	struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
	460	int index;
	461
	462	/* Release SOFT reset to let MII talk to PHY */
	463	clrbits_le32(&regs->mac1, MAC1_SOFT_RESET);
	464
	465	/* Configure Full/Half Duplex mode */
	466	if (miiphy_duplex(dev->name, CONFIG_PHY_ADDR) == FULL) {
	467	setbits_le32(&regs->mac2, MAC2_FULL_DUPLEX);
	468	setbits_le32(&regs->command, COMMAND_FULL_DUPLEX);
	469	writel(0x15, &regs->ipgt);
	470	} else {
	471	writel(0x12, &regs->ipgt);
	472	}
	473
	474	/* Configure 100MBit/10MBit mode */
	475	if (miiphy_speed(dev->name, CONFIG_PHY_ADDR) == _100BASET)
	476	writel(SUPP_SPEED, &regs->supp);
	477	else
	478	writel(0, &regs->supp);
	479
	480	/* Initial MAC initialization */
	481	writel(MAC1_PASS_ALL_RX_FRAMES, &regs->mac1);
	482	writel(MAC2_PAD_CRC_ENABLE \| MAC2_CRC_ENABLE, &regs->mac2);
	483	writel(PKTSIZE_ALIGN, &regs->maxf);
	484
	485	/* Retries: 15 (0xF). Collision window: 57 (0x37). */
	486	writel(0x370F, &regs->clrt);
	487
	488	/* Set IP gap pt 2 to default 0x12 but pt 1 to non-default 0 */
	489	writel(0x0012, &regs->ipgr);
	490
	491	/* pass runt (smaller than 64 bytes) frames */
492	writel(COMMAND_PASSRUNTFRAME, &regs->command);
493
494	/* Save station address */
495	writel((unsigned long) (dev->enetaddr[0] \|
496	(dev->enetaddr[1] << 8)), &regs->sa2);
497	writel((unsigned long) (dev->enetaddr[2] \|
498	(dev->enetaddr[3] << 8)), &regs->sa1);
499	writel((unsigned long) (dev->enetaddr[4] \|
500	(dev->enetaddr[5] << 8)), &regs->sa0);
501
502	/* set up transmit buffers */
503	for (index = 0; index < TX_BUF_COUNT; index++) {
504	bufs->tx_desc[index].control = 0;
505	bufs->tx_stat[index].statusinfo = 0;
506	}
507	writel((u32)(&bufs->tx_desc), (u32 *)&regs->txdescriptor);
508	writel((u32)(&bufs->tx_stat), &regs->txstatus);
509	writel(TX_BUF_COUNT-1, &regs->txdescriptornumber);
510
511	/* set up receive buffers */
512	for (index = 0; index < RX_BUF_COUNT; index++) {
513	bufs->rx_desc[index].packet =
514	(u32) (bufs->rx_buf+index*PKTSIZE_ALIGN);
515	bufs->rx_desc[index].control = PKTSIZE_ALIGN - 1;
516	bufs->rx_stat[index].statusinfo = 0;
517	bufs->rx_stat[index].statushashcrc = 0;
518	}
519	writel((u32)(&bufs->rx_desc), &regs->rxdescriptor);
520	writel((u32)(&bufs->rx_stat), &regs->rxstatus);
521	writel(RX_BUF_COUNT-1, &regs->rxdescriptornumber);
522
523	/* Enable broadcast and matching address packets */
524	writel(RXFILTERCTRL_ACCEPTBROADCAST \|
525	RXFILTERCTRL_ACCEPTPERFECT, &regs->rxfilterctrl);
526
527	/* Clear and disable interrupts */
528	writel(0xFFFF, &regs->intclear);
529	writel(0, &regs->intenable);
530
531	/* Enable receive and transmit mode of MAC ethernet core */
532	setbits_le32(&regs->command, COMMAND_RXENABLE \| COMMAND_TXENABLE);
533	setbits_le32(&regs->mac1, MAC1_RECV_ENABLE);
534
535	/*
536	* Perform a 'dummy' first send to work around Ethernet.1
537	* erratum (see ES_LPC3250 rev. 9 dated 1 June 2011).
538	* Use zeroed "index" variable as the dummy.
539	*/
540
541	index = 0;
542	lpc32xx_eth_send(dev, &index, 4);
543
544	return 0;
545	}
546
547	static int lpc32xx_eth_halt(struct eth_device *dev)
548	{
549	struct lpc32xx_eth_device *lpc32xx_eth_device =
550	container_of(dev, struct lpc32xx_eth_device, dev);
551	struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
552
553	/* Reset all MAC logic */
554	writel(MAC1_RESETS, &regs->mac1);
555	writel(COMMAND_RESETS, &regs->command);
556	/* Let reset condition settle */
557	udelay(2000);
558
559	return 0;
560	}
561
562	#if defined(CONFIG_PHYLIB)
563	int lpc32xx_eth_phylib_init(struct eth_device *dev, int phyid)
564	{
565	struct mii_dev *bus;
566	struct phy_device *phydev;
567	int ret;
568
569	bus = mdio_alloc();
570	if (!bus) {
571	printf("mdio_alloc failed\n");
572	return -ENOMEM;
573	}
574	bus->read = lpc32xx_eth_phy_read;
575	bus->write = lpc32xx_eth_phy_write;
576	sprintf(bus->name, dev->name);
577
578	ret = mdio_register(bus);
579	if (ret) {
580	printf("mdio_register failed\n");
581	free(bus);
582	return -ENOMEM;
583	}
584
585	phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_MII);
586	if (!phydev) {
587	printf("phy_connect failed\n");
588	return -ENODEV;
589	}
590
591	phy_config(phydev);
592	phy_startup(phydev);
593
594	return 0;
595	}
596	#endif
597
598	int lpc32xx_eth_initialize(bd_t *bis)
599	{
600	struct eth_device *dev = &lpc32xx_eth.dev;
601	struct lpc32xx_eth_registers *regs = lpc32xx_eth.regs;
602
603	/*
604	* Set RMII management clock rate. With HCLK at 104 MHz and
605	* a divider of 28, this will be 3.72 MHz.
606	*/
607
608	writel(MCFG_CLOCK_SELECT_DIV28, &regs->mcfg);
609
610	/* Reset all MAC logic */
611	writel(MAC1_RESETS, &regs->mac1);
612	writel(COMMAND_RESETS, &regs->command);
613
614	/* wait 10 ms for the whole I/F to reset */
615	udelay(10000);
616
617	/* must be less than sizeof(dev->name) */
618	strcpy(dev->name, "eth0");
619
620	dev->init = (void *)lpc32xx_eth_init;
621	dev->halt = (void *)lpc32xx_eth_halt;
622	dev->send = (void *)lpc32xx_eth_send;
623	dev->recv = (void *)lpc32xx_eth_recv;
624	dev->write_hwaddr = (void *)lpc32xx_eth_write_hwaddr;
625
626	/* Release SOFT reset to let MII talk to PHY */
627	clrbits_le32(&regs->mac1, MAC1_SOFT_RESET);
628
629	/* register driver before talking to phy */
630	eth_register(dev);
631
632	#if defined(CONFIG_PHYLIB)
633	lpc32xx_eth_phylib_init(dev, 0);
634	#elif defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII)
635	miiphy_register(dev->name, mii_reg_read, mii_reg_write);
636	#endif
637
638	return 0;
639	}