[people/ms/u-boot.git] / drivers / net / mcffec.c

/*
 * (C) Copyright 2000-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2007 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <malloc.h>

#include <command.h>
#include <net.h>
#include <netdev.h>
#include <miiphy.h>

#include <asm/fec.h>
#include <asm/immap.h>

#undef	ET_DEBUG
#undef	MII_DEBUG

/* Ethernet Transmit and Receive Buffers */
#define DBUF_LENGTH		1520
#define TX_BUF_CNT		2
#define PKT_MAXBUF_SIZE		1518
#define PKT_MINBUF_SIZE		64
#define PKT_MAXBLR_SIZE		1520
#define LAST_PKTBUFSRX		PKTBUFSRX - 1
#define BD_ENET_RX_W_E		(BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
#define BD_ENET_TX_RDY_LST	(BD_ENET_TX_READY | BD_ENET_TX_LAST)

DECLARE_GLOBAL_DATA_PTR;

struct fec_info_s fec_info[] = {
#ifdef CONFIG_SYS_FEC0_IOBASE
	{
	 0,			/* index */
	 CONFIG_SYS_FEC0_IOBASE,	/* io base */
	 CONFIG_SYS_FEC0_PINMUX,	/* gpio pin muxing */
	 CONFIG_SYS_FEC0_MIIBASE,	/* mii base */
	 -1,			/* phy_addr */
	 0,			/* duplex and speed */
	 0,			/* phy name */
	 0,			/* phyname init */
	 0,			/* RX BD */
	 0,			/* TX BD */
	 0,			/* rx Index */
	 0,			/* tx Index */
	 0,			/* tx buffer */
	 0,			/* initialized flag */
	 (struct fec_info_s *)-1,
	 },
#endif
#ifdef CONFIG_SYS_FEC1_IOBASE
	{
	 1,			/* index */
	 CONFIG_SYS_FEC1_IOBASE,	/* io base */
	 CONFIG_SYS_FEC1_PINMUX,	/* gpio pin muxing */
	 CONFIG_SYS_FEC1_MIIBASE,	/* mii base */
	 -1,			/* phy_addr */
	 0,			/* duplex and speed */
	 0,			/* phy name */
	 0,			/* phy name init */
#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
	 (cbd_t *)DBUF_LENGTH,	/* RX BD */
#else
	 0,			/* RX BD */
#endif
	 0,			/* TX BD */
	 0,			/* rx Index */
	 0,			/* tx Index */
	 0,			/* tx buffer */
	 0,			/* initialized flag */
	 (struct fec_info_s *)-1,
	 }
#endif
};

int fec_recv(struct eth_device *dev);
int fec_init(struct eth_device *dev, bd_t * bd);
void fec_halt(struct eth_device *dev);
void fec_reset(struct eth_device *dev);

void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd)
{
	if ((dup_spd >> 16) == FULL) {
		/* Set maximum frame length */
		fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
		    FEC_RCR_PROM | 0x100;
		fecp->tcr = FEC_TCR_FDEN;
	} else {
		/* Half duplex mode */
		fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
		    FEC_RCR_MII_MODE | FEC_RCR_DRT;
		fecp->tcr &= ~FEC_TCR_FDEN;
	}

	if ((dup_spd & 0xFFFF) == _100BASET) {
#ifdef CONFIG_MCF5445x
		fecp->rcr &= ~0x200;	/* disabled 10T base */
#endif
#ifdef MII_DEBUG
		printf("100Mbps\n");
#endif
		bd->bi_ethspeed = 100;
	} else {
#ifdef CONFIG_MCF5445x
		fecp->rcr |= 0x200;	/* enabled 10T base */
#endif
#ifdef MII_DEBUG
		printf("10Mbps\n");
#endif
		bd->bi_ethspeed = 10;
	}
}

static int fec_send(struct eth_device *dev, void *packet, int length)
{
	struct fec_info_s *info = dev->priv;
	volatile fec_t *fecp = (fec_t *) (info->iobase);
	int j, rc;
	u16 phyStatus;

	miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus);

	/* section 16.9.23.3
	 * Wait for ready
	 */
	j = 0;
	while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
	       (j < MCFFEC_TOUT_LOOP)) {
		udelay(1);
		j++;
	}
	if (j >= MCFFEC_TOUT_LOOP) {
		printf("TX not ready\n");
	}

	info->txbd[info->txIdx].cbd_bufaddr = (uint) packet;
	info->txbd[info->txIdx].cbd_datlen = length;
	info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST;

	/* Activate transmit Buffer Descriptor polling */
	fecp->tdar = 0x01000000;	/* Descriptor polling active    */

#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM
	/*
	 * FEC unable to initial transmit data packet.
	 * A nop will ensure the descriptor polling active completed.
	 * CF Internal RAM has shorter cycle access than DRAM. If use
	 * DRAM as Buffer descriptor and data, a nop is a must.
	 * Affect only V2 and V3.
	 */
	__asm__ ("nop");

#endif

#ifdef CONFIG_SYS_UNIFY_CACHE
	icache_invalid();
#endif

	j = 0;
	while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
	       (j < MCFFEC_TOUT_LOOP)) {
		udelay(1);
		j++;
	}
	if (j >= MCFFEC_TOUT_LOOP) {
		printf("TX timeout\n");
	}

#ifdef ET_DEBUG
	printf("%s[%d] %s: cycles: %d    status: %x  retry cnt: %d\n",
	       __FILE__, __LINE__, __FUNCTION__, j,
	       info->txbd[info->txIdx].cbd_sc,
	       (info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2);
#endif

	/* return only status bits */
	rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
	info->txIdx = (info->txIdx + 1) % TX_BUF_CNT;

	return rc;
}

int fec_recv(struct eth_device *dev)
{
	struct fec_info_s *info = dev->priv;
	volatile fec_t *fecp = (fec_t *) (info->iobase);
	int length;

	for (;;) {
#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM
#endif
#ifdef CONFIG_SYS_UNIFY_CACHE
		icache_invalid();
#endif
		/* section 16.9.23.2 */
		if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
			length = -1;
			break;	/* nothing received - leave for() loop */
		}

		length = info->rxbd[info->rxIdx].cbd_datlen;

		if (info->rxbd[info->rxIdx].cbd_sc & 0x003f) {
			printf("%s[%d] err: %x\n",
			       __FUNCTION__, __LINE__,
			       info->rxbd[info->rxIdx].cbd_sc);
#ifdef ET_DEBUG
			printf("%s[%d] err: %x\n",
			       __FUNCTION__, __LINE__,
			       info->rxbd[info->rxIdx].cbd_sc);
#endif
		} else {

			length -= 4;
			/* Pass the packet up to the protocol layers. */
			net_process_received_packet(net_rx_packets[info->rxIdx],
						    length);

			fecp->eir |= FEC_EIR_RXF;
		}

		/* Give the buffer back to the FEC. */
		info->rxbd[info->rxIdx].cbd_datlen = 0;

		/* wrap around buffer index when necessary */
		if (info->rxIdx == LAST_PKTBUFSRX) {
			info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E;
			info->rxIdx = 0;
		} else {
			info->rxbd[info->rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
			info->rxIdx++;
		}

		/* Try to fill Buffer Descriptors */
		fecp->rdar = 0x01000000;	/* Descriptor polling active    */
	}

	return length;
}

#ifdef ET_DEBUG
void dbgFecRegs(struct eth_device *dev)
{
	struct fec_info_s *info = dev->priv;
	volatile fec_t *fecp = (fec_t *) (info->iobase);

	printf("=====\n");
	printf("ievent       %x - %x\n", (int)&fecp->eir, fecp->eir);
	printf("imask        %x - %x\n", (int)&fecp->eimr, fecp->eimr);
	printf("r_des_active %x - %x\n", (int)&fecp->rdar, fecp->rdar);
	printf("x_des_active %x - %x\n", (int)&fecp->tdar, fecp->tdar);
	printf("ecntrl       %x - %x\n", (int)&fecp->ecr, fecp->ecr);
	printf("mii_mframe   %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
	printf("mii_speed    %x - %x\n", (int)&fecp->mscr, fecp->mscr);
	printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
	printf("r_cntrl      %x - %x\n", (int)&fecp->rcr, fecp->rcr);
	printf("x_cntrl      %x - %x\n", (int)&fecp->tcr, fecp->tcr);
	printf("padr_l       %x - %x\n", (int)&fecp->palr, fecp->palr);
	printf("padr_u       %x - %x\n", (int)&fecp->paur, fecp->paur);
	printf("op_pause     %x - %x\n", (int)&fecp->opd, fecp->opd);
	printf("iadr_u       %x - %x\n", (int)&fecp->iaur, fecp->iaur);
	printf("iadr_l       %x - %x\n", (int)&fecp->ialr, fecp->ialr);
	printf("gadr_u       %x - %x\n", (int)&fecp->gaur, fecp->gaur);
	printf("gadr_l       %x - %x\n", (int)&fecp->galr, fecp->galr);
	printf("x_wmrk       %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
	printf("r_bound      %x - %x\n", (int)&fecp->frbr, fecp->frbr);
	printf("r_fstart     %x - %x\n", (int)&fecp->frsr, fecp->frsr);
	printf("r_drng       %x - %x\n", (int)&fecp->erdsr, fecp->erdsr);
	printf("x_drng       %x - %x\n", (int)&fecp->etdsr, fecp->etdsr);
	printf("r_bufsz      %x - %x\n", (int)&fecp->emrbr, fecp->emrbr);

	printf("\n");
	printf("rmon_t_drop        %x - %x\n", (int)&fecp->rmon_t_drop,
	       fecp->rmon_t_drop);
	printf("rmon_t_packets     %x - %x\n", (int)&fecp->rmon_t_packets,
	       fecp->rmon_t_packets);
	printf("rmon_t_bc_pkt      %x - %x\n", (int)&fecp->rmon_t_bc_pkt,
	       fecp->rmon_t_bc_pkt);
	printf("rmon_t_mc_pkt      %x - %x\n", (int)&fecp->rmon_t_mc_pkt,
	       fecp->rmon_t_mc_pkt);
	printf("rmon_t_crc_align   %x - %x\n", (int)&fecp->rmon_t_crc_align,
	       fecp->rmon_t_crc_align);
	printf("rmon_t_undersize   %x - %x\n", (int)&fecp->rmon_t_undersize,
	       fecp->rmon_t_undersize);
	printf("rmon_t_oversize    %x - %x\n", (int)&fecp->rmon_t_oversize,
	       fecp->rmon_t_oversize);
	printf("rmon_t_frag        %x - %x\n", (int)&fecp->rmon_t_frag,
	       fecp->rmon_t_frag);
	printf("rmon_t_jab         %x - %x\n", (int)&fecp->rmon_t_jab,
	       fecp->rmon_t_jab);
	printf("rmon_t_col         %x - %x\n", (int)&fecp->rmon_t_col,
	       fecp->rmon_t_col);
	printf("rmon_t_p64         %x - %x\n", (int)&fecp->rmon_t_p64,
	       fecp->rmon_t_p64);
	printf("rmon_t_p65to127    %x - %x\n", (int)&fecp->rmon_t_p65to127,
	       fecp->rmon_t_p65to127);
	printf("rmon_t_p128to255   %x - %x\n", (int)&fecp->rmon_t_p128to255,
	       fecp->rmon_t_p128to255);
	printf("rmon_t_p256to511   %x - %x\n", (int)&fecp->rmon_t_p256to511,
	       fecp->rmon_t_p256to511);
	printf("rmon_t_p512to1023  %x - %x\n", (int)&fecp->rmon_t_p512to1023,
	       fecp->rmon_t_p512to1023);
	printf("rmon_t_p1024to2047 %x - %x\n", (int)&fecp->rmon_t_p1024to2047,
	       fecp->rmon_t_p1024to2047);
	printf("rmon_t_p_gte2048   %x - %x\n", (int)&fecp->rmon_t_p_gte2048,
	       fecp->rmon_t_p_gte2048);
	printf("rmon_t_octets      %x - %x\n", (int)&fecp->rmon_t_octets,
	       fecp->rmon_t_octets);

	printf("\n");
	printf("ieee_t_drop      %x - %x\n", (int)&fecp->ieee_t_drop,
	       fecp->ieee_t_drop);
	printf("ieee_t_frame_ok  %x - %x\n", (int)&fecp->ieee_t_frame_ok,
	       fecp->ieee_t_frame_ok);
	printf("ieee_t_1col      %x - %x\n", (int)&fecp->ieee_t_1col,
	       fecp->ieee_t_1col);
	printf("ieee_t_mcol      %x - %x\n", (int)&fecp->ieee_t_mcol,
	       fecp->ieee_t_mcol);
	printf("ieee_t_def       %x - %x\n", (int)&fecp->ieee_t_def,
	       fecp->ieee_t_def);
	printf("ieee_t_lcol      %x - %x\n", (int)&fecp->ieee_t_lcol,
	       fecp->ieee_t_lcol);
	printf("ieee_t_excol     %x - %x\n", (int)&fecp->ieee_t_excol,
	       fecp->ieee_t_excol);
	printf("ieee_t_macerr    %x - %x\n", (int)&fecp->ieee_t_macerr,
	       fecp->ieee_t_macerr);
	printf("ieee_t_cserr     %x - %x\n", (int)&fecp->ieee_t_cserr,
	       fecp->ieee_t_cserr);
	printf("ieee_t_sqe       %x - %x\n", (int)&fecp->ieee_t_sqe,
	       fecp->ieee_t_sqe);
	printf("ieee_t_fdxfc     %x - %x\n", (int)&fecp->ieee_t_fdxfc,
	       fecp->ieee_t_fdxfc);
	printf("ieee_t_octets_ok %x - %x\n", (int)&fecp->ieee_t_octets_ok,
	       fecp->ieee_t_octets_ok);

	printf("\n");
	printf("rmon_r_drop        %x - %x\n", (int)&fecp->rmon_r_drop,
	       fecp->rmon_r_drop);
	printf("rmon_r_packets     %x - %x\n", (int)&fecp->rmon_r_packets,
	       fecp->rmon_r_packets);
	printf("rmon_r_bc_pkt      %x - %x\n", (int)&fecp->rmon_r_bc_pkt,
	       fecp->rmon_r_bc_pkt);
	printf("rmon_r_mc_pkt      %x - %x\n", (int)&fecp->rmon_r_mc_pkt,
	       fecp->rmon_r_mc_pkt);
	printf("rmon_r_crc_align   %x - %x\n", (int)&fecp->rmon_r_crc_align,
	       fecp->rmon_r_crc_align);
	printf("rmon_r_undersize   %x - %x\n", (int)&fecp->rmon_r_undersize,
	       fecp->rmon_r_undersize);
	printf("rmon_r_oversize    %x - %x\n", (int)&fecp->rmon_r_oversize,
	       fecp->rmon_r_oversize);
	printf("rmon_r_frag        %x - %x\n", (int)&fecp->rmon_r_frag,
	       fecp->rmon_r_frag);
	printf("rmon_r_jab         %x - %x\n", (int)&fecp->rmon_r_jab,
	       fecp->rmon_r_jab);
	printf("rmon_r_p64         %x - %x\n", (int)&fecp->rmon_r_p64,
	       fecp->rmon_r_p64);
	printf("rmon_r_p65to127    %x - %x\n", (int)&fecp->rmon_r_p65to127,
	       fecp->rmon_r_p65to127);
	printf("rmon_r_p128to255   %x - %x\n", (int)&fecp->rmon_r_p128to255,
	       fecp->rmon_r_p128to255);
	printf("rmon_r_p256to511   %x - %x\n", (int)&fecp->rmon_r_p256to511,
	       fecp->rmon_r_p256to511);
	printf("rmon_r_p512to1023  %x - %x\n", (int)&fecp->rmon_r_p512to1023,
	       fecp->rmon_r_p512to1023);
	printf("rmon_r_p1024to2047 %x - %x\n", (int)&fecp->rmon_r_p1024to2047,
	       fecp->rmon_r_p1024to2047);
	printf("rmon_r_p_gte2048   %x - %x\n", (int)&fecp->rmon_r_p_gte2048,
	       fecp->rmon_r_p_gte2048);
	printf("rmon_r_octets      %x - %x\n", (int)&fecp->rmon_r_octets,
	       fecp->rmon_r_octets);

	printf("\n");
	printf("ieee_r_drop      %x - %x\n", (int)&fecp->ieee_r_drop,
	       fecp->ieee_r_drop);
	printf("ieee_r_frame_ok  %x - %x\n", (int)&fecp->ieee_r_frame_ok,
	       fecp->ieee_r_frame_ok);
	printf("ieee_r_crc       %x - %x\n", (int)&fecp->ieee_r_crc,
	       fecp->ieee_r_crc);
	printf("ieee_r_align     %x - %x\n", (int)&fecp->ieee_r_align,
	       fecp->ieee_r_align);
	printf("ieee_r_macerr    %x - %x\n", (int)&fecp->ieee_r_macerr,
	       fecp->ieee_r_macerr);
	printf("ieee_r_fdxfc     %x - %x\n", (int)&fecp->ieee_r_fdxfc,
	       fecp->ieee_r_fdxfc);
	printf("ieee_r_octets_ok %x - %x\n", (int)&fecp->ieee_r_octets_ok,
	       fecp->ieee_r_octets_ok);

	printf("\n\n\n");
}
#endif

int fec_init(struct eth_device *dev, bd_t * bd)
{
	struct fec_info_s *info = dev->priv;
	volatile fec_t *fecp = (fec_t *) (info->iobase);
	int i;
	uchar ea[6];

	fecpin_setclear(dev, 1);

	fec_reset(dev);

#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
	defined (CONFIG_SYS_DISCOVER_PHY)

	mii_init();

	setFecDuplexSpeed(fecp, bd, info->dup_spd);
#else
#ifndef CONFIG_SYS_DISCOVER_PHY
	setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
#endif				/* ifndef CONFIG_SYS_DISCOVER_PHY */
#endif				/* CONFIG_CMD_MII || CONFIG_MII */

	/* We use strictly polling mode only */
	fecp->eimr = 0;

	/* Clear any pending interrupt */
	fecp->eir = 0xffffffff;

	/* Set station address   */
	if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE) {
#ifdef CONFIG_SYS_FEC1_IOBASE
		volatile fec_t *fecp1 = (fec_t *) (CONFIG_SYS_FEC1_IOBASE);
		eth_getenv_enetaddr("eth1addr", ea);
		fecp1->palr =
		    (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
		fecp1->paur = (ea[4] << 24) | (ea[5] << 16);
#endif
		eth_getenv_enetaddr("ethaddr", ea);
		fecp->palr =
		    (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
		fecp->paur = (ea[4] << 24) | (ea[5] << 16);
	} else {
#ifdef CONFIG_SYS_FEC0_IOBASE
		volatile fec_t *fecp0 = (fec_t *) (CONFIG_SYS_FEC0_IOBASE);
		eth_getenv_enetaddr("ethaddr", ea);
		fecp0->palr =
		    (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
		fecp0->paur = (ea[4] << 24) | (ea[5] << 16);
#endif
#ifdef CONFIG_SYS_FEC1_IOBASE
		eth_getenv_enetaddr("eth1addr", ea);
		fecp->palr =
		    (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
		fecp->paur = (ea[4] << 24) | (ea[5] << 16);
#endif
	}

	/* Clear unicast address hash table */
	fecp->iaur = 0;
	fecp->ialr = 0;

	/* Clear multicast address hash table */
	fecp->gaur = 0;
	fecp->galr = 0;

	/* Set maximum receive buffer size. */
	fecp->emrbr = PKT_MAXBLR_SIZE;

	/*
	 * Setup Buffers and Buffer Desriptors
	 */
	info->rxIdx = 0;
	info->txIdx = 0;

	/*
	 * Setup Receiver Buffer Descriptors (13.14.24.18)
	 * Settings:
	 *     Empty, Wrap
	 */
	for (i = 0; i < PKTBUFSRX; i++) {
		info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
		info->rxbd[i].cbd_datlen = 0;	/* Reset */
		info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
	}
	info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;

	/*
	 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
	 * Settings:
	 *    Last, Tx CRC
	 */
	for (i = 0; i < TX_BUF_CNT; i++) {
		info->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
		info->txbd[i].cbd_datlen = 0;	/* Reset */
		info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
	}
	info->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;

	/* Set receive and transmit descriptor base */
	fecp->erdsr = (unsigned int)(&info->rxbd[0]);
	fecp->etdsr = (unsigned int)(&info->txbd[0]);

	/* Now enable the transmit and receive processing */
	fecp->ecr |= FEC_ECR_ETHER_EN;

	/* And last, try to fill Rx Buffer Descriptors */
	fecp->rdar = 0x01000000;	/* Descriptor polling active    */

	return 1;
}

void fec_reset(struct eth_device *dev)
{
	struct fec_info_s *info = dev->priv;
	volatile fec_t *fecp = (fec_t *) (info->iobase);
	int i;

	fecp->ecr = FEC_ECR_RESET;
	for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
		udelay(1);
	}
	if (i == FEC_RESET_DELAY) {
		printf("FEC_RESET_DELAY timeout\n");
	}
}

void fec_halt(struct eth_device *dev)
{
	struct fec_info_s *info = dev->priv;

	fec_reset(dev);

	fecpin_setclear(dev, 0);

	info->rxIdx = info->txIdx = 0;
	memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t));
	memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t));
	memset(info->txbuf, 0, DBUF_LENGTH);
}

int mcffec_initialize(bd_t * bis)
{
	struct eth_device *dev;
	int i;
#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
	u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
#endif

	for (i = 0; i < ARRAY_SIZE(fec_info); i++) {

		dev =
		    (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE,
						  sizeof *dev);
		if (dev == NULL)
			hang();

		memset(dev, 0, sizeof(*dev));

		sprintf(dev->name, "FEC%d", fec_info[i].index);

		dev->priv = &fec_info[i];
		dev->init = fec_init;
		dev->halt = fec_halt;
		dev->send = fec_send;
		dev->recv = fec_recv;

		/* setup Receive and Transmit buffer descriptor */
#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
		fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp);
		tmp = (u32)fec_info[i].rxbd;
		fec_info[i].txbd =
		    (cbd_t *)((u32)fec_info[i].txbd + tmp +
		    (PKTBUFSRX * sizeof(cbd_t)));
		tmp = (u32)fec_info[i].txbd;
		fec_info[i].txbuf =
		    (char *)((u32)fec_info[i].txbuf + tmp +
		    (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
		tmp = (u32)fec_info[i].txbuf;
#else
		fec_info[i].rxbd =
		    (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
				       (PKTBUFSRX * sizeof(cbd_t)));
		fec_info[i].txbd =
		    (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
				       (TX_BUF_CNT * sizeof(cbd_t)));
		fec_info[i].txbuf =
		    (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
#endif

#ifdef ET_DEBUG
		printf("rxbd %x txbd %x\n",
		       (int)fec_info[i].rxbd, (int)fec_info[i].txbd);
#endif

		fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);

		eth_register(dev);

#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
		int retval;
		struct mii_dev *mdiodev = mdio_alloc();
		if (!mdiodev)
			return -ENOMEM;
		strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
		mdiodev->read = mcffec_miiphy_read;
		mdiodev->write = mcffec_miiphy_write;

		retval = mdio_register(mdiodev);
		if (retval < 0)
			return retval;
#endif
		if (i > 0)
			fec_info[i - 1].next = &fec_info[i];
	}
	fec_info[i - 1].next = &fec_info[0];

	/* default speed */
	bis->bi_ethspeed = 10;

	return 0;
}
Commit	Line	Data
8e585f02 TL	1	/*
	2	* (C) Copyright 2000-2004
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
f2208fbc	5	* (C) Copyright 2007 Freescale Semiconductor, Inc.
8e585f02 TL	6	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8e585f02 TL	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
8e585f02 TL	9	*/
	10
	11	#include <common.h>
	12	#include <malloc.h>
	13
8e585f02	14	#include <command.h>
8e585f02	15	#include <net.h>
89973f8a	16	#include <netdev.h>
8e585f02 TL	17	#include <miiphy.h>
8e585f02 TL	18
54bdcc9f TL	19	#include <asm/fec.h>
	20	#include <asm/immap.h>
	21
8e585f02 TL	22	#undef ET_DEBUG
	23	#undef MII_DEBUG
	24
	25	/* Ethernet Transmit and Receive Buffers */
f2208fbc TL	26	#define DBUF_LENGTH 1520
f2208fbc TL	27	#define TX_BUF_CNT 2
8e585f02 TL	28	#define PKT_MAXBUF_SIZE 1518
	29	#define PKT_MINBUF_SIZE 64
	30	#define PKT_MAXBLR_SIZE 1520
	31	#define LAST_PKTBUFSRX PKTBUFSRX - 1
	32	#define BD_ENET_RX_W_E (BD_ENET_RX_WRAP \| BD_ENET_RX_EMPTY)
	33	#define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY \| BD_ENET_TX_LAST)
	34
	35	DECLARE_GLOBAL_DATA_PTR;
	36
8e585f02	37	struct fec_info_s fec_info[] = {
6d0f6bcf	38	#ifdef CONFIG_SYS_FEC0_IOBASE
8e585f02 TL	39	{
8e585f02 TL	40	0, /* index */
6d0f6bcf JCPV	41	CONFIG_SYS_FEC0_IOBASE, /* io base */
	42	CONFIG_SYS_FEC0_PINMUX, /* gpio pin muxing */
	43	CONFIG_SYS_FEC0_MIIBASE, /* mii base */
8e585f02 TL	44	-1, /* phy_addr */
	45	0, /* duplex and speed */
	46	0, /* phy name */
	47	0, /* phyname init */
	48	0, /* RX BD */
	49	0, /* TX BD */
	50	0, /* rx Index */
	51	0, /* tx Index */
	52	0, /* tx buffer */
	53	0, /* initialized flag */
1803f7f9	54	(struct fec_info_s *)-1,
8e585f02 TL	55	},
8e585f02 TL	56	#endif
6d0f6bcf	57	#ifdef CONFIG_SYS_FEC1_IOBASE
8e585f02 TL	58	{
8e585f02 TL	59	1, /* index */
6d0f6bcf JCPV	60	CONFIG_SYS_FEC1_IOBASE, /* io base */
	61	CONFIG_SYS_FEC1_PINMUX, /* gpio pin muxing */
	62	CONFIG_SYS_FEC1_MIIBASE, /* mii base */
8e585f02 TL	63	-1, /* phy_addr */
	64	0, /* duplex and speed */
	65	0, /* phy name */
	66	0, /* phy name init */
6d0f6bcf	67	#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
1803f7f9 TL	68	(cbd_t )DBUF_LENGTH, / RX BD */
1803f7f9 TL	69	#else
8e585f02	70	0, /* RX BD */
1803f7f9	71	#endif
8e585f02 TL	72	0, /* TX BD */
	73	0, /* rx Index */
	74	0, /* tx Index */
	75	0, /* tx buffer */
	76	0, /* initialized flag */
1803f7f9	77	(struct fec_info_s *)-1,
8e585f02 TL	78	}
	79	#endif
	80	};
	81
8e585f02 TL	82	int fec_recv(struct eth_device *dev);
	83	int fec_init(struct eth_device dev, bd_t bd);
	84	void fec_halt(struct eth_device *dev);
	85	void fec_reset(struct eth_device *dev);
	86
8e585f02 TL	87	void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd)
	88	{
	89	if ((dup_spd >> 16) == FULL) {
	90	/* Set maximum frame length */
	91	fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) \| FEC_RCR_MII_MODE \|
	92	FEC_RCR_PROM \| 0x100;
	93	fecp->tcr = FEC_TCR_FDEN;
	94	} else {
	95	/* Half duplex mode */
	96	fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) \|
	97	FEC_RCR_MII_MODE \| FEC_RCR_DRT;
	98	fecp->tcr &= ~FEC_TCR_FDEN;
	99	}
	100
	101	if ((dup_spd & 0xFFFF) == _100BASET) {
ff36fbb2 TL	102	#ifdef CONFIG_MCF5445x
	103	fecp->rcr &= ~0x200; /* disabled 10T base */
	104	#endif
8e585f02 TL	105	#ifdef MII_DEBUG
	106	printf("100Mbps\n");
	107	#endif
	108	bd->bi_ethspeed = 100;
	109	} else {
ff36fbb2 TL	110	#ifdef CONFIG_MCF5445x
	111	fecp->rcr \|= 0x200; /* enabled 10T base */
	112	#endif
8e585f02 TL	113	#ifdef MII_DEBUG
	114	printf("10Mbps\n");
	115	#endif
	116	bd->bi_ethspeed = 10;
	117	}
	118	}
	119
10cbe3b6	120	static int fec_send(struct eth_device dev, void packet, int length)
8e585f02 TL	121	{
	122	struct fec_info_s *info = dev->priv;
	123	volatile fec_t fecp = (fec_t ) (info->iobase);
	124	int j, rc;
	125	u16 phyStatus;
	126
8ef583a0	127	miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus);
8e585f02 TL	128
	129	/* section 16.9.23.3
	130	* Wait for ready
	131	*/
	132	j = 0;
	133	while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
	134	(j < MCFFEC_TOUT_LOOP)) {
	135	udelay(1);
	136	j++;
	137	}
	138	if (j >= MCFFEC_TOUT_LOOP) {
	139	printf("TX not ready\n");
	140	}
0dca874d	141
8e585f02 TL	142	info->txbd[info->txIdx].cbd_bufaddr = (uint) packet;
	143	info->txbd[info->txIdx].cbd_datlen = length;
	144	info->txbd[info->txIdx].cbd_sc \|= BD_ENET_TX_RDY_LST;
	145
	146	/* Activate transmit Buffer Descriptor polling */
	147	fecp->tdar = 0x01000000; /* Descriptor polling active */
	148
6d0f6bcf	149	#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM
1803f7f9 TL	150	/*
1803f7f9 TL	151	* FEC unable to initial transmit data packet.
f605479d	152	* A nop will ensure the descriptor polling active completed.
1803f7f9 TL	153	* CF Internal RAM has shorter cycle access than DRAM. If use
	154	* DRAM as Buffer descriptor and data, a nop is a must.
	155	* Affect only V2 and V3.
f605479d	156	*/
f605479d	157	__asm__ ("nop");
1803f7f9	158
f605479d TL	159	#endif
f605479d TL	160
6d0f6bcf	161	#ifdef CONFIG_SYS_UNIFY_CACHE
f2208fbc TL	162	icache_invalid();
f2208fbc TL	163	#endif
1803f7f9	164
0dca874d	165	j = 0;
8e585f02 TL	166	while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
	167	(j < MCFFEC_TOUT_LOOP)) {
	168	udelay(1);
	169	j++;
	170	}
	171	if (j >= MCFFEC_TOUT_LOOP) {
	172	printf("TX timeout\n");
	173	}
0dca874d	174
8e585f02 TL	175	#ifdef ET_DEBUG
	176	printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
	177	__FILE__, __LINE__, __FUNCTION__, j,
	178	info->txbd[info->txIdx].cbd_sc,
	179	(info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2);
	180	#endif
	181
0dca874d	182	/* return only status bits */
8e585f02 TL	183	rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
	184	info->txIdx = (info->txIdx + 1) % TX_BUF_CNT;
	185
	186	return rc;
	187	}
	188
	189	int fec_recv(struct eth_device *dev)
	190	{
	191	struct fec_info_s *info = dev->priv;
	192	volatile fec_t fecp = (fec_t ) (info->iobase);
	193	int length;
	194
	195	for (;;) {
6d0f6bcf	196	#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM
1803f7f9	197	#endif
6d0f6bcf	198	#ifdef CONFIG_SYS_UNIFY_CACHE
53677ef1	199	icache_invalid();
0dca874d	200	#endif
8e585f02 TL	201	/* section 16.9.23.2 */
	202	if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
	203	length = -1;
	204	break; /* nothing received - leave for() loop */
	205	}
	206
	207	length = info->rxbd[info->rxIdx].cbd_datlen;
	208
	209	if (info->rxbd[info->rxIdx].cbd_sc & 0x003f) {
	210	printf("%s[%d] err: %x\n",
	211	__FUNCTION__, __LINE__,
	212	info->rxbd[info->rxIdx].cbd_sc);
	213	#ifdef ET_DEBUG
	214	printf("%s[%d] err: %x\n",
	215	__FUNCTION__, __LINE__,
	216	info->rxbd[info->rxIdx].cbd_sc);
	217	#endif
	218	} else {
	219
	220	length -= 4;
	221	/* Pass the packet up to the protocol layers. */
1fd92db8 JH	222	net_process_received_packet(net_rx_packets[info->rxIdx],
1fd92db8 JH	223	length);
8e585f02 TL	224
	225	fecp->eir \|= FEC_EIR_RXF;
	226	}
	227
	228	/* Give the buffer back to the FEC. */
	229	info->rxbd[info->rxIdx].cbd_datlen = 0;
	230
	231	/* wrap around buffer index when necessary */
	232	if (info->rxIdx == LAST_PKTBUFSRX) {
	233	info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E;
	234	info->rxIdx = 0;
	235	} else {
	236	info->rxbd[info->rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
	237	info->rxIdx++;
	238	}
	239
	240	/* Try to fill Buffer Descriptors */
	241	fecp->rdar = 0x01000000; /* Descriptor polling active */
	242	}
	243
	244	return length;
	245	}
	246
8e585f02 TL	247	#ifdef ET_DEBUG
	248	void dbgFecRegs(struct eth_device *dev)
	249	{
	250	struct fec_info_s *info = dev->priv;
	251	volatile fec_t fecp = (fec_t ) (info->iobase);
	252
	253	printf("=====\n");
	254	printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
	255	printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
	256	printf("r_des_active %x - %x\n", (int)&fecp->rdar, fecp->rdar);
	257	printf("x_des_active %x - %x\n", (int)&fecp->tdar, fecp->tdar);
	258	printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
	259	printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
	260	printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
	261	printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
	262	printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
	263	printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
	264	printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
	265	printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
	266	printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
	267	printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
	268	printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
	269	printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
	270	printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
	271	printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
	272	printf("r_bound %x - %x\n", (int)&fecp->frbr, fecp->frbr);
	273	printf("r_fstart %x - %x\n", (int)&fecp->frsr, fecp->frsr);
	274	printf("r_drng %x - %x\n", (int)&fecp->erdsr, fecp->erdsr);
	275	printf("x_drng %x - %x\n", (int)&fecp->etdsr, fecp->etdsr);
	276	printf("r_bufsz %x - %x\n", (int)&fecp->emrbr, fecp->emrbr);
	277
	278	printf("\n");
	279	printf("rmon_t_drop %x - %x\n", (int)&fecp->rmon_t_drop,
	280	fecp->rmon_t_drop);
	281	printf("rmon_t_packets %x - %x\n", (int)&fecp->rmon_t_packets,
	282	fecp->rmon_t_packets);
	283	printf("rmon_t_bc_pkt %x - %x\n", (int)&fecp->rmon_t_bc_pkt,
	284	fecp->rmon_t_bc_pkt);
	285	printf("rmon_t_mc_pkt %x - %x\n", (int)&fecp->rmon_t_mc_pkt,
	286	fecp->rmon_t_mc_pkt);
	287	printf("rmon_t_crc_align %x - %x\n", (int)&fecp->rmon_t_crc_align,
	288	fecp->rmon_t_crc_align);
	289	printf("rmon_t_undersize %x - %x\n", (int)&fecp->rmon_t_undersize,
	290	fecp->rmon_t_undersize);
	291	printf("rmon_t_oversize %x - %x\n", (int)&fecp->rmon_t_oversize,
	292	fecp->rmon_t_oversize);
	293	printf("rmon_t_frag %x - %x\n", (int)&fecp->rmon_t_frag,
	294	fecp->rmon_t_frag);
	295	printf("rmon_t_jab %x - %x\n", (int)&fecp->rmon_t_jab,
	296	fecp->rmon_t_jab);
	297	printf("rmon_t_col %x - %x\n", (int)&fecp->rmon_t_col,
	298	fecp->rmon_t_col);
	299	printf("rmon_t_p64 %x - %x\n", (int)&fecp->rmon_t_p64,
	300	fecp->rmon_t_p64);
	301	printf("rmon_t_p65to127 %x - %x\n", (int)&fecp->rmon_t_p65to127,
	302	fecp->rmon_t_p65to127);
	303	printf("rmon_t_p128to255 %x - %x\n", (int)&fecp->rmon_t_p128to255,
	304	fecp->rmon_t_p128to255);
	305	printf("rmon_t_p256to511 %x - %x\n", (int)&fecp->rmon_t_p256to511,
	306	fecp->rmon_t_p256to511);
	307	printf("rmon_t_p512to1023 %x - %x\n", (int)&fecp->rmon_t_p512to1023,
	308	fecp->rmon_t_p512to1023);
	309	printf("rmon_t_p1024to2047 %x - %x\n", (int)&fecp->rmon_t_p1024to2047,
	310	fecp->rmon_t_p1024to2047);
311	printf("rmon_t_p_gte2048 %x - %x\n", (int)&fecp->rmon_t_p_gte2048,
312	fecp->rmon_t_p_gte2048);
313	printf("rmon_t_octets %x - %x\n", (int)&fecp->rmon_t_octets,
314	fecp->rmon_t_octets);
315
316	printf("\n");
317	printf("ieee_t_drop %x - %x\n", (int)&fecp->ieee_t_drop,
318	fecp->ieee_t_drop);
319	printf("ieee_t_frame_ok %x - %x\n", (int)&fecp->ieee_t_frame_ok,
320	fecp->ieee_t_frame_ok);
321	printf("ieee_t_1col %x - %x\n", (int)&fecp->ieee_t_1col,
322	fecp->ieee_t_1col);
323	printf("ieee_t_mcol %x - %x\n", (int)&fecp->ieee_t_mcol,
324	fecp->ieee_t_mcol);
325	printf("ieee_t_def %x - %x\n", (int)&fecp->ieee_t_def,
326	fecp->ieee_t_def);
327	printf("ieee_t_lcol %x - %x\n", (int)&fecp->ieee_t_lcol,
328	fecp->ieee_t_lcol);
329	printf("ieee_t_excol %x - %x\n", (int)&fecp->ieee_t_excol,
330	fecp->ieee_t_excol);
331	printf("ieee_t_macerr %x - %x\n", (int)&fecp->ieee_t_macerr,
332	fecp->ieee_t_macerr);
333	printf("ieee_t_cserr %x - %x\n", (int)&fecp->ieee_t_cserr,
334	fecp->ieee_t_cserr);
335	printf("ieee_t_sqe %x - %x\n", (int)&fecp->ieee_t_sqe,
336	fecp->ieee_t_sqe);
337	printf("ieee_t_fdxfc %x - %x\n", (int)&fecp->ieee_t_fdxfc,
338	fecp->ieee_t_fdxfc);
339	printf("ieee_t_octets_ok %x - %x\n", (int)&fecp->ieee_t_octets_ok,
340	fecp->ieee_t_octets_ok);
341
342	printf("\n");
343	printf("rmon_r_drop %x - %x\n", (int)&fecp->rmon_r_drop,
344	fecp->rmon_r_drop);
345	printf("rmon_r_packets %x - %x\n", (int)&fecp->rmon_r_packets,
346	fecp->rmon_r_packets);
347	printf("rmon_r_bc_pkt %x - %x\n", (int)&fecp->rmon_r_bc_pkt,
348	fecp->rmon_r_bc_pkt);
349	printf("rmon_r_mc_pkt %x - %x\n", (int)&fecp->rmon_r_mc_pkt,
350	fecp->rmon_r_mc_pkt);
351	printf("rmon_r_crc_align %x - %x\n", (int)&fecp->rmon_r_crc_align,
352	fecp->rmon_r_crc_align);
353	printf("rmon_r_undersize %x - %x\n", (int)&fecp->rmon_r_undersize,
354	fecp->rmon_r_undersize);
355	printf("rmon_r_oversize %x - %x\n", (int)&fecp->rmon_r_oversize,
356	fecp->rmon_r_oversize);
357	printf("rmon_r_frag %x - %x\n", (int)&fecp->rmon_r_frag,
358	fecp->rmon_r_frag);
359	printf("rmon_r_jab %x - %x\n", (int)&fecp->rmon_r_jab,
360	fecp->rmon_r_jab);
361	printf("rmon_r_p64 %x - %x\n", (int)&fecp->rmon_r_p64,
362	fecp->rmon_r_p64);
363	printf("rmon_r_p65to127 %x - %x\n", (int)&fecp->rmon_r_p65to127,
364	fecp->rmon_r_p65to127);
365	printf("rmon_r_p128to255 %x - %x\n", (int)&fecp->rmon_r_p128to255,
366	fecp->rmon_r_p128to255);
367	printf("rmon_r_p256to511 %x - %x\n", (int)&fecp->rmon_r_p256to511,
368	fecp->rmon_r_p256to511);
369	printf("rmon_r_p512to1023 %x - %x\n", (int)&fecp->rmon_r_p512to1023,
370	fecp->rmon_r_p512to1023);
371	printf("rmon_r_p1024to2047 %x - %x\n", (int)&fecp->rmon_r_p1024to2047,
372	fecp->rmon_r_p1024to2047);
373	printf("rmon_r_p_gte2048 %x - %x\n", (int)&fecp->rmon_r_p_gte2048,
374	fecp->rmon_r_p_gte2048);
375	printf("rmon_r_octets %x - %x\n", (int)&fecp->rmon_r_octets,
376	fecp->rmon_r_octets);
377
378	printf("\n");
379	printf("ieee_r_drop %x - %x\n", (int)&fecp->ieee_r_drop,
380	fecp->ieee_r_drop);
381	printf("ieee_r_frame_ok %x - %x\n", (int)&fecp->ieee_r_frame_ok,
382	fecp->ieee_r_frame_ok);
383	printf("ieee_r_crc %x - %x\n", (int)&fecp->ieee_r_crc,
384	fecp->ieee_r_crc);
385	printf("ieee_r_align %x - %x\n", (int)&fecp->ieee_r_align,
386	fecp->ieee_r_align);
387	printf("ieee_r_macerr %x - %x\n", (int)&fecp->ieee_r_macerr,
388	fecp->ieee_r_macerr);
389	printf("ieee_r_fdxfc %x - %x\n", (int)&fecp->ieee_r_fdxfc,
390	fecp->ieee_r_fdxfc);
391	printf("ieee_r_octets_ok %x - %x\n", (int)&fecp->ieee_r_octets_ok,
392	fecp->ieee_r_octets_ok);
393
394	printf("\n\n\n");
395	}
396	#endif
397
398	int fec_init(struct eth_device dev, bd_t bd)
399	{
400	struct fec_info_s *info = dev->priv;
401	volatile fec_t fecp = (fec_t ) (info->iobase);
402	int i;
d3f87148	403	uchar ea[6];
8e585f02 TL	404
	405	fecpin_setclear(dev, 1);
	406
	407	fec_reset(dev);
	408
ab77bc54	409	#if defined(CONFIG_CMD_MII) \|\| defined (CONFIG_MII) \|\| \
6d0f6bcf	410	defined (CONFIG_SYS_DISCOVER_PHY)
8e585f02 TL	411
	412	mii_init();
	413
	414	setFecDuplexSpeed(fecp, bd, info->dup_spd);
	415	#else
6d0f6bcf	416	#ifndef CONFIG_SYS_DISCOVER_PHY
8e585f02	417	setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) \| FECSPEED);
6d0f6bcf	418	#endif /* ifndef CONFIG_SYS_DISCOVER_PHY */
ab77bc54	419	#endif /* CONFIG_CMD_MII \|\| CONFIG_MII */
8e585f02 TL	420
	421	/* We use strictly polling mode only */
	422	fecp->eimr = 0;
	423
	424	/* Clear any pending interrupt */
	425	fecp->eir = 0xffffffff;
	426
	427	/* Set station address */
6d0f6bcf JCPV	428	if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE) {
	429	#ifdef CONFIG_SYS_FEC1_IOBASE
	430	volatile fec_t fecp1 = (fec_t ) (CONFIG_SYS_FEC1_IOBASE);
d3f87148	431	eth_getenv_enetaddr("eth1addr", ea);
8ae158cd TL	432	fecp1->palr =
	433	(ea[0] << 24) \| (ea[1] << 16) \| (ea[2] << 8) \| (ea[3]);
	434	fecp1->paur = (ea[4] << 24) \| (ea[5] << 16);
	435	#endif
d3f87148	436	eth_getenv_enetaddr("ethaddr", ea);
8ae158cd TL	437	fecp->palr =
	438	(ea[0] << 24) \| (ea[1] << 16) \| (ea[2] << 8) \| (ea[3]);
	439	fecp->paur = (ea[4] << 24) \| (ea[5] << 16);
8e585f02	440	} else {
6d0f6bcf JCPV	441	#ifdef CONFIG_SYS_FEC0_IOBASE
6d0f6bcf JCPV	442	volatile fec_t fecp0 = (fec_t ) (CONFIG_SYS_FEC0_IOBASE);
d3f87148	443	eth_getenv_enetaddr("ethaddr", ea);
8ae158cd TL	444	fecp0->palr =
	445	(ea[0] << 24) \| (ea[1] << 16) \| (ea[2] << 8) \| (ea[3]);
	446	fecp0->paur = (ea[4] << 24) \| (ea[5] << 16);
	447	#endif
6d0f6bcf	448	#ifdef CONFIG_SYS_FEC1_IOBASE
d3f87148	449	eth_getenv_enetaddr("eth1addr", ea);
8ae158cd TL	450	fecp->palr =
	451	(ea[0] << 24) \| (ea[1] << 16) \| (ea[2] << 8) \| (ea[3]);
	452	fecp->paur = (ea[4] << 24) \| (ea[5] << 16);
8e585f02 TL	453	#endif
	454	}
	455
8e585f02 TL	456	/* Clear unicast address hash table */
	457	fecp->iaur = 0;
	458	fecp->ialr = 0;
	459
	460	/* Clear multicast address hash table */
	461	fecp->gaur = 0;
	462	fecp->galr = 0;
	463
	464	/* Set maximum receive buffer size. */
	465	fecp->emrbr = PKT_MAXBLR_SIZE;
	466
	467	/*
	468	* Setup Buffers and Buffer Desriptors
	469	*/
	470	info->rxIdx = 0;
	471	info->txIdx = 0;
	472
	473	/*
	474	* Setup Receiver Buffer Descriptors (13.14.24.18)
	475	* Settings:
	476	* Empty, Wrap
	477	*/
	478	for (i = 0; i < PKTBUFSRX; i++) {
	479	info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
	480	info->rxbd[i].cbd_datlen = 0; /* Reset */
1fd92db8	481	info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
8e585f02 TL	482	}
	483	info->rxbd[PKTBUFSRX - 1].cbd_sc \|= BD_ENET_RX_WRAP;
	484
	485	/*
	486	* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
	487	* Settings:
	488	* Last, Tx CRC
	489	*/
	490	for (i = 0; i < TX_BUF_CNT; i++) {
	491	info->txbd[i].cbd_sc = BD_ENET_TX_LAST \| BD_ENET_TX_TC;
	492	info->txbd[i].cbd_datlen = 0; /* Reset */
	493	info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
	494	}
	495	info->txbd[TX_BUF_CNT - 1].cbd_sc \|= BD_ENET_TX_WRAP;
	496
	497	/* Set receive and transmit descriptor base */
	498	fecp->erdsr = (unsigned int)(&info->rxbd[0]);
	499	fecp->etdsr = (unsigned int)(&info->txbd[0]);
	500
	501	/* Now enable the transmit and receive processing */
	502	fecp->ecr \|= FEC_ECR_ETHER_EN;
	503
	504	/* And last, try to fill Rx Buffer Descriptors */
	505	fecp->rdar = 0x01000000; /* Descriptor polling active */
	506
	507	return 1;
	508	}
	509
	510	void fec_reset(struct eth_device *dev)
	511	{
	512	struct fec_info_s *info = dev->priv;
	513	volatile fec_t fecp = (fec_t ) (info->iobase);
	514	int i;
	515
	516	fecp->ecr = FEC_ECR_RESET;
	517	for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
	518	udelay(1);
	519	}
	520	if (i == FEC_RESET_DELAY) {
	521	printf("FEC_RESET_DELAY timeout\n");
	522	}
	523	}
	524
	525	void fec_halt(struct eth_device *dev)
	526	{
	527	struct fec_info_s *info = dev->priv;
	528
	529	fec_reset(dev);
	530
	531	fecpin_setclear(dev, 0);
	532
	533	info->rxIdx = info->txIdx = 0;
	534	memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t));
	535	memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t));
	536	memset(info->txbuf, 0, DBUF_LENGTH);
	537	}
	538
	539	int mcffec_initialize(bd_t * bis)
	540	{
	541	struct eth_device *dev;
	542	int i;
6d0f6bcf JCPV	543	#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
6d0f6bcf JCPV	544	u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
1803f7f9	545	#endif
8e585f02	546
a62cd29c	547	for (i = 0; i < ARRAY_SIZE(fec_info); i++) {
8e585f02	548
f2208fbc	549	dev =
6d0f6bcf	550	(struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE,
f2208fbc	551	sizeof *dev);
8e585f02 TL	552	if (dev == NULL)
	553	hang();
	554
	555	memset(dev, 0, sizeof(*dev));
	556
	557	sprintf(dev->name, "FEC%d", fec_info[i].index);
	558
	559	dev->priv = &fec_info[i];
	560	dev->init = fec_init;
	561	dev->halt = fec_halt;
	562	dev->send = fec_send;
	563	dev->recv = fec_recv;
	564
	565	/* setup Receive and Transmit buffer descriptor */
6d0f6bcf	566	#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
1803f7f9 TL	567	fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp);
	568	tmp = (u32)fec_info[i].rxbd;
	569	fec_info[i].txbd =
	570	(cbd_t *)((u32)fec_info[i].txbd + tmp +
	571	(PKTBUFSRX * sizeof(cbd_t)));
	572	tmp = (u32)fec_info[i].txbd;
	573	fec_info[i].txbuf =
	574	(char *)((u32)fec_info[i].txbuf + tmp +
6d0f6bcf	575	(CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
1803f7f9 TL	576	tmp = (u32)fec_info[i].txbuf;
1803f7f9 TL	577	#else
8e585f02	578	fec_info[i].rxbd =
6d0f6bcf	579	(cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
f2208fbc	580	(PKTBUFSRX * sizeof(cbd_t)));
8e585f02	581	fec_info[i].txbd =
6d0f6bcf	582	(cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
f2208fbc TL	583	(TX_BUF_CNT * sizeof(cbd_t)));
f2208fbc TL	584	fec_info[i].txbuf =
6d0f6bcf	585	(char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
1803f7f9 TL	586	#endif
1803f7f9 TL	587
8e585f02 TL	588	#ifdef ET_DEBUG
	589	printf("rxbd %x txbd %x\n",
	590	(int)fec_info[i].rxbd, (int)fec_info[i].txbd);
	591	#endif
	592
6d0f6bcf	593	fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
8e585f02 TL	594
	595	eth_register(dev);
	596
ab77bc54	597	#if defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII)
5a49f174 JH	598	int retval;
	599	struct mii_dev *mdiodev = mdio_alloc();
	600	if (!mdiodev)
	601	return -ENOMEM;
	602	strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
	603	mdiodev->read = mcffec_miiphy_read;
	604	mdiodev->write = mcffec_miiphy_write;
	605
	606	retval = mdio_register(mdiodev);
	607	if (retval < 0)
	608	return retval;
8e585f02	609	#endif
1803f7f9 TL	610	if (i > 0)
1803f7f9 TL	611	fec_info[i - 1].next = &fec_info[i];
8e585f02	612	}
1803f7f9	613	fec_info[i - 1].next = &fec_info[0];
8e585f02 TL	614
	615	/* default speed */
	616	bis->bi_ethspeed = 10;
	617
86882b80	618	return 0;
8e585f02	619	}