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[thirdparty/linux.git] / drivers / net / natsemi.c
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1da177e4
LT		 1/* natsemi.c: A Linux PCI Ethernet driver for the NatSemi DP8381x series. */
2/*
3 Written/copyright 1999-2001 by Donald Becker.
4 Portions copyright (c) 2001,2002 Sun Microsystems (thockin@sun.com)
5 Portions copyright 2001,2002 Manfred Spraul (manfred@colorfullife.com)
b27a16b7 6 Portions copyright 2004 Harald Welte <laforge@gnumonks.org>
1da177e4
LT		 7
8 This software may be used and distributed according to the terms of
9 the GNU General Public License (GPL), incorporated herein by reference.
10 Drivers based on or derived from this code fall under the GPL and must
11 retain the authorship, copyright and license notice. This file is not
12 a complete program and may only be used when the entire operating
13 system is licensed under the GPL. License for under other terms may be
14 available. Contact the original author for details.
15
16 The original author may be reached as becker@scyld.com, or at
17 Scyld Computing Corporation
18 410 Severn Ave., Suite 210
19 Annapolis MD 21403
20
21 Support information and updates available at
22 http://www.scyld.com/network/netsemi.html
03a8c661 23 [link no longer provides useful info -jgarzik]
1da177e4
LT		 24
25
1da177e4
LT		 26 TODO:
27 * big endian support with CFG:BEM instead of cpu_to_le32
1da177e4
LT		 28*/
29
1da177e4
LT		 30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/string.h>
33#include <linux/timer.h>
34#include <linux/errno.h>
35#include <linux/ioport.h>
36#include <linux/slab.h>
37#include <linux/interrupt.h>
38#include <linux/pci.h>
39#include <linux/netdevice.h>
40#include <linux/etherdevice.h>
41#include <linux/skbuff.h>
42#include <linux/init.h>
43#include <linux/spinlock.h>
44#include <linux/ethtool.h>
45#include <linux/delay.h>
46#include <linux/rtnetlink.h>
47#include <linux/mii.h>
48#include <linux/crc32.h>
49#include <linux/bitops.h>
b27a16b7 50#include <linux/prefetch.h>
1da177e4
LT		 51#include <asm/processor.h> /* Processor type for cache alignment. */
52#include <asm/io.h>
53#include <asm/irq.h>
54#include <asm/uaccess.h>
55
56#define DRV_NAME "natsemi"
d5b20697
AG		 57#define DRV_VERSION "2.1"
58#define DRV_RELDATE "Sept 11, 2006"
1da177e4
LT		 59
60#define RX_OFFSET 2
61
62/* Updated to recommendations in pci-skeleton v2.03. */
63
64/* The user-configurable values.
65 These may be modified when a driver module is loaded.*/
66
67#define NATSEMI_DEF_MSG (NETIF_MSG_DRV | \
68 NETIF_MSG_LINK | \
69 NETIF_MSG_WOL | \
70 NETIF_MSG_RX_ERR | \
71 NETIF_MSG_TX_ERR)
72static int debug = -1;
73
1da177e4
LT		 74static int mtu;
75
76/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
77 This chip uses a 512 element hash table based on the Ethernet CRC. */
f71e1309 78static const int multicast_filter_limit = 100;
1da177e4
LT		 79
80/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
81 Setting to > 1518 effectively disables this feature. */
82static int rx_copybreak;
83
1a147809
MB		 84static int dspcfg_workaround = 1;
85
1da177e4
LT		 86/* Used to pass the media type, etc.
87 Both 'options[]' and 'full_duplex[]' should exist for driver
88 interoperability.
89 The media type is usually passed in 'options[]'.
90*/
91#define MAX_UNITS 8 /* More are supported, limit only on options */
92static int options[MAX_UNITS];
93static int full_duplex[MAX_UNITS];
94
95/* Operational parameters that are set at compile time. */
96
97/* Keep the ring sizes a power of two for compile efficiency.
98 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
99 Making the Tx ring too large decreases the effectiveness of channel
100 bonding and packet priority.
101 There are no ill effects from too-large receive rings. */
102#define TX_RING_SIZE 16
103#define TX_QUEUE_LEN 10 /* Limit ring entries actually used, min 4. */
104#define RX_RING_SIZE 32
105
106/* Operational parameters that usually are not changed. */
107/* Time in jiffies before concluding the transmitter is hung. */
108#define TX_TIMEOUT (2*HZ)
109
110#define NATSEMI_HW_TIMEOUT 400
f2cade13 111#define NATSEMI_TIMER_FREQ 5*HZ
1da177e4
LT		 112#define NATSEMI_PG0_NREGS 64
113#define NATSEMI_RFDR_NREGS 8
114#define NATSEMI_PG1_NREGS 4
115#define NATSEMI_NREGS (NATSEMI_PG0_NREGS + NATSEMI_RFDR_NREGS + \
116 NATSEMI_PG1_NREGS)
117#define NATSEMI_REGS_VER 1 /* v1 added RFDR registers */
118#define NATSEMI_REGS_SIZE (NATSEMI_NREGS * sizeof(u32))
1da177e4
LT		 119
120/* Buffer sizes:
121 * The nic writes 32-bit values, even if the upper bytes of
122 * a 32-bit value are beyond the end of the buffer.
123 */
124#define NATSEMI_HEADERS 22 /* 2*mac,type,vlan,crc */
125#define NATSEMI_PADDING 16 /* 2 bytes should be sufficient */
126#define NATSEMI_LONGPKT 1518 /* limit for normal packets */
127#define NATSEMI_RX_LIMIT 2046 /* maximum supported by hardware */
128
129/* These identify the driver base version and may not be removed. */
23410495 130static const char version[] __devinitconst =
1da177e4
LT		 131 KERN_INFO DRV_NAME " dp8381x driver, version "
132 DRV_VERSION ", " DRV_RELDATE "\n"
ad361c98
JP		 133 " originally by Donald Becker <becker@scyld.com>\n"
134 " 2.4.x kernel port by Jeff Garzik, Tjeerd Mulder\n";
1da177e4
LT		 135
136MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
137MODULE_DESCRIPTION("National Semiconductor DP8381x series PCI Ethernet driver");
138MODULE_LICENSE("GPL");
139
1da177e4
LT		 140module_param(mtu, int, 0);
141module_param(debug, int, 0);
142module_param(rx_copybreak, int, 0);
1a147809 143module_param(dspcfg_workaround, int, 1);
1da177e4
LT		 144module_param_array(options, int, NULL, 0);
145module_param_array(full_duplex, int, NULL, 0);
1da177e4
LT		 146MODULE_PARM_DESC(mtu, "DP8381x MTU (all boards)");
147MODULE_PARM_DESC(debug, "DP8381x default debug level");
6aa20a22 148MODULE_PARM_DESC(rx_copybreak,
1da177e4 149 "DP8381x copy breakpoint for copy-only-tiny-frames");
1a147809 150MODULE_PARM_DESC(dspcfg_workaround, "DP8381x: control DspCfg workaround");
6aa20a22 151MODULE_PARM_DESC(options,
1da177e4
LT		 152 "DP8381x: Bits 0-3: media type, bit 17: full duplex");
153MODULE_PARM_DESC(full_duplex, "DP8381x full duplex setting(s) (1)");
154
155/*
156 Theory of Operation
157
158I. Board Compatibility
159
160This driver is designed for National Semiconductor DP83815 PCI Ethernet NIC.
161It also works with other chips in in the DP83810 series.
162
163II. Board-specific settings
164
165This driver requires the PCI interrupt line to be valid.
166It honors the EEPROM-set values.
167
168III. Driver operation
169
170IIIa. Ring buffers
171
172This driver uses two statically allocated fixed-size descriptor lists
173formed into rings by a branch from the final descriptor to the beginning of
174the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
175The NatSemi design uses a 'next descriptor' pointer that the driver forms
176into a list.
177
178IIIb/c. Transmit/Receive Structure
179
180This driver uses a zero-copy receive and transmit scheme.
181The driver allocates full frame size skbuffs for the Rx ring buffers at
182open() time and passes the skb->data field to the chip as receive data
183buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
184a fresh skbuff is allocated and the frame is copied to the new skbuff.
185When the incoming frame is larger, the skbuff is passed directly up the
186protocol stack. Buffers consumed this way are replaced by newly allocated
187skbuffs in a later phase of receives.
188
189The RX_COPYBREAK value is chosen to trade-off the memory wasted by
190using a full-sized skbuff for small frames vs. the copying costs of larger
191frames. New boards are typically used in generously configured machines
192and the underfilled buffers have negligible impact compared to the benefit of
193a single allocation size, so the default value of zero results in never
194copying packets. When copying is done, the cost is usually mitigated by using
195a combined copy/checksum routine. Copying also preloads the cache, which is
196most useful with small frames.
197
198A subtle aspect of the operation is that unaligned buffers are not permitted
199by the hardware. Thus the IP header at offset 14 in an ethernet frame isn't
200longword aligned for further processing. On copies frames are put into the
201skbuff at an offset of "+2", 16-byte aligning the IP header.
202
203IIId. Synchronization
204
205Most operations are synchronized on the np->lock irq spinlock, except the
6344f052
MB		 206recieve and transmit paths which are synchronised using a combination of
207hardware descriptor ownership, disabling interrupts and NAPI poll scheduling.
1da177e4
LT		 208
209IVb. References
210
211http://www.scyld.com/expert/100mbps.html
212http://www.scyld.com/expert/NWay.html
213Datasheet is available from:
214http://www.national.com/pf/DP/DP83815.html
215
216IVc. Errata
217
218None characterised.
219*/
220
221
222
1da177e4
LT		 223/*
224 * Support for fibre connections on Am79C874:
225 * This phy needs a special setup when connected to a fibre cable.
226 * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/22235.pdf
227 */
228#define PHYID_AM79C874 0x0022561b
229
a2b524b2
JG		 230enum {
231 MII_MCTRL = 0x15, /* mode control register */
232 MII_FX_SEL = 0x0001, /* 100BASE-FX (fiber) */
233 MII_EN_SCRM = 0x0004, /* enable scrambler (tp) */
234};
1da177e4 235
6aab4447
MB		 236enum {
237 NATSEMI_FLAG_IGNORE_PHY = 0x1,
238};
6aa20a22 239
1da177e4 240/* array of board data directly indexed by pci_tbl[x].driver_data */
aa738adf 241static struct {
1da177e4
LT		 242 const char *name;
243 unsigned long flags;
a2b524b2 244 unsigned int eeprom_size;
1da177e4 245} natsemi_pci_info[] __devinitdata = {
6aab4447 246 { "Aculab E1/T1 PMXc cPCI carrier card", NATSEMI_FLAG_IGNORE_PHY, 128 },
a2b524b2 247 { "NatSemi DP8381[56]", 0, 24 },
1da177e4
LT		 248};
249
a3aa1884 250static DEFINE_PCI_DEVICE_TABLE(natsemi_pci_tbl) = {
6aab4447 251 { PCI_VENDOR_ID_NS, 0x0020, 0x12d9, 0x000c, 0, 0, 0 },
36c843d5 252 { PCI_VENDOR_ID_NS, 0x0020, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
a2b524b2 253 { } /* terminate list */
1da177e4
LT		 254};
255MODULE_DEVICE_TABLE(pci, natsemi_pci_tbl);
256
257/* Offsets to the device registers.
258 Unlike software-only systems, device drivers interact with complex hardware.
259 It's not useful to define symbolic names for every register bit in the
260 device.
261*/
262enum register_offsets {
263 ChipCmd = 0x00,
264 ChipConfig = 0x04,
265 EECtrl = 0x08,
266 PCIBusCfg = 0x0C,
267 IntrStatus = 0x10,
268 IntrMask = 0x14,
269 IntrEnable = 0x18,
270 IntrHoldoff = 0x1C, /* DP83816 only */
271 TxRingPtr = 0x20,
272 TxConfig = 0x24,
273 RxRingPtr = 0x30,
274 RxConfig = 0x34,
275 ClkRun = 0x3C,
276 WOLCmd = 0x40,
277 PauseCmd = 0x44,
278 RxFilterAddr = 0x48,
279 RxFilterData = 0x4C,
280 BootRomAddr = 0x50,
281 BootRomData = 0x54,
282 SiliconRev = 0x58,
283 StatsCtrl = 0x5C,
284 StatsData = 0x60,
285 RxPktErrs = 0x60,
286 RxMissed = 0x68,
287 RxCRCErrs = 0x64,
288 BasicControl = 0x80,
289 BasicStatus = 0x84,
290 AnegAdv = 0x90,
291 AnegPeer = 0x94,
292 PhyStatus = 0xC0,
293 MIntrCtrl = 0xC4,
294 MIntrStatus = 0xC8,
295 PhyCtrl = 0xE4,
296
297 /* These are from the spec, around page 78... on a separate table.
298 * The meaning of these registers depend on the value of PGSEL. */
299 PGSEL = 0xCC,
300 PMDCSR = 0xE4,
301 TSTDAT = 0xFC,
302 DSPCFG = 0xF4,
303 SDCFG = 0xF8
304};
305/* the values for the 'magic' registers above (PGSEL=1) */
306#define PMDCSR_VAL 0x189c /* enable preferred adaptation circuitry */
307#define TSTDAT_VAL 0x0
308#define DSPCFG_VAL 0x5040
309#define SDCFG_VAL 0x008c /* set voltage thresholds for Signal Detect */
310#define DSPCFG_LOCK 0x20 /* coefficient lock bit in DSPCFG */
311#define DSPCFG_COEF 0x1000 /* see coefficient (in TSTDAT) bit in DSPCFG */
312#define TSTDAT_FIXED 0xe8 /* magic number for bad coefficients */
313
314/* misc PCI space registers */
315enum pci_register_offsets {
316 PCIPM = 0x44,
317};
318
319enum ChipCmd_bits {
320 ChipReset = 0x100,
321 RxReset = 0x20,
322 TxReset = 0x10,
323 RxOff = 0x08,
324 RxOn = 0x04,
325 TxOff = 0x02,
326 TxOn = 0x01,
327};
328
329enum ChipConfig_bits {
330 CfgPhyDis = 0x200,
331 CfgPhyRst = 0x400,
332 CfgExtPhy = 0x1000,
333 CfgAnegEnable = 0x2000,
334 CfgAneg100 = 0x4000,
335 CfgAnegFull = 0x8000,
336 CfgAnegDone = 0x8000000,
337 CfgFullDuplex = 0x20000000,
338 CfgSpeed100 = 0x40000000,
339 CfgLink = 0x80000000,
340};
341
342enum EECtrl_bits {
343 EE_ShiftClk = 0x04,
344 EE_DataIn = 0x01,
345 EE_ChipSelect = 0x08,
346 EE_DataOut = 0x02,
347 MII_Data = 0x10,
348 MII_Write = 0x20,
349 MII_ShiftClk = 0x40,
350};
351
352enum PCIBusCfg_bits {
353 EepromReload = 0x4,
354};
355
356/* Bits in the interrupt status/mask registers. */
357enum IntrStatus_bits {
358 IntrRxDone = 0x0001,
359 IntrRxIntr = 0x0002,
360 IntrRxErr = 0x0004,
361 IntrRxEarly = 0x0008,
362 IntrRxIdle = 0x0010,
363 IntrRxOverrun = 0x0020,
364 IntrTxDone = 0x0040,
365 IntrTxIntr = 0x0080,
366 IntrTxErr = 0x0100,
367 IntrTxIdle = 0x0200,
368 IntrTxUnderrun = 0x0400,
369 StatsMax = 0x0800,
370 SWInt = 0x1000,
371 WOLPkt = 0x2000,
372 LinkChange = 0x4000,
373 IntrHighBits = 0x8000,
374 RxStatusFIFOOver = 0x10000,
375 IntrPCIErr = 0xf00000,
376 RxResetDone = 0x1000000,
377 TxResetDone = 0x2000000,
378 IntrAbnormalSummary = 0xCD20,
379};
380
381/*
382 * Default Interrupts:
383 * Rx OK, Rx Packet Error, Rx Overrun,
384 * Tx OK, Tx Packet Error, Tx Underrun,
385 * MIB Service, Phy Interrupt, High Bits,
386 * Rx Status FIFO overrun,
387 * Received Target Abort, Received Master Abort,
388 * Signalled System Error, Received Parity Error
389 */
390#define DEFAULT_INTR 0x00f1cd65
391
392enum TxConfig_bits {
393 TxDrthMask = 0x3f,
394 TxFlthMask = 0x3f00,
395 TxMxdmaMask = 0x700000,
396 TxMxdma_512 = 0x0,
397 TxMxdma_4 = 0x100000,
398 TxMxdma_8 = 0x200000,
399 TxMxdma_16 = 0x300000,
400 TxMxdma_32 = 0x400000,
401 TxMxdma_64 = 0x500000,
402 TxMxdma_128 = 0x600000,
403 TxMxdma_256 = 0x700000,
404 TxCollRetry = 0x800000,
405 TxAutoPad = 0x10000000,
406 TxMacLoop = 0x20000000,
407 TxHeartIgn = 0x40000000,
408 TxCarrierIgn = 0x80000000
409};
410
6aa20a22 411/*
1da177e4
LT		 412 * Tx Configuration:
413 * - 256 byte DMA burst length
414 * - fill threshold 512 bytes (i.e. restart DMA when 512 bytes are free)
415 * - 64 bytes initial drain threshold (i.e. begin actual transmission
416 * when 64 byte are in the fifo)
417 * - on tx underruns, increase drain threshold by 64.
418 * - at most use a drain threshold of 1472 bytes: The sum of the fill
419 * threshold and the drain threshold must be less than 2016 bytes.
420 *
421 */
422#define TX_FLTH_VAL ((512/32) << 8)
423#define TX_DRTH_VAL_START (64/32)
424#define TX_DRTH_VAL_INC 2
425#define TX_DRTH_VAL_LIMIT (1472/32)
426
427enum RxConfig_bits {
428 RxDrthMask = 0x3e,
429 RxMxdmaMask = 0x700000,
430 RxMxdma_512 = 0x0,
431 RxMxdma_4 = 0x100000,
432 RxMxdma_8 = 0x200000,
433 RxMxdma_16 = 0x300000,
434 RxMxdma_32 = 0x400000,
435 RxMxdma_64 = 0x500000,
436 RxMxdma_128 = 0x600000,
437 RxMxdma_256 = 0x700000,
438 RxAcceptLong = 0x8000000,
439 RxAcceptTx = 0x10000000,
440 RxAcceptRunt = 0x40000000,
441 RxAcceptErr = 0x80000000
442};
443#define RX_DRTH_VAL (128/8)
444
445enum ClkRun_bits {
446 PMEEnable = 0x100,
447 PMEStatus = 0x8000,
448};
449
450enum WolCmd_bits {
451 WakePhy = 0x1,
452 WakeUnicast = 0x2,
453 WakeMulticast = 0x4,
454 WakeBroadcast = 0x8,
455 WakeArp = 0x10,
456 WakePMatch0 = 0x20,
457 WakePMatch1 = 0x40,
458 WakePMatch2 = 0x80,
459 WakePMatch3 = 0x100,
460 WakeMagic = 0x200,
461 WakeMagicSecure = 0x400,
462 SecureHack = 0x100000,
463 WokePhy = 0x400000,
464 WokeUnicast = 0x800000,
465 WokeMulticast = 0x1000000,
466 WokeBroadcast = 0x2000000,
467 WokeArp = 0x4000000,
468 WokePMatch0 = 0x8000000,
469 WokePMatch1 = 0x10000000,
470 WokePMatch2 = 0x20000000,
471 WokePMatch3 = 0x40000000,
472 WokeMagic = 0x80000000,
473 WakeOptsSummary = 0x7ff
474};
475
476enum RxFilterAddr_bits {
477 RFCRAddressMask = 0x3ff,
478 AcceptMulticast = 0x00200000,
479 AcceptMyPhys = 0x08000000,
480 AcceptAllPhys = 0x10000000,
481 AcceptAllMulticast = 0x20000000,
482 AcceptBroadcast = 0x40000000,
483 RxFilterEnable = 0x80000000
484};
485
486enum StatsCtrl_bits {
487 StatsWarn = 0x1,
488 StatsFreeze = 0x2,
489 StatsClear = 0x4,
490 StatsStrobe = 0x8,
491};
492
493enum MIntrCtrl_bits {
494 MICRIntEn = 0x2,
495};
496
497enum PhyCtrl_bits {
498 PhyAddrMask = 0x1f,
499};
500
501#define PHY_ADDR_NONE 32
502#define PHY_ADDR_INTERNAL 1
503
504/* values we might find in the silicon revision register */
505#define SRR_DP83815_C 0x0302
506#define SRR_DP83815_D 0x0403
507#define SRR_DP83816_A4 0x0504
508#define SRR_DP83816_A5 0x0505
509
510/* The Rx and Tx buffer descriptors. */
511/* Note that using only 32 bit fields simplifies conversion to big-endian
512 architectures. */
513struct netdev_desc {
eca1ad82
AV		 514 __le32 next_desc;
515 __le32 cmd_status;
516 __le32 addr;
517 __le32 software_use;
1da177e4
LT		 518};
519
520/* Bits in network_desc.status */
521enum desc_status_bits {
522 DescOwn=0x80000000, DescMore=0x40000000, DescIntr=0x20000000,
523 DescNoCRC=0x10000000, DescPktOK=0x08000000,
524 DescSizeMask=0xfff,
525
526 DescTxAbort=0x04000000, DescTxFIFO=0x02000000,
527 DescTxCarrier=0x01000000, DescTxDefer=0x00800000,
528 DescTxExcDefer=0x00400000, DescTxOOWCol=0x00200000,
529 DescTxExcColl=0x00100000, DescTxCollCount=0x000f0000,
530
531 DescRxAbort=0x04000000, DescRxOver=0x02000000,
532 DescRxDest=0x01800000, DescRxLong=0x00400000,
533 DescRxRunt=0x00200000, DescRxInvalid=0x00100000,
534 DescRxCRC=0x00080000, DescRxAlign=0x00040000,
535 DescRxLoop=0x00020000, DesRxColl=0x00010000,
536};
537
538struct netdev_private {
539 /* Descriptor rings first for alignment */
540 dma_addr_t ring_dma;
541 struct netdev_desc *rx_ring;
542 struct netdev_desc *tx_ring;
543 /* The addresses of receive-in-place skbuffs */
544 struct sk_buff *rx_skbuff[RX_RING_SIZE];
545 dma_addr_t rx_dma[RX_RING_SIZE];
546 /* address of a sent-in-place packet/buffer, for later free() */
547 struct sk_buff *tx_skbuff[TX_RING_SIZE];
548 dma_addr_t tx_dma[TX_RING_SIZE];
bea3348e
SH		 549 struct net_device *dev;
550 struct napi_struct napi;
1da177e4
LT		 551 struct net_device_stats stats;
552 /* Media monitoring timer */
553 struct timer_list timer;
554 /* Frequently used values: keep some adjacent for cache effect */
555 struct pci_dev *pci_dev;
556 struct netdev_desc *rx_head_desc;
557 /* Producer/consumer ring indices */
558 unsigned int cur_rx, dirty_rx;
559 unsigned int cur_tx, dirty_tx;
560 /* Based on MTU+slack. */
561 unsigned int rx_buf_sz;
562 int oom;
b27a16b7
MB		 563 /* Interrupt status */
564 u32 intr_status;
1da177e4
LT		 565 /* Do not touch the nic registers */
566 int hands_off;
68c90166
MB		 567 /* Don't pay attention to the reported link state. */
568 int ignore_phy;
1da177e4
LT		 569 /* external phy that is used: only valid if dev->if_port != PORT_TP */
570 int mii;
571 int phy_addr_external;
572 unsigned int full_duplex;
573 /* Rx filter */
574 u32 cur_rx_mode;
575 u32 rx_filter[16];
576 /* FIFO and PCI burst thresholds */
577 u32 tx_config, rx_config;
578 /* original contents of ClkRun register */
579 u32 SavedClkRun;
580 /* silicon revision */
581 u32 srr;
582 /* expected DSPCFG value */
583 u16 dspcfg;
1a147809 584 int dspcfg_workaround;
1da177e4
LT		 585 /* parms saved in ethtool format */
586 u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */
587 u8 duplex; /* Duplex, half or full */
588 u8 autoneg; /* Autonegotiation enabled */
589 /* MII transceiver section */
590 u16 advertising;
591 unsigned int iosize;
592 spinlock_t lock;
593 u32 msg_enable;
a8b4cf42
MB		 594 /* EEPROM data */
595 int eeprom_size;
1da177e4
LT		 596};
597
598static void move_int_phy(struct net_device *dev, int addr);
599static int eeprom_read(void __iomem *ioaddr, int location);
600static int mdio_read(struct net_device *dev, int reg);
601static void mdio_write(struct net_device *dev, int reg, u16 data);
602static void init_phy_fixup(struct net_device *dev);
603static int miiport_read(struct net_device *dev, int phy_id, int reg);
604static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data);
605static int find_mii(struct net_device *dev);
606static void natsemi_reset(struct net_device *dev);
607static void natsemi_reload_eeprom(struct net_device *dev);
608static void natsemi_stop_rxtx(struct net_device *dev);
609static int netdev_open(struct net_device *dev);
610static void do_cable_magic(struct net_device *dev);
611static void undo_cable_magic(struct net_device *dev);
612static void check_link(struct net_device *dev);
613static void netdev_timer(unsigned long data);
614static void dump_ring(struct net_device *dev);
ed4cb133 615static void ns_tx_timeout(struct net_device *dev);
1da177e4
LT		 616static int alloc_ring(struct net_device *dev);
617static void refill_rx(struct net_device *dev);
618static void init_ring(struct net_device *dev);
619static void drain_tx(struct net_device *dev);
620static void drain_ring(struct net_device *dev);
621static void free_ring(struct net_device *dev);
622static void reinit_ring(struct net_device *dev);
623static void init_registers(struct net_device *dev);
61357325 624static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
7d12e780 625static irqreturn_t intr_handler(int irq, void *dev_instance);
1da177e4 626static void netdev_error(struct net_device *dev, int intr_status);
bea3348e 627static int natsemi_poll(struct napi_struct *napi, int budget);
b27a16b7 628static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do);
1da177e4
LT		 629static void netdev_tx_done(struct net_device *dev);
630static int natsemi_change_mtu(struct net_device *dev, int new_mtu);
631#ifdef CONFIG_NET_POLL_CONTROLLER
632static void natsemi_poll_controller(struct net_device *dev);
633#endif
634static void __set_rx_mode(struct net_device *dev);
635static void set_rx_mode(struct net_device *dev);
636static void __get_stats(struct net_device *dev);
637static struct net_device_stats *get_stats(struct net_device *dev);
638static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
639static int netdev_set_wol(struct net_device *dev, u32 newval);
640static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur);
641static int netdev_set_sopass(struct net_device *dev, u8 *newval);
642static int netdev_get_sopass(struct net_device *dev, u8 *data);
643static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
644static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
645static void enable_wol_mode(struct net_device *dev, int enable_intr);
646static int netdev_close(struct net_device *dev);
647static int netdev_get_regs(struct net_device *dev, u8 *buf);
648static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
7282d491 649static const struct ethtool_ops ethtool_ops;
1da177e4 650
1a147809
MB		 651#define NATSEMI_ATTR(_name) \
652static ssize_t natsemi_show_##_name(struct device *dev, \
653 struct device_attribute *attr, char *buf); \
654 static ssize_t natsemi_set_##_name(struct device *dev, \
655 struct device_attribute *attr, \
656 const char *buf, size_t count); \
657 static DEVICE_ATTR(_name, 0644, natsemi_show_##_name, natsemi_set_##_name)
658
659#define NATSEMI_CREATE_FILE(_dev, _name) \
660 device_create_file(&_dev->dev, &dev_attr_##_name)
661#define NATSEMI_REMOVE_FILE(_dev, _name) \
f6c42865 662 device_remove_file(&_dev->dev, &dev_attr_##_name)
1a147809
MB		 663
664NATSEMI_ATTR(dspcfg_workaround);
665
666static ssize_t natsemi_show_dspcfg_workaround(struct device *dev,
7d2e3cb7 667 struct device_attribute *attr,
1a147809
MB		 668 char *buf)
669{
670 struct netdev_private *np = netdev_priv(to_net_dev(dev));
671
672 return sprintf(buf, "%s\n", np->dspcfg_workaround ? "on" : "off");
673}
674
675static ssize_t natsemi_set_dspcfg_workaround(struct device *dev,
676 struct device_attribute *attr,
677 const char *buf, size_t count)
678{
679 struct netdev_private *np = netdev_priv(to_net_dev(dev));
680 int new_setting;
d41f2d17 681 unsigned long flags;
1a147809
MB		 682
683 /* Find out the new setting */
684 if (!strncmp("on", buf, count - 1) || !strncmp("1", buf, count - 1))
685 new_setting = 1;
8e95a202
JP		 686 else if (!strncmp("off", buf, count - 1) ||
687 !strncmp("0", buf, count - 1))
1a147809
MB		 688 new_setting = 0;
689 else
7d2e3cb7 690 return count;
1a147809
MB		 691
692 spin_lock_irqsave(&np->lock, flags);
693
694 np->dspcfg_workaround = new_setting;
695
696 spin_unlock_irqrestore(&np->lock, flags);
697
698 return count;
699}
700
1da177e4
LT		 701static inline void __iomem *ns_ioaddr(struct net_device *dev)
702{
703 return (void __iomem *) dev->base_addr;
704}
705
b27a16b7
MB		 706static inline void natsemi_irq_enable(struct net_device *dev)
707{
708 writel(1, ns_ioaddr(dev) + IntrEnable);
709 readl(ns_ioaddr(dev) + IntrEnable);
710}
711
712static inline void natsemi_irq_disable(struct net_device *dev)
713{
714 writel(0, ns_ioaddr(dev) + IntrEnable);
715 readl(ns_ioaddr(dev) + IntrEnable);
716}
717
1da177e4
LT		 718static void move_int_phy(struct net_device *dev, int addr)
719{
720 struct netdev_private *np = netdev_priv(dev);
721 void __iomem *ioaddr = ns_ioaddr(dev);
722 int target = 31;
723
6aa20a22 724 /*
1da177e4
LT		 725 * The internal phy is visible on the external mii bus. Therefore we must
726 * move it away before we can send commands to an external phy.
727 * There are two addresses we must avoid:
728 * - the address on the external phy that is used for transmission.
729 * - the address that we want to access. User space can access phys
730 * on the mii bus with SIOCGMIIREG/SIOCSMIIREG, independant from the
731 * phy that is used for transmission.
732 */
733
734 if (target == addr)
735 target--;
736 if (target == np->phy_addr_external)
737 target--;
738 writew(target, ioaddr + PhyCtrl);
739 readw(ioaddr + PhyCtrl);
740 udelay(1);
741}
742
5a40f09b
JG		 743static void __devinit natsemi_init_media (struct net_device *dev)
744{
745 struct netdev_private *np = netdev_priv(dev);
746 u32 tmp;
747
68c90166
MB		 748 if (np->ignore_phy)
749 netif_carrier_on(dev);
750 else
751 netif_carrier_off(dev);
5a40f09b
JG		 752
753 /* get the initial settings from hardware */
754 tmp = mdio_read(dev, MII_BMCR);
755 np->speed = (tmp & BMCR_SPEED100)? SPEED_100 : SPEED_10;
756 np->duplex = (tmp & BMCR_FULLDPLX)? DUPLEX_FULL : DUPLEX_HALF;
757 np->autoneg = (tmp & BMCR_ANENABLE)? AUTONEG_ENABLE: AUTONEG_DISABLE;
758 np->advertising= mdio_read(dev, MII_ADVERTISE);
759
8e95a202
JP		 760 if ((np->advertising & ADVERTISE_ALL) != ADVERTISE_ALL &&
761 netif_msg_probe(np)) {
5a40f09b
JG		 762 printk(KERN_INFO "natsemi %s: Transceiver default autonegotiation %s "
763 "10%s %s duplex.\n",
764 pci_name(np->pci_dev),
765 (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE)?
766 "enabled, advertise" : "disabled, force",
767 (np->advertising &
768 (ADVERTISE_100FULL|ADVERTISE_100HALF))?
769 "0" : "",
770 (np->advertising &
771 (ADVERTISE_100FULL|ADVERTISE_10FULL))?
772 "full" : "half");
773 }
774 if (netif_msg_probe(np))
775 printk(KERN_INFO
776 "natsemi %s: Transceiver status %#04x advertising %#04x.\n",
777 pci_name(np->pci_dev), mdio_read(dev, MII_BMSR),
778 np->advertising);
779
780}
781
2b7d0c70
SH		 782static const struct net_device_ops natsemi_netdev_ops = {
783 .ndo_open = netdev_open,
784 .ndo_stop = netdev_close,
785 .ndo_start_xmit = start_tx,
786 .ndo_get_stats = get_stats,
787 .ndo_set_multicast_list = set_rx_mode,
788 .ndo_change_mtu = natsemi_change_mtu,
789 .ndo_do_ioctl = netdev_ioctl,
790 .ndo_tx_timeout = ns_tx_timeout,
791 .ndo_set_mac_address = eth_mac_addr,
792 .ndo_validate_addr = eth_validate_addr,
793#ifdef CONFIG_NET_POLL_CONTROLLER
794 .ndo_poll_controller = natsemi_poll_controller,
795#endif
796};
797
1da177e4
LT		 798static int __devinit natsemi_probe1 (struct pci_dev *pdev,
799 const struct pci_device_id *ent)
800{
801 struct net_device *dev;
802 struct netdev_private *np;
803 int i, option, irq, chip_idx = ent->driver_data;
804 static int find_cnt = -1;
703bb99c
SS		 805 resource_size_t iostart;
806 unsigned long iosize;
1da177e4
LT		 807 void __iomem *ioaddr;
808 const int pcibar = 1; /* PCI base address register */
809 int prev_eedata;
810 u32 tmp;
811
812/* when built into the kernel, we only print version if device is found */
813#ifndef MODULE
814 static int printed_version;
815 if (!printed_version++)
816 printk(version);
817#endif
818
819 i = pci_enable_device(pdev);
820 if (i) return i;
821
822 /* natsemi has a non-standard PM control register
823 * in PCI config space. Some boards apparently need
824 * to be brought to D0 in this manner.
825 */
826 pci_read_config_dword(pdev, PCIPM, &tmp);
827 if (tmp & PCI_PM_CTRL_STATE_MASK) {
828 /* D0 state, disable PME assertion */
829 u32 newtmp = tmp & ~PCI_PM_CTRL_STATE_MASK;
830 pci_write_config_dword(pdev, PCIPM, newtmp);
831 }
832
833 find_cnt++;
834 iostart = pci_resource_start(pdev, pcibar);
835 iosize = pci_resource_len(pdev, pcibar);
836 irq = pdev->irq;
837
a2b524b2 838 pci_set_master(pdev);
1da177e4
LT		 839
840 dev = alloc_etherdev(sizeof (struct netdev_private));
841 if (!dev)
842 return -ENOMEM;
1da177e4
LT		 843 SET_NETDEV_DEV(dev, &pdev->dev);
844
845 i = pci_request_regions(pdev, DRV_NAME);
846 if (i)
847 goto err_pci_request_regions;
848
849 ioaddr = ioremap(iostart, iosize);
850 if (!ioaddr) {
851 i = -ENOMEM;
852 goto err_ioremap;
853 }
854
855 /* Work around the dropped serial bit. */
856 prev_eedata = eeprom_read(ioaddr, 6);
857 for (i = 0; i < 3; i++) {
858 int eedata = eeprom_read(ioaddr, i + 7);
859 dev->dev_addr[i*2] = (eedata << 1) + (prev_eedata >> 15);
860 dev->dev_addr[i*2+1] = eedata >> 7;
861 prev_eedata = eedata;
862 }
863
864 dev->base_addr = (unsigned long __force) ioaddr;
865 dev->irq = irq;
866
867 np = netdev_priv(dev);
bea3348e 868 netif_napi_add(dev, &np->napi, natsemi_poll, 64);
bbbab5ca 869 np->dev = dev;
1da177e4
LT		 870
871 np->pci_dev = pdev;
872 pci_set_drvdata(pdev, dev);
873 np->iosize = iosize;
874 spin_lock_init(&np->lock);
875 np->msg_enable = (debug >= 0) ? (1<<debug)-1 : NATSEMI_DEF_MSG;
876 np->hands_off = 0;
b27a16b7 877 np->intr_status = 0;
a2b524b2 878 np->eeprom_size = natsemi_pci_info[chip_idx].eeprom_size;
6aab4447
MB		 879 if (natsemi_pci_info[chip_idx].flags & NATSEMI_FLAG_IGNORE_PHY)
880 np->ignore_phy = 1;
881 else
882 np->ignore_phy = 0;
1a147809 883 np->dspcfg_workaround = dspcfg_workaround;
1da177e4
LT		 884
885 /* Initial port:
68c90166 886 * - If configured to ignore the PHY set up for external.
1da177e4
LT		 887 * - If the nic was configured to use an external phy and if find_mii
888 * finds a phy: use external port, first phy that replies.
889 * - Otherwise: internal port.
890 * Note that the phy address for the internal phy doesn't matter:
891 * The address would be used to access a phy over the mii bus, but
892 * the internal phy is accessed through mapped registers.
893 */
68c90166 894 if (np->ignore_phy || readl(ioaddr + ChipConfig) & CfgExtPhy)
1da177e4
LT		 895 dev->if_port = PORT_MII;
896 else
897 dev->if_port = PORT_TP;
898 /* Reset the chip to erase previous misconfiguration. */
899 natsemi_reload_eeprom(dev);
900 natsemi_reset(dev);
901
902 if (dev->if_port != PORT_TP) {
903 np->phy_addr_external = find_mii(dev);
68c90166
MB		 904 /* If we're ignoring the PHY it doesn't matter if we can't
905 * find one. */
906 if (!np->ignore_phy && np->phy_addr_external == PHY_ADDR_NONE) {
1da177e4
LT		 907 dev->if_port = PORT_TP;
908 np->phy_addr_external = PHY_ADDR_INTERNAL;
909 }
910 } else {
911 np->phy_addr_external = PHY_ADDR_INTERNAL;
912 }
913
914 option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
915 if (dev->mem_start)
916 option = dev->mem_start;
917
918 /* The lower four bits are the media type. */
919 if (option) {
920 if (option & 0x200)
921 np->full_duplex = 1;
922 if (option & 15)
923 printk(KERN_INFO
924 "natsemi %s: ignoring user supplied media type %d",
925 pci_name(np->pci_dev), option & 15);
926 }
927 if (find_cnt < MAX_UNITS && full_duplex[find_cnt])
928 np->full_duplex = 1;
929
2b7d0c70 930 dev->netdev_ops = &natsemi_netdev_ops;
1da177e4 931 dev->watchdog_timeo = TX_TIMEOUT;
b27a16b7 932
1da177e4
LT		 933 SET_ETHTOOL_OPS(dev, &ethtool_ops);
934
935 if (mtu)
936 dev->mtu = mtu;
937
5a40f09b 938 natsemi_init_media(dev);
1da177e4
LT		 939
940 /* save the silicon revision for later querying */
941 np->srr = readl(ioaddr + SiliconRev);
942 if (netif_msg_hw(np))
943 printk(KERN_INFO "natsemi %s: silicon revision %#04x.\n",
944 pci_name(np->pci_dev), np->srr);
945
946 i = register_netdev(dev);
947 if (i)
948 goto err_register_netdev;
949
1a147809
MB		 950 if (NATSEMI_CREATE_FILE(pdev, dspcfg_workaround))
951 goto err_create_file;
952
1da177e4 953 if (netif_msg_drv(np)) {
703bb99c 954 printk(KERN_INFO "natsemi %s: %s at %#08llx "
e174961c 955 "(%s), %pM, IRQ %d",
703bb99c
SS		 956 dev->name, natsemi_pci_info[chip_idx].name,
957 (unsigned long long)iostart, pci_name(np->pci_dev),
e174961c 958 dev->dev_addr, irq);
1da177e4
LT		 959 if (dev->if_port == PORT_TP)
960 printk(", port TP.\n");
68c90166
MB		 961 else if (np->ignore_phy)
962 printk(", port MII, ignoring PHY\n");
1da177e4
LT		 963 else
964 printk(", port MII, phy ad %d.\n", np->phy_addr_external);
965 }
966 return 0;
967
1a147809
MB		 968 err_create_file:
969 unregister_netdev(dev);
970
1da177e4
LT		 971 err_register_netdev:
972 iounmap(ioaddr);
973
974 err_ioremap:
975 pci_release_regions(pdev);
976 pci_set_drvdata(pdev, NULL);
977
978 err_pci_request_regions:
979 free_netdev(dev);
980 return i;
981}
982
983
984/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
985 The EEPROM code is for the common 93c06/46 EEPROMs with 6 bit addresses. */
986
987/* Delay between EEPROM clock transitions.
988 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
989 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
990 made udelay() unreliable.
991 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is
405bbe9f 992 deprecated.
1da177e4
LT		 993*/
994#define eeprom_delay(ee_addr) readl(ee_addr)
995
996#define EE_Write0 (EE_ChipSelect)
997#define EE_Write1 (EE_ChipSelect | EE_DataIn)
998
999/* The EEPROM commands include the alway-set leading bit. */
1000enum EEPROM_Cmds {
1001 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
1002};
1003
1004static int eeprom_read(void __iomem *addr, int location)
1005{
1006 int i;
1007 int retval = 0;
1008 void __iomem *ee_addr = addr + EECtrl;
1009 int read_cmd = location | EE_ReadCmd;
1010
1011 writel(EE_Write0, ee_addr);
1012
1013 /* Shift the read command bits out. */
1014 for (i = 10; i >= 0; i--) {
1015 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
1016 writel(dataval, ee_addr);
1017 eeprom_delay(ee_addr);
1018 writel(dataval | EE_ShiftClk, ee_addr);
1019 eeprom_delay(ee_addr);
1020 }
1021 writel(EE_ChipSelect, ee_addr);
1022 eeprom_delay(ee_addr);
1023
1024 for (i = 0; i < 16; i++) {
1025 writel(EE_ChipSelect | EE_ShiftClk, ee_addr);
1026 eeprom_delay(ee_addr);
1027 retval |= (readl(ee_addr) & EE_DataOut) ? 1 << i : 0;
1028 writel(EE_ChipSelect, ee_addr);
1029 eeprom_delay(ee_addr);
1030 }
1031
1032 /* Terminate the EEPROM access. */
1033 writel(EE_Write0, ee_addr);
1034 writel(0, ee_addr);
1035 return retval;
1036}
1037
1038/* MII transceiver control section.
1039 * The 83815 series has an internal transceiver, and we present the
1040 * internal management registers as if they were MII connected.
1041 * External Phy registers are referenced through the MII interface.
1042 */
1043
1044/* clock transitions >= 20ns (25MHz)
1045 * One readl should be good to PCI @ 100MHz
1046 */
1047#define mii_delay(ioaddr) readl(ioaddr + EECtrl)
1048
1049static int mii_getbit (struct net_device *dev)
1050{
1051 int data;
1052 void __iomem *ioaddr = ns_ioaddr(dev);
1053
1054 writel(MII_ShiftClk, ioaddr + EECtrl);
1055 data = readl(ioaddr + EECtrl);
1056 writel(0, ioaddr + EECtrl);
1057 mii_delay(ioaddr);
1058 return (data & MII_Data)? 1 : 0;
1059}
1060
1061static void mii_send_bits (struct net_device *dev, u32 data, int len)
1062{
1063 u32 i;
1064 void __iomem *ioaddr = ns_ioaddr(dev);
1065
1066 for (i = (1 << (len-1)); i; i >>= 1)
1067 {
1068 u32 mdio_val = MII_Write | ((data & i)? MII_Data : 0);
1069 writel(mdio_val, ioaddr + EECtrl);
1070 mii_delay(ioaddr);
1071 writel(mdio_val | MII_ShiftClk, ioaddr + EECtrl);
1072 mii_delay(ioaddr);
1073 }
1074 writel(0, ioaddr + EECtrl);
1075 mii_delay(ioaddr);
1076}
1077
1078static int miiport_read(struct net_device *dev, int phy_id, int reg)
1079{
1080 u32 cmd;
1081 int i;
1082 u32 retval = 0;
1083
1084 /* Ensure sync */
1085 mii_send_bits (dev, 0xffffffff, 32);
1086 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1087 /* ST,OP = 0110'b for read operation */
1088 cmd = (0x06 << 10) | (phy_id << 5) | reg;
1089 mii_send_bits (dev, cmd, 14);
1090 /* Turnaround */
1091 if (mii_getbit (dev))
1092 return 0;
1093 /* Read data */
1094 for (i = 0; i < 16; i++) {
1095 retval <<= 1;
1096 retval |= mii_getbit (dev);
1097 }
1098 /* End cycle */
1099 mii_getbit (dev);
1100 return retval;
1101}
1102
1103static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data)
1104{
1105 u32 cmd;
1106
1107 /* Ensure sync */
1108 mii_send_bits (dev, 0xffffffff, 32);
1109 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1110 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1111 cmd = (0x5002 << 16) | (phy_id << 23) | (reg << 18) | data;
1112 mii_send_bits (dev, cmd, 32);
1113 /* End cycle */
1114 mii_getbit (dev);
1115}
1116
1117static int mdio_read(struct net_device *dev, int reg)
1118{
1119 struct netdev_private *np = netdev_priv(dev);
1120 void __iomem *ioaddr = ns_ioaddr(dev);
1121
1122 /* The 83815 series has two ports:
1123 * - an internal transceiver
1124 * - an external mii bus
1125 */
1126 if (dev->if_port == PORT_TP)
1127 return readw(ioaddr+BasicControl+(reg<<2));
1128 else
1129 return miiport_read(dev, np->phy_addr_external, reg);
1130}
1131
1132static void mdio_write(struct net_device *dev, int reg, u16 data)
1133{
1134 struct netdev_private *np = netdev_priv(dev);
1135 void __iomem *ioaddr = ns_ioaddr(dev);
1136
1137 /* The 83815 series has an internal transceiver; handle separately */
1138 if (dev->if_port == PORT_TP)
1139 writew(data, ioaddr+BasicControl+(reg<<2));
1140 else
1141 miiport_write(dev, np->phy_addr_external, reg, data);
1142}
1143
1144static void init_phy_fixup(struct net_device *dev)
1145{
1146 struct netdev_private *np = netdev_priv(dev);
1147 void __iomem *ioaddr = ns_ioaddr(dev);
1148 int i;
1149 u32 cfg;
1150 u16 tmp;
1151
1152 /* restore stuff lost when power was out */
1153 tmp = mdio_read(dev, MII_BMCR);
1154 if (np->autoneg == AUTONEG_ENABLE) {
1155 /* renegotiate if something changed */
8e95a202
JP		 1156 if ((tmp & BMCR_ANENABLE) == 0 ||
1157 np->advertising != mdio_read(dev, MII_ADVERTISE))
1da177e4
LT		 1158 {
1159 /* turn on autonegotiation and force negotiation */
1160 tmp |= (BMCR_ANENABLE | BMCR_ANRESTART);
1161 mdio_write(dev, MII_ADVERTISE, np->advertising);
1162 }
1163 } else {
1164 /* turn off auto negotiation, set speed and duplexity */
1165 tmp &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX);
1166 if (np->speed == SPEED_100)
1167 tmp |= BMCR_SPEED100;
1168 if (np->duplex == DUPLEX_FULL)
1169 tmp |= BMCR_FULLDPLX;
6aa20a22 1170 /*
1da177e4
LT		 1171 * Note: there is no good way to inform the link partner
1172 * that our capabilities changed. The user has to unplug
1173 * and replug the network cable after some changes, e.g.
1174 * after switching from 10HD, autoneg off to 100 HD,
1175 * autoneg off.
1176 */
1177 }
1178 mdio_write(dev, MII_BMCR, tmp);
1179 readl(ioaddr + ChipConfig);
1180 udelay(1);
1181
1182 /* find out what phy this is */
1183 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1184 + mdio_read(dev, MII_PHYSID2);
1185
1186 /* handle external phys here */
1187 switch (np->mii) {
1188 case PHYID_AM79C874:
1189 /* phy specific configuration for fibre/tp operation */
1190 tmp = mdio_read(dev, MII_MCTRL);
1191 tmp &= ~(MII_FX_SEL | MII_EN_SCRM);
1192 if (dev->if_port == PORT_FIBRE)
1193 tmp |= MII_FX_SEL;
1194 else
1195 tmp |= MII_EN_SCRM;
1196 mdio_write(dev, MII_MCTRL, tmp);
1197 break;
1198 default:
1199 break;
1200 }
1201 cfg = readl(ioaddr + ChipConfig);
1202 if (cfg & CfgExtPhy)
1203 return;
1204
1205 /* On page 78 of the spec, they recommend some settings for "optimum
1206 performance" to be done in sequence. These settings optimize some
1207 of the 100Mbit autodetection circuitry. They say we only want to
1208 do this for rev C of the chip, but engineers at NSC (Bradley
1209 Kennedy) recommends always setting them. If you don't, you get
1210 errors on some autonegotiations that make the device unusable.
1211
1212 It seems that the DSP needs a few usec to reinitialize after
1213 the start of the phy. Just retry writing these values until they
1214 stick.
1215 */
1216 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1217
1218 int dspcfg;
1219 writew(1, ioaddr + PGSEL);
1220 writew(PMDCSR_VAL, ioaddr + PMDCSR);
1221 writew(TSTDAT_VAL, ioaddr + TSTDAT);
1222 np->dspcfg = (np->srr <= SRR_DP83815_C)?
1223 DSPCFG_VAL : (DSPCFG_COEF | readw(ioaddr + DSPCFG));
1224 writew(np->dspcfg, ioaddr + DSPCFG);
1225 writew(SDCFG_VAL, ioaddr + SDCFG);
1226 writew(0, ioaddr + PGSEL);
1227 readl(ioaddr + ChipConfig);
1228 udelay(10);
1229
1230 writew(1, ioaddr + PGSEL);
1231 dspcfg = readw(ioaddr + DSPCFG);
1232 writew(0, ioaddr + PGSEL);
1233 if (np->dspcfg == dspcfg)
1234 break;
1235 }
1236
1237 if (netif_msg_link(np)) {
1238 if (i==NATSEMI_HW_TIMEOUT) {
1239 printk(KERN_INFO
1240 "%s: DSPCFG mismatch after retrying for %d usec.\n",
1241 dev->name, i*10);
1242 } else {
1243 printk(KERN_INFO
1244 "%s: DSPCFG accepted after %d usec.\n",
1245 dev->name, i*10);
1246 }
1247 }
1248 /*
1249 * Enable PHY Specific event based interrupts. Link state change
1250 * and Auto-Negotiation Completion are among the affected.
1251 * Read the intr status to clear it (needed for wake events).
1252 */
1253 readw(ioaddr + MIntrStatus);
1254 writew(MICRIntEn, ioaddr + MIntrCtrl);
1255}
1256
1257static int switch_port_external(struct net_device *dev)
1258{
1259 struct netdev_private *np = netdev_priv(dev);
1260 void __iomem *ioaddr = ns_ioaddr(dev);
1261 u32 cfg;
1262
1263 cfg = readl(ioaddr + ChipConfig);
1264 if (cfg & CfgExtPhy)
1265 return 0;
1266
1267 if (netif_msg_link(np)) {
1268 printk(KERN_INFO "%s: switching to external transceiver.\n",
1269 dev->name);
1270 }
1271
1272 /* 1) switch back to external phy */
1273 writel(cfg | (CfgExtPhy | CfgPhyDis), ioaddr + ChipConfig);
1274 readl(ioaddr + ChipConfig);
1275 udelay(1);
1276
1277 /* 2) reset the external phy: */
1278 /* resetting the external PHY has been known to cause a hub supplying
1279 * power over Ethernet to kill the power. We don't want to kill
1280 * power to this computer, so we avoid resetting the phy.
1281 */
1282
1283 /* 3) reinit the phy fixup, it got lost during power down. */
1284 move_int_phy(dev, np->phy_addr_external);
1285 init_phy_fixup(dev);
1286
1287 return 1;
1288}
1289
1290static int switch_port_internal(struct net_device *dev)
1291{
1292 struct netdev_private *np = netdev_priv(dev);
1293 void __iomem *ioaddr = ns_ioaddr(dev);
1294 int i;
1295 u32 cfg;
1296 u16 bmcr;
1297
1298 cfg = readl(ioaddr + ChipConfig);
1299 if (!(cfg &CfgExtPhy))
1300 return 0;
1301
1302 if (netif_msg_link(np)) {
1303 printk(KERN_INFO "%s: switching to internal transceiver.\n",
1304 dev->name);
1305 }
1306 /* 1) switch back to internal phy: */
1307 cfg = cfg & ~(CfgExtPhy | CfgPhyDis);
1308 writel(cfg, ioaddr + ChipConfig);
1309 readl(ioaddr + ChipConfig);
1310 udelay(1);
6aa20a22 1311
1da177e4
LT		 1312 /* 2) reset the internal phy: */
1313 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1314 writel(bmcr | BMCR_RESET, ioaddr+BasicControl+(MII_BMCR<<2));
1315 readl(ioaddr + ChipConfig);
1316 udelay(10);
1317 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1318 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1319 if (!(bmcr & BMCR_RESET))
1320 break;
1321 udelay(10);
1322 }
1323 if (i==NATSEMI_HW_TIMEOUT && netif_msg_link(np)) {
1324 printk(KERN_INFO
1325 "%s: phy reset did not complete in %d usec.\n",
1326 dev->name, i*10);
1327 }
1328 /* 3) reinit the phy fixup, it got lost during power down. */
1329 init_phy_fixup(dev);
1330
1331 return 1;
1332}
1333
1334/* Scan for a PHY on the external mii bus.
1335 * There are two tricky points:
1336 * - Do not scan while the internal phy is enabled. The internal phy will
1337 * crash: e.g. reads from the DSPCFG register will return odd values and
1338 * the nasty random phy reset code will reset the nic every few seconds.
1339 * - The internal phy must be moved around, an external phy could
1340 * have the same address as the internal phy.
1341 */
1342static int find_mii(struct net_device *dev)
1343{
1344 struct netdev_private *np = netdev_priv(dev);
1345 int tmp;
1346 int i;
1347 int did_switch;
1348
1349 /* Switch to external phy */
1350 did_switch = switch_port_external(dev);
6aa20a22 1351
1da177e4
LT		 1352 /* Scan the possible phy addresses:
1353 *
1354 * PHY address 0 means that the phy is in isolate mode. Not yet
1355 * supported due to lack of test hardware. User space should
1356 * handle it through ethtool.
1357 */
1358 for (i = 1; i <= 31; i++) {
1359 move_int_phy(dev, i);
1360 tmp = miiport_read(dev, i, MII_BMSR);
1361 if (tmp != 0xffff && tmp != 0x0000) {
1362 /* found something! */
1363 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1364 + mdio_read(dev, MII_PHYSID2);
1365 if (netif_msg_probe(np)) {
1366 printk(KERN_INFO "natsemi %s: found external phy %08x at address %d.\n",
1367 pci_name(np->pci_dev), np->mii, i);
1368 }
1369 break;
1370 }
1371 }
1372 /* And switch back to internal phy: */
1373 if (did_switch)
1374 switch_port_internal(dev);
1375 return i;
1376}
1377
1378/* CFG bits [13:16] [18:23] */
1379#define CFG_RESET_SAVE 0xfde000
1380/* WCSR bits [0:4] [9:10] */
1381#define WCSR_RESET_SAVE 0x61f
1382/* RFCR bits [20] [22] [27:31] */
1383#define RFCR_RESET_SAVE 0xf8500000;
1384
1385static void natsemi_reset(struct net_device *dev)
1386{
1387 int i;
1388 u32 cfg;
1389 u32 wcsr;
1390 u32 rfcr;
1391 u16 pmatch[3];
1392 u16 sopass[3];
1393 struct netdev_private *np = netdev_priv(dev);
1394 void __iomem *ioaddr = ns_ioaddr(dev);
1395
1396 /*
1397 * Resetting the chip causes some registers to be lost.
1398 * Natsemi suggests NOT reloading the EEPROM while live, so instead
1399 * we save the state that would have been loaded from EEPROM
1400 * on a normal power-up (see the spec EEPROM map). This assumes
1401 * whoever calls this will follow up with init_registers() eventually.
1402 */
1403
1404 /* CFG */
1405 cfg = readl(ioaddr + ChipConfig) & CFG_RESET_SAVE;
1406 /* WCSR */
1407 wcsr = readl(ioaddr + WOLCmd) & WCSR_RESET_SAVE;
1408 /* RFCR */
1409 rfcr = readl(ioaddr + RxFilterAddr) & RFCR_RESET_SAVE;
1410 /* PMATCH */
1411 for (i = 0; i < 3; i++) {
1412 writel(i*2, ioaddr + RxFilterAddr);
1413 pmatch[i] = readw(ioaddr + RxFilterData);
1414 }
1415 /* SOPAS */
1416 for (i = 0; i < 3; i++) {
1417 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1418 sopass[i] = readw(ioaddr + RxFilterData);
1419 }
1420
1421 /* now whack the chip */
1422 writel(ChipReset, ioaddr + ChipCmd);
1423 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1424 if (!(readl(ioaddr + ChipCmd) & ChipReset))
1425 break;
1426 udelay(5);
1427 }
1428 if (i==NATSEMI_HW_TIMEOUT) {
1429 printk(KERN_WARNING "%s: reset did not complete in %d usec.\n",
1430 dev->name, i*5);
1431 } else if (netif_msg_hw(np)) {
1432 printk(KERN_DEBUG "%s: reset completed in %d usec.\n",
1433 dev->name, i*5);
1434 }
1435
1436 /* restore CFG */
1437 cfg |= readl(ioaddr + ChipConfig) & ~CFG_RESET_SAVE;
1438 /* turn on external phy if it was selected */
1439 if (dev->if_port == PORT_TP)
1440 cfg &= ~(CfgExtPhy | CfgPhyDis);
1441 else
1442 cfg |= (CfgExtPhy | CfgPhyDis);
1443 writel(cfg, ioaddr + ChipConfig);
1444 /* restore WCSR */
1445 wcsr |= readl(ioaddr + WOLCmd) & ~WCSR_RESET_SAVE;
1446 writel(wcsr, ioaddr + WOLCmd);
1447 /* read RFCR */
1448 rfcr |= readl(ioaddr + RxFilterAddr) & ~RFCR_RESET_SAVE;
1449 /* restore PMATCH */
1450 for (i = 0; i < 3; i++) {
1451 writel(i*2, ioaddr + RxFilterAddr);
1452 writew(pmatch[i], ioaddr + RxFilterData);
1453 }
1454 for (i = 0; i < 3; i++) {
1455 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1456 writew(sopass[i], ioaddr + RxFilterData);
1457 }
1458 /* restore RFCR */
1459 writel(rfcr, ioaddr + RxFilterAddr);
1460}
1461
e72fd96e
MB		 1462static void reset_rx(struct net_device *dev)
1463{
1464 int i;
1465 struct netdev_private *np = netdev_priv(dev);
1466 void __iomem *ioaddr = ns_ioaddr(dev);
1467
1468 np->intr_status &= ~RxResetDone;
1469
1470 writel(RxReset, ioaddr + ChipCmd);
1471
1472 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1473 np->intr_status |= readl(ioaddr + IntrStatus);
1474 if (np->intr_status & RxResetDone)
1475 break;
1476 udelay(15);
1477 }
1478 if (i==NATSEMI_HW_TIMEOUT) {
1479 printk(KERN_WARNING "%s: RX reset did not complete in %d usec.\n",
1480 dev->name, i*15);
1481 } else if (netif_msg_hw(np)) {
1482 printk(KERN_WARNING "%s: RX reset took %d usec.\n",
1483 dev->name, i*15);
1484 }
1485}
1486
1da177e4
LT		 1487static void natsemi_reload_eeprom(struct net_device *dev)
1488{
1489 struct netdev_private *np = netdev_priv(dev);
1490 void __iomem *ioaddr = ns_ioaddr(dev);
1491 int i;
1492
1493 writel(EepromReload, ioaddr + PCIBusCfg);
1494 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1495 udelay(50);
1496 if (!(readl(ioaddr + PCIBusCfg) & EepromReload))
1497 break;
1498 }
1499 if (i==NATSEMI_HW_TIMEOUT) {
1500 printk(KERN_WARNING "natsemi %s: EEPROM did not reload in %d usec.\n",
1501 pci_name(np->pci_dev), i*50);
1502 } else if (netif_msg_hw(np)) {
1503 printk(KERN_DEBUG "natsemi %s: EEPROM reloaded in %d usec.\n",
1504 pci_name(np->pci_dev), i*50);
1505 }
1506}
1507
1508static void natsemi_stop_rxtx(struct net_device *dev)
1509{
1510 void __iomem * ioaddr = ns_ioaddr(dev);
1511 struct netdev_private *np = netdev_priv(dev);
1512 int i;
1513
1514 writel(RxOff | TxOff, ioaddr + ChipCmd);
1515 for(i=0;i< NATSEMI_HW_TIMEOUT;i++) {
1516 if ((readl(ioaddr + ChipCmd) & (TxOn|RxOn)) == 0)
1517 break;
1518 udelay(5);
1519 }
1520 if (i==NATSEMI_HW_TIMEOUT) {
1521 printk(KERN_WARNING "%s: Tx/Rx process did not stop in %d usec.\n",
1522 dev->name, i*5);
1523 } else if (netif_msg_hw(np)) {
1524 printk(KERN_DEBUG "%s: Tx/Rx process stopped in %d usec.\n",
1525 dev->name, i*5);
1526 }
1527}
1528
1529static int netdev_open(struct net_device *dev)
1530{
1531 struct netdev_private *np = netdev_priv(dev);
1532 void __iomem * ioaddr = ns_ioaddr(dev);
1533 int i;
1534
1535 /* Reset the chip, just in case. */
1536 natsemi_reset(dev);
1537
a0607fd3 1538 i = request_irq(dev->irq, intr_handler, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 1539 if (i) return i;
1540
1541 if (netif_msg_ifup(np))
1542 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
1543 dev->name, dev->irq);
1544 i = alloc_ring(dev);
1545 if (i < 0) {
1546 free_irq(dev->irq, dev);
1547 return i;
1548 }
bea3348e
SH		 1549 napi_enable(&np->napi);
1550
1da177e4
LT		 1551 init_ring(dev);
1552 spin_lock_irq(&np->lock);
1553 init_registers(dev);
1554 /* now set the MAC address according to dev->dev_addr */
1555 for (i = 0; i < 3; i++) {
1556 u16 mac = (dev->dev_addr[2*i+1]<<8) + dev->dev_addr[2*i];
1557
1558 writel(i*2, ioaddr + RxFilterAddr);
1559 writew(mac, ioaddr + RxFilterData);
1560 }
1561 writel(np->cur_rx_mode, ioaddr + RxFilterAddr);
1562 spin_unlock_irq(&np->lock);
1563
1564 netif_start_queue(dev);
1565
1566 if (netif_msg_ifup(np))
1567 printk(KERN_DEBUG "%s: Done netdev_open(), status: %#08x.\n",
1568 dev->name, (int)readl(ioaddr + ChipCmd));
1569
1570 /* Set the timer to check for link beat. */
1571 init_timer(&np->timer);
0e5d5442 1572 np->timer.expires = round_jiffies(jiffies + NATSEMI_TIMER_FREQ);
1da177e4
LT		 1573 np->timer.data = (unsigned long)dev;
1574 np->timer.function = &netdev_timer; /* timer handler */
1575 add_timer(&np->timer);
1576
1577 return 0;
1578}
1579
1580static void do_cable_magic(struct net_device *dev)
1581{
1582 struct netdev_private *np = netdev_priv(dev);
1583 void __iomem *ioaddr = ns_ioaddr(dev);
1584
1585 if (dev->if_port != PORT_TP)
1586 return;
1587
1588 if (np->srr >= SRR_DP83816_A5)
1589 return;
1590
1591 /*
1592 * 100 MBit links with short cables can trip an issue with the chip.
1593 * The problem manifests as lots of CRC errors and/or flickering
1594 * activity LED while idle. This process is based on instructions
1595 * from engineers at National.
1596 */
1597 if (readl(ioaddr + ChipConfig) & CfgSpeed100) {
1598 u16 data;
1599
1600 writew(1, ioaddr + PGSEL);
1601 /*
1602 * coefficient visibility should already be enabled via
1603 * DSPCFG | 0x1000
1604 */
1605 data = readw(ioaddr + TSTDAT) & 0xff;
1606 /*
1607 * the value must be negative, and within certain values
1608 * (these values all come from National)
1609 */
1610 if (!(data & 0x80) || ((data >= 0xd8) && (data <= 0xff))) {
ddfce6bb 1611 np = netdev_priv(dev);
1da177e4
LT		 1612
1613 /* the bug has been triggered - fix the coefficient */
1614 writew(TSTDAT_FIXED, ioaddr + TSTDAT);
1615 /* lock the value */
1616 data = readw(ioaddr + DSPCFG);
1617 np->dspcfg = data | DSPCFG_LOCK;
1618 writew(np->dspcfg, ioaddr + DSPCFG);
1619 }
1620 writew(0, ioaddr + PGSEL);
1621 }
1622}
1623
1624static void undo_cable_magic(struct net_device *dev)
1625{
1626 u16 data;
1627 struct netdev_private *np = netdev_priv(dev);
1628 void __iomem * ioaddr = ns_ioaddr(dev);
1629
1630 if (dev->if_port != PORT_TP)
1631 return;
1632
1633 if (np->srr >= SRR_DP83816_A5)
1634 return;
1635
1636 writew(1, ioaddr + PGSEL);
1637 /* make sure the lock bit is clear */
1638 data = readw(ioaddr + DSPCFG);
1639 np->dspcfg = data & ~DSPCFG_LOCK;
1640 writew(np->dspcfg, ioaddr + DSPCFG);
1641 writew(0, ioaddr + PGSEL);
1642}
1643
1644static void check_link(struct net_device *dev)
1645{
1646 struct netdev_private *np = netdev_priv(dev);
1647 void __iomem * ioaddr = ns_ioaddr(dev);
68c90166 1648 int duplex = np->duplex;
1da177e4 1649 u16 bmsr;
6aa20a22 1650
68c90166
MB		 1651 /* If we are ignoring the PHY then don't try reading it. */
1652 if (np->ignore_phy)
1653 goto propagate_state;
1654
1da177e4
LT		 1655 /* The link status field is latched: it remains low after a temporary
1656 * link failure until it's read. We need the current link status,
1657 * thus read twice.
1658 */
1659 mdio_read(dev, MII_BMSR);
1660 bmsr = mdio_read(dev, MII_BMSR);
1661
1662 if (!(bmsr & BMSR_LSTATUS)) {
1663 if (netif_carrier_ok(dev)) {
1664 if (netif_msg_link(np))
1665 printk(KERN_NOTICE "%s: link down.\n",
68c90166 1666 dev->name);
1da177e4
LT		 1667 netif_carrier_off(dev);
1668 undo_cable_magic(dev);
1669 }
1670 return;
1671 }
1672 if (!netif_carrier_ok(dev)) {
1673 if (netif_msg_link(np))
1674 printk(KERN_NOTICE "%s: link up.\n", dev->name);
1675 netif_carrier_on(dev);
1676 do_cable_magic(dev);
1677 }
1678
1679 duplex = np->full_duplex;
1680 if (!duplex) {
1681 if (bmsr & BMSR_ANEGCOMPLETE) {
1682 int tmp = mii_nway_result(
1683 np->advertising & mdio_read(dev, MII_LPA));
1684 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
1685 duplex = 1;
1686 } else if (mdio_read(dev, MII_BMCR) & BMCR_FULLDPLX)
1687 duplex = 1;
1688 }
1689
68c90166 1690propagate_state:
1da177e4
LT		 1691 /* if duplex is set then bit 28 must be set, too */
1692 if (duplex ^ !!(np->rx_config & RxAcceptTx)) {
1693 if (netif_msg_link(np))
1694 printk(KERN_INFO
1695 "%s: Setting %s-duplex based on negotiated "
1696 "link capability.\n", dev->name,
1697 duplex ? "full" : "half");
1698 if (duplex) {
1699 np->rx_config |= RxAcceptTx;
1700 np->tx_config |= TxCarrierIgn | TxHeartIgn;
1701 } else {
1702 np->rx_config &= ~RxAcceptTx;
1703 np->tx_config &= ~(TxCarrierIgn | TxHeartIgn);
1704 }
1705 writel(np->tx_config, ioaddr + TxConfig);
1706 writel(np->rx_config, ioaddr + RxConfig);
1707 }
1708}
1709
1710static void init_registers(struct net_device *dev)
1711{
1712 struct netdev_private *np = netdev_priv(dev);
1713 void __iomem * ioaddr = ns_ioaddr(dev);
1714
1715 init_phy_fixup(dev);
1716
1717 /* clear any interrupts that are pending, such as wake events */
1718 readl(ioaddr + IntrStatus);
1719
1720 writel(np->ring_dma, ioaddr + RxRingPtr);
1721 writel(np->ring_dma + RX_RING_SIZE * sizeof(struct netdev_desc),
1722 ioaddr + TxRingPtr);
1723
1724 /* Initialize other registers.
1725 * Configure the PCI bus bursts and FIFO thresholds.
1726 * Configure for standard, in-spec Ethernet.
1727 * Start with half-duplex. check_link will update
1728 * to the correct settings.
1729 */
1730
1731 /* DRTH: 2: start tx if 64 bytes are in the fifo
1732 * FLTH: 0x10: refill with next packet if 512 bytes are free
1733 * MXDMA: 0: up to 256 byte bursts.
1734 * MXDMA must be <= FLTH
1735 * ECRETRY=1
1736 * ATP=1
1737 */
1738 np->tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 |
1739 TX_FLTH_VAL | TX_DRTH_VAL_START;
1740 writel(np->tx_config, ioaddr + TxConfig);
1741
1742 /* DRTH 0x10: start copying to memory if 128 bytes are in the fifo
1743 * MXDMA 0: up to 256 byte bursts
1744 */
1745 np->rx_config = RxMxdma_256 | RX_DRTH_VAL;
1746 /* if receive ring now has bigger buffers than normal, enable jumbo */
1747 if (np->rx_buf_sz > NATSEMI_LONGPKT)
1748 np->rx_config |= RxAcceptLong;
1749
1750 writel(np->rx_config, ioaddr + RxConfig);
1751
1752 /* Disable PME:
1753 * The PME bit is initialized from the EEPROM contents.
1754 * PCI cards probably have PME disabled, but motherboard
1755 * implementations may have PME set to enable WakeOnLan.
1756 * With PME set the chip will scan incoming packets but
1757 * nothing will be written to memory. */
1758 np->SavedClkRun = readl(ioaddr + ClkRun);
1759 writel(np->SavedClkRun & ~PMEEnable, ioaddr + ClkRun);
1760 if (np->SavedClkRun & PMEStatus && netif_msg_wol(np)) {
1761 printk(KERN_NOTICE "%s: Wake-up event %#08x\n",
1762 dev->name, readl(ioaddr + WOLCmd));
1763 }
1764
1765 check_link(dev);
1766 __set_rx_mode(dev);
1767
1768 /* Enable interrupts by setting the interrupt mask. */
1769 writel(DEFAULT_INTR, ioaddr + IntrMask);
14fdd90e 1770 natsemi_irq_enable(dev);
1da177e4
LT		 1771
1772 writel(RxOn | TxOn, ioaddr + ChipCmd);
1773 writel(StatsClear, ioaddr + StatsCtrl); /* Clear Stats */
1774}
1775
1776/*
1777 * netdev_timer:
1778 * Purpose:
1779 * 1) check for link changes. Usually they are handled by the MII interrupt
1780 * but it doesn't hurt to check twice.
1781 * 2) check for sudden death of the NIC:
1782 * It seems that a reference set for this chip went out with incorrect info,
1783 * and there exist boards that aren't quite right. An unexpected voltage
1784 * drop can cause the PHY to get itself in a weird state (basically reset).
1a147809
MB		 1785 * NOTE: this only seems to affect revC chips. The user can disable
1786 * this check via dspcfg_workaround sysfs option.
1da177e4
LT		 1787 * 3) check of death of the RX path due to OOM
1788 */
1789static void netdev_timer(unsigned long data)
1790{
1791 struct net_device *dev = (struct net_device *)data;
1792 struct netdev_private *np = netdev_priv(dev);
1793 void __iomem * ioaddr = ns_ioaddr(dev);
f2cade13 1794 int next_tick = NATSEMI_TIMER_FREQ;
1da177e4
LT		 1795
1796 if (netif_msg_timer(np)) {
1797 /* DO NOT read the IntrStatus register,
1798 * a read clears any pending interrupts.
1799 */
1800 printk(KERN_DEBUG "%s: Media selection timer tick.\n",
1801 dev->name);
1802 }
1803
1804 if (dev->if_port == PORT_TP) {
1805 u16 dspcfg;
1806
1807 spin_lock_irq(&np->lock);
1808 /* check for a nasty random phy-reset - use dspcfg as a flag */
1809 writew(1, ioaddr+PGSEL);
1810 dspcfg = readw(ioaddr+DSPCFG);
1811 writew(0, ioaddr+PGSEL);
1a147809 1812 if (np->dspcfg_workaround && dspcfg != np->dspcfg) {
1da177e4
LT		 1813 if (!netif_queue_stopped(dev)) {
1814 spin_unlock_irq(&np->lock);
d0ed4864 1815 if (netif_msg_drv(np))
1da177e4
LT		 1816 printk(KERN_NOTICE "%s: possible phy reset: "
1817 "re-initializing\n", dev->name);
1818 disable_irq(dev->irq);
1819 spin_lock_irq(&np->lock);
1820 natsemi_stop_rxtx(dev);
1821 dump_ring(dev);
1822 reinit_ring(dev);
1823 init_registers(dev);
1824 spin_unlock_irq(&np->lock);
1825 enable_irq(dev->irq);
1826 } else {
1827 /* hurry back */
1828 next_tick = HZ;
1829 spin_unlock_irq(&np->lock);
1830 }
1831 } else {
1832 /* init_registers() calls check_link() for the above case */
1833 check_link(dev);
1834 spin_unlock_irq(&np->lock);
1835 }
1836 } else {
1837 spin_lock_irq(&np->lock);
1838 check_link(dev);
1839 spin_unlock_irq(&np->lock);
1840 }
1841 if (np->oom) {
1842 disable_irq(dev->irq);
1843 np->oom = 0;
1844 refill_rx(dev);
1845 enable_irq(dev->irq);
1846 if (!np->oom) {
1847 writel(RxOn, ioaddr + ChipCmd);
1848 } else {
1849 next_tick = 1;
1850 }
1851 }
0e5d5442
MB		 1852
1853 if (next_tick > 1)
1854 mod_timer(&np->timer, round_jiffies(jiffies + next_tick));
1855 else
1856 mod_timer(&np->timer, jiffies + next_tick);
1da177e4
LT		 1857}
1858
1859static void dump_ring(struct net_device *dev)
1860{
1861 struct netdev_private *np = netdev_priv(dev);
1862
1863 if (netif_msg_pktdata(np)) {
1864 int i;
1865 printk(KERN_DEBUG " Tx ring at %p:\n", np->tx_ring);
1866 for (i = 0; i < TX_RING_SIZE; i++) {
1867 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1868 i, np->tx_ring[i].next_desc,
1869 np->tx_ring[i].cmd_status,
1870 np->tx_ring[i].addr);
1871 }
1872 printk(KERN_DEBUG " Rx ring %p:\n", np->rx_ring);
1873 for (i = 0; i < RX_RING_SIZE; i++) {
1874 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1875 i, np->rx_ring[i].next_desc,
1876 np->rx_ring[i].cmd_status,
1877 np->rx_ring[i].addr);
1878 }
1879 }
1880}
1881
ed4cb133 1882static void ns_tx_timeout(struct net_device *dev)
1da177e4
LT		 1883{
1884 struct netdev_private *np = netdev_priv(dev);
1885 void __iomem * ioaddr = ns_ioaddr(dev);
1886
1887 disable_irq(dev->irq);
1888 spin_lock_irq(&np->lock);
1889 if (!np->hands_off) {
1890 if (netif_msg_tx_err(np))
1891 printk(KERN_WARNING
1892 "%s: Transmit timed out, status %#08x,"
1893 " resetting...\n",
1894 dev->name, readl(ioaddr + IntrStatus));
1895 dump_ring(dev);
1896
1897 natsemi_reset(dev);
1898 reinit_ring(dev);
1899 init_registers(dev);
1900 } else {
1901 printk(KERN_WARNING
1902 "%s: tx_timeout while in hands_off state?\n",
1903 dev->name);
1904 }
1905 spin_unlock_irq(&np->lock);
1906 enable_irq(dev->irq);
1907
1ae5dc34 1908 dev->trans_start = jiffies; /* prevent tx timeout */
1da177e4
LT		 1909 np->stats.tx_errors++;
1910 netif_wake_queue(dev);
1911}
1912
1913static int alloc_ring(struct net_device *dev)
1914{
1915 struct netdev_private *np = netdev_priv(dev);
1916 np->rx_ring = pci_alloc_consistent(np->pci_dev,
1917 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
1918 &np->ring_dma);
1919 if (!np->rx_ring)
1920 return -ENOMEM;
1921 np->tx_ring = &np->rx_ring[RX_RING_SIZE];
1922 return 0;
1923}
1924
1925static void refill_rx(struct net_device *dev)
1926{
1927 struct netdev_private *np = netdev_priv(dev);
1928
1929 /* Refill the Rx ring buffers. */
1930 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1931 struct sk_buff *skb;
1932 int entry = np->dirty_rx % RX_RING_SIZE;
1933 if (np->rx_skbuff[entry] == NULL) {
1934 unsigned int buflen = np->rx_buf_sz+NATSEMI_PADDING;
1935 skb = dev_alloc_skb(buflen);
1936 np->rx_skbuff[entry] = skb;
1937 if (skb == NULL)
1938 break; /* Better luck next round. */
1939 skb->dev = dev; /* Mark as being used by this device. */
1940 np->rx_dma[entry] = pci_map_single(np->pci_dev,
689be439 1941 skb->data, buflen, PCI_DMA_FROMDEVICE);
1da177e4
LT		 1942 np->rx_ring[entry].addr = cpu_to_le32(np->rx_dma[entry]);
1943 }
1944 np->rx_ring[entry].cmd_status = cpu_to_le32(np->rx_buf_sz);
1945 }
1946 if (np->cur_rx - np->dirty_rx == RX_RING_SIZE) {
1947 if (netif_msg_rx_err(np))
1948 printk(KERN_WARNING "%s: going OOM.\n", dev->name);
1949 np->oom = 1;
1950 }
1951}
1952
1953static void set_bufsize(struct net_device *dev)
1954{
1955 struct netdev_private *np = netdev_priv(dev);
1956 if (dev->mtu <= ETH_DATA_LEN)
1957 np->rx_buf_sz = ETH_DATA_LEN + NATSEMI_HEADERS;
1958 else
1959 np->rx_buf_sz = dev->mtu + NATSEMI_HEADERS;
1960}
1961
1962/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1963static void init_ring(struct net_device *dev)
1964{
1965 struct netdev_private *np = netdev_priv(dev);
1966 int i;
1967
1968 /* 1) TX ring */
1969 np->dirty_tx = np->cur_tx = 0;
1970 for (i = 0; i < TX_RING_SIZE; i++) {
1971 np->tx_skbuff[i] = NULL;
1972 np->tx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1973 +sizeof(struct netdev_desc)
1974 *((i+1)%TX_RING_SIZE+RX_RING_SIZE));
1975 np->tx_ring[i].cmd_status = 0;
1976 }
1977
1978 /* 2) RX ring */
1979 np->dirty_rx = 0;
1980 np->cur_rx = RX_RING_SIZE;
1981 np->oom = 0;
1982 set_bufsize(dev);
1983
1984 np->rx_head_desc = &np->rx_ring[0];
1985
1986 /* Please be carefull before changing this loop - at least gcc-2.95.1
1987 * miscompiles it otherwise.
1988 */
1989 /* Initialize all Rx descriptors. */
1990 for (i = 0; i < RX_RING_SIZE; i++) {
1991 np->rx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1992 +sizeof(struct netdev_desc)
1993 *((i+1)%RX_RING_SIZE));
1994 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
1995 np->rx_skbuff[i] = NULL;
1996 }
1997 refill_rx(dev);
1998 dump_ring(dev);
1999}
2000
2001static void drain_tx(struct net_device *dev)
2002{
2003 struct netdev_private *np = netdev_priv(dev);
2004 int i;
2005
2006 for (i = 0; i < TX_RING_SIZE; i++) {
2007 if (np->tx_skbuff[i]) {
2008 pci_unmap_single(np->pci_dev,
2009 np->tx_dma[i], np->tx_skbuff[i]->len,
2010 PCI_DMA_TODEVICE);
2011 dev_kfree_skb(np->tx_skbuff[i]);
2012 np->stats.tx_dropped++;
2013 }
2014 np->tx_skbuff[i] = NULL;
2015 }
2016}
2017
2018static void drain_rx(struct net_device *dev)
2019{
2020 struct netdev_private *np = netdev_priv(dev);
2021 unsigned int buflen = np->rx_buf_sz;
2022 int i;
2023
2024 /* Free all the skbuffs in the Rx queue. */
2025 for (i = 0; i < RX_RING_SIZE; i++) {
2026 np->rx_ring[i].cmd_status = 0;
eca1ad82 2027 np->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1da177e4
LT		 2028 if (np->rx_skbuff[i]) {
2029 pci_unmap_single(np->pci_dev,
2030 np->rx_dma[i], buflen,
2031 PCI_DMA_FROMDEVICE);
2032 dev_kfree_skb(np->rx_skbuff[i]);
2033 }
2034 np->rx_skbuff[i] = NULL;
2035 }
2036}
2037
2038static void drain_ring(struct net_device *dev)
2039{
2040 drain_rx(dev);
2041 drain_tx(dev);
2042}
2043
2044static void free_ring(struct net_device *dev)
2045{
2046 struct netdev_private *np = netdev_priv(dev);
2047 pci_free_consistent(np->pci_dev,
2048 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
2049 np->rx_ring, np->ring_dma);
2050}
2051
2052static void reinit_rx(struct net_device *dev)
2053{
2054 struct netdev_private *np = netdev_priv(dev);
2055 int i;
2056
2057 /* RX Ring */
2058 np->dirty_rx = 0;
2059 np->cur_rx = RX_RING_SIZE;
2060 np->rx_head_desc = &np->rx_ring[0];
2061 /* Initialize all Rx descriptors. */
2062 for (i = 0; i < RX_RING_SIZE; i++)
2063 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
2064
2065 refill_rx(dev);
2066}
2067
2068static void reinit_ring(struct net_device *dev)
2069{
2070 struct netdev_private *np = netdev_priv(dev);
2071 int i;
2072
2073 /* drain TX ring */
2074 drain_tx(dev);
2075 np->dirty_tx = np->cur_tx = 0;
2076 for (i=0;i<TX_RING_SIZE;i++)
2077 np->tx_ring[i].cmd_status = 0;
2078
2079 reinit_rx(dev);
2080}
2081
61357325 2082static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 2083{
2084 struct netdev_private *np = netdev_priv(dev);
2085 void __iomem * ioaddr = ns_ioaddr(dev);
2086 unsigned entry;
6006f7f5 2087 unsigned long flags;
1da177e4
LT		 2088
2089 /* Note: Ordering is important here, set the field with the
2090 "ownership" bit last, and only then increment cur_tx. */
2091
2092 /* Calculate the next Tx descriptor entry. */
2093 entry = np->cur_tx % TX_RING_SIZE;
2094
2095 np->tx_skbuff[entry] = skb;
2096 np->tx_dma[entry] = pci_map_single(np->pci_dev,
2097 skb->data,skb->len, PCI_DMA_TODEVICE);
2098
2099 np->tx_ring[entry].addr = cpu_to_le32(np->tx_dma[entry]);
2100
6006f7f5 2101 spin_lock_irqsave(&np->lock, flags);
1da177e4
LT		 2102
2103 if (!np->hands_off) {
2104 np->tx_ring[entry].cmd_status = cpu_to_le32(DescOwn | skb->len);
2105 /* StrongARM: Explicitly cache flush np->tx_ring and
2106 * skb->data,skb->len. */
2107 wmb();
2108 np->cur_tx++;
2109 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) {
2110 netdev_tx_done(dev);
2111 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1)
2112 netif_stop_queue(dev);
2113 }
2114 /* Wake the potentially-idle transmit channel. */
2115 writel(TxOn, ioaddr + ChipCmd);
2116 } else {
2117 dev_kfree_skb_irq(skb);
2118 np->stats.tx_dropped++;
2119 }
6006f7f5 2120 spin_unlock_irqrestore(&np->lock, flags);
1da177e4 2121
1da177e4
LT		 2122 if (netif_msg_tx_queued(np)) {
2123 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
2124 dev->name, np->cur_tx, entry);
2125 }
6ed10654 2126 return NETDEV_TX_OK;
1da177e4
LT		 2127}
2128
2129static void netdev_tx_done(struct net_device *dev)
2130{
2131 struct netdev_private *np = netdev_priv(dev);
2132
2133 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
2134 int entry = np->dirty_tx % TX_RING_SIZE;
2135 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescOwn))
2136 break;
2137 if (netif_msg_tx_done(np))
2138 printk(KERN_DEBUG
2139 "%s: tx frame #%d finished, status %#08x.\n",
2140 dev->name, np->dirty_tx,
2141 le32_to_cpu(np->tx_ring[entry].cmd_status));
2142 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescPktOK)) {
2143 np->stats.tx_packets++;
2144 np->stats.tx_bytes += np->tx_skbuff[entry]->len;
2145 } else { /* Various Tx errors */
2146 int tx_status =
2147 le32_to_cpu(np->tx_ring[entry].cmd_status);
2148 if (tx_status & (DescTxAbort|DescTxExcColl))
2149 np->stats.tx_aborted_errors++;
2150 if (tx_status & DescTxFIFO)
2151 np->stats.tx_fifo_errors++;
2152 if (tx_status & DescTxCarrier)
2153 np->stats.tx_carrier_errors++;
2154 if (tx_status & DescTxOOWCol)
2155 np->stats.tx_window_errors++;
2156 np->stats.tx_errors++;
2157 }
2158 pci_unmap_single(np->pci_dev,np->tx_dma[entry],
2159 np->tx_skbuff[entry]->len,
2160 PCI_DMA_TODEVICE);
2161 /* Free the original skb. */
2162 dev_kfree_skb_irq(np->tx_skbuff[entry]);
2163 np->tx_skbuff[entry] = NULL;
2164 }
8e95a202
JP		 2165 if (netif_queue_stopped(dev) &&
2166 np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
1da177e4
LT		 2167 /* The ring is no longer full, wake queue. */
2168 netif_wake_queue(dev);
2169 }
2170}
2171
b27a16b7
MB		 2172/* The interrupt handler doesn't actually handle interrupts itself, it
2173 * schedules a NAPI poll if there is anything to do. */
7d12e780 2174static irqreturn_t intr_handler(int irq, void *dev_instance)
1da177e4
LT		 2175{
2176 struct net_device *dev = dev_instance;
2177 struct netdev_private *np = netdev_priv(dev);
2178 void __iomem * ioaddr = ns_ioaddr(dev);
1da177e4 2179
069f8256
MB		 2180 /* Reading IntrStatus automatically acknowledges so don't do
2181 * that while interrupts are disabled, (for example, while a
2182 * poll is scheduled). */
2183 if (np->hands_off || !readl(ioaddr + IntrEnable))
1da177e4 2184 return IRQ_NONE;
6aa20a22 2185
b27a16b7 2186 np->intr_status = readl(ioaddr + IntrStatus);
1da177e4 2187
069f8256
MB		 2188 if (!np->intr_status)
2189 return IRQ_NONE;
2190
b27a16b7
MB		 2191 if (netif_msg_intr(np))
2192 printk(KERN_DEBUG
2193 "%s: Interrupt, status %#08x, mask %#08x.\n",
2194 dev->name, np->intr_status,
2195 readl(ioaddr + IntrMask));
1da177e4 2196
b27a16b7
MB		 2197 prefetch(&np->rx_skbuff[np->cur_rx % RX_RING_SIZE]);
2198
288379f0 2199 if (napi_schedule_prep(&np->napi)) {
b27a16b7
MB		 2200 /* Disable interrupts and register for poll */
2201 natsemi_irq_disable(dev);
288379f0 2202 __napi_schedule(&np->napi);
069f8256
MB		 2203 } else
2204 printk(KERN_WARNING
2205 "%s: Ignoring interrupt, status %#08x, mask %#08x.\n",
2206 dev->name, np->intr_status,
2207 readl(ioaddr + IntrMask));
2208
b27a16b7
MB		 2209 return IRQ_HANDLED;
2210}
2211
2212/* This is the NAPI poll routine. As well as the standard RX handling
2213 * it also handles all other interrupts that the chip might raise.
2214 */
bea3348e 2215static int natsemi_poll(struct napi_struct *napi, int budget)
b27a16b7 2216{
bea3348e
SH		 2217 struct netdev_private *np = container_of(napi, struct netdev_private, napi);
2218 struct net_device *dev = np->dev;
b27a16b7 2219 void __iomem * ioaddr = ns_ioaddr(dev);
b27a16b7
MB		 2220 int work_done = 0;
2221
2222 do {
069f8256
MB		 2223 if (netif_msg_intr(np))
2224 printk(KERN_DEBUG
2225 "%s: Poll, status %#08x, mask %#08x.\n",
2226 dev->name, np->intr_status,
2227 readl(ioaddr + IntrMask));
2228
d2a90036
MB		 2229 /* netdev_rx() may read IntrStatus again if the RX state
2230 * machine falls over so do it first. */
2231 if (np->intr_status &
2232 (IntrRxDone | IntrRxIntr | RxStatusFIFOOver |
2233 IntrRxErr | IntrRxOverrun)) {
bea3348e 2234 netdev_rx(dev, &work_done, budget);
d2a90036
MB		 2235 }
2236
b27a16b7
MB		 2237 if (np->intr_status &
2238 (IntrTxDone | IntrTxIntr | IntrTxIdle | IntrTxErr)) {
1da177e4
LT		 2239 spin_lock(&np->lock);
2240 netdev_tx_done(dev);
2241 spin_unlock(&np->lock);
2242 }
2243
2244 /* Abnormal error summary/uncommon events handlers. */
b27a16b7
MB		 2245 if (np->intr_status & IntrAbnormalSummary)
2246 netdev_error(dev, np->intr_status);
6aa20a22 2247
bea3348e
SH		 2248 if (work_done >= budget)
2249 return work_done;
b27a16b7
MB		 2250
2251 np->intr_status = readl(ioaddr + IntrStatus);
2252 } while (np->intr_status);
1da177e4 2253
288379f0 2254 napi_complete(napi);
b27a16b7
MB		 2255
2256 /* Reenable interrupts providing nothing is trying to shut
2257 * the chip down. */
2258 spin_lock(&np->lock);
4ec24119 2259 if (!np->hands_off)
b27a16b7
MB		 2260 natsemi_irq_enable(dev);
2261 spin_unlock(&np->lock);
2262
bea3348e 2263 return work_done;
1da177e4
LT		 2264}
2265
2266/* This routine is logically part of the interrupt handler, but separated
2267 for clarity and better register allocation. */
b27a16b7 2268static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do)
1da177e4
LT		 2269{
2270 struct netdev_private *np = netdev_priv(dev);
2271 int entry = np->cur_rx % RX_RING_SIZE;
2272 int boguscnt = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
2273 s32 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2274 unsigned int buflen = np->rx_buf_sz;
2275 void __iomem * ioaddr = ns_ioaddr(dev);
2276
2277 /* If the driver owns the next entry it's a new packet. Send it up. */
2278 while (desc_status < 0) { /* e.g. & DescOwn */
2279 int pkt_len;
2280 if (netif_msg_rx_status(np))
2281 printk(KERN_DEBUG
2282 " netdev_rx() entry %d status was %#08x.\n",
2283 entry, desc_status);
2284 if (--boguscnt < 0)
2285 break;
b27a16b7
MB		 2286
2287 if (*work_done >= work_to_do)
2288 break;
2289
2290 (*work_done)++;
2291
1da177e4
LT		 2292 pkt_len = (desc_status & DescSizeMask) - 4;
2293 if ((desc_status&(DescMore|DescPktOK|DescRxLong)) != DescPktOK){
2294 if (desc_status & DescMore) {
6006f7f5
SS		 2295 unsigned long flags;
2296
1da177e4
LT		 2297 if (netif_msg_rx_err(np))
2298 printk(KERN_WARNING
2299 "%s: Oversized(?) Ethernet "
2300 "frame spanned multiple "
2301 "buffers, entry %#08x "
2302 "status %#08x.\n", dev->name,
2303 np->cur_rx, desc_status);
2304 np->stats.rx_length_errors++;
e72fd96e
MB		 2305
2306 /* The RX state machine has probably
2307 * locked up beneath us. Follow the
2308 * reset procedure documented in
2309 * AN-1287. */
2310
6006f7f5 2311 spin_lock_irqsave(&np->lock, flags);
e72fd96e
MB		 2312 reset_rx(dev);
2313 reinit_rx(dev);
2314 writel(np->ring_dma, ioaddr + RxRingPtr);
2315 check_link(dev);
6006f7f5 2316 spin_unlock_irqrestore(&np->lock, flags);
e72fd96e
MB		 2317
2318 /* We'll enable RX on exit from this
2319 * function. */
2320 break;
2321
1da177e4
LT		 2322 } else {
2323 /* There was an error. */
2324 np->stats.rx_errors++;
2325 if (desc_status & (DescRxAbort|DescRxOver))
2326 np->stats.rx_over_errors++;
2327 if (desc_status & (DescRxLong|DescRxRunt))
2328 np->stats.rx_length_errors++;
2329 if (desc_status & (DescRxInvalid|DescRxAlign))
2330 np->stats.rx_frame_errors++;
2331 if (desc_status & DescRxCRC)
2332 np->stats.rx_crc_errors++;
2333 }
2334 } else if (pkt_len > np->rx_buf_sz) {
2335 /* if this is the tail of a double buffer
2336 * packet, we've already counted the error
2337 * on the first part. Ignore the second half.
2338 */
2339 } else {
2340 struct sk_buff *skb;
2341 /* Omit CRC size. */
2342 /* Check if the packet is long enough to accept
2343 * without copying to a minimally-sized skbuff. */
8e95a202
JP		 2344 if (pkt_len < rx_copybreak &&
2345 (skb = dev_alloc_skb(pkt_len + RX_OFFSET)) != NULL) {
1da177e4
LT		 2346 /* 16 byte align the IP header */
2347 skb_reserve(skb, RX_OFFSET);
2348 pci_dma_sync_single_for_cpu(np->pci_dev,
2349 np->rx_dma[entry],
2350 buflen,
2351 PCI_DMA_FROMDEVICE);
8c7b7faa
DM		 2352 skb_copy_to_linear_data(skb,
2353 np->rx_skbuff[entry]->data, pkt_len);
1da177e4
LT		 2354 skb_put(skb, pkt_len);
2355 pci_dma_sync_single_for_device(np->pci_dev,
2356 np->rx_dma[entry],
2357 buflen,
2358 PCI_DMA_FROMDEVICE);
2359 } else {
2360 pci_unmap_single(np->pci_dev, np->rx_dma[entry],
2361 buflen, PCI_DMA_FROMDEVICE);
2362 skb_put(skb = np->rx_skbuff[entry], pkt_len);
2363 np->rx_skbuff[entry] = NULL;
2364 }
2365 skb->protocol = eth_type_trans(skb, dev);
b27a16b7 2366 netif_receive_skb(skb);
1da177e4
LT		 2367 np->stats.rx_packets++;
2368 np->stats.rx_bytes += pkt_len;
2369 }
2370 entry = (++np->cur_rx) % RX_RING_SIZE;
2371 np->rx_head_desc = &np->rx_ring[entry];
2372 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2373 }
2374 refill_rx(dev);
2375
2376 /* Restart Rx engine if stopped. */
2377 if (np->oom)
2378 mod_timer(&np->timer, jiffies + 1);
2379 else
2380 writel(RxOn, ioaddr + ChipCmd);
2381}
2382
2383static void netdev_error(struct net_device *dev, int intr_status)
2384{
2385 struct netdev_private *np = netdev_priv(dev);
2386 void __iomem * ioaddr = ns_ioaddr(dev);
2387
2388 spin_lock(&np->lock);
2389 if (intr_status & LinkChange) {
2390 u16 lpa = mdio_read(dev, MII_LPA);
8e95a202
JP		 2391 if (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE &&
2392 netif_msg_link(np)) {
1da177e4
LT		 2393 printk(KERN_INFO
2394 "%s: Autonegotiation advertising"
2395 " %#04x partner %#04x.\n", dev->name,
2396 np->advertising, lpa);
2397 }
2398
2399 /* read MII int status to clear the flag */
2400 readw(ioaddr + MIntrStatus);
2401 check_link(dev);
2402 }
2403 if (intr_status & StatsMax) {
2404 __get_stats(dev);
2405 }
2406 if (intr_status & IntrTxUnderrun) {
2407 if ((np->tx_config & TxDrthMask) < TX_DRTH_VAL_LIMIT) {
2408 np->tx_config += TX_DRTH_VAL_INC;
2409 if (netif_msg_tx_err(np))
2410 printk(KERN_NOTICE
2411 "%s: increased tx threshold, txcfg %#08x.\n",
2412 dev->name, np->tx_config);
2413 } else {
2414 if (netif_msg_tx_err(np))
2415 printk(KERN_NOTICE
2416 "%s: tx underrun with maximum tx threshold, txcfg %#08x.\n",
2417 dev->name, np->tx_config);
2418 }
2419 writel(np->tx_config, ioaddr + TxConfig);
2420 }
2421 if (intr_status & WOLPkt && netif_msg_wol(np)) {
2422 int wol_status = readl(ioaddr + WOLCmd);
2423 printk(KERN_NOTICE "%s: Link wake-up event %#08x\n",
2424 dev->name, wol_status);
2425 }
2426 if (intr_status & RxStatusFIFOOver) {
2427 if (netif_msg_rx_err(np) && netif_msg_intr(np)) {
2428 printk(KERN_NOTICE "%s: Rx status FIFO overrun\n",
2429 dev->name);
2430 }
2431 np->stats.rx_fifo_errors++;
c76720cf 2432 np->stats.rx_errors++;
1da177e4
LT		 2433 }
2434 /* Hmmmmm, it's not clear how to recover from PCI faults. */
2435 if (intr_status & IntrPCIErr) {
2436 printk(KERN_NOTICE "%s: PCI error %#08x\n", dev->name,
2437 intr_status & IntrPCIErr);
2438 np->stats.tx_fifo_errors++;
c76720cf 2439 np->stats.tx_errors++;
1da177e4 2440 np->stats.rx_fifo_errors++;
c76720cf 2441 np->stats.rx_errors++;
1da177e4
LT		 2442 }
2443 spin_unlock(&np->lock);
2444}
2445
2446static void __get_stats(struct net_device *dev)
2447{
2448 void __iomem * ioaddr = ns_ioaddr(dev);
2449 struct netdev_private *np = netdev_priv(dev);
2450
2451 /* The chip only need report frame silently dropped. */
2452 np->stats.rx_crc_errors += readl(ioaddr + RxCRCErrs);
2453 np->stats.rx_missed_errors += readl(ioaddr + RxMissed);
2454}
2455
2456static struct net_device_stats *get_stats(struct net_device *dev)
2457{
2458 struct netdev_private *np = netdev_priv(dev);
2459
2460 /* The chip only need report frame silently dropped. */
2461 spin_lock_irq(&np->lock);
2462 if (netif_running(dev) && !np->hands_off)
2463 __get_stats(dev);
2464 spin_unlock_irq(&np->lock);
2465
2466 return &np->stats;
2467}
2468
2469#ifdef CONFIG_NET_POLL_CONTROLLER
2470static void natsemi_poll_controller(struct net_device *dev)
2471{
2472 disable_irq(dev->irq);
069f8256 2473 intr_handler(dev->irq, dev);
1da177e4
LT		 2474 enable_irq(dev->irq);
2475}
2476#endif
2477
2478#define HASH_TABLE 0x200
2479static void __set_rx_mode(struct net_device *dev)
2480{
2481 void __iomem * ioaddr = ns_ioaddr(dev);
2482 struct netdev_private *np = netdev_priv(dev);
2483 u8 mc_filter[64]; /* Multicast hash filter */
2484 u32 rx_mode;
2485
2486 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1da177e4
LT		 2487 rx_mode = RxFilterEnable | AcceptBroadcast
2488 | AcceptAllMulticast | AcceptAllPhys | AcceptMyPhys;
4cd24eaf 2489 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 2490 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 2491 rx_mode = RxFilterEnable | AcceptBroadcast
2492 | AcceptAllMulticast | AcceptMyPhys;
2493 } else {
22bedad3 2494 struct netdev_hw_addr *ha;
1da177e4 2495 int i;
f9dcbcc9 2496
1da177e4 2497 memset(mc_filter, 0, sizeof(mc_filter));
22bedad3
JP		 2498 netdev_for_each_mc_addr(ha, dev) {
2499 int b = (ether_crc(ETH_ALEN, ha->addr) >> 23) & 0x1ff;
ddfce6bb 2500 mc_filter[b/8] |= (1 << (b & 0x07));
1da177e4
LT		 2501 }
2502 rx_mode = RxFilterEnable | AcceptBroadcast
2503 | AcceptMulticast | AcceptMyPhys;
2504 for (i = 0; i < 64; i += 2) {
760f86d7
HX		 2505 writel(HASH_TABLE + i, ioaddr + RxFilterAddr);
2506 writel((mc_filter[i + 1] << 8) + mc_filter[i],
2507 ioaddr + RxFilterData);
1da177e4
LT		 2508 }
2509 }
2510 writel(rx_mode, ioaddr + RxFilterAddr);
2511 np->cur_rx_mode = rx_mode;
2512}
2513
2514static int natsemi_change_mtu(struct net_device *dev, int new_mtu)
2515{
2516 if (new_mtu < 64 || new_mtu > NATSEMI_RX_LIMIT-NATSEMI_HEADERS)
2517 return -EINVAL;
2518
2519 dev->mtu = new_mtu;
2520
2521 /* synchronized against open : rtnl_lock() held by caller */
2522 if (netif_running(dev)) {
2523 struct netdev_private *np = netdev_priv(dev);
2524 void __iomem * ioaddr = ns_ioaddr(dev);
2525
2526 disable_irq(dev->irq);
2527 spin_lock(&np->lock);
2528 /* stop engines */
2529 natsemi_stop_rxtx(dev);
2530 /* drain rx queue */
2531 drain_rx(dev);
2532 /* change buffers */
2533 set_bufsize(dev);
2534 reinit_rx(dev);
2535 writel(np->ring_dma, ioaddr + RxRingPtr);
2536 /* restart engines */
2537 writel(RxOn | TxOn, ioaddr + ChipCmd);
2538 spin_unlock(&np->lock);
2539 enable_irq(dev->irq);
2540 }
2541 return 0;
2542}
2543
2544static void set_rx_mode(struct net_device *dev)
2545{
2546 struct netdev_private *np = netdev_priv(dev);
2547 spin_lock_irq(&np->lock);
2548 if (!np->hands_off)
2549 __set_rx_mode(dev);
2550 spin_unlock_irq(&np->lock);
2551}
2552
2553static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2554{
2555 struct netdev_private *np = netdev_priv(dev);
2556 strncpy(info->driver, DRV_NAME, ETHTOOL_BUSINFO_LEN);
2557 strncpy(info->version, DRV_VERSION, ETHTOOL_BUSINFO_LEN);
2558 strncpy(info->bus_info, pci_name(np->pci_dev), ETHTOOL_BUSINFO_LEN);
2559}
2560
2561static int get_regs_len(struct net_device *dev)
2562{
2563 return NATSEMI_REGS_SIZE;
2564}
2565
2566static int get_eeprom_len(struct net_device *dev)
2567{
a8b4cf42
MB		 2568 struct netdev_private *np = netdev_priv(dev);
2569 return np->eeprom_size;
1da177e4
LT		 2570}
2571
2572static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2573{
2574 struct netdev_private *np = netdev_priv(dev);
2575 spin_lock_irq(&np->lock);
2576 netdev_get_ecmd(dev, ecmd);
2577 spin_unlock_irq(&np->lock);
2578 return 0;
2579}
2580
2581static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2582{
2583 struct netdev_private *np = netdev_priv(dev);
2584 int res;
2585 spin_lock_irq(&np->lock);
2586 res = netdev_set_ecmd(dev, ecmd);
2587 spin_unlock_irq(&np->lock);
2588 return res;
2589}
2590
2591static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2592{
2593 struct netdev_private *np = netdev_priv(dev);
2594 spin_lock_irq(&np->lock);
2595 netdev_get_wol(dev, &wol->supported, &wol->wolopts);
2596 netdev_get_sopass(dev, wol->sopass);
2597 spin_unlock_irq(&np->lock);
2598}
2599
2600static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2601{
2602 struct netdev_private *np = netdev_priv(dev);
2603 int res;
2604 spin_lock_irq(&np->lock);
2605 netdev_set_wol(dev, wol->wolopts);
2606 res = netdev_set_sopass(dev, wol->sopass);
2607 spin_unlock_irq(&np->lock);
2608 return res;
2609}
2610
2611static void get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
2612{
2613 struct netdev_private *np = netdev_priv(dev);
2614 regs->version = NATSEMI_REGS_VER;
2615 spin_lock_irq(&np->lock);
2616 netdev_get_regs(dev, buf);
2617 spin_unlock_irq(&np->lock);
2618}
2619
2620static u32 get_msglevel(struct net_device *dev)
2621{
2622 struct netdev_private *np = netdev_priv(dev);
2623 return np->msg_enable;
2624}
2625
2626static void set_msglevel(struct net_device *dev, u32 val)
2627{
2628 struct netdev_private *np = netdev_priv(dev);
2629 np->msg_enable = val;
2630}
2631
2632static int nway_reset(struct net_device *dev)
2633{
2634 int tmp;
2635 int r = -EINVAL;
2636 /* if autoneg is off, it's an error */
2637 tmp = mdio_read(dev, MII_BMCR);
2638 if (tmp & BMCR_ANENABLE) {
2639 tmp |= (BMCR_ANRESTART);
2640 mdio_write(dev, MII_BMCR, tmp);
2641 r = 0;
2642 }
2643 return r;
2644}
2645
2646static u32 get_link(struct net_device *dev)
2647{
2648 /* LSTATUS is latched low until a read - so read twice */
2649 mdio_read(dev, MII_BMSR);
2650 return (mdio_read(dev, MII_BMSR)&BMSR_LSTATUS) ? 1:0;
2651}
2652
2653static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
2654{
2655 struct netdev_private *np = netdev_priv(dev);
a8b4cf42 2656 u8 *eebuf;
1da177e4
LT		 2657 int res;
2658
a8b4cf42
MB		 2659 eebuf = kmalloc(np->eeprom_size, GFP_KERNEL);
2660 if (!eebuf)
2661 return -ENOMEM;
2662
1da177e4
LT		 2663 eeprom->magic = PCI_VENDOR_ID_NS | (PCI_DEVICE_ID_NS_83815<<16);
2664 spin_lock_irq(&np->lock);
2665 res = netdev_get_eeprom(dev, eebuf);
2666 spin_unlock_irq(&np->lock);
2667 if (!res)
2668 memcpy(data, eebuf+eeprom->offset, eeprom->len);
a8b4cf42 2669 kfree(eebuf);
1da177e4
LT		 2670 return res;
2671}
2672
7282d491 2673static const struct ethtool_ops ethtool_ops = {
1da177e4
LT		 2674 .get_drvinfo = get_drvinfo,
2675 .get_regs_len = get_regs_len,
2676 .get_eeprom_len = get_eeprom_len,
2677 .get_settings = get_settings,
2678 .set_settings = set_settings,
2679 .get_wol = get_wol,
2680 .set_wol = set_wol,
2681 .get_regs = get_regs,
2682 .get_msglevel = get_msglevel,
2683 .set_msglevel = set_msglevel,
2684 .nway_reset = nway_reset,
2685 .get_link = get_link,
2686 .get_eeprom = get_eeprom,
2687};
2688
2689static int netdev_set_wol(struct net_device *dev, u32 newval)
2690{
2691 struct netdev_private *np = netdev_priv(dev);
2692 void __iomem * ioaddr = ns_ioaddr(dev);
2693 u32 data = readl(ioaddr + WOLCmd) & ~WakeOptsSummary;
2694
2695 /* translate to bitmasks this chip understands */
2696 if (newval & WAKE_PHY)
2697 data |= WakePhy;
2698 if (newval & WAKE_UCAST)
2699 data |= WakeUnicast;
2700 if (newval & WAKE_MCAST)
2701 data |= WakeMulticast;
2702 if (newval & WAKE_BCAST)
2703 data |= WakeBroadcast;
2704 if (newval & WAKE_ARP)
2705 data |= WakeArp;
2706 if (newval & WAKE_MAGIC)
2707 data |= WakeMagic;
2708 if (np->srr >= SRR_DP83815_D) {
2709 if (newval & WAKE_MAGICSECURE) {
2710 data |= WakeMagicSecure;
2711 }
2712 }
2713
2714 writel(data, ioaddr + WOLCmd);
2715
2716 return 0;
2717}
2718
2719static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur)
2720{
2721 struct netdev_private *np = netdev_priv(dev);
2722 void __iomem * ioaddr = ns_ioaddr(dev);
2723 u32 regval = readl(ioaddr + WOLCmd);
2724
2725 *supported = (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST
2726 | WAKE_ARP | WAKE_MAGIC);
2727
2728 if (np->srr >= SRR_DP83815_D) {
2729 /* SOPASS works on revD and higher */
2730 *supported |= WAKE_MAGICSECURE;
2731 }
2732 *cur = 0;
2733
2734 /* translate from chip bitmasks */
2735 if (regval & WakePhy)
2736 *cur |= WAKE_PHY;
2737 if (regval & WakeUnicast)
2738 *cur |= WAKE_UCAST;
2739 if (regval & WakeMulticast)
2740 *cur |= WAKE_MCAST;
2741 if (regval & WakeBroadcast)
2742 *cur |= WAKE_BCAST;
2743 if (regval & WakeArp)
2744 *cur |= WAKE_ARP;
2745 if (regval & WakeMagic)
2746 *cur |= WAKE_MAGIC;
2747 if (regval & WakeMagicSecure) {
2748 /* this can be on in revC, but it's broken */
2749 *cur |= WAKE_MAGICSECURE;
2750 }
2751
2752 return 0;
2753}
2754
2755static int netdev_set_sopass(struct net_device *dev, u8 *newval)
2756{
2757 struct netdev_private *np = netdev_priv(dev);
2758 void __iomem * ioaddr = ns_ioaddr(dev);
2759 u16 *sval = (u16 *)newval;
2760 u32 addr;
2761
2762 if (np->srr < SRR_DP83815_D) {
2763 return 0;
2764 }
2765
2766 /* enable writing to these registers by disabling the RX filter */
2767 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2768 addr &= ~RxFilterEnable;
2769 writel(addr, ioaddr + RxFilterAddr);
2770
2771 /* write the three words to (undocumented) RFCR vals 0xa, 0xc, 0xe */
2772 writel(addr | 0xa, ioaddr + RxFilterAddr);
2773 writew(sval[0], ioaddr + RxFilterData);
2774
2775 writel(addr | 0xc, ioaddr + RxFilterAddr);
2776 writew(sval[1], ioaddr + RxFilterData);
2777
2778 writel(addr | 0xe, ioaddr + RxFilterAddr);
2779 writew(sval[2], ioaddr + RxFilterData);
2780
2781 /* re-enable the RX filter */
2782 writel(addr | RxFilterEnable, ioaddr + RxFilterAddr);
2783
2784 return 0;
2785}
2786
2787static int netdev_get_sopass(struct net_device *dev, u8 *data)
2788{
2789 struct netdev_private *np = netdev_priv(dev);
2790 void __iomem * ioaddr = ns_ioaddr(dev);
2791 u16 *sval = (u16 *)data;
2792 u32 addr;
2793
2794 if (np->srr < SRR_DP83815_D) {
2795 sval[0] = sval[1] = sval[2] = 0;
2796 return 0;
2797 }
2798
2799 /* read the three words from (undocumented) RFCR vals 0xa, 0xc, 0xe */
2800 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2801
2802 writel(addr | 0xa, ioaddr + RxFilterAddr);
2803 sval[0] = readw(ioaddr + RxFilterData);
2804
2805 writel(addr | 0xc, ioaddr + RxFilterAddr);
2806 sval[1] = readw(ioaddr + RxFilterData);
2807
2808 writel(addr | 0xe, ioaddr + RxFilterAddr);
2809 sval[2] = readw(ioaddr + RxFilterData);
2810
2811 writel(addr, ioaddr + RxFilterAddr);
2812
2813 return 0;
2814}
2815
2816static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2817{
2818 struct netdev_private *np = netdev_priv(dev);
2819 u32 tmp;
2820
2821 ecmd->port = dev->if_port;
2822 ecmd->speed = np->speed;
2823 ecmd->duplex = np->duplex;
2824 ecmd->autoneg = np->autoneg;
2825 ecmd->advertising = 0;
2826 if (np->advertising & ADVERTISE_10HALF)
2827 ecmd->advertising |= ADVERTISED_10baseT_Half;
2828 if (np->advertising & ADVERTISE_10FULL)
2829 ecmd->advertising |= ADVERTISED_10baseT_Full;
2830 if (np->advertising & ADVERTISE_100HALF)
2831 ecmd->advertising |= ADVERTISED_100baseT_Half;
2832 if (np->advertising & ADVERTISE_100FULL)
2833 ecmd->advertising |= ADVERTISED_100baseT_Full;
2834 ecmd->supported = (SUPPORTED_Autoneg |
2835 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2836 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2837 SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_FIBRE);
2838 ecmd->phy_address = np->phy_addr_external;
2839 /*
2840 * We intentionally report the phy address of the external
2841 * phy, even if the internal phy is used. This is necessary
2842 * to work around a deficiency of the ethtool interface:
2843 * It's only possible to query the settings of the active
6aa20a22 2844 * port. Therefore
1da177e4
LT		 2845 * # ethtool -s ethX port mii
2846 * actually sends an ioctl to switch to port mii with the
2847 * settings that are used for the current active port.
2848 * If we would report a different phy address in this
2849 * command, then
2850 * # ethtool -s ethX port tp;ethtool -s ethX port mii
2851 * would unintentionally change the phy address.
2852 *
2853 * Fortunately the phy address doesn't matter with the
2854 * internal phy...
2855 */
2856
2857 /* set information based on active port type */
2858 switch (ecmd->port) {
2859 default:
2860 case PORT_TP:
2861 ecmd->advertising |= ADVERTISED_TP;
2862 ecmd->transceiver = XCVR_INTERNAL;
2863 break;
2864 case PORT_MII:
2865 ecmd->advertising |= ADVERTISED_MII;
2866 ecmd->transceiver = XCVR_EXTERNAL;
2867 break;
2868 case PORT_FIBRE:
2869 ecmd->advertising |= ADVERTISED_FIBRE;
2870 ecmd->transceiver = XCVR_EXTERNAL;
2871 break;
2872 }
2873
2874 /* if autonegotiation is on, try to return the active speed/duplex */
2875 if (ecmd->autoneg == AUTONEG_ENABLE) {
2876 ecmd->advertising |= ADVERTISED_Autoneg;
2877 tmp = mii_nway_result(
2878 np->advertising & mdio_read(dev, MII_LPA));
2879 if (tmp == LPA_100FULL || tmp == LPA_100HALF)
2880 ecmd->speed = SPEED_100;
2881 else
2882 ecmd->speed = SPEED_10;
2883 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
2884 ecmd->duplex = DUPLEX_FULL;
2885 else
2886 ecmd->duplex = DUPLEX_HALF;
2887 }
2888
2889 /* ignore maxtxpkt, maxrxpkt for now */
2890
2891 return 0;
2892}
2893
2894static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2895{
2896 struct netdev_private *np = netdev_priv(dev);
2897
2898 if (ecmd->port != PORT_TP && ecmd->port != PORT_MII && ecmd->port != PORT_FIBRE)
2899 return -EINVAL;
2900 if (ecmd->transceiver != XCVR_INTERNAL && ecmd->transceiver != XCVR_EXTERNAL)
2901 return -EINVAL;
2902 if (ecmd->autoneg == AUTONEG_ENABLE) {
2903 if ((ecmd->advertising & (ADVERTISED_10baseT_Half |
2904 ADVERTISED_10baseT_Full |
2905 ADVERTISED_100baseT_Half |
2906 ADVERTISED_100baseT_Full)) == 0) {
2907 return -EINVAL;
2908 }
2909 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
2910 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
2911 return -EINVAL;
2912 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2913 return -EINVAL;
2914 } else {
2915 return -EINVAL;
2916 }
2917
68c90166
MB		 2918 /*
2919 * If we're ignoring the PHY then autoneg and the internal
2920 * transciever are really not going to work so don't let the
2921 * user select them.
2922 */
2923 if (np->ignore_phy && (ecmd->autoneg == AUTONEG_ENABLE ||
2924 ecmd->port == PORT_TP))
2925 return -EINVAL;
2926
1da177e4
LT		 2927 /*
2928 * maxtxpkt, maxrxpkt: ignored for now.
2929 *
2930 * transceiver:
2931 * PORT_TP is always XCVR_INTERNAL, PORT_MII and PORT_FIBRE are always
2932 * XCVR_EXTERNAL. The implementation thus ignores ecmd->transceiver and
2933 * selects based on ecmd->port.
2934 *
2935 * Actually PORT_FIBRE is nearly identical to PORT_MII: it's for fibre
2936 * phys that are connected to the mii bus. It's used to apply fibre
2937 * specific updates.
2938 */
2939
2940 /* WHEW! now lets bang some bits */
2941
2942 /* save the parms */
2943 dev->if_port = ecmd->port;
2944 np->autoneg = ecmd->autoneg;
2945 np->phy_addr_external = ecmd->phy_address & PhyAddrMask;
2946 if (np->autoneg == AUTONEG_ENABLE) {
2947 /* advertise only what has been requested */
2948 np->advertising &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2949 if (ecmd->advertising & ADVERTISED_10baseT_Half)
2950 np->advertising |= ADVERTISE_10HALF;
2951 if (ecmd->advertising & ADVERTISED_10baseT_Full)
2952 np->advertising |= ADVERTISE_10FULL;
2953 if (ecmd->advertising & ADVERTISED_100baseT_Half)
2954 np->advertising |= ADVERTISE_100HALF;
2955 if (ecmd->advertising & ADVERTISED_100baseT_Full)
2956 np->advertising |= ADVERTISE_100FULL;
2957 } else {
2958 np->speed = ecmd->speed;
2959 np->duplex = ecmd->duplex;
2960 /* user overriding the initial full duplex parm? */
2961 if (np->duplex == DUPLEX_HALF)
2962 np->full_duplex = 0;
2963 }
2964
2965 /* get the right phy enabled */
2966 if (ecmd->port == PORT_TP)
2967 switch_port_internal(dev);
2968 else
2969 switch_port_external(dev);
2970
2971 /* set parms and see how this affected our link status */
2972 init_phy_fixup(dev);
2973 check_link(dev);
2974 return 0;
2975}
2976
2977static int netdev_get_regs(struct net_device *dev, u8 *buf)
2978{
2979 int i;
2980 int j;
2981 u32 rfcr;
2982 u32 *rbuf = (u32 *)buf;
2983 void __iomem * ioaddr = ns_ioaddr(dev);
2984
2985 /* read non-mii page 0 of registers */
2986 for (i = 0; i < NATSEMI_PG0_NREGS/2; i++) {
2987 rbuf[i] = readl(ioaddr + i*4);
2988 }
2989
2990 /* read current mii registers */
2991 for (i = NATSEMI_PG0_NREGS/2; i < NATSEMI_PG0_NREGS; i++)
2992 rbuf[i] = mdio_read(dev, i & 0x1f);
2993
2994 /* read only the 'magic' registers from page 1 */
2995 writew(1, ioaddr + PGSEL);
2996 rbuf[i++] = readw(ioaddr + PMDCSR);
2997 rbuf[i++] = readw(ioaddr + TSTDAT);
2998 rbuf[i++] = readw(ioaddr + DSPCFG);
2999 rbuf[i++] = readw(ioaddr + SDCFG);
3000 writew(0, ioaddr + PGSEL);
3001
3002 /* read RFCR indexed registers */
3003 rfcr = readl(ioaddr + RxFilterAddr);
3004 for (j = 0; j < NATSEMI_RFDR_NREGS; j++) {
3005 writel(j*2, ioaddr + RxFilterAddr);
3006 rbuf[i++] = readw(ioaddr + RxFilterData);
3007 }
3008 writel(rfcr, ioaddr + RxFilterAddr);
3009
3010 /* the interrupt status is clear-on-read - see if we missed any */
3011 if (rbuf[4] & rbuf[5]) {
3012 printk(KERN_WARNING
3013 "%s: shoot, we dropped an interrupt (%#08x)\n",
3014 dev->name, rbuf[4] & rbuf[5]);
3015 }
3016
3017 return 0;
3018}
3019
3020#define SWAP_BITS(x) ( (((x) & 0x0001) << 15) | (((x) & 0x0002) << 13) \
3021 | (((x) & 0x0004) << 11) | (((x) & 0x0008) << 9) \
3022 | (((x) & 0x0010) << 7) | (((x) & 0x0020) << 5) \
3023 | (((x) & 0x0040) << 3) | (((x) & 0x0080) << 1) \
3024 | (((x) & 0x0100) >> 1) | (((x) & 0x0200) >> 3) \
3025 | (((x) & 0x0400) >> 5) | (((x) & 0x0800) >> 7) \
3026 | (((x) & 0x1000) >> 9) | (((x) & 0x2000) >> 11) \
3027 | (((x) & 0x4000) >> 13) | (((x) & 0x8000) >> 15) )
3028
3029static int netdev_get_eeprom(struct net_device *dev, u8 *buf)
3030{
3031 int i;
3032 u16 *ebuf = (u16 *)buf;
3033 void __iomem * ioaddr = ns_ioaddr(dev);
a8b4cf42 3034 struct netdev_private *np = netdev_priv(dev);
1da177e4
LT		 3035
3036 /* eeprom_read reads 16 bits, and indexes by 16 bits */
a8b4cf42 3037 for (i = 0; i < np->eeprom_size/2; i++) {
1da177e4
LT		 3038 ebuf[i] = eeprom_read(ioaddr, i);
3039 /* The EEPROM itself stores data bit-swapped, but eeprom_read
3040 * reads it back "sanely". So we swap it back here in order to
3041 * present it to userland as it is stored. */
3042 ebuf[i] = SWAP_BITS(ebuf[i]);
3043 }
3044 return 0;
3045}
3046
3047static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3048{
3049 struct mii_ioctl_data *data = if_mii(rq);
3050 struct netdev_private *np = netdev_priv(dev);
3051
3052 switch(cmd) {
3053 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1da177e4
LT		 3054 data->phy_id = np->phy_addr_external;
3055 /* Fall Through */
3056
3057 case SIOCGMIIREG: /* Read MII PHY register. */
1da177e4
LT		 3058 /* The phy_id is not enough to uniquely identify
3059 * the intended target. Therefore the command is sent to
3060 * the given mii on the current port.
3061 */
3062 if (dev->if_port == PORT_TP) {
3063 if ((data->phy_id & 0x1f) == np->phy_addr_external)
3064 data->val_out = mdio_read(dev,
3065 data->reg_num & 0x1f);
3066 else
3067 data->val_out = 0;
3068 } else {
3069 move_int_phy(dev, data->phy_id & 0x1f);
3070 data->val_out = miiport_read(dev, data->phy_id & 0x1f,
3071 data->reg_num & 0x1f);
3072 }
3073 return 0;
3074
3075 case SIOCSMIIREG: /* Write MII PHY register. */
1da177e4
LT		 3076 if (dev->if_port == PORT_TP) {
3077 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3078 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3079 np->advertising = data->val_in;
3080 mdio_write(dev, data->reg_num & 0x1f,
3081 data->val_in);
3082 }
3083 } else {
3084 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3085 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3086 np->advertising = data->val_in;
3087 }
3088 move_int_phy(dev, data->phy_id & 0x1f);
3089 miiport_write(dev, data->phy_id & 0x1f,
3090 data->reg_num & 0x1f,
3091 data->val_in);
3092 }
3093 return 0;
3094 default:
3095 return -EOPNOTSUPP;
3096 }
3097}
3098
3099static void enable_wol_mode(struct net_device *dev, int enable_intr)
3100{
3101 void __iomem * ioaddr = ns_ioaddr(dev);
3102 struct netdev_private *np = netdev_priv(dev);
3103
3104 if (netif_msg_wol(np))
3105 printk(KERN_INFO "%s: remaining active for wake-on-lan\n",
3106 dev->name);
3107
3108 /* For WOL we must restart the rx process in silent mode.
3109 * Write NULL to the RxRingPtr. Only possible if
3110 * rx process is stopped
3111 */
3112 writel(0, ioaddr + RxRingPtr);
3113
3114 /* read WoL status to clear */
3115 readl(ioaddr + WOLCmd);
3116
3117 /* PME on, clear status */
3118 writel(np->SavedClkRun | PMEEnable | PMEStatus, ioaddr + ClkRun);
3119
3120 /* and restart the rx process */
3121 writel(RxOn, ioaddr + ChipCmd);
3122
3123 if (enable_intr) {
3124 /* enable the WOL interrupt.
3125 * Could be used to send a netlink message.
3126 */
3127 writel(WOLPkt | LinkChange, ioaddr + IntrMask);
14fdd90e 3128 natsemi_irq_enable(dev);
1da177e4
LT		 3129 }
3130}
3131
3132static int netdev_close(struct net_device *dev)
3133{
3134 void __iomem * ioaddr = ns_ioaddr(dev);
3135 struct netdev_private *np = netdev_priv(dev);
3136
3137 if (netif_msg_ifdown(np))
3138 printk(KERN_DEBUG
3139 "%s: Shutting down ethercard, status was %#04x.\n",
3140 dev->name, (int)readl(ioaddr + ChipCmd));
3141 if (netif_msg_pktdata(np))
3142 printk(KERN_DEBUG
3143 "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
3144 dev->name, np->cur_tx, np->dirty_tx,
3145 np->cur_rx, np->dirty_rx);
3146
bea3348e
SH		 3147 napi_disable(&np->napi);
3148
1da177e4
LT		 3149 /*
3150 * FIXME: what if someone tries to close a device
3151 * that is suspended?
3152 * Should we reenable the nic to switch to
3153 * the final WOL settings?
3154 */
3155
3156 del_timer_sync(&np->timer);
3157 disable_irq(dev->irq);
3158 spin_lock_irq(&np->lock);
b27a16b7 3159 natsemi_irq_disable(dev);
1da177e4
LT		 3160 np->hands_off = 1;
3161 spin_unlock_irq(&np->lock);
3162 enable_irq(dev->irq);
3163
3164 free_irq(dev->irq, dev);
3165
3166 /* Interrupt disabled, interrupt handler released,
3167 * queue stopped, timer deleted, rtnl_lock held
3168 * All async codepaths that access the driver are disabled.
3169 */
3170 spin_lock_irq(&np->lock);
3171 np->hands_off = 0;
3172 readl(ioaddr + IntrMask);
3173 readw(ioaddr + MIntrStatus);
3174
3175 /* Freeze Stats */
3176 writel(StatsFreeze, ioaddr + StatsCtrl);
3177
3178 /* Stop the chip's Tx and Rx processes. */
3179 natsemi_stop_rxtx(dev);
3180
3181 __get_stats(dev);
3182 spin_unlock_irq(&np->lock);
3183
3184 /* clear the carrier last - an interrupt could reenable it otherwise */
3185 netif_carrier_off(dev);
3186 netif_stop_queue(dev);
3187
3188 dump_ring(dev);
3189 drain_ring(dev);
3190 free_ring(dev);
3191
3192 {
3193 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3194 if (wol) {
3195 /* restart the NIC in WOL mode.
3196 * The nic must be stopped for this.
3197 */
3198 enable_wol_mode(dev, 0);
3199 } else {
3200 /* Restore PME enable bit unmolested */
3201 writel(np->SavedClkRun, ioaddr + ClkRun);
3202 }
3203 }
3204 return 0;
3205}
3206
3207
3208static void __devexit natsemi_remove1 (struct pci_dev *pdev)
3209{
3210 struct net_device *dev = pci_get_drvdata(pdev);
3211 void __iomem * ioaddr = ns_ioaddr(dev);
3212
1a147809 3213 NATSEMI_REMOVE_FILE(pdev, dspcfg_workaround);
1da177e4
LT		 3214 unregister_netdev (dev);
3215 pci_release_regions (pdev);
3216 iounmap(ioaddr);
3217 free_netdev (dev);
3218 pci_set_drvdata(pdev, NULL);
3219}
3220
3221#ifdef CONFIG_PM
3222
3223/*
3224 * The ns83815 chip doesn't have explicit RxStop bits.
3225 * Kicking the Rx or Tx process for a new packet reenables the Rx process
3226 * of the nic, thus this function must be very careful:
3227 *
3228 * suspend/resume synchronization:
3229 * entry points:
3230 * netdev_open, netdev_close, netdev_ioctl, set_rx_mode, intr_handler,
ed4cb133 3231 * start_tx, ns_tx_timeout
1da177e4
LT		 3232 *
3233 * No function accesses the hardware without checking np->hands_off.
3234 * the check occurs under spin_lock_irq(&np->lock);
3235 * exceptions:
3236 * * netdev_ioctl: noncritical access.
3237 * * netdev_open: cannot happen due to the device_detach
3238 * * netdev_close: doesn't hurt.
3239 * * netdev_timer: timer stopped by natsemi_suspend.
3240 * * intr_handler: doesn't acquire the spinlock. suspend calls
3241 * disable_irq() to enforce synchronization.
b27a16b7
MB		 3242 * * natsemi_poll: checks before reenabling interrupts. suspend
3243 * sets hands_off, disables interrupts and then waits with
bea3348e 3244 * napi_disable().
1da177e4
LT		 3245 *
3246 * Interrupts must be disabled, otherwise hands_off can cause irq storms.
3247 */
3248
3249static int natsemi_suspend (struct pci_dev *pdev, pm_message_t state)
3250{
3251 struct net_device *dev = pci_get_drvdata (pdev);
3252 struct netdev_private *np = netdev_priv(dev);
3253 void __iomem * ioaddr = ns_ioaddr(dev);
3254
3255 rtnl_lock();
3256 if (netif_running (dev)) {
3257 del_timer_sync(&np->timer);
3258
3259 disable_irq(dev->irq);
3260 spin_lock_irq(&np->lock);
3261
14fdd90e 3262 natsemi_irq_disable(dev);
1da177e4
LT		 3263 np->hands_off = 1;
3264 natsemi_stop_rxtx(dev);
3265 netif_stop_queue(dev);
3266
3267 spin_unlock_irq(&np->lock);
3268 enable_irq(dev->irq);
3269
bea3348e 3270 napi_disable(&np->napi);
b27a16b7 3271
1da177e4
LT		 3272 /* Update the error counts. */
3273 __get_stats(dev);
3274
3275 /* pci_power_off(pdev, -1); */
3276 drain_ring(dev);
3277 {
3278 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3279 /* Restore PME enable bit */
3280 if (wol) {
3281 /* restart the NIC in WOL mode.
3282 * The nic must be stopped for this.
3283 * FIXME: use the WOL interrupt
3284 */
3285 enable_wol_mode(dev, 0);
3286 } else {
3287 /* Restore PME enable bit unmolested */
3288 writel(np->SavedClkRun, ioaddr + ClkRun);
3289 }
3290 }
3291 }
3292 netif_device_detach(dev);
3293 rtnl_unlock();
3294 return 0;
3295}
3296
3297
3298static int natsemi_resume (struct pci_dev *pdev)
3299{
3300 struct net_device *dev = pci_get_drvdata (pdev);
3301 struct netdev_private *np = netdev_priv(dev);
a8a935da 3302 int ret = 0;
1da177e4
LT		 3303
3304 rtnl_lock();
3305 if (netif_device_present(dev))
3306 goto out;
3307 if (netif_running(dev)) {
3308 BUG_ON(!np->hands_off);
a8a935da
MB		 3309 ret = pci_enable_device(pdev);
3310 if (ret < 0) {
3311 dev_err(&pdev->dev,
3312 "pci_enable_device() failed: %d\n", ret);
3313 goto out;
3314 }
1da177e4
LT		 3315 /* pci_power_on(pdev); */
3316
bea3348e
SH		 3317 napi_enable(&np->napi);
3318
1da177e4
LT		 3319 natsemi_reset(dev);
3320 init_ring(dev);
3321 disable_irq(dev->irq);
3322 spin_lock_irq(&np->lock);
3323 np->hands_off = 0;
3324 init_registers(dev);
3325 netif_device_attach(dev);
3326 spin_unlock_irq(&np->lock);
3327 enable_irq(dev->irq);
3328
0e5d5442 3329 mod_timer(&np->timer, round_jiffies(jiffies + 1*HZ));
1da177e4
LT		 3330 }
3331 netif_device_attach(dev);
3332out:
3333 rtnl_unlock();
a8a935da 3334 return ret;
1da177e4
LT		 3335}
3336
3337#endif /* CONFIG_PM */
3338
3339static struct pci_driver natsemi_driver = {
3340 .name = DRV_NAME,
3341 .id_table = natsemi_pci_tbl,
3342 .probe = natsemi_probe1,
3343 .remove = __devexit_p(natsemi_remove1),
3344#ifdef CONFIG_PM
3345 .suspend = natsemi_suspend,
3346 .resume = natsemi_resume,
3347#endif
3348};
3349
3350static int __init natsemi_init_mod (void)
3351{
3352/* when a module, this is printed whether or not devices are found in probe */
3353#ifdef MODULE
3354 printk(version);
3355#endif
3356
29917620 3357 return pci_register_driver(&natsemi_driver);
1da177e4
LT		 3358}
3359
3360static void __exit natsemi_exit_mod (void)
3361{
3362 pci_unregister_driver (&natsemi_driver);
3363}
3364
3365module_init(natsemi_init_mod);
3366module_exit(natsemi_exit_mod);
3367
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