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c609719b WD |
1 | /* |
2 | * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de. | |
3 | * | |
4 | * This driver for AMD PCnet network controllers is derived from the | |
5 | * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer. | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | #include <common.h> | |
27 | #include <malloc.h> | |
28 | #include <net.h> | |
e3090534 | 29 | #include <netdev.h> |
c609719b WD |
30 | #include <asm/io.h> |
31 | #include <pci.h> | |
32 | ||
33 | #if 0 | |
11ea26fd | 34 | #define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */ |
c609719b WD |
35 | #endif |
36 | ||
37 | #if PCNET_DEBUG_LEVEL > 0 | |
39539887 | 38 | #define PCNET_DEBUG1(fmt,args...) printf (fmt ,##args) |
c609719b | 39 | #if PCNET_DEBUG_LEVEL > 1 |
39539887 | 40 | #define PCNET_DEBUG2(fmt,args...) printf (fmt ,##args) |
c609719b | 41 | #else |
39539887 | 42 | #define PCNET_DEBUG2(fmt,args...) |
c609719b WD |
43 | #endif |
44 | #else | |
39539887 WD |
45 | #define PCNET_DEBUG1(fmt,args...) |
46 | #define PCNET_DEBUG2(fmt,args...) | |
c609719b WD |
47 | #endif |
48 | ||
c609719b WD |
49 | #if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975) |
50 | #error "Macro for PCnet chip version is not defined!" | |
51 | #endif | |
52 | ||
53 | /* | |
54 | * Set the number of Tx and Rx buffers, using Log_2(# buffers). | |
55 | * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. | |
56 | * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4). | |
57 | */ | |
58 | #define PCNET_LOG_TX_BUFFERS 0 | |
59 | #define PCNET_LOG_RX_BUFFERS 2 | |
60 | ||
61 | #define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS)) | |
62 | #define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12) | |
63 | ||
64 | #define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS)) | |
65 | #define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4) | |
66 | ||
67 | #define PKT_BUF_SZ 1544 | |
68 | ||
69 | /* The PCNET Rx and Tx ring descriptors. */ | |
70 | struct pcnet_rx_head { | |
11ea26fd WD |
71 | u32 base; |
72 | s16 buf_length; | |
73 | s16 status; | |
74 | u32 msg_length; | |
75 | u32 reserved; | |
c609719b WD |
76 | }; |
77 | ||
78 | struct pcnet_tx_head { | |
11ea26fd WD |
79 | u32 base; |
80 | s16 length; | |
81 | s16 status; | |
82 | u32 misc; | |
83 | u32 reserved; | |
c609719b WD |
84 | }; |
85 | ||
86 | /* The PCNET 32-Bit initialization block, described in databook. */ | |
87 | struct pcnet_init_block { | |
11ea26fd WD |
88 | u16 mode; |
89 | u16 tlen_rlen; | |
90 | u8 phys_addr[6]; | |
91 | u16 reserved; | |
92 | u32 filter[2]; | |
93 | /* Receive and transmit ring base, along with extra bits. */ | |
94 | u32 rx_ring; | |
95 | u32 tx_ring; | |
96 | u32 reserved2; | |
c609719b WD |
97 | }; |
98 | ||
99 | typedef struct pcnet_priv { | |
11ea26fd WD |
100 | struct pcnet_rx_head rx_ring[RX_RING_SIZE]; |
101 | struct pcnet_tx_head tx_ring[TX_RING_SIZE]; | |
102 | struct pcnet_init_block init_block; | |
103 | /* Receive Buffer space */ | |
104 | unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4]; | |
105 | int cur_rx; | |
106 | int cur_tx; | |
c609719b WD |
107 | } pcnet_priv_t; |
108 | ||
109 | static pcnet_priv_t *lp; | |
110 | ||
111 | /* Offsets from base I/O address for WIO mode */ | |
112 | #define PCNET_RDP 0x10 | |
113 | #define PCNET_RAP 0x12 | |
114 | #define PCNET_RESET 0x14 | |
115 | #define PCNET_BDP 0x16 | |
116 | ||
117 | static u16 pcnet_read_csr (struct eth_device *dev, int index) | |
118 | { | |
11ea26fd WD |
119 | outw (index, dev->iobase + PCNET_RAP); |
120 | return inw (dev->iobase + PCNET_RDP); | |
c609719b WD |
121 | } |
122 | ||
123 | static void pcnet_write_csr (struct eth_device *dev, int index, u16 val) | |
124 | { | |
11ea26fd WD |
125 | outw (index, dev->iobase + PCNET_RAP); |
126 | outw (val, dev->iobase + PCNET_RDP); | |
c609719b WD |
127 | } |
128 | ||
129 | static u16 pcnet_read_bcr (struct eth_device *dev, int index) | |
130 | { | |
11ea26fd WD |
131 | outw (index, dev->iobase + PCNET_RAP); |
132 | return inw (dev->iobase + PCNET_BDP); | |
c609719b WD |
133 | } |
134 | ||
135 | static void pcnet_write_bcr (struct eth_device *dev, int index, u16 val) | |
136 | { | |
11ea26fd WD |
137 | outw (index, dev->iobase + PCNET_RAP); |
138 | outw (val, dev->iobase + PCNET_BDP); | |
c609719b WD |
139 | } |
140 | ||
141 | static void pcnet_reset (struct eth_device *dev) | |
142 | { | |
11ea26fd | 143 | inw (dev->iobase + PCNET_RESET); |
c609719b WD |
144 | } |
145 | ||
146 | static int pcnet_check (struct eth_device *dev) | |
147 | { | |
11ea26fd WD |
148 | outw (88, dev->iobase + PCNET_RAP); |
149 | return (inw (dev->iobase + PCNET_RAP) == 88); | |
c609719b WD |
150 | } |
151 | ||
11ea26fd WD |
152 | static int pcnet_init (struct eth_device *dev, bd_t * bis); |
153 | static int pcnet_send (struct eth_device *dev, volatile void *packet, | |
154 | int length); | |
155 | static int pcnet_recv (struct eth_device *dev); | |
156 | static void pcnet_halt (struct eth_device *dev); | |
157 | static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num); | |
c609719b WD |
158 | |
159 | #define PCI_TO_MEM(d,a) pci_phys_to_mem((pci_dev_t)d->priv, (u_long)(a)) | |
160 | #define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a))) | |
161 | ||
162 | static struct pci_device_id supported[] = { | |
11ea26fd WD |
163 | {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE}, |
164 | {} | |
c609719b WD |
165 | }; |
166 | ||
167 | ||
11ea26fd | 168 | int pcnet_initialize (bd_t * bis) |
c609719b | 169 | { |
11ea26fd WD |
170 | pci_dev_t devbusfn; |
171 | struct eth_device *dev; | |
172 | u16 command, status; | |
173 | int dev_nr = 0; | |
174 | ||
175 | PCNET_DEBUG1 ("\npcnet_initialize...\n"); | |
176 | ||
177 | for (dev_nr = 0;; dev_nr++) { | |
178 | ||
179 | /* | |
180 | * Find the PCnet PCI device(s). | |
181 | */ | |
182 | if ((devbusfn = pci_find_devices (supported, dev_nr)) < 0) { | |
183 | break; | |
184 | } | |
185 | ||
186 | /* | |
187 | * Allocate and pre-fill the device structure. | |
188 | */ | |
189 | dev = (struct eth_device *) malloc (sizeof *dev); | |
190 | dev->priv = (void *) devbusfn; | |
191 | sprintf (dev->name, "pcnet#%d", dev_nr); | |
192 | ||
193 | /* | |
194 | * Setup the PCI device. | |
195 | */ | |
196 | pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, | |
197 | (unsigned int *) &dev->iobase); | |
38656319 | 198 | dev->iobase=pci_io_to_phys (devbusfn, dev->iobase); |
11ea26fd WD |
199 | dev->iobase &= ~0xf; |
200 | ||
201 | PCNET_DEBUG1 ("%s: devbusfn=0x%x iobase=0x%x: ", | |
202 | dev->name, devbusfn, dev->iobase); | |
203 | ||
204 | command = PCI_COMMAND_IO | PCI_COMMAND_MASTER; | |
205 | pci_write_config_word (devbusfn, PCI_COMMAND, command); | |
206 | pci_read_config_word (devbusfn, PCI_COMMAND, &status); | |
207 | if ((status & command) != command) { | |
208 | printf ("%s: Couldn't enable IO access or Bus Mastering\n", dev->name); | |
209 | free (dev); | |
210 | continue; | |
211 | } | |
212 | ||
213 | pci_write_config_byte (devbusfn, PCI_LATENCY_TIMER, 0x40); | |
214 | ||
215 | /* | |
216 | * Probe the PCnet chip. | |
217 | */ | |
218 | if (pcnet_probe (dev, bis, dev_nr) < 0) { | |
219 | free (dev); | |
220 | continue; | |
221 | } | |
222 | ||
223 | /* | |
224 | * Setup device structure and register the driver. | |
225 | */ | |
226 | dev->init = pcnet_init; | |
227 | dev->halt = pcnet_halt; | |
228 | dev->send = pcnet_send; | |
229 | dev->recv = pcnet_recv; | |
230 | ||
231 | eth_register (dev); | |
c609719b WD |
232 | } |
233 | ||
11ea26fd | 234 | udelay (10 * 1000); |
c609719b | 235 | |
11ea26fd | 236 | return dev_nr; |
c609719b WD |
237 | } |
238 | ||
11ea26fd | 239 | static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr) |
c609719b | 240 | { |
11ea26fd WD |
241 | int chip_version; |
242 | char *chipname; | |
243 | ||
c609719b | 244 | #ifdef PCNET_HAS_PROM |
11ea26fd | 245 | int i; |
c609719b WD |
246 | #endif |
247 | ||
11ea26fd WD |
248 | /* Reset the PCnet controller */ |
249 | pcnet_reset (dev); | |
250 | ||
251 | /* Check if register access is working */ | |
252 | if (pcnet_read_csr (dev, 0) != 4 || !pcnet_check (dev)) { | |
253 | printf ("%s: CSR register access check failed\n", dev->name); | |
254 | return -1; | |
255 | } | |
256 | ||
257 | /* Identify the chip */ | |
258 | chip_version = | |
259 | pcnet_read_csr (dev, 88) | (pcnet_read_csr (dev, 89) << 16); | |
260 | if ((chip_version & 0xfff) != 0x003) | |
261 | return -1; | |
262 | chip_version = (chip_version >> 12) & 0xffff; | |
263 | switch (chip_version) { | |
264 | case 0x2621: | |
265 | chipname = "PCnet/PCI II 79C970A"; /* PCI */ | |
266 | break; | |
c609719b | 267 | #ifdef CONFIG_PCNET_79C973 |
11ea26fd WD |
268 | case 0x2625: |
269 | chipname = "PCnet/FAST III 79C973"; /* PCI */ | |
270 | break; | |
c609719b WD |
271 | #endif |
272 | #ifdef CONFIG_PCNET_79C975 | |
11ea26fd WD |
273 | case 0x2627: |
274 | chipname = "PCnet/FAST III 79C975"; /* PCI */ | |
275 | break; | |
c609719b | 276 | #endif |
11ea26fd WD |
277 | default: |
278 | printf ("%s: PCnet version %#x not supported\n", | |
279 | dev->name, chip_version); | |
280 | return -1; | |
281 | } | |
c609719b | 282 | |
11ea26fd | 283 | PCNET_DEBUG1 ("AMD %s\n", chipname); |
c609719b WD |
284 | |
285 | #ifdef PCNET_HAS_PROM | |
11ea26fd WD |
286 | /* |
287 | * In most chips, after a chip reset, the ethernet address is read from | |
288 | * the station address PROM at the base address and programmed into the | |
289 | * "Physical Address Registers" CSR12-14. | |
290 | */ | |
291 | for (i = 0; i < 3; i++) { | |
292 | unsigned int val; | |
293 | ||
294 | val = pcnet_read_csr (dev, i + 12) & 0x0ffff; | |
295 | /* There may be endianness issues here. */ | |
296 | dev->enetaddr[2 * i] = val & 0x0ff; | |
297 | dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff; | |
298 | } | |
c609719b WD |
299 | #endif /* PCNET_HAS_PROM */ |
300 | ||
11ea26fd | 301 | return 0; |
c609719b WD |
302 | } |
303 | ||
11ea26fd | 304 | static int pcnet_init (struct eth_device *dev, bd_t * bis) |
c609719b | 305 | { |
11ea26fd WD |
306 | int i, val; |
307 | u32 addr; | |
c609719b | 308 | |
11ea26fd | 309 | PCNET_DEBUG1 ("%s: pcnet_init...\n", dev->name); |
c609719b | 310 | |
11ea26fd WD |
311 | /* Switch pcnet to 32bit mode */ |
312 | pcnet_write_bcr (dev, 20, 2); | |
c609719b WD |
313 | |
314 | #ifdef CONFIG_PN62 | |
11ea26fd WD |
315 | /* Setup LED registers */ |
316 | val = pcnet_read_bcr (dev, 2) | 0x1000; | |
317 | pcnet_write_bcr (dev, 2, val); /* enable LEDPE */ | |
318 | pcnet_write_bcr (dev, 4, 0x5080); /* 100MBit */ | |
319 | pcnet_write_bcr (dev, 5, 0x40c0); /* LNKSE */ | |
320 | pcnet_write_bcr (dev, 6, 0x4090); /* TX Activity */ | |
321 | pcnet_write_bcr (dev, 7, 0x4084); /* RX Activity */ | |
c609719b WD |
322 | #endif |
323 | ||
11ea26fd WD |
324 | /* Set/reset autoselect bit */ |
325 | val = pcnet_read_bcr (dev, 2) & ~2; | |
326 | val |= 2; | |
327 | pcnet_write_bcr (dev, 2, val); | |
c609719b | 328 | |
11ea26fd WD |
329 | /* Enable auto negotiate, setup, disable fd */ |
330 | val = pcnet_read_bcr (dev, 32) & ~0x98; | |
331 | val |= 0x20; | |
332 | pcnet_write_bcr (dev, 32, val); | |
c609719b | 333 | |
11ea26fd WD |
334 | /* |
335 | * We only maintain one structure because the drivers will never | |
336 | * be used concurrently. In 32bit mode the RX and TX ring entries | |
337 | * must be aligned on 16-byte boundaries. | |
338 | */ | |
339 | if (lp == NULL) { | |
340 | addr = (u32) malloc (sizeof (pcnet_priv_t) + 0x10); | |
341 | addr = (addr + 0xf) & ~0xf; | |
342 | lp = (pcnet_priv_t *) addr; | |
343 | } | |
c609719b | 344 | |
11ea26fd WD |
345 | lp->init_block.mode = cpu_to_le16 (0x0000); |
346 | lp->init_block.filter[0] = 0x00000000; | |
347 | lp->init_block.filter[1] = 0x00000000; | |
348 | ||
349 | /* | |
350 | * Initialize the Rx ring. | |
351 | */ | |
352 | lp->cur_rx = 0; | |
353 | for (i = 0; i < RX_RING_SIZE; i++) { | |
354 | lp->rx_ring[i].base = PCI_TO_MEM_LE (dev, lp->rx_buf[i]); | |
355 | lp->rx_ring[i].buf_length = cpu_to_le16 (-PKT_BUF_SZ); | |
356 | lp->rx_ring[i].status = cpu_to_le16 (0x8000); | |
357 | PCNET_DEBUG1 | |
358 | ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i, | |
359 | lp->rx_ring[i].base, lp->rx_ring[i].buf_length, | |
360 | lp->rx_ring[i].status); | |
361 | } | |
362 | ||
363 | /* | |
364 | * Initialize the Tx ring. The Tx buffer address is filled in as | |
365 | * needed, but we do need to clear the upper ownership bit. | |
366 | */ | |
c609719b | 367 | lp->cur_tx = 0; |
11ea26fd WD |
368 | for (i = 0; i < TX_RING_SIZE; i++) { |
369 | lp->tx_ring[i].base = 0; | |
370 | lp->tx_ring[i].status = 0; | |
371 | } | |
c609719b | 372 | |
11ea26fd WD |
373 | /* |
374 | * Setup Init Block. | |
375 | */ | |
376 | PCNET_DEBUG1 ("Init block at 0x%p: MAC", &lp->init_block); | |
c609719b | 377 | |
11ea26fd WD |
378 | for (i = 0; i < 6; i++) { |
379 | lp->init_block.phys_addr[i] = dev->enetaddr[i]; | |
380 | PCNET_DEBUG1 (" %02x", lp->init_block.phys_addr[i]); | |
381 | } | |
382 | ||
383 | lp->init_block.tlen_rlen = cpu_to_le16 (TX_RING_LEN_BITS | | |
384 | RX_RING_LEN_BITS); | |
385 | lp->init_block.rx_ring = PCI_TO_MEM_LE (dev, lp->rx_ring); | |
386 | lp->init_block.tx_ring = PCI_TO_MEM_LE (dev, lp->tx_ring); | |
387 | ||
388 | PCNET_DEBUG1 ("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n", | |
389 | lp->init_block.tlen_rlen, | |
390 | lp->init_block.rx_ring, lp->init_block.tx_ring); | |
c609719b | 391 | |
c609719b | 392 | /* |
11ea26fd | 393 | * Tell the controller where the Init Block is located. |
c609719b | 394 | */ |
11ea26fd WD |
395 | addr = PCI_TO_MEM (dev, &lp->init_block); |
396 | pcnet_write_csr (dev, 1, addr & 0xffff); | |
397 | pcnet_write_csr (dev, 2, (addr >> 16) & 0xffff); | |
398 | ||
399 | pcnet_write_csr (dev, 4, 0x0915); | |
400 | pcnet_write_csr (dev, 0, 0x0001); /* start */ | |
401 | ||
402 | /* Wait for Init Done bit */ | |
403 | for (i = 10000; i > 0; i--) { | |
404 | if (pcnet_read_csr (dev, 0) & 0x0100) | |
405 | break; | |
406 | udelay (10); | |
c609719b | 407 | } |
11ea26fd WD |
408 | if (i <= 0) { |
409 | printf ("%s: TIMEOUT: controller init failed\n", dev->name); | |
410 | pcnet_reset (dev); | |
411 | return -1; | |
c609719b | 412 | } |
c609719b | 413 | |
11ea26fd WD |
414 | /* |
415 | * Finally start network controller operation. | |
416 | */ | |
417 | pcnet_write_csr (dev, 0, 0x0002); | |
418 | ||
419 | return 0; | |
c609719b WD |
420 | } |
421 | ||
11ea26fd WD |
422 | static int pcnet_send (struct eth_device *dev, volatile void *packet, |
423 | int pkt_len) | |
c609719b | 424 | { |
11ea26fd WD |
425 | int i, status; |
426 | struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx]; | |
427 | ||
428 | PCNET_DEBUG2 ("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, | |
429 | packet); | |
430 | ||
431 | /* Wait for completion by testing the OWN bit */ | |
432 | for (i = 1000; i > 0; i--) { | |
433 | status = le16_to_cpu (entry->status); | |
434 | if ((status & 0x8000) == 0) | |
435 | break; | |
436 | udelay (100); | |
437 | PCNET_DEBUG2 ("."); | |
438 | } | |
439 | if (i <= 0) { | |
440 | printf ("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n", | |
441 | dev->name, lp->cur_tx, status); | |
442 | pkt_len = 0; | |
443 | goto failure; | |
444 | } | |
445 | ||
446 | /* | |
447 | * Setup Tx ring. Caution: the write order is important here, | |
448 | * set the status with the "ownership" bits last. | |
449 | */ | |
450 | status = 0x8300; | |
451 | entry->length = le16_to_cpu (-pkt_len); | |
452 | entry->misc = 0x00000000; | |
453 | entry->base = PCI_TO_MEM_LE (dev, packet); | |
454 | entry->status = le16_to_cpu (status); | |
455 | ||
456 | /* Trigger an immediate send poll. */ | |
457 | pcnet_write_csr (dev, 0, 0x0008); | |
458 | ||
459 | failure: | |
460 | if (++lp->cur_tx >= TX_RING_SIZE) | |
461 | lp->cur_tx = 0; | |
462 | ||
463 | PCNET_DEBUG2 ("done\n"); | |
464 | return pkt_len; | |
465 | } | |
466 | ||
467 | static int pcnet_recv (struct eth_device *dev) | |
468 | { | |
469 | struct pcnet_rx_head *entry; | |
470 | int pkt_len = 0; | |
471 | u16 status; | |
472 | ||
473 | while (1) { | |
474 | entry = &lp->rx_ring[lp->cur_rx]; | |
475 | /* | |
476 | * If we own the next entry, it's a new packet. Send it up. | |
477 | */ | |
478 | if (((status = le16_to_cpu (entry->status)) & 0x8000) != 0) { | |
479 | break; | |
480 | } | |
481 | status >>= 8; | |
482 | ||
483 | if (status != 0x03) { /* There was an error. */ | |
484 | ||
485 | printf ("%s: Rx%d", dev->name, lp->cur_rx); | |
486 | PCNET_DEBUG1 (" (status=0x%x)", status); | |
487 | if (status & 0x20) | |
488 | printf (" Frame"); | |
489 | if (status & 0x10) | |
490 | printf (" Overflow"); | |
491 | if (status & 0x08) | |
492 | printf (" CRC"); | |
493 | if (status & 0x04) | |
494 | printf (" Fifo"); | |
495 | printf (" Error\n"); | |
496 | entry->status &= le16_to_cpu (0x03ff); | |
497 | ||
498 | } else { | |
499 | ||
500 | pkt_len = | |
501 | (le32_to_cpu (entry->msg_length) & 0xfff) - 4; | |
502 | if (pkt_len < 60) { | |
503 | printf ("%s: Rx%d: invalid packet length %d\n", dev->name, lp->cur_rx, pkt_len); | |
504 | } else { | |
505 | NetReceive (lp->rx_buf[lp->cur_rx], pkt_len); | |
506 | PCNET_DEBUG2 ("Rx%d: %d bytes from 0x%p\n", | |
507 | lp->cur_rx, pkt_len, | |
508 | lp->rx_buf[lp->cur_rx]); | |
509 | } | |
510 | } | |
511 | entry->status |= cpu_to_le16 (0x8000); | |
512 | ||
513 | if (++lp->cur_rx >= RX_RING_SIZE) | |
514 | lp->cur_rx = 0; | |
515 | } | |
516 | return pkt_len; | |
c609719b WD |
517 | } |
518 | ||
11ea26fd WD |
519 | static void pcnet_halt (struct eth_device *dev) |
520 | { | |
521 | int i; | |
522 | ||
523 | PCNET_DEBUG1 ("%s: pcnet_halt...\n", dev->name); | |
524 | ||
525 | /* Reset the PCnet controller */ | |
526 | pcnet_reset (dev); | |
527 | ||
528 | /* Wait for Stop bit */ | |
529 | for (i = 1000; i > 0; i--) { | |
530 | if (pcnet_read_csr (dev, 0) & 0x4) | |
531 | break; | |
532 | udelay (10); | |
533 | } | |
534 | if (i <= 0) { | |
535 | printf ("%s: TIMEOUT: controller reset failed\n", dev->name); | |
536 | } | |
537 | } |