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Commit | Line | Data |
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c609719b WD |
1 | /* |
2 | * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de. | |
3 | * | |
4 | * This driver for AMD PCnet network controllers is derived from the | |
5 | * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer. | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
c609719b WD |
8 | */ |
9 | ||
10 | #include <common.h> | |
11 | #include <malloc.h> | |
12 | #include <net.h> | |
e3090534 | 13 | #include <netdev.h> |
c609719b WD |
14 | #include <asm/io.h> |
15 | #include <pci.h> | |
16 | ||
11ea26fd | 17 | #define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */ |
c609719b | 18 | |
138b6089 WD |
19 | #define PCNET_DEBUG1(fmt,args...) \ |
20 | debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args) | |
21 | #define PCNET_DEBUG2(fmt,args...) \ | |
22 | debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args) | |
c609719b | 23 | |
c609719b WD |
24 | #if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975) |
25 | #error "Macro for PCnet chip version is not defined!" | |
26 | #endif | |
27 | ||
28 | /* | |
29 | * Set the number of Tx and Rx buffers, using Log_2(# buffers). | |
30 | * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. | |
31 | * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4). | |
32 | */ | |
33 | #define PCNET_LOG_TX_BUFFERS 0 | |
34 | #define PCNET_LOG_RX_BUFFERS 2 | |
35 | ||
36 | #define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS)) | |
37 | #define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12) | |
38 | ||
39 | #define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS)) | |
40 | #define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4) | |
41 | ||
42 | #define PKT_BUF_SZ 1544 | |
43 | ||
44 | /* The PCNET Rx and Tx ring descriptors. */ | |
45 | struct pcnet_rx_head { | |
11ea26fd WD |
46 | u32 base; |
47 | s16 buf_length; | |
48 | s16 status; | |
49 | u32 msg_length; | |
50 | u32 reserved; | |
c609719b WD |
51 | }; |
52 | ||
53 | struct pcnet_tx_head { | |
11ea26fd WD |
54 | u32 base; |
55 | s16 length; | |
56 | s16 status; | |
57 | u32 misc; | |
58 | u32 reserved; | |
c609719b WD |
59 | }; |
60 | ||
61 | /* The PCNET 32-Bit initialization block, described in databook. */ | |
62 | struct pcnet_init_block { | |
11ea26fd WD |
63 | u16 mode; |
64 | u16 tlen_rlen; | |
65 | u8 phys_addr[6]; | |
66 | u16 reserved; | |
67 | u32 filter[2]; | |
68 | /* Receive and transmit ring base, along with extra bits. */ | |
69 | u32 rx_ring; | |
70 | u32 tx_ring; | |
71 | u32 reserved2; | |
c609719b WD |
72 | }; |
73 | ||
f1ae382d | 74 | struct pcnet_uncached_priv { |
11ea26fd WD |
75 | struct pcnet_rx_head rx_ring[RX_RING_SIZE]; |
76 | struct pcnet_tx_head tx_ring[TX_RING_SIZE]; | |
77 | struct pcnet_init_block init_block; | |
f1ae382d PB |
78 | }; |
79 | ||
80 | typedef struct pcnet_priv { | |
81 | struct pcnet_uncached_priv *uc; | |
11ea26fd | 82 | /* Receive Buffer space */ |
a354ddc3 | 83 | unsigned char (*rx_buf)[RX_RING_SIZE][PKT_BUF_SZ + 4]; |
11ea26fd WD |
84 | int cur_rx; |
85 | int cur_tx; | |
c609719b WD |
86 | } pcnet_priv_t; |
87 | ||
88 | static pcnet_priv_t *lp; | |
89 | ||
90 | /* Offsets from base I/O address for WIO mode */ | |
91 | #define PCNET_RDP 0x10 | |
92 | #define PCNET_RAP 0x12 | |
93 | #define PCNET_RESET 0x14 | |
94 | #define PCNET_BDP 0x16 | |
95 | ||
6011dabd | 96 | static u16 pcnet_read_csr(struct eth_device *dev, int index) |
c609719b | 97 | { |
6011dabd PB |
98 | outw(index, dev->iobase + PCNET_RAP); |
99 | return inw(dev->iobase + PCNET_RDP); | |
c609719b WD |
100 | } |
101 | ||
6011dabd | 102 | static void pcnet_write_csr(struct eth_device *dev, int index, u16 val) |
c609719b | 103 | { |
6011dabd PB |
104 | outw(index, dev->iobase + PCNET_RAP); |
105 | outw(val, dev->iobase + PCNET_RDP); | |
c609719b WD |
106 | } |
107 | ||
6011dabd | 108 | static u16 pcnet_read_bcr(struct eth_device *dev, int index) |
c609719b | 109 | { |
6011dabd PB |
110 | outw(index, dev->iobase + PCNET_RAP); |
111 | return inw(dev->iobase + PCNET_BDP); | |
c609719b WD |
112 | } |
113 | ||
6011dabd | 114 | static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val) |
c609719b | 115 | { |
6011dabd PB |
116 | outw(index, dev->iobase + PCNET_RAP); |
117 | outw(val, dev->iobase + PCNET_BDP); | |
c609719b WD |
118 | } |
119 | ||
6011dabd | 120 | static void pcnet_reset(struct eth_device *dev) |
c609719b | 121 | { |
6011dabd | 122 | inw(dev->iobase + PCNET_RESET); |
c609719b WD |
123 | } |
124 | ||
6011dabd | 125 | static int pcnet_check(struct eth_device *dev) |
c609719b | 126 | { |
6011dabd PB |
127 | outw(88, dev->iobase + PCNET_RAP); |
128 | return inw(dev->iobase + PCNET_RAP) == 88; | |
c609719b WD |
129 | } |
130 | ||
11ea26fd | 131 | static int pcnet_init (struct eth_device *dev, bd_t * bis); |
f92a151c | 132 | static int pcnet_send(struct eth_device *dev, void *packet, int length); |
11ea26fd WD |
133 | static int pcnet_recv (struct eth_device *dev); |
134 | static void pcnet_halt (struct eth_device *dev); | |
135 | static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num); | |
c609719b | 136 | |
54fbcb0c | 137 | #define PCI_TO_MEM(d, a) pci_virt_to_mem((pci_dev_t)d->priv, (a)) |
c609719b WD |
138 | #define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a))) |
139 | ||
140 | static struct pci_device_id supported[] = { | |
11ea26fd WD |
141 | {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE}, |
142 | {} | |
c609719b WD |
143 | }; |
144 | ||
145 | ||
6011dabd | 146 | int pcnet_initialize(bd_t *bis) |
c609719b | 147 | { |
11ea26fd WD |
148 | pci_dev_t devbusfn; |
149 | struct eth_device *dev; | |
150 | u16 command, status; | |
151 | int dev_nr = 0; | |
152 | ||
6011dabd | 153 | PCNET_DEBUG1("\npcnet_initialize...\n"); |
11ea26fd WD |
154 | |
155 | for (dev_nr = 0;; dev_nr++) { | |
156 | ||
157 | /* | |
158 | * Find the PCnet PCI device(s). | |
159 | */ | |
6011dabd PB |
160 | devbusfn = pci_find_devices(supported, dev_nr); |
161 | if (devbusfn < 0) | |
11ea26fd | 162 | break; |
11ea26fd WD |
163 | |
164 | /* | |
165 | * Allocate and pre-fill the device structure. | |
166 | */ | |
6011dabd | 167 | dev = (struct eth_device *)malloc(sizeof(*dev)); |
5ed0eeca NI |
168 | if (!dev) { |
169 | printf("pcnet: Can not allocate memory\n"); | |
170 | break; | |
171 | } | |
172 | memset(dev, 0, sizeof(*dev)); | |
6011dabd PB |
173 | dev->priv = (void *)devbusfn; |
174 | sprintf(dev->name, "pcnet#%d", dev_nr); | |
11ea26fd WD |
175 | |
176 | /* | |
177 | * Setup the PCI device. | |
178 | */ | |
6011dabd PB |
179 | pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, |
180 | (unsigned int *)&dev->iobase); | |
181 | dev->iobase = pci_io_to_phys(devbusfn, dev->iobase); | |
11ea26fd WD |
182 | dev->iobase &= ~0xf; |
183 | ||
6011dabd PB |
184 | PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ", |
185 | dev->name, devbusfn, dev->iobase); | |
11ea26fd WD |
186 | |
187 | command = PCI_COMMAND_IO | PCI_COMMAND_MASTER; | |
6011dabd PB |
188 | pci_write_config_word(devbusfn, PCI_COMMAND, command); |
189 | pci_read_config_word(devbusfn, PCI_COMMAND, &status); | |
11ea26fd | 190 | if ((status & command) != command) { |
6011dabd PB |
191 | printf("%s: Couldn't enable IO access or Bus Mastering\n", |
192 | dev->name); | |
193 | free(dev); | |
11ea26fd WD |
194 | continue; |
195 | } | |
196 | ||
6011dabd | 197 | pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40); |
11ea26fd WD |
198 | |
199 | /* | |
200 | * Probe the PCnet chip. | |
201 | */ | |
6011dabd PB |
202 | if (pcnet_probe(dev, bis, dev_nr) < 0) { |
203 | free(dev); | |
11ea26fd WD |
204 | continue; |
205 | } | |
206 | ||
207 | /* | |
208 | * Setup device structure and register the driver. | |
209 | */ | |
210 | dev->init = pcnet_init; | |
211 | dev->halt = pcnet_halt; | |
212 | dev->send = pcnet_send; | |
213 | dev->recv = pcnet_recv; | |
214 | ||
6011dabd | 215 | eth_register(dev); |
c609719b WD |
216 | } |
217 | ||
6011dabd | 218 | udelay(10 * 1000); |
c609719b | 219 | |
11ea26fd | 220 | return dev_nr; |
c609719b WD |
221 | } |
222 | ||
6011dabd | 223 | static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr) |
c609719b | 224 | { |
11ea26fd WD |
225 | int chip_version; |
226 | char *chipname; | |
227 | ||
c609719b | 228 | #ifdef PCNET_HAS_PROM |
11ea26fd | 229 | int i; |
c609719b WD |
230 | #endif |
231 | ||
11ea26fd | 232 | /* Reset the PCnet controller */ |
6011dabd | 233 | pcnet_reset(dev); |
11ea26fd WD |
234 | |
235 | /* Check if register access is working */ | |
6011dabd PB |
236 | if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) { |
237 | printf("%s: CSR register access check failed\n", dev->name); | |
11ea26fd WD |
238 | return -1; |
239 | } | |
240 | ||
241 | /* Identify the chip */ | |
242 | chip_version = | |
6011dabd | 243 | pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev, 89) << 16); |
11ea26fd WD |
244 | if ((chip_version & 0xfff) != 0x003) |
245 | return -1; | |
246 | chip_version = (chip_version >> 12) & 0xffff; | |
247 | switch (chip_version) { | |
248 | case 0x2621: | |
249 | chipname = "PCnet/PCI II 79C970A"; /* PCI */ | |
250 | break; | |
c609719b | 251 | #ifdef CONFIG_PCNET_79C973 |
11ea26fd WD |
252 | case 0x2625: |
253 | chipname = "PCnet/FAST III 79C973"; /* PCI */ | |
254 | break; | |
c609719b WD |
255 | #endif |
256 | #ifdef CONFIG_PCNET_79C975 | |
11ea26fd WD |
257 | case 0x2627: |
258 | chipname = "PCnet/FAST III 79C975"; /* PCI */ | |
259 | break; | |
c609719b | 260 | #endif |
11ea26fd | 261 | default: |
6011dabd PB |
262 | printf("%s: PCnet version %#x not supported\n", |
263 | dev->name, chip_version); | |
11ea26fd WD |
264 | return -1; |
265 | } | |
c609719b | 266 | |
6011dabd | 267 | PCNET_DEBUG1("AMD %s\n", chipname); |
c609719b WD |
268 | |
269 | #ifdef PCNET_HAS_PROM | |
11ea26fd WD |
270 | /* |
271 | * In most chips, after a chip reset, the ethernet address is read from | |
272 | * the station address PROM at the base address and programmed into the | |
273 | * "Physical Address Registers" CSR12-14. | |
274 | */ | |
275 | for (i = 0; i < 3; i++) { | |
276 | unsigned int val; | |
277 | ||
6011dabd | 278 | val = pcnet_read_csr(dev, i + 12) & 0x0ffff; |
11ea26fd WD |
279 | /* There may be endianness issues here. */ |
280 | dev->enetaddr[2 * i] = val & 0x0ff; | |
281 | dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff; | |
282 | } | |
c609719b WD |
283 | #endif /* PCNET_HAS_PROM */ |
284 | ||
11ea26fd | 285 | return 0; |
c609719b WD |
286 | } |
287 | ||
6011dabd | 288 | static int pcnet_init(struct eth_device *dev, bd_t *bis) |
c609719b | 289 | { |
f1ae382d | 290 | struct pcnet_uncached_priv *uc; |
11ea26fd WD |
291 | int i, val; |
292 | u32 addr; | |
c609719b | 293 | |
6011dabd | 294 | PCNET_DEBUG1("%s: pcnet_init...\n", dev->name); |
c609719b | 295 | |
11ea26fd | 296 | /* Switch pcnet to 32bit mode */ |
6011dabd | 297 | pcnet_write_bcr(dev, 20, 2); |
c609719b | 298 | |
11ea26fd | 299 | /* Set/reset autoselect bit */ |
6011dabd | 300 | val = pcnet_read_bcr(dev, 2) & ~2; |
11ea26fd | 301 | val |= 2; |
6011dabd | 302 | pcnet_write_bcr(dev, 2, val); |
c609719b | 303 | |
11ea26fd | 304 | /* Enable auto negotiate, setup, disable fd */ |
6011dabd | 305 | val = pcnet_read_bcr(dev, 32) & ~0x98; |
11ea26fd | 306 | val |= 0x20; |
6011dabd | 307 | pcnet_write_bcr(dev, 32, val); |
c609719b | 308 | |
62715a2c PB |
309 | /* |
310 | * Enable NOUFLO on supported controllers, with the transmit | |
311 | * start point set to the full packet. This will cause entire | |
312 | * packets to be buffered by the ethernet controller before | |
313 | * transmission, eliminating underflows which are common on | |
314 | * slower devices. Controllers which do not support NOUFLO will | |
315 | * simply be left with a larger transmit FIFO threshold. | |
316 | */ | |
317 | val = pcnet_read_bcr(dev, 18); | |
318 | val |= 1 << 11; | |
319 | pcnet_write_bcr(dev, 18, val); | |
320 | val = pcnet_read_csr(dev, 80); | |
321 | val |= 0x3 << 10; | |
322 | pcnet_write_csr(dev, 80, val); | |
323 | ||
11ea26fd WD |
324 | /* |
325 | * We only maintain one structure because the drivers will never | |
326 | * be used concurrently. In 32bit mode the RX and TX ring entries | |
327 | * must be aligned on 16-byte boundaries. | |
328 | */ | |
329 | if (lp == NULL) { | |
6011dabd | 330 | addr = (u32)malloc(sizeof(pcnet_priv_t) + 0x10); |
11ea26fd | 331 | addr = (addr + 0xf) & ~0xf; |
6011dabd | 332 | lp = (pcnet_priv_t *)addr; |
f1ae382d PB |
333 | |
334 | addr = (u32)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->uc)); | |
335 | flush_dcache_range(addr, addr + sizeof(*lp->uc)); | |
336 | addr = UNCACHED_SDRAM(addr); | |
337 | lp->uc = (struct pcnet_uncached_priv *)addr; | |
a354ddc3 PB |
338 | |
339 | addr = (u32)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->rx_buf)); | |
340 | flush_dcache_range(addr, addr + sizeof(*lp->rx_buf)); | |
341 | lp->rx_buf = (void *)addr; | |
11ea26fd | 342 | } |
c609719b | 343 | |
f1ae382d PB |
344 | uc = lp->uc; |
345 | ||
346 | uc->init_block.mode = cpu_to_le16(0x0000); | |
347 | uc->init_block.filter[0] = 0x00000000; | |
348 | uc->init_block.filter[1] = 0x00000000; | |
11ea26fd WD |
349 | |
350 | /* | |
351 | * Initialize the Rx ring. | |
352 | */ | |
353 | lp->cur_rx = 0; | |
354 | for (i = 0; i < RX_RING_SIZE; i++) { | |
a354ddc3 | 355 | uc->rx_ring[i].base = PCI_TO_MEM_LE(dev, (*lp->rx_buf)[i]); |
f1ae382d PB |
356 | uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ); |
357 | uc->rx_ring[i].status = cpu_to_le16(0x8000); | |
11ea26fd WD |
358 | PCNET_DEBUG1 |
359 | ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i, | |
f1ae382d PB |
360 | uc->rx_ring[i].base, uc->rx_ring[i].buf_length, |
361 | uc->rx_ring[i].status); | |
11ea26fd WD |
362 | } |
363 | ||
364 | /* | |
365 | * Initialize the Tx ring. The Tx buffer address is filled in as | |
366 | * needed, but we do need to clear the upper ownership bit. | |
367 | */ | |
c609719b | 368 | lp->cur_tx = 0; |
11ea26fd | 369 | for (i = 0; i < TX_RING_SIZE; i++) { |
f1ae382d PB |
370 | uc->tx_ring[i].base = 0; |
371 | uc->tx_ring[i].status = 0; | |
11ea26fd | 372 | } |
c609719b | 373 | |
11ea26fd WD |
374 | /* |
375 | * Setup Init Block. | |
376 | */ | |
f1ae382d | 377 | PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block); |
c609719b | 378 | |
11ea26fd | 379 | for (i = 0; i < 6; i++) { |
f1ae382d PB |
380 | lp->uc->init_block.phys_addr[i] = dev->enetaddr[i]; |
381 | PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]); | |
11ea26fd WD |
382 | } |
383 | ||
f1ae382d | 384 | uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS | |
6011dabd | 385 | RX_RING_LEN_BITS); |
f1ae382d PB |
386 | uc->init_block.rx_ring = PCI_TO_MEM_LE(dev, uc->rx_ring); |
387 | uc->init_block.tx_ring = PCI_TO_MEM_LE(dev, uc->tx_ring); | |
11ea26fd | 388 | |
6011dabd | 389 | PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n", |
f1ae382d PB |
390 | uc->init_block.tlen_rlen, |
391 | uc->init_block.rx_ring, uc->init_block.tx_ring); | |
c609719b | 392 | |
c609719b | 393 | /* |
11ea26fd | 394 | * Tell the controller where the Init Block is located. |
c609719b | 395 | */ |
f1ae382d PB |
396 | barrier(); |
397 | addr = PCI_TO_MEM(dev, &lp->uc->init_block); | |
6011dabd PB |
398 | pcnet_write_csr(dev, 1, addr & 0xffff); |
399 | pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff); | |
11ea26fd | 400 | |
6011dabd PB |
401 | pcnet_write_csr(dev, 4, 0x0915); |
402 | pcnet_write_csr(dev, 0, 0x0001); /* start */ | |
11ea26fd WD |
403 | |
404 | /* Wait for Init Done bit */ | |
405 | for (i = 10000; i > 0; i--) { | |
6011dabd | 406 | if (pcnet_read_csr(dev, 0) & 0x0100) |
11ea26fd | 407 | break; |
6011dabd | 408 | udelay(10); |
c609719b | 409 | } |
11ea26fd | 410 | if (i <= 0) { |
6011dabd PB |
411 | printf("%s: TIMEOUT: controller init failed\n", dev->name); |
412 | pcnet_reset(dev); | |
11ea26fd | 413 | return -1; |
c609719b | 414 | } |
c609719b | 415 | |
11ea26fd WD |
416 | /* |
417 | * Finally start network controller operation. | |
418 | */ | |
6011dabd | 419 | pcnet_write_csr(dev, 0, 0x0002); |
11ea26fd WD |
420 | |
421 | return 0; | |
c609719b WD |
422 | } |
423 | ||
f92a151c | 424 | static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) |
c609719b | 425 | { |
11ea26fd | 426 | int i, status; |
f1ae382d | 427 | struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx]; |
11ea26fd | 428 | |
6011dabd PB |
429 | PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, |
430 | packet); | |
11ea26fd | 431 | |
f3ac866c PB |
432 | flush_dcache_range((unsigned long)packet, |
433 | (unsigned long)packet + pkt_len); | |
434 | ||
11ea26fd WD |
435 | /* Wait for completion by testing the OWN bit */ |
436 | for (i = 1000; i > 0; i--) { | |
6fb49e4a | 437 | status = readw(&entry->status); |
11ea26fd WD |
438 | if ((status & 0x8000) == 0) |
439 | break; | |
6011dabd PB |
440 | udelay(100); |
441 | PCNET_DEBUG2("."); | |
11ea26fd WD |
442 | } |
443 | if (i <= 0) { | |
6011dabd PB |
444 | printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n", |
445 | dev->name, lp->cur_tx, status); | |
11ea26fd WD |
446 | pkt_len = 0; |
447 | goto failure; | |
448 | } | |
449 | ||
450 | /* | |
451 | * Setup Tx ring. Caution: the write order is important here, | |
452 | * set the status with the "ownership" bits last. | |
453 | */ | |
6fb49e4a PB |
454 | writew(-pkt_len, &entry->length); |
455 | writel(0, &entry->misc); | |
456 | writel(PCI_TO_MEM(dev, packet), &entry->base); | |
457 | writew(0x8300, &entry->status); | |
11ea26fd WD |
458 | |
459 | /* Trigger an immediate send poll. */ | |
6011dabd | 460 | pcnet_write_csr(dev, 0, 0x0008); |
11ea26fd WD |
461 | |
462 | failure: | |
463 | if (++lp->cur_tx >= TX_RING_SIZE) | |
464 | lp->cur_tx = 0; | |
465 | ||
6011dabd | 466 | PCNET_DEBUG2("done\n"); |
11ea26fd WD |
467 | return pkt_len; |
468 | } | |
469 | ||
470 | static int pcnet_recv (struct eth_device *dev) | |
471 | { | |
472 | struct pcnet_rx_head *entry; | |
a354ddc3 | 473 | unsigned char *buf; |
11ea26fd | 474 | int pkt_len = 0; |
6fb49e4a | 475 | u16 status, err_status; |
11ea26fd WD |
476 | |
477 | while (1) { | |
f1ae382d | 478 | entry = &lp->uc->rx_ring[lp->cur_rx]; |
11ea26fd WD |
479 | /* |
480 | * If we own the next entry, it's a new packet. Send it up. | |
481 | */ | |
6fb49e4a | 482 | status = readw(&entry->status); |
6011dabd | 483 | if ((status & 0x8000) != 0) |
11ea26fd | 484 | break; |
6fb49e4a | 485 | err_status = status >> 8; |
11ea26fd | 486 | |
6fb49e4a | 487 | if (err_status != 0x03) { /* There was an error. */ |
6011dabd | 488 | printf("%s: Rx%d", dev->name, lp->cur_rx); |
6fb49e4a PB |
489 | PCNET_DEBUG1(" (status=0x%x)", err_status); |
490 | if (err_status & 0x20) | |
6011dabd | 491 | printf(" Frame"); |
6fb49e4a | 492 | if (err_status & 0x10) |
6011dabd | 493 | printf(" Overflow"); |
6fb49e4a | 494 | if (err_status & 0x08) |
6011dabd | 495 | printf(" CRC"); |
6fb49e4a | 496 | if (err_status & 0x04) |
6011dabd PB |
497 | printf(" Fifo"); |
498 | printf(" Error\n"); | |
6fb49e4a | 499 | status &= 0x03ff; |
11ea26fd WD |
500 | |
501 | } else { | |
6fb49e4a | 502 | pkt_len = (readl(&entry->msg_length) & 0xfff) - 4; |
11ea26fd | 503 | if (pkt_len < 60) { |
6011dabd PB |
504 | printf("%s: Rx%d: invalid packet length %d\n", |
505 | dev->name, lp->cur_rx, pkt_len); | |
11ea26fd | 506 | } else { |
a354ddc3 PB |
507 | buf = (*lp->rx_buf)[lp->cur_rx]; |
508 | invalidate_dcache_range((unsigned long)buf, | |
509 | (unsigned long)buf + pkt_len); | |
1fd92db8 | 510 | net_process_received_packet(buf, pkt_len); |
6011dabd | 511 | PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n", |
a354ddc3 | 512 | lp->cur_rx, pkt_len, buf); |
11ea26fd WD |
513 | } |
514 | } | |
6fb49e4a PB |
515 | |
516 | status |= 0x8000; | |
517 | writew(status, &entry->status); | |
11ea26fd WD |
518 | |
519 | if (++lp->cur_rx >= RX_RING_SIZE) | |
520 | lp->cur_rx = 0; | |
521 | } | |
522 | return pkt_len; | |
c609719b WD |
523 | } |
524 | ||
6011dabd | 525 | static void pcnet_halt(struct eth_device *dev) |
11ea26fd WD |
526 | { |
527 | int i; | |
528 | ||
6011dabd | 529 | PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name); |
11ea26fd WD |
530 | |
531 | /* Reset the PCnet controller */ | |
6011dabd | 532 | pcnet_reset(dev); |
11ea26fd WD |
533 | |
534 | /* Wait for Stop bit */ | |
535 | for (i = 1000; i > 0; i--) { | |
6011dabd | 536 | if (pcnet_read_csr(dev, 0) & 0x4) |
11ea26fd | 537 | break; |
6011dabd | 538 | udelay(10); |
11ea26fd | 539 | } |
6011dabd PB |
540 | if (i <= 0) |
541 | printf("%s: TIMEOUT: controller reset failed\n", dev->name); | |
11ea26fd | 542 | } |