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a2443fd1 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
cb646e2b RC |
2 | /* |
3 | * Driver for the National Semiconductor DP83640 PHYTER | |
4 | * | |
5 | * Copyright (C) 2010 OMICRON electronics GmbH | |
cb646e2b | 6 | */ |
8d242488 JP |
7 | |
8 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
9 | ||
539e44d2 | 10 | #include <linux/crc32.h> |
cb646e2b RC |
11 | #include <linux/ethtool.h> |
12 | #include <linux/kernel.h> | |
13 | #include <linux/list.h> | |
14 | #include <linux/mii.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/net_tstamp.h> | |
17 | #include <linux/netdevice.h> | |
408eccce | 18 | #include <linux/if_vlan.h> |
cb646e2b RC |
19 | #include <linux/phy.h> |
20 | #include <linux/ptp_classify.h> | |
21 | #include <linux/ptp_clock_kernel.h> | |
22 | ||
23 | #include "dp83640_reg.h" | |
24 | ||
25 | #define DP83640_PHY_ID 0x20005ce1 | |
26 | #define PAGESEL 0x13 | |
8028837d | 27 | #define MAX_RXTS 64 |
49b3fd4a | 28 | #define N_EXT_TS 6 |
ad01577a | 29 | #define N_PER_OUT 7 |
cb646e2b RC |
30 | #define PSF_PTPVER 2 |
31 | #define PSF_EVNT 0x4000 | |
32 | #define PSF_RX 0x2000 | |
33 | #define PSF_TX 0x1000 | |
34 | #define EXT_EVENT 1 | |
49b3fd4a | 35 | #define CAL_EVENT 7 |
397a253a | 36 | #define CAL_TRIGGER 1 |
86dd3612 | 37 | #define DP83640_N_PINS 12 |
cb646e2b | 38 | |
1642182e SG |
39 | #define MII_DP83640_MICR 0x11 |
40 | #define MII_DP83640_MISR 0x12 | |
41 | ||
42 | #define MII_DP83640_MICR_OE 0x1 | |
43 | #define MII_DP83640_MICR_IE 0x2 | |
44 | ||
45 | #define MII_DP83640_MISR_RHF_INT_EN 0x01 | |
46 | #define MII_DP83640_MISR_FHF_INT_EN 0x02 | |
47 | #define MII_DP83640_MISR_ANC_INT_EN 0x04 | |
48 | #define MII_DP83640_MISR_DUP_INT_EN 0x08 | |
49 | #define MII_DP83640_MISR_SPD_INT_EN 0x10 | |
50 | #define MII_DP83640_MISR_LINK_INT_EN 0x20 | |
51 | #define MII_DP83640_MISR_ED_INT_EN 0x40 | |
52 | #define MII_DP83640_MISR_LQ_INT_EN 0x80 | |
53 | ||
cb646e2b RC |
54 | /* phyter seems to miss the mark by 16 ns */ |
55 | #define ADJTIME_FIX 16 | |
56 | ||
4b063258 SS |
57 | #define SKB_TIMESTAMP_TIMEOUT 2 /* jiffies */ |
58 | ||
cb646e2b RC |
59 | #if defined(__BIG_ENDIAN) |
60 | #define ENDIAN_FLAG 0 | |
61 | #elif defined(__LITTLE_ENDIAN) | |
62 | #define ENDIAN_FLAG PSF_ENDIAN | |
63 | #endif | |
64 | ||
63502b8d SS |
65 | struct dp83640_skb_info { |
66 | int ptp_type; | |
67 | unsigned long tmo; | |
68 | }; | |
cb646e2b RC |
69 | |
70 | struct phy_rxts { | |
71 | u16 ns_lo; /* ns[15:0] */ | |
72 | u16 ns_hi; /* overflow[1:0], ns[29:16] */ | |
73 | u16 sec_lo; /* sec[15:0] */ | |
74 | u16 sec_hi; /* sec[31:16] */ | |
75 | u16 seqid; /* sequenceId[15:0] */ | |
76 | u16 msgtype; /* messageType[3:0], hash[11:0] */ | |
77 | }; | |
78 | ||
79 | struct phy_txts { | |
80 | u16 ns_lo; /* ns[15:0] */ | |
81 | u16 ns_hi; /* overflow[1:0], ns[29:16] */ | |
82 | u16 sec_lo; /* sec[15:0] */ | |
83 | u16 sec_hi; /* sec[31:16] */ | |
84 | }; | |
85 | ||
86 | struct rxts { | |
87 | struct list_head list; | |
88 | unsigned long tmo; | |
89 | u64 ns; | |
90 | u16 seqid; | |
91 | u8 msgtype; | |
92 | u16 hash; | |
93 | }; | |
94 | ||
95 | struct dp83640_clock; | |
96 | ||
97 | struct dp83640_private { | |
98 | struct list_head list; | |
99 | struct dp83640_clock *clock; | |
100 | struct phy_device *phydev; | |
4715f65f | 101 | struct mii_timestamper mii_ts; |
4b063258 | 102 | struct delayed_work ts_work; |
cb646e2b RC |
103 | int hwts_tx_en; |
104 | int hwts_rx_en; | |
105 | int layer; | |
106 | int version; | |
107 | /* remember state of cfg0 during calibration */ | |
108 | int cfg0; | |
109 | /* remember the last event time stamp */ | |
110 | struct phy_txts edata; | |
111 | /* list of rx timestamps */ | |
112 | struct list_head rxts; | |
113 | struct list_head rxpool; | |
114 | struct rxts rx_pool_data[MAX_RXTS]; | |
115 | /* protects above three fields from concurrent access */ | |
116 | spinlock_t rx_lock; | |
117 | /* queues of incoming and outgoing packets */ | |
118 | struct sk_buff_head rx_queue; | |
119 | struct sk_buff_head tx_queue; | |
120 | }; | |
121 | ||
122 | struct dp83640_clock { | |
123 | /* keeps the instance in the 'phyter_clocks' list */ | |
124 | struct list_head list; | |
125 | /* we create one clock instance per MII bus */ | |
126 | struct mii_bus *bus; | |
127 | /* protects extended registers from concurrent access */ | |
128 | struct mutex extreg_lock; | |
129 | /* remembers which page was last selected */ | |
130 | int page; | |
131 | /* our advertised capabilities */ | |
132 | struct ptp_clock_info caps; | |
133 | /* protects the three fields below from concurrent access */ | |
134 | struct mutex clock_lock; | |
135 | /* the one phyter from which we shall read */ | |
136 | struct dp83640_private *chosen; | |
137 | /* list of the other attached phyters, not chosen */ | |
138 | struct list_head phylist; | |
139 | /* reference to our PTP hardware clock */ | |
140 | struct ptp_clock *ptp_clock; | |
141 | }; | |
142 | ||
143 | /* globals */ | |
144 | ||
49b3fd4a RC |
145 | enum { |
146 | CALIBRATE_GPIO, | |
147 | PEROUT_GPIO, | |
148 | EXTTS0_GPIO, | |
149 | EXTTS1_GPIO, | |
150 | EXTTS2_GPIO, | |
151 | EXTTS3_GPIO, | |
152 | EXTTS4_GPIO, | |
153 | EXTTS5_GPIO, | |
154 | GPIO_TABLE_SIZE | |
155 | }; | |
156 | ||
cb646e2b | 157 | static int chosen_phy = -1; |
49b3fd4a RC |
158 | static ushort gpio_tab[GPIO_TABLE_SIZE] = { |
159 | 1, 2, 3, 4, 8, 9, 10, 11 | |
160 | }; | |
cb646e2b RC |
161 | |
162 | module_param(chosen_phy, int, 0444); | |
49b3fd4a | 163 | module_param_array(gpio_tab, ushort, NULL, 0444); |
cb646e2b RC |
164 | |
165 | MODULE_PARM_DESC(chosen_phy, \ | |
166 | "The address of the PHY to use for the ancillary clock features"); | |
49b3fd4a RC |
167 | MODULE_PARM_DESC(gpio_tab, \ |
168 | "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6"); | |
cb646e2b | 169 | |
86dd3612 RC |
170 | static void dp83640_gpio_defaults(struct ptp_pin_desc *pd) |
171 | { | |
172 | int i, index; | |
173 | ||
174 | for (i = 0; i < DP83640_N_PINS; i++) { | |
175 | snprintf(pd[i].name, sizeof(pd[i].name), "GPIO%d", 1 + i); | |
176 | pd[i].index = i; | |
177 | } | |
178 | ||
179 | for (i = 0; i < GPIO_TABLE_SIZE; i++) { | |
180 | if (gpio_tab[i] < 1 || gpio_tab[i] > DP83640_N_PINS) { | |
181 | pr_err("gpio_tab[%d]=%hu out of range", i, gpio_tab[i]); | |
182 | return; | |
183 | } | |
184 | } | |
185 | ||
186 | index = gpio_tab[CALIBRATE_GPIO] - 1; | |
187 | pd[index].func = PTP_PF_PHYSYNC; | |
188 | pd[index].chan = 0; | |
189 | ||
190 | index = gpio_tab[PEROUT_GPIO] - 1; | |
191 | pd[index].func = PTP_PF_PEROUT; | |
192 | pd[index].chan = 0; | |
193 | ||
194 | for (i = EXTTS0_GPIO; i < GPIO_TABLE_SIZE; i++) { | |
195 | index = gpio_tab[i] - 1; | |
196 | pd[index].func = PTP_PF_EXTTS; | |
197 | pd[index].chan = i - EXTTS0_GPIO; | |
198 | } | |
199 | } | |
200 | ||
cb646e2b RC |
201 | /* a list of clocks and a mutex to protect it */ |
202 | static LIST_HEAD(phyter_clocks); | |
203 | static DEFINE_MUTEX(phyter_clocks_lock); | |
204 | ||
205 | static void rx_timestamp_work(struct work_struct *work); | |
206 | ||
207 | /* extended register access functions */ | |
208 | ||
209 | #define BROADCAST_ADDR 31 | |
210 | ||
e5a03bfd AL |
211 | static inline int broadcast_write(struct phy_device *phydev, u32 regnum, |
212 | u16 val) | |
cb646e2b | 213 | { |
e5a03bfd | 214 | return mdiobus_write(phydev->mdio.bus, BROADCAST_ADDR, regnum, val); |
cb646e2b RC |
215 | } |
216 | ||
217 | /* Caller must hold extreg_lock. */ | |
218 | static int ext_read(struct phy_device *phydev, int page, u32 regnum) | |
219 | { | |
220 | struct dp83640_private *dp83640 = phydev->priv; | |
221 | int val; | |
222 | ||
223 | if (dp83640->clock->page != page) { | |
e5a03bfd | 224 | broadcast_write(phydev, PAGESEL, page); |
cb646e2b RC |
225 | dp83640->clock->page = page; |
226 | } | |
227 | val = phy_read(phydev, regnum); | |
228 | ||
229 | return val; | |
230 | } | |
231 | ||
232 | /* Caller must hold extreg_lock. */ | |
233 | static void ext_write(int broadcast, struct phy_device *phydev, | |
234 | int page, u32 regnum, u16 val) | |
235 | { | |
236 | struct dp83640_private *dp83640 = phydev->priv; | |
237 | ||
238 | if (dp83640->clock->page != page) { | |
e5a03bfd | 239 | broadcast_write(phydev, PAGESEL, page); |
cb646e2b RC |
240 | dp83640->clock->page = page; |
241 | } | |
242 | if (broadcast) | |
e5a03bfd | 243 | broadcast_write(phydev, regnum, val); |
cb646e2b RC |
244 | else |
245 | phy_write(phydev, regnum, val); | |
246 | } | |
247 | ||
248 | /* Caller must hold extreg_lock. */ | |
249 | static int tdr_write(int bc, struct phy_device *dev, | |
41c2c18f | 250 | const struct timespec64 *ts, u16 cmd) |
cb646e2b RC |
251 | { |
252 | ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */ | |
253 | ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */ | |
254 | ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */ | |
255 | ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/ | |
256 | ||
257 | ext_write(bc, dev, PAGE4, PTP_CTL, cmd); | |
258 | ||
259 | return 0; | |
260 | } | |
261 | ||
262 | /* convert phy timestamps into driver timestamps */ | |
263 | ||
264 | static void phy2rxts(struct phy_rxts *p, struct rxts *rxts) | |
265 | { | |
266 | u32 sec; | |
267 | ||
268 | sec = p->sec_lo; | |
269 | sec |= p->sec_hi << 16; | |
270 | ||
271 | rxts->ns = p->ns_lo; | |
272 | rxts->ns |= (p->ns_hi & 0x3fff) << 16; | |
273 | rxts->ns += ((u64)sec) * 1000000000ULL; | |
274 | rxts->seqid = p->seqid; | |
275 | rxts->msgtype = (p->msgtype >> 12) & 0xf; | |
276 | rxts->hash = p->msgtype & 0x0fff; | |
4b063258 | 277 | rxts->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT; |
cb646e2b RC |
278 | } |
279 | ||
280 | static u64 phy2txts(struct phy_txts *p) | |
281 | { | |
282 | u64 ns; | |
283 | u32 sec; | |
284 | ||
285 | sec = p->sec_lo; | |
286 | sec |= p->sec_hi << 16; | |
287 | ||
288 | ns = p->ns_lo; | |
289 | ns |= (p->ns_hi & 0x3fff) << 16; | |
290 | ns += ((u64)sec) * 1000000000ULL; | |
291 | ||
292 | return ns; | |
293 | } | |
294 | ||
621bdecc | 295 | static int periodic_output(struct dp83640_clock *clock, |
ad01577a SS |
296 | struct ptp_clock_request *clkreq, bool on, |
297 | int trigger) | |
49b3fd4a RC |
298 | { |
299 | struct dp83640_private *dp83640 = clock->chosen; | |
300 | struct phy_device *phydev = dp83640->phydev; | |
564ca56e | 301 | u32 sec, nsec, pwidth; |
ad01577a | 302 | u16 gpio, ptp_trig, val; |
49b3fd4a | 303 | |
621bdecc | 304 | if (on) { |
ad01577a SS |
305 | gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT, |
306 | trigger); | |
621bdecc RC |
307 | if (gpio < 1) |
308 | return -EINVAL; | |
309 | } else { | |
310 | gpio = 0; | |
311 | } | |
312 | ||
49b3fd4a RC |
313 | ptp_trig = TRIG_WR | |
314 | (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT | | |
315 | (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT | | |
316 | TRIG_PER | | |
317 | TRIG_PULSE; | |
318 | ||
319 | val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; | |
320 | ||
321 | if (!on) { | |
322 | val |= TRIG_DIS; | |
323 | mutex_lock(&clock->extreg_lock); | |
324 | ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig); | |
325 | ext_write(0, phydev, PAGE4, PTP_CTL, val); | |
326 | mutex_unlock(&clock->extreg_lock); | |
621bdecc | 327 | return 0; |
49b3fd4a RC |
328 | } |
329 | ||
330 | sec = clkreq->perout.start.sec; | |
331 | nsec = clkreq->perout.start.nsec; | |
564ca56e RC |
332 | pwidth = clkreq->perout.period.sec * 1000000000UL; |
333 | pwidth += clkreq->perout.period.nsec; | |
334 | pwidth /= 2; | |
49b3fd4a RC |
335 | |
336 | mutex_lock(&clock->extreg_lock); | |
337 | ||
338 | ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig); | |
339 | ||
340 | /*load trigger*/ | |
341 | val |= TRIG_LOAD; | |
342 | ext_write(0, phydev, PAGE4, PTP_CTL, val); | |
343 | ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff); /* ns[15:0] */ | |
344 | ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16); /* ns[31:16] */ | |
345 | ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff); /* sec[15:0] */ | |
346 | ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16); /* sec[31:16] */ | |
564ca56e RC |
347 | ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); /* ns[15:0] */ |
348 | ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); /* ns[31:16] */ | |
35e872ae SS |
349 | /* Triggers 0 and 1 has programmable pulsewidth2 */ |
350 | if (trigger < 2) { | |
351 | ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); | |
352 | ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); | |
353 | } | |
49b3fd4a RC |
354 | |
355 | /*enable trigger*/ | |
356 | val &= ~TRIG_LOAD; | |
357 | val |= TRIG_EN; | |
358 | ext_write(0, phydev, PAGE4, PTP_CTL, val); | |
359 | ||
360 | mutex_unlock(&clock->extreg_lock); | |
621bdecc | 361 | return 0; |
49b3fd4a RC |
362 | } |
363 | ||
cb646e2b RC |
364 | /* ptp clock methods */ |
365 | ||
e4788b80 | 366 | static int ptp_dp83640_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) |
cb646e2b RC |
367 | { |
368 | struct dp83640_clock *clock = | |
369 | container_of(ptp, struct dp83640_clock, caps); | |
370 | struct phy_device *phydev = clock->chosen->phydev; | |
371 | u64 rate; | |
372 | int neg_adj = 0; | |
373 | u16 hi, lo; | |
374 | ||
e4788b80 | 375 | if (scaled_ppm < 0) { |
cb646e2b | 376 | neg_adj = 1; |
e4788b80 | 377 | scaled_ppm = -scaled_ppm; |
cb646e2b | 378 | } |
e4788b80 RC |
379 | rate = scaled_ppm; |
380 | rate <<= 13; | |
381 | rate = div_u64(rate, 15625); | |
cb646e2b RC |
382 | |
383 | hi = (rate >> 16) & PTP_RATE_HI_MASK; | |
384 | if (neg_adj) | |
385 | hi |= PTP_RATE_DIR; | |
386 | ||
387 | lo = rate & 0xffff; | |
388 | ||
389 | mutex_lock(&clock->extreg_lock); | |
390 | ||
391 | ext_write(1, phydev, PAGE4, PTP_RATEH, hi); | |
392 | ext_write(1, phydev, PAGE4, PTP_RATEL, lo); | |
393 | ||
394 | mutex_unlock(&clock->extreg_lock); | |
395 | ||
396 | return 0; | |
397 | } | |
398 | ||
399 | static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta) | |
400 | { | |
401 | struct dp83640_clock *clock = | |
402 | container_of(ptp, struct dp83640_clock, caps); | |
403 | struct phy_device *phydev = clock->chosen->phydev; | |
41c2c18f | 404 | struct timespec64 ts; |
cb646e2b RC |
405 | int err; |
406 | ||
407 | delta += ADJTIME_FIX; | |
408 | ||
41c2c18f | 409 | ts = ns_to_timespec64(delta); |
cb646e2b RC |
410 | |
411 | mutex_lock(&clock->extreg_lock); | |
412 | ||
413 | err = tdr_write(1, phydev, &ts, PTP_STEP_CLK); | |
414 | ||
415 | mutex_unlock(&clock->extreg_lock); | |
416 | ||
417 | return err; | |
418 | } | |
419 | ||
41c2c18f RC |
420 | static int ptp_dp83640_gettime(struct ptp_clock_info *ptp, |
421 | struct timespec64 *ts) | |
cb646e2b RC |
422 | { |
423 | struct dp83640_clock *clock = | |
424 | container_of(ptp, struct dp83640_clock, caps); | |
425 | struct phy_device *phydev = clock->chosen->phydev; | |
426 | unsigned int val[4]; | |
427 | ||
428 | mutex_lock(&clock->extreg_lock); | |
429 | ||
430 | ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK); | |
431 | ||
432 | val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */ | |
433 | val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */ | |
434 | val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */ | |
435 | val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */ | |
436 | ||
437 | mutex_unlock(&clock->extreg_lock); | |
438 | ||
439 | ts->tv_nsec = val[0] | (val[1] << 16); | |
440 | ts->tv_sec = val[2] | (val[3] << 16); | |
441 | ||
442 | return 0; | |
443 | } | |
444 | ||
445 | static int ptp_dp83640_settime(struct ptp_clock_info *ptp, | |
41c2c18f | 446 | const struct timespec64 *ts) |
cb646e2b RC |
447 | { |
448 | struct dp83640_clock *clock = | |
449 | container_of(ptp, struct dp83640_clock, caps); | |
450 | struct phy_device *phydev = clock->chosen->phydev; | |
451 | int err; | |
452 | ||
453 | mutex_lock(&clock->extreg_lock); | |
454 | ||
455 | err = tdr_write(1, phydev, ts, PTP_LOAD_CLK); | |
456 | ||
457 | mutex_unlock(&clock->extreg_lock); | |
458 | ||
459 | return err; | |
460 | } | |
461 | ||
462 | static int ptp_dp83640_enable(struct ptp_clock_info *ptp, | |
463 | struct ptp_clock_request *rq, int on) | |
464 | { | |
465 | struct dp83640_clock *clock = | |
466 | container_of(ptp, struct dp83640_clock, caps); | |
467 | struct phy_device *phydev = clock->chosen->phydev; | |
fbf4b934 | 468 | unsigned int index; |
49b3fd4a | 469 | u16 evnt, event_num, gpio_num; |
cb646e2b RC |
470 | |
471 | switch (rq->type) { | |
472 | case PTP_CLK_REQ_EXTTS: | |
e8e9c98d JK |
473 | /* Reject requests with unsupported flags */ |
474 | if (rq->extts.flags & ~(PTP_ENABLE_FEATURE | | |
475 | PTP_RISING_EDGE | | |
6138e687 RC |
476 | PTP_FALLING_EDGE | |
477 | PTP_STRICT_FLAGS)) | |
e8e9c98d | 478 | return -EOPNOTSUPP; |
9289252b RC |
479 | |
480 | /* Reject requests to enable time stamping on both edges. */ | |
481 | if ((rq->extts.flags & PTP_STRICT_FLAGS) && | |
482 | (rq->extts.flags & PTP_ENABLE_FEATURE) && | |
483 | (rq->extts.flags & PTP_EXTTS_EDGES) == PTP_EXTTS_EDGES) | |
484 | return -EOPNOTSUPP; | |
485 | ||
49b3fd4a | 486 | index = rq->extts.index; |
fbf4b934 | 487 | if (index >= N_EXT_TS) |
cb646e2b | 488 | return -EINVAL; |
49b3fd4a RC |
489 | event_num = EXT_EVENT + index; |
490 | evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT; | |
cb646e2b | 491 | if (on) { |
faa89716 RC |
492 | gpio_num = 1 + ptp_find_pin(clock->ptp_clock, |
493 | PTP_PF_EXTTS, index); | |
494 | if (gpio_num < 1) | |
495 | return -EINVAL; | |
49b3fd4a | 496 | evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT; |
80671bd2 SS |
497 | if (rq->extts.flags & PTP_FALLING_EDGE) |
498 | evnt |= EVNT_FALL; | |
499 | else | |
500 | evnt |= EVNT_RISE; | |
cb646e2b | 501 | } |
a935865c | 502 | mutex_lock(&clock->extreg_lock); |
cb646e2b | 503 | ext_write(0, phydev, PAGE5, PTP_EVNT, evnt); |
a935865c | 504 | mutex_unlock(&clock->extreg_lock); |
cb646e2b | 505 | return 0; |
49b3fd4a RC |
506 | |
507 | case PTP_CLK_REQ_PEROUT: | |
7f9048f1 JK |
508 | /* Reject requests with unsupported flags */ |
509 | if (rq->perout.flags) | |
510 | return -EOPNOTSUPP; | |
ad01577a | 511 | if (rq->perout.index >= N_PER_OUT) |
49b3fd4a | 512 | return -EINVAL; |
ad01577a | 513 | return periodic_output(clock, rq, on, rq->perout.index); |
49b3fd4a | 514 | |
cb646e2b RC |
515 | default: |
516 | break; | |
517 | } | |
518 | ||
519 | return -EOPNOTSUPP; | |
520 | } | |
521 | ||
86dd3612 RC |
522 | static int ptp_dp83640_verify(struct ptp_clock_info *ptp, unsigned int pin, |
523 | enum ptp_pin_function func, unsigned int chan) | |
524 | { | |
6f39eb87 SS |
525 | struct dp83640_clock *clock = |
526 | container_of(ptp, struct dp83640_clock, caps); | |
527 | ||
528 | if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC && | |
529 | !list_empty(&clock->phylist)) | |
530 | return 1; | |
531 | ||
532 | if (func == PTP_PF_PHYSYNC) | |
533 | return 1; | |
534 | ||
86dd3612 RC |
535 | return 0; |
536 | } | |
537 | ||
cb646e2b RC |
538 | static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 }; |
539 | static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F }; | |
540 | ||
541 | static void enable_status_frames(struct phy_device *phydev, bool on) | |
542 | { | |
a935865c RC |
543 | struct dp83640_private *dp83640 = phydev->priv; |
544 | struct dp83640_clock *clock = dp83640->clock; | |
cb646e2b RC |
545 | u16 cfg0 = 0, ver; |
546 | ||
547 | if (on) | |
548 | cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG; | |
549 | ||
550 | ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT; | |
551 | ||
a935865c RC |
552 | mutex_lock(&clock->extreg_lock); |
553 | ||
cb646e2b RC |
554 | ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0); |
555 | ext_write(0, phydev, PAGE6, PSF_CFG1, ver); | |
556 | ||
a935865c RC |
557 | mutex_unlock(&clock->extreg_lock); |
558 | ||
cb646e2b | 559 | if (!phydev->attached_dev) { |
ab2a605f AL |
560 | phydev_warn(phydev, |
561 | "expected to find an attached netdevice\n"); | |
cb646e2b RC |
562 | return; |
563 | } | |
564 | ||
565 | if (on) { | |
566 | if (dev_mc_add(phydev->attached_dev, status_frame_dst)) | |
ab2a605f | 567 | phydev_warn(phydev, "failed to add mc address\n"); |
cb646e2b RC |
568 | } else { |
569 | if (dev_mc_del(phydev->attached_dev, status_frame_dst)) | |
ab2a605f | 570 | phydev_warn(phydev, "failed to delete mc address\n"); |
cb646e2b RC |
571 | } |
572 | } | |
573 | ||
574 | static bool is_status_frame(struct sk_buff *skb, int type) | |
575 | { | |
576 | struct ethhdr *h = eth_hdr(skb); | |
577 | ||
578 | if (PTP_CLASS_V2_L2 == type && | |
579 | !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src))) | |
580 | return true; | |
581 | else | |
582 | return false; | |
583 | } | |
584 | ||
585 | static int expired(struct rxts *rxts) | |
586 | { | |
587 | return time_after(jiffies, rxts->tmo); | |
588 | } | |
589 | ||
590 | /* Caller must hold rx_lock. */ | |
591 | static void prune_rx_ts(struct dp83640_private *dp83640) | |
592 | { | |
593 | struct list_head *this, *next; | |
594 | struct rxts *rxts; | |
595 | ||
596 | list_for_each_safe(this, next, &dp83640->rxts) { | |
597 | rxts = list_entry(this, struct rxts, list); | |
598 | if (expired(rxts)) { | |
599 | list_del_init(&rxts->list); | |
600 | list_add(&rxts->list, &dp83640->rxpool); | |
601 | } | |
602 | } | |
603 | } | |
604 | ||
605 | /* synchronize the phyters so they act as one clock */ | |
606 | ||
607 | static void enable_broadcast(struct phy_device *phydev, int init_page, int on) | |
608 | { | |
609 | int val; | |
610 | phy_write(phydev, PAGESEL, 0); | |
611 | val = phy_read(phydev, PHYCR2); | |
612 | if (on) | |
613 | val |= BC_WRITE; | |
614 | else | |
615 | val &= ~BC_WRITE; | |
616 | phy_write(phydev, PHYCR2, val); | |
617 | phy_write(phydev, PAGESEL, init_page); | |
618 | } | |
619 | ||
620 | static void recalibrate(struct dp83640_clock *clock) | |
621 | { | |
622 | s64 now, diff; | |
623 | struct phy_txts event_ts; | |
41c2c18f | 624 | struct timespec64 ts; |
cb646e2b RC |
625 | struct list_head *this; |
626 | struct dp83640_private *tmp; | |
627 | struct phy_device *master = clock->chosen->phydev; | |
49b3fd4a | 628 | u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val; |
cb646e2b RC |
629 | |
630 | trigger = CAL_TRIGGER; | |
62582a7e | 631 | cal_gpio = 1 + ptp_find_pin_unlocked(clock->ptp_clock, PTP_PF_PHYSYNC, 0); |
e0155950 | 632 | if (cal_gpio < 1) { |
f42cf8d6 | 633 | pr_err("PHY calibration pin not available - PHY is not calibrated."); |
e0155950 SS |
634 | return; |
635 | } | |
cb646e2b RC |
636 | |
637 | mutex_lock(&clock->extreg_lock); | |
638 | ||
639 | /* | |
640 | * enable broadcast, disable status frames, enable ptp clock | |
641 | */ | |
642 | list_for_each(this, &clock->phylist) { | |
643 | tmp = list_entry(this, struct dp83640_private, list); | |
644 | enable_broadcast(tmp->phydev, clock->page, 1); | |
645 | tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0); | |
646 | ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0); | |
647 | ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE); | |
648 | } | |
649 | enable_broadcast(master, clock->page, 1); | |
650 | cfg0 = ext_read(master, PAGE5, PSF_CFG0); | |
651 | ext_write(0, master, PAGE5, PSF_CFG0, 0); | |
652 | ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE); | |
653 | ||
654 | /* | |
655 | * enable an event timestamp | |
656 | */ | |
657 | evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE; | |
658 | evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT; | |
659 | evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT; | |
660 | ||
661 | list_for_each(this, &clock->phylist) { | |
662 | tmp = list_entry(this, struct dp83640_private, list); | |
663 | ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt); | |
664 | } | |
665 | ext_write(0, master, PAGE5, PTP_EVNT, evnt); | |
666 | ||
667 | /* | |
668 | * configure a trigger | |
669 | */ | |
670 | ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE; | |
671 | ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT; | |
672 | ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT; | |
673 | ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig); | |
674 | ||
675 | /* load trigger */ | |
676 | val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; | |
677 | val |= TRIG_LOAD; | |
678 | ext_write(0, master, PAGE4, PTP_CTL, val); | |
679 | ||
680 | /* enable trigger */ | |
681 | val &= ~TRIG_LOAD; | |
682 | val |= TRIG_EN; | |
683 | ext_write(0, master, PAGE4, PTP_CTL, val); | |
684 | ||
685 | /* disable trigger */ | |
686 | val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; | |
687 | val |= TRIG_DIS; | |
688 | ext_write(0, master, PAGE4, PTP_CTL, val); | |
689 | ||
690 | /* | |
691 | * read out and correct offsets | |
692 | */ | |
693 | val = ext_read(master, PAGE4, PTP_STS); | |
c4fabb8b | 694 | phydev_info(master, "master PTP_STS 0x%04hx\n", val); |
cb646e2b | 695 | val = ext_read(master, PAGE4, PTP_ESTS); |
c4fabb8b | 696 | phydev_info(master, "master PTP_ESTS 0x%04hx\n", val); |
cb646e2b RC |
697 | event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA); |
698 | event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA); | |
699 | event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA); | |
700 | event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA); | |
701 | now = phy2txts(&event_ts); | |
702 | ||
703 | list_for_each(this, &clock->phylist) { | |
704 | tmp = list_entry(this, struct dp83640_private, list); | |
705 | val = ext_read(tmp->phydev, PAGE4, PTP_STS); | |
c4fabb8b | 706 | phydev_info(tmp->phydev, "slave PTP_STS 0x%04hx\n", val); |
cb646e2b | 707 | val = ext_read(tmp->phydev, PAGE4, PTP_ESTS); |
c4fabb8b | 708 | phydev_info(tmp->phydev, "slave PTP_ESTS 0x%04hx\n", val); |
cb646e2b RC |
709 | event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA); |
710 | event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA); | |
711 | event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA); | |
712 | event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA); | |
713 | diff = now - (s64) phy2txts(&event_ts); | |
c4fabb8b AL |
714 | phydev_info(tmp->phydev, "slave offset %lld nanoseconds\n", |
715 | diff); | |
cb646e2b | 716 | diff += ADJTIME_FIX; |
41c2c18f | 717 | ts = ns_to_timespec64(diff); |
cb646e2b RC |
718 | tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK); |
719 | } | |
720 | ||
721 | /* | |
722 | * restore status frames | |
723 | */ | |
724 | list_for_each(this, &clock->phylist) { | |
725 | tmp = list_entry(this, struct dp83640_private, list); | |
726 | ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0); | |
727 | } | |
728 | ext_write(0, master, PAGE5, PSF_CFG0, cfg0); | |
729 | ||
730 | mutex_unlock(&clock->extreg_lock); | |
731 | } | |
732 | ||
733 | /* time stamping methods */ | |
734 | ||
49b3fd4a RC |
735 | static inline u16 exts_chan_to_edata(int ch) |
736 | { | |
737 | return 1 << ((ch + EXT_EVENT) * 2); | |
738 | } | |
739 | ||
2331038a | 740 | static int decode_evnt(struct dp83640_private *dp83640, |
13322f2e | 741 | void *data, int len, u16 ests) |
cb646e2b | 742 | { |
2331038a | 743 | struct phy_txts *phy_txts; |
cb646e2b | 744 | struct ptp_clock_event event; |
49b3fd4a | 745 | int i, parsed; |
cb646e2b | 746 | int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK; |
2331038a RC |
747 | u16 ext_status = 0; |
748 | ||
13322f2e CR |
749 | /* calculate length of the event timestamp status message */ |
750 | if (ests & MULT_EVNT) | |
751 | parsed = (words + 2) * sizeof(u16); | |
752 | else | |
753 | parsed = (words + 1) * sizeof(u16); | |
754 | ||
755 | /* check if enough data is available */ | |
756 | if (len < parsed) | |
757 | return len; | |
758 | ||
2331038a RC |
759 | if (ests & MULT_EVNT) { |
760 | ext_status = *(u16 *) data; | |
761 | data += sizeof(ext_status); | |
762 | } | |
763 | ||
764 | phy_txts = data; | |
cb646e2b | 765 | |
d331e758 | 766 | switch (words) { |
cb646e2b RC |
767 | case 3: |
768 | dp83640->edata.sec_hi = phy_txts->sec_hi; | |
d331e758 | 769 | /* fall through */ |
cb646e2b RC |
770 | case 2: |
771 | dp83640->edata.sec_lo = phy_txts->sec_lo; | |
d331e758 | 772 | /* fall through */ |
cb646e2b RC |
773 | case 1: |
774 | dp83640->edata.ns_hi = phy_txts->ns_hi; | |
d331e758 | 775 | /* fall through */ |
cb646e2b RC |
776 | case 0: |
777 | dp83640->edata.ns_lo = phy_txts->ns_lo; | |
778 | } | |
779 | ||
13322f2e | 780 | if (!ext_status) { |
49b3fd4a RC |
781 | i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT; |
782 | ext_status = exts_chan_to_edata(i); | |
783 | } | |
784 | ||
cb646e2b | 785 | event.type = PTP_CLOCK_EXTTS; |
cb646e2b RC |
786 | event.timestamp = phy2txts(&dp83640->edata); |
787 | ||
a0077a9f SS |
788 | /* Compensate for input path and synchronization delays */ |
789 | event.timestamp -= 35; | |
790 | ||
49b3fd4a RC |
791 | for (i = 0; i < N_EXT_TS; i++) { |
792 | if (ext_status & exts_chan_to_edata(i)) { | |
793 | event.index = i; | |
794 | ptp_clock_event(dp83640->clock->ptp_clock, &event); | |
795 | } | |
796 | } | |
2331038a | 797 | |
13322f2e | 798 | return parsed; |
cb646e2b RC |
799 | } |
800 | ||
539e44d2 SS |
801 | #define DP83640_PACKET_HASH_OFFSET 20 |
802 | #define DP83640_PACKET_HASH_LEN 10 | |
803 | ||
63502b8d SS |
804 | static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts) |
805 | { | |
539e44d2 | 806 | u16 *seqid, hash; |
63502b8d SS |
807 | unsigned int offset = 0; |
808 | u8 *msgtype, *data = skb_mac_header(skb); | |
809 | ||
810 | /* check sequenceID, messageType, 12 bit hash of offset 20-29 */ | |
811 | ||
812 | if (type & PTP_CLASS_VLAN) | |
813 | offset += VLAN_HLEN; | |
814 | ||
815 | switch (type & PTP_CLASS_PMASK) { | |
816 | case PTP_CLASS_IPV4: | |
cca04b28 | 817 | offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN; |
63502b8d SS |
818 | break; |
819 | case PTP_CLASS_IPV6: | |
820 | offset += ETH_HLEN + IP6_HLEN + UDP_HLEN; | |
821 | break; | |
822 | case PTP_CLASS_L2: | |
823 | offset += ETH_HLEN; | |
824 | break; | |
825 | default: | |
826 | return 0; | |
827 | } | |
828 | ||
829 | if (skb->len + ETH_HLEN < offset + OFF_PTP_SEQUENCE_ID + sizeof(*seqid)) | |
830 | return 0; | |
831 | ||
832 | if (unlikely(type & PTP_CLASS_V1)) | |
833 | msgtype = data + offset + OFF_PTP_CONTROL; | |
834 | else | |
835 | msgtype = data + offset; | |
539e44d2 SS |
836 | if (rxts->msgtype != (*msgtype & 0xf)) |
837 | return 0; | |
63502b8d SS |
838 | |
839 | seqid = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID); | |
539e44d2 SS |
840 | if (rxts->seqid != ntohs(*seqid)) |
841 | return 0; | |
842 | ||
843 | hash = ether_crc(DP83640_PACKET_HASH_LEN, | |
844 | data + offset + DP83640_PACKET_HASH_OFFSET) >> 20; | |
845 | if (rxts->hash != hash) | |
846 | return 0; | |
63502b8d | 847 | |
539e44d2 | 848 | return 1; |
63502b8d SS |
849 | } |
850 | ||
cb646e2b RC |
851 | static void decode_rxts(struct dp83640_private *dp83640, |
852 | struct phy_rxts *phy_rxts) | |
853 | { | |
854 | struct rxts *rxts; | |
63502b8d SS |
855 | struct skb_shared_hwtstamps *shhwtstamps = NULL; |
856 | struct sk_buff *skb; | |
cb646e2b | 857 | unsigned long flags; |
81e8f2e9 MR |
858 | u8 overflow; |
859 | ||
860 | overflow = (phy_rxts->ns_hi >> 14) & 0x3; | |
861 | if (overflow) | |
862 | pr_debug("rx timestamp queue overflow, count %d\n", overflow); | |
cb646e2b RC |
863 | |
864 | spin_lock_irqsave(&dp83640->rx_lock, flags); | |
865 | ||
866 | prune_rx_ts(dp83640); | |
867 | ||
868 | if (list_empty(&dp83640->rxpool)) { | |
8d242488 | 869 | pr_debug("rx timestamp pool is empty\n"); |
cb646e2b RC |
870 | goto out; |
871 | } | |
872 | rxts = list_first_entry(&dp83640->rxpool, struct rxts, list); | |
873 | list_del_init(&rxts->list); | |
874 | phy2rxts(phy_rxts, rxts); | |
63502b8d | 875 | |
adbe088f | 876 | spin_lock(&dp83640->rx_queue.lock); |
63502b8d SS |
877 | skb_queue_walk(&dp83640->rx_queue, skb) { |
878 | struct dp83640_skb_info *skb_info; | |
879 | ||
880 | skb_info = (struct dp83640_skb_info *)skb->cb; | |
881 | if (match(skb, skb_info->ptp_type, rxts)) { | |
882 | __skb_unlink(skb, &dp83640->rx_queue); | |
883 | shhwtstamps = skb_hwtstamps(skb); | |
884 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); | |
885 | shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns); | |
63502b8d SS |
886 | list_add(&rxts->list, &dp83640->rxpool); |
887 | break; | |
888 | } | |
889 | } | |
adbe088f | 890 | spin_unlock(&dp83640->rx_queue.lock); |
63502b8d SS |
891 | |
892 | if (!shhwtstamps) | |
893 | list_add_tail(&rxts->list, &dp83640->rxts); | |
cb646e2b RC |
894 | out: |
895 | spin_unlock_irqrestore(&dp83640->rx_lock, flags); | |
d36b82bc SS |
896 | |
897 | if (shhwtstamps) | |
898 | netif_rx_ni(skb); | |
cb646e2b RC |
899 | } |
900 | ||
901 | static void decode_txts(struct dp83640_private *dp83640, | |
902 | struct phy_txts *phy_txts) | |
903 | { | |
904 | struct skb_shared_hwtstamps shhwtstamps; | |
53bc8d2a | 905 | struct dp83640_skb_info *skb_info; |
cb646e2b | 906 | struct sk_buff *skb; |
81e8f2e9 | 907 | u8 overflow; |
53bc8d2a | 908 | u64 ns; |
cb646e2b RC |
909 | |
910 | /* We must already have the skb that triggered this. */ | |
53bc8d2a | 911 | again: |
cb646e2b | 912 | skb = skb_dequeue(&dp83640->tx_queue); |
cb646e2b | 913 | if (!skb) { |
8d242488 | 914 | pr_debug("have timestamp but tx_queue empty\n"); |
cb646e2b RC |
915 | return; |
916 | } | |
81e8f2e9 MR |
917 | |
918 | overflow = (phy_txts->ns_hi >> 14) & 0x3; | |
919 | if (overflow) { | |
920 | pr_debug("tx timestamp queue overflow, count %d\n", overflow); | |
921 | while (skb) { | |
db9d8b29 | 922 | kfree_skb(skb); |
81e8f2e9 MR |
923 | skb = skb_dequeue(&dp83640->tx_queue); |
924 | } | |
925 | return; | |
926 | } | |
53bc8d2a SAS |
927 | skb_info = (struct dp83640_skb_info *)skb->cb; |
928 | if (time_after(jiffies, skb_info->tmo)) { | |
929 | kfree_skb(skb); | |
930 | goto again; | |
931 | } | |
81e8f2e9 | 932 | |
cb646e2b RC |
933 | ns = phy2txts(phy_txts); |
934 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | |
935 | shhwtstamps.hwtstamp = ns_to_ktime(ns); | |
936 | skb_complete_tx_timestamp(skb, &shhwtstamps); | |
937 | } | |
938 | ||
939 | static void decode_status_frame(struct dp83640_private *dp83640, | |
940 | struct sk_buff *skb) | |
941 | { | |
942 | struct phy_rxts *phy_rxts; | |
943 | struct phy_txts *phy_txts; | |
944 | u8 *ptr; | |
945 | int len, size; | |
946 | u16 ests, type; | |
947 | ||
948 | ptr = skb->data + 2; | |
949 | ||
950 | for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) { | |
951 | ||
952 | type = *(u16 *)ptr; | |
953 | ests = type & 0x0fff; | |
954 | type = type & 0xf000; | |
955 | len -= sizeof(type); | |
956 | ptr += sizeof(type); | |
957 | ||
958 | if (PSF_RX == type && len >= sizeof(*phy_rxts)) { | |
959 | ||
960 | phy_rxts = (struct phy_rxts *) ptr; | |
961 | decode_rxts(dp83640, phy_rxts); | |
962 | size = sizeof(*phy_rxts); | |
963 | ||
964 | } else if (PSF_TX == type && len >= sizeof(*phy_txts)) { | |
965 | ||
966 | phy_txts = (struct phy_txts *) ptr; | |
967 | decode_txts(dp83640, phy_txts); | |
968 | size = sizeof(*phy_txts); | |
969 | ||
13322f2e | 970 | } else if (PSF_EVNT == type) { |
cb646e2b | 971 | |
13322f2e | 972 | size = decode_evnt(dp83640, ptr, len, ests); |
cb646e2b RC |
973 | |
974 | } else { | |
975 | size = 0; | |
976 | break; | |
977 | } | |
978 | ptr += size; | |
979 | } | |
980 | } | |
981 | ||
dccaa9e0 RC |
982 | static int is_sync(struct sk_buff *skb, int type) |
983 | { | |
984 | u8 *data = skb->data, *msgtype; | |
985 | unsigned int offset = 0; | |
986 | ||
ae5c6c6d SS |
987 | if (type & PTP_CLASS_VLAN) |
988 | offset += VLAN_HLEN; | |
989 | ||
990 | switch (type & PTP_CLASS_PMASK) { | |
991 | case PTP_CLASS_IPV4: | |
cca04b28 | 992 | offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN; |
dccaa9e0 | 993 | break; |
ae5c6c6d SS |
994 | case PTP_CLASS_IPV6: |
995 | offset += ETH_HLEN + IP6_HLEN + UDP_HLEN; | |
dccaa9e0 | 996 | break; |
ae5c6c6d SS |
997 | case PTP_CLASS_L2: |
998 | offset += ETH_HLEN; | |
dccaa9e0 RC |
999 | break; |
1000 | default: | |
1001 | return 0; | |
1002 | } | |
1003 | ||
1004 | if (type & PTP_CLASS_V1) | |
1005 | offset += OFF_PTP_CONTROL; | |
1006 | ||
1007 | if (skb->len < offset + 1) | |
1008 | return 0; | |
1009 | ||
1010 | msgtype = data + offset; | |
1011 | ||
1012 | return (*msgtype & 0xf) == 0; | |
1013 | } | |
1014 | ||
cb646e2b RC |
1015 | static void dp83640_free_clocks(void) |
1016 | { | |
1017 | struct dp83640_clock *clock; | |
1018 | struct list_head *this, *next; | |
1019 | ||
1020 | mutex_lock(&phyter_clocks_lock); | |
1021 | ||
1022 | list_for_each_safe(this, next, &phyter_clocks) { | |
1023 | clock = list_entry(this, struct dp83640_clock, list); | |
1024 | if (!list_empty(&clock->phylist)) { | |
8d242488 | 1025 | pr_warn("phy list non-empty while unloading\n"); |
cb646e2b RC |
1026 | BUG(); |
1027 | } | |
1028 | list_del(&clock->list); | |
1029 | mutex_destroy(&clock->extreg_lock); | |
1030 | mutex_destroy(&clock->clock_lock); | |
1031 | put_device(&clock->bus->dev); | |
86dd3612 | 1032 | kfree(clock->caps.pin_config); |
cb646e2b RC |
1033 | kfree(clock); |
1034 | } | |
1035 | ||
1036 | mutex_unlock(&phyter_clocks_lock); | |
1037 | } | |
1038 | ||
1039 | static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus) | |
1040 | { | |
1041 | INIT_LIST_HEAD(&clock->list); | |
1042 | clock->bus = bus; | |
1043 | mutex_init(&clock->extreg_lock); | |
1044 | mutex_init(&clock->clock_lock); | |
1045 | INIT_LIST_HEAD(&clock->phylist); | |
1046 | clock->caps.owner = THIS_MODULE; | |
1047 | sprintf(clock->caps.name, "dp83640 timer"); | |
1048 | clock->caps.max_adj = 1953124; | |
1049 | clock->caps.n_alarm = 0; | |
1050 | clock->caps.n_ext_ts = N_EXT_TS; | |
ad01577a | 1051 | clock->caps.n_per_out = N_PER_OUT; |
86dd3612 | 1052 | clock->caps.n_pins = DP83640_N_PINS; |
cb646e2b | 1053 | clock->caps.pps = 0; |
e4788b80 | 1054 | clock->caps.adjfine = ptp_dp83640_adjfine; |
cb646e2b | 1055 | clock->caps.adjtime = ptp_dp83640_adjtime; |
41c2c18f RC |
1056 | clock->caps.gettime64 = ptp_dp83640_gettime; |
1057 | clock->caps.settime64 = ptp_dp83640_settime; | |
cb646e2b | 1058 | clock->caps.enable = ptp_dp83640_enable; |
86dd3612 RC |
1059 | clock->caps.verify = ptp_dp83640_verify; |
1060 | /* | |
1061 | * Convert the module param defaults into a dynamic pin configuration. | |
1062 | */ | |
1063 | dp83640_gpio_defaults(clock->caps.pin_config); | |
cb646e2b RC |
1064 | /* |
1065 | * Get a reference to this bus instance. | |
1066 | */ | |
1067 | get_device(&bus->dev); | |
1068 | } | |
1069 | ||
1070 | static int choose_this_phy(struct dp83640_clock *clock, | |
1071 | struct phy_device *phydev) | |
1072 | { | |
1073 | if (chosen_phy == -1 && !clock->chosen) | |
1074 | return 1; | |
1075 | ||
e5a03bfd | 1076 | if (chosen_phy == phydev->mdio.addr) |
cb646e2b RC |
1077 | return 1; |
1078 | ||
1079 | return 0; | |
1080 | } | |
1081 | ||
1082 | static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock) | |
1083 | { | |
1084 | if (clock) | |
1085 | mutex_lock(&clock->clock_lock); | |
1086 | return clock; | |
1087 | } | |
1088 | ||
1089 | /* | |
1090 | * Look up and lock a clock by bus instance. | |
1091 | * If there is no clock for this bus, then create it first. | |
1092 | */ | |
1093 | static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus) | |
1094 | { | |
1095 | struct dp83640_clock *clock = NULL, *tmp; | |
1096 | struct list_head *this; | |
1097 | ||
1098 | mutex_lock(&phyter_clocks_lock); | |
1099 | ||
1100 | list_for_each(this, &phyter_clocks) { | |
1101 | tmp = list_entry(this, struct dp83640_clock, list); | |
1102 | if (tmp->bus == bus) { | |
1103 | clock = tmp; | |
1104 | break; | |
1105 | } | |
1106 | } | |
1107 | if (clock) | |
1108 | goto out; | |
1109 | ||
1110 | clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL); | |
1111 | if (!clock) | |
1112 | goto out; | |
1113 | ||
6396bb22 KC |
1114 | clock->caps.pin_config = kcalloc(DP83640_N_PINS, |
1115 | sizeof(struct ptp_pin_desc), | |
1116 | GFP_KERNEL); | |
86dd3612 RC |
1117 | if (!clock->caps.pin_config) { |
1118 | kfree(clock); | |
1119 | clock = NULL; | |
1120 | goto out; | |
1121 | } | |
cb646e2b | 1122 | dp83640_clock_init(clock, bus); |
86530837 | 1123 | list_add_tail(&clock->list, &phyter_clocks); |
cb646e2b RC |
1124 | out: |
1125 | mutex_unlock(&phyter_clocks_lock); | |
1126 | ||
1127 | return dp83640_clock_get(clock); | |
1128 | } | |
1129 | ||
1130 | static void dp83640_clock_put(struct dp83640_clock *clock) | |
1131 | { | |
1132 | mutex_unlock(&clock->clock_lock); | |
1133 | } | |
1134 | ||
76327a35 EH |
1135 | static int dp83640_soft_reset(struct phy_device *phydev) |
1136 | { | |
1137 | int ret; | |
1138 | ||
1139 | ret = genphy_soft_reset(phydev); | |
1140 | if (ret < 0) | |
1141 | return ret; | |
1142 | ||
1143 | /* From DP83640 datasheet: "Software driver code must wait 3 us | |
1144 | * following a software reset before allowing further serial MII | |
1145 | * operations with the DP83640." | |
1146 | */ | |
1147 | udelay(10); /* Taking udelay inaccuracy into account */ | |
1148 | ||
1149 | return 0; | |
1150 | } | |
1151 | ||
62ad9684 SS |
1152 | static int dp83640_config_init(struct phy_device *phydev) |
1153 | { | |
602b1099 SS |
1154 | struct dp83640_private *dp83640 = phydev->priv; |
1155 | struct dp83640_clock *clock = dp83640->clock; | |
1156 | ||
1157 | if (clock->chosen && !list_empty(&clock->phylist)) | |
1158 | recalibrate(clock); | |
a935865c RC |
1159 | else { |
1160 | mutex_lock(&clock->extreg_lock); | |
602b1099 | 1161 | enable_broadcast(phydev, clock->page, 1); |
a935865c RC |
1162 | mutex_unlock(&clock->extreg_lock); |
1163 | } | |
602b1099 | 1164 | |
62ad9684 | 1165 | enable_status_frames(phydev, true); |
a935865c RC |
1166 | |
1167 | mutex_lock(&clock->extreg_lock); | |
62ad9684 | 1168 | ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE); |
a935865c RC |
1169 | mutex_unlock(&clock->extreg_lock); |
1170 | ||
62ad9684 SS |
1171 | return 0; |
1172 | } | |
1173 | ||
1642182e SG |
1174 | static int dp83640_ack_interrupt(struct phy_device *phydev) |
1175 | { | |
1176 | int err = phy_read(phydev, MII_DP83640_MISR); | |
1177 | ||
1178 | if (err < 0) | |
1179 | return err; | |
1180 | ||
1181 | return 0; | |
1182 | } | |
1183 | ||
1184 | static int dp83640_config_intr(struct phy_device *phydev) | |
1185 | { | |
1186 | int micr; | |
1187 | int misr; | |
1188 | int err; | |
1189 | ||
1190 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { | |
1191 | misr = phy_read(phydev, MII_DP83640_MISR); | |
1192 | if (misr < 0) | |
1193 | return misr; | |
1194 | misr |= | |
1195 | (MII_DP83640_MISR_ANC_INT_EN | | |
1196 | MII_DP83640_MISR_DUP_INT_EN | | |
1197 | MII_DP83640_MISR_SPD_INT_EN | | |
1198 | MII_DP83640_MISR_LINK_INT_EN); | |
1199 | err = phy_write(phydev, MII_DP83640_MISR, misr); | |
1200 | if (err < 0) | |
1201 | return err; | |
1202 | ||
1203 | micr = phy_read(phydev, MII_DP83640_MICR); | |
1204 | if (micr < 0) | |
1205 | return micr; | |
1206 | micr |= | |
1207 | (MII_DP83640_MICR_OE | | |
1208 | MII_DP83640_MICR_IE); | |
1209 | return phy_write(phydev, MII_DP83640_MICR, micr); | |
1210 | } else { | |
1211 | micr = phy_read(phydev, MII_DP83640_MICR); | |
1212 | if (micr < 0) | |
1213 | return micr; | |
1214 | micr &= | |
1215 | ~(MII_DP83640_MICR_OE | | |
1216 | MII_DP83640_MICR_IE); | |
1217 | err = phy_write(phydev, MII_DP83640_MICR, micr); | |
1218 | if (err < 0) | |
1219 | return err; | |
1220 | ||
1221 | misr = phy_read(phydev, MII_DP83640_MISR); | |
1222 | if (misr < 0) | |
1223 | return misr; | |
1224 | misr &= | |
1225 | ~(MII_DP83640_MISR_ANC_INT_EN | | |
1226 | MII_DP83640_MISR_DUP_INT_EN | | |
1227 | MII_DP83640_MISR_SPD_INT_EN | | |
1228 | MII_DP83640_MISR_LINK_INT_EN); | |
1229 | return phy_write(phydev, MII_DP83640_MISR, misr); | |
1230 | } | |
1231 | } | |
1232 | ||
4715f65f | 1233 | static int dp83640_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr) |
cb646e2b | 1234 | { |
4715f65f RC |
1235 | struct dp83640_private *dp83640 = |
1236 | container_of(mii_ts, struct dp83640_private, mii_ts); | |
cb646e2b RC |
1237 | struct hwtstamp_config cfg; |
1238 | u16 txcfg0, rxcfg0; | |
1239 | ||
1240 | if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) | |
1241 | return -EFAULT; | |
1242 | ||
1243 | if (cfg.flags) /* reserved for future extensions */ | |
1244 | return -EINVAL; | |
1245 | ||
dccaa9e0 | 1246 | if (cfg.tx_type < 0 || cfg.tx_type > HWTSTAMP_TX_ONESTEP_SYNC) |
cb646e2b | 1247 | return -ERANGE; |
dccaa9e0 RC |
1248 | |
1249 | dp83640->hwts_tx_en = cfg.tx_type; | |
cb646e2b RC |
1250 | |
1251 | switch (cfg.rx_filter) { | |
1252 | case HWTSTAMP_FILTER_NONE: | |
1253 | dp83640->hwts_rx_en = 0; | |
1254 | dp83640->layer = 0; | |
1255 | dp83640->version = 0; | |
1256 | break; | |
1257 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
1258 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
1259 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
1260 | dp83640->hwts_rx_en = 1; | |
a1f8723f SS |
1261 | dp83640->layer = PTP_CLASS_L4; |
1262 | dp83640->version = PTP_CLASS_V1; | |
cb646e2b RC |
1263 | break; |
1264 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
1265 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
1266 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
1267 | dp83640->hwts_rx_en = 1; | |
a1f8723f SS |
1268 | dp83640->layer = PTP_CLASS_L4; |
1269 | dp83640->version = PTP_CLASS_V2; | |
cb646e2b RC |
1270 | break; |
1271 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
1272 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
1273 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
1274 | dp83640->hwts_rx_en = 1; | |
a1f8723f SS |
1275 | dp83640->layer = PTP_CLASS_L2; |
1276 | dp83640->version = PTP_CLASS_V2; | |
cb646e2b RC |
1277 | break; |
1278 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
1279 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
1280 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
1281 | dp83640->hwts_rx_en = 1; | |
a1f8723f SS |
1282 | dp83640->layer = PTP_CLASS_L4 | PTP_CLASS_L2; |
1283 | dp83640->version = PTP_CLASS_V2; | |
cb646e2b RC |
1284 | break; |
1285 | default: | |
1286 | return -ERANGE; | |
1287 | } | |
1288 | ||
1289 | txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT; | |
1290 | rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT; | |
1291 | ||
a1f8723f | 1292 | if (dp83640->layer & PTP_CLASS_L2) { |
cb646e2b RC |
1293 | txcfg0 |= TX_L2_EN; |
1294 | rxcfg0 |= RX_L2_EN; | |
1295 | } | |
a1f8723f | 1296 | if (dp83640->layer & PTP_CLASS_L4) { |
cb646e2b RC |
1297 | txcfg0 |= TX_IPV6_EN | TX_IPV4_EN; |
1298 | rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN; | |
1299 | } | |
1300 | ||
1301 | if (dp83640->hwts_tx_en) | |
1302 | txcfg0 |= TX_TS_EN; | |
1303 | ||
dccaa9e0 RC |
1304 | if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC) |
1305 | txcfg0 |= SYNC_1STEP | CHK_1STEP; | |
1306 | ||
cb646e2b RC |
1307 | if (dp83640->hwts_rx_en) |
1308 | rxcfg0 |= RX_TS_EN; | |
1309 | ||
1310 | mutex_lock(&dp83640->clock->extreg_lock); | |
1311 | ||
4715f65f RC |
1312 | ext_write(0, dp83640->phydev, PAGE5, PTP_TXCFG0, txcfg0); |
1313 | ext_write(0, dp83640->phydev, PAGE5, PTP_RXCFG0, rxcfg0); | |
cb646e2b RC |
1314 | |
1315 | mutex_unlock(&dp83640->clock->extreg_lock); | |
1316 | ||
1317 | return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; | |
1318 | } | |
1319 | ||
1320 | static void rx_timestamp_work(struct work_struct *work) | |
1321 | { | |
1322 | struct dp83640_private *dp83640 = | |
4b063258 | 1323 | container_of(work, struct dp83640_private, ts_work.work); |
cb646e2b | 1324 | struct sk_buff *skb; |
cb646e2b | 1325 | |
63502b8d SS |
1326 | /* Deliver expired packets. */ |
1327 | while ((skb = skb_dequeue(&dp83640->rx_queue))) { | |
1328 | struct dp83640_skb_info *skb_info; | |
1329 | ||
1330 | skb_info = (struct dp83640_skb_info *)skb->cb; | |
1331 | if (!time_after(jiffies, skb_info->tmo)) { | |
1332 | skb_queue_head(&dp83640->rx_queue, skb); | |
1333 | break; | |
cb646e2b | 1334 | } |
63502b8d | 1335 | |
72092cc4 | 1336 | netif_rx_ni(skb); |
cb646e2b RC |
1337 | } |
1338 | ||
63502b8d | 1339 | if (!skb_queue_empty(&dp83640->rx_queue)) |
4b063258 | 1340 | schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT); |
cb646e2b RC |
1341 | } |
1342 | ||
4715f65f | 1343 | static bool dp83640_rxtstamp(struct mii_timestamper *mii_ts, |
cb646e2b RC |
1344 | struct sk_buff *skb, int type) |
1345 | { | |
4715f65f RC |
1346 | struct dp83640_private *dp83640 = |
1347 | container_of(mii_ts, struct dp83640_private, mii_ts); | |
63502b8d SS |
1348 | struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb; |
1349 | struct list_head *this, *next; | |
1350 | struct rxts *rxts; | |
1351 | struct skb_shared_hwtstamps *shhwtstamps = NULL; | |
1352 | unsigned long flags; | |
cb646e2b | 1353 | |
cb646e2b RC |
1354 | if (is_status_frame(skb, type)) { |
1355 | decode_status_frame(dp83640, skb); | |
ae6e86b7 RC |
1356 | kfree_skb(skb); |
1357 | return true; | |
cb646e2b RC |
1358 | } |
1359 | ||
a12f78c5 SS |
1360 | if (!dp83640->hwts_rx_en) |
1361 | return false; | |
1362 | ||
a1f8723f SS |
1363 | if ((type & dp83640->version) == 0 || (type & dp83640->layer) == 0) |
1364 | return false; | |
1365 | ||
63502b8d | 1366 | spin_lock_irqsave(&dp83640->rx_lock, flags); |
ccf6ee9a | 1367 | prune_rx_ts(dp83640); |
63502b8d SS |
1368 | list_for_each_safe(this, next, &dp83640->rxts) { |
1369 | rxts = list_entry(this, struct rxts, list); | |
1370 | if (match(skb, type, rxts)) { | |
1371 | shhwtstamps = skb_hwtstamps(skb); | |
1372 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); | |
1373 | shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns); | |
63502b8d SS |
1374 | list_del_init(&rxts->list); |
1375 | list_add(&rxts->list, &dp83640->rxpool); | |
1376 | break; | |
1377 | } | |
1378 | } | |
1379 | spin_unlock_irqrestore(&dp83640->rx_lock, flags); | |
1380 | ||
1381 | if (!shhwtstamps) { | |
1382 | skb_info->ptp_type = type; | |
4b063258 | 1383 | skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT; |
63502b8d | 1384 | skb_queue_tail(&dp83640->rx_queue, skb); |
4b063258 | 1385 | schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT); |
d36b82bc SS |
1386 | } else { |
1387 | netif_rx_ni(skb); | |
63502b8d | 1388 | } |
cb646e2b RC |
1389 | |
1390 | return true; | |
1391 | } | |
1392 | ||
4715f65f | 1393 | static void dp83640_txtstamp(struct mii_timestamper *mii_ts, |
cb646e2b RC |
1394 | struct sk_buff *skb, int type) |
1395 | { | |
53bc8d2a | 1396 | struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb; |
4715f65f RC |
1397 | struct dp83640_private *dp83640 = |
1398 | container_of(mii_ts, struct dp83640_private, mii_ts); | |
cb646e2b | 1399 | |
dccaa9e0 RC |
1400 | switch (dp83640->hwts_tx_en) { |
1401 | ||
1402 | case HWTSTAMP_TX_ONESTEP_SYNC: | |
1403 | if (is_sync(skb, type)) { | |
62bccb8c | 1404 | kfree_skb(skb); |
dccaa9e0 RC |
1405 | return; |
1406 | } | |
1407 | /* fall through */ | |
1408 | case HWTSTAMP_TX_ON: | |
e2e2f51d | 1409 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
53bc8d2a | 1410 | skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT; |
dccaa9e0 | 1411 | skb_queue_tail(&dp83640->tx_queue, skb); |
dccaa9e0 RC |
1412 | break; |
1413 | ||
1414 | case HWTSTAMP_TX_OFF: | |
1415 | default: | |
62bccb8c | 1416 | kfree_skb(skb); |
dccaa9e0 | 1417 | break; |
cb646e2b | 1418 | } |
cb646e2b RC |
1419 | } |
1420 | ||
4715f65f RC |
1421 | static int dp83640_ts_info(struct mii_timestamper *mii_ts, |
1422 | struct ethtool_ts_info *info) | |
7dff3499 | 1423 | { |
4715f65f RC |
1424 | struct dp83640_private *dp83640 = |
1425 | container_of(mii_ts, struct dp83640_private, mii_ts); | |
7dff3499 RC |
1426 | |
1427 | info->so_timestamping = | |
1428 | SOF_TIMESTAMPING_TX_HARDWARE | | |
1429 | SOF_TIMESTAMPING_RX_HARDWARE | | |
1430 | SOF_TIMESTAMPING_RAW_HARDWARE; | |
1431 | info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock); | |
1432 | info->tx_types = | |
1433 | (1 << HWTSTAMP_TX_OFF) | | |
1434 | (1 << HWTSTAMP_TX_ON) | | |
1435 | (1 << HWTSTAMP_TX_ONESTEP_SYNC); | |
1436 | info->rx_filters = | |
1437 | (1 << HWTSTAMP_FILTER_NONE) | | |
1438 | (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | | |
7dff3499 | 1439 | (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | |
7dff3499 | 1440 | (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | |
11b1544b | 1441 | (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); |
7dff3499 RC |
1442 | return 0; |
1443 | } | |
1444 | ||
12d0efb9 RC |
1445 | static int dp83640_probe(struct phy_device *phydev) |
1446 | { | |
1447 | struct dp83640_clock *clock; | |
1448 | struct dp83640_private *dp83640; | |
1449 | int err = -ENOMEM, i; | |
1450 | ||
1451 | if (phydev->mdio.addr == BROADCAST_ADDR) | |
1452 | return 0; | |
1453 | ||
1454 | clock = dp83640_clock_get_bus(phydev->mdio.bus); | |
1455 | if (!clock) | |
1456 | goto no_clock; | |
1457 | ||
1458 | dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL); | |
1459 | if (!dp83640) | |
1460 | goto no_memory; | |
1461 | ||
1462 | dp83640->phydev = phydev; | |
4715f65f RC |
1463 | dp83640->mii_ts.rxtstamp = dp83640_rxtstamp; |
1464 | dp83640->mii_ts.txtstamp = dp83640_txtstamp; | |
1465 | dp83640->mii_ts.hwtstamp = dp83640_hwtstamp; | |
1466 | dp83640->mii_ts.ts_info = dp83640_ts_info; | |
12d0efb9 | 1467 | |
4715f65f | 1468 | INIT_DELAYED_WORK(&dp83640->ts_work, rx_timestamp_work); |
12d0efb9 RC |
1469 | INIT_LIST_HEAD(&dp83640->rxts); |
1470 | INIT_LIST_HEAD(&dp83640->rxpool); | |
1471 | for (i = 0; i < MAX_RXTS; i++) | |
1472 | list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool); | |
1473 | ||
4715f65f | 1474 | phydev->mii_ts = &dp83640->mii_ts; |
12d0efb9 RC |
1475 | phydev->priv = dp83640; |
1476 | ||
1477 | spin_lock_init(&dp83640->rx_lock); | |
1478 | skb_queue_head_init(&dp83640->rx_queue); | |
1479 | skb_queue_head_init(&dp83640->tx_queue); | |
1480 | ||
1481 | dp83640->clock = clock; | |
1482 | ||
1483 | if (choose_this_phy(clock, phydev)) { | |
1484 | clock->chosen = dp83640; | |
1485 | clock->ptp_clock = ptp_clock_register(&clock->caps, | |
1486 | &phydev->mdio.dev); | |
1487 | if (IS_ERR(clock->ptp_clock)) { | |
1488 | err = PTR_ERR(clock->ptp_clock); | |
1489 | goto no_register; | |
1490 | } | |
1491 | } else | |
1492 | list_add_tail(&dp83640->list, &clock->phylist); | |
1493 | ||
1494 | dp83640_clock_put(clock); | |
1495 | return 0; | |
1496 | ||
1497 | no_register: | |
1498 | clock->chosen = NULL; | |
1499 | kfree(dp83640); | |
1500 | no_memory: | |
1501 | dp83640_clock_put(clock); | |
1502 | no_clock: | |
1503 | return err; | |
1504 | } | |
1505 | ||
1506 | static void dp83640_remove(struct phy_device *phydev) | |
1507 | { | |
1508 | struct dp83640_clock *clock; | |
1509 | struct list_head *this, *next; | |
1510 | struct dp83640_private *tmp, *dp83640 = phydev->priv; | |
1511 | ||
1512 | if (phydev->mdio.addr == BROADCAST_ADDR) | |
1513 | return; | |
1514 | ||
4715f65f RC |
1515 | phydev->mii_ts = NULL; |
1516 | ||
12d0efb9 RC |
1517 | enable_status_frames(phydev, false); |
1518 | cancel_delayed_work_sync(&dp83640->ts_work); | |
1519 | ||
1520 | skb_queue_purge(&dp83640->rx_queue); | |
1521 | skb_queue_purge(&dp83640->tx_queue); | |
1522 | ||
1523 | clock = dp83640_clock_get(dp83640->clock); | |
1524 | ||
1525 | if (dp83640 == clock->chosen) { | |
1526 | ptp_clock_unregister(clock->ptp_clock); | |
1527 | clock->chosen = NULL; | |
1528 | } else { | |
1529 | list_for_each_safe(this, next, &clock->phylist) { | |
1530 | tmp = list_entry(this, struct dp83640_private, list); | |
1531 | if (tmp == dp83640) { | |
1532 | list_del_init(&tmp->list); | |
1533 | break; | |
1534 | } | |
1535 | } | |
1536 | } | |
1537 | ||
1538 | dp83640_clock_put(clock); | |
1539 | kfree(dp83640); | |
1540 | } | |
1541 | ||
cb646e2b RC |
1542 | static struct phy_driver dp83640_driver = { |
1543 | .phy_id = DP83640_PHY_ID, | |
1544 | .phy_id_mask = 0xfffffff0, | |
1545 | .name = "NatSemi DP83640", | |
dcdecdcf | 1546 | /* PHY_BASIC_FEATURES */ |
cb646e2b RC |
1547 | .probe = dp83640_probe, |
1548 | .remove = dp83640_remove, | |
76327a35 | 1549 | .soft_reset = dp83640_soft_reset, |
62ad9684 | 1550 | .config_init = dp83640_config_init, |
1642182e SG |
1551 | .ack_interrupt = dp83640_ack_interrupt, |
1552 | .config_intr = dp83640_config_intr, | |
cb646e2b RC |
1553 | }; |
1554 | ||
1555 | static int __init dp83640_init(void) | |
1556 | { | |
be01da72 | 1557 | return phy_driver_register(&dp83640_driver, THIS_MODULE); |
cb646e2b RC |
1558 | } |
1559 | ||
1560 | static void __exit dp83640_exit(void) | |
1561 | { | |
1562 | dp83640_free_clocks(); | |
1563 | phy_driver_unregister(&dp83640_driver); | |
1564 | } | |
1565 | ||
1566 | MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver"); | |
fbf4b934 | 1567 | MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>"); |
cb646e2b RC |
1568 | MODULE_LICENSE("GPL"); |
1569 | ||
1570 | module_init(dp83640_init); | |
1571 | module_exit(dp83640_exit); | |
1572 | ||
86ff9baa | 1573 | static struct mdio_device_id __maybe_unused dp83640_tbl[] = { |
cb646e2b RC |
1574 | { DP83640_PHY_ID, 0xfffffff0 }, |
1575 | { } | |
1576 | }; | |
1577 | ||
1578 | MODULE_DEVICE_TABLE(mdio, dp83640_tbl); |