[thirdparty/linux.git] / drivers / net / phy / icplus.c

/*
 * Driver for ICPlus PHYs
 *
 * Copyright (c) 2007 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/errno.h>
#include <linux/unistd.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/spinlock.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/phy.h>

#include <asm/io.h>
#include <asm/irq.h>
#include <linux/uaccess.h>

MODULE_DESCRIPTION("ICPlus IP175C/IP101A/IP101G/IC1001 PHY drivers");
MODULE_AUTHOR("Michael Barkowski");
MODULE_LICENSE("GPL");

/* IP101A/G - IP1001 */
#define IP10XX_SPEC_CTRL_STATUS		16	/* Spec. Control Register */
#define IP1001_RXPHASE_SEL		(1<<0)	/* Add delay on RX_CLK */
#define IP1001_TXPHASE_SEL		(1<<1)	/* Add delay on TX_CLK */
#define IP1001_SPEC_CTRL_STATUS_2	20	/* IP1001 Spec. Control Reg 2 */
#define IP1001_APS_ON			11	/* IP1001 APS Mode  bit */
#define IP101A_G_APS_ON			2	/* IP101A/G APS Mode bit */
#define IP101A_G_IRQ_CONF_STATUS	0x11	/* Conf Info IRQ & Status Reg */
#define	IP101A_G_IRQ_PIN_USED		(1<<15) /* INTR pin used */
#define	IP101A_G_IRQ_DEFAULT		IP101A_G_IRQ_PIN_USED

static int ip175c_config_init(struct phy_device *phydev)
{
	int err, i;
	static int full_reset_performed;

	if (full_reset_performed == 0) {

		/* master reset */
		err = mdiobus_write(phydev->mdio.bus, 30, 0, 0x175c);
		if (err < 0)
			return err;

		/* ensure no bus delays overlap reset period */
		err = mdiobus_read(phydev->mdio.bus, 30, 0);

		/* data sheet specifies reset period is 2 msec */
		mdelay(2);

		/* enable IP175C mode */
		err = mdiobus_write(phydev->mdio.bus, 29, 31, 0x175c);
		if (err < 0)
			return err;

		/* Set MII0 speed and duplex (in PHY mode) */
		err = mdiobus_write(phydev->mdio.bus, 29, 22, 0x420);
		if (err < 0)
			return err;

		/* reset switch ports */
		for (i = 0; i < 5; i++) {
			err = mdiobus_write(phydev->mdio.bus, i,
					    MII_BMCR, BMCR_RESET);
			if (err < 0)
				return err;
		}

		for (i = 0; i < 5; i++)
			err = mdiobus_read(phydev->mdio.bus, i, MII_BMCR);

		mdelay(2);

		full_reset_performed = 1;
	}

	if (phydev->mdio.addr != 4) {
		phydev->state = PHY_RUNNING;
		phydev->speed = SPEED_100;
		phydev->duplex = DUPLEX_FULL;
		phydev->link = 1;
		netif_carrier_on(phydev->attached_dev);
	}

	return 0;
}

static int ip1xx_reset(struct phy_device *phydev)
{
	int bmcr;

	/* Software Reset PHY */
	bmcr = phy_read(phydev, MII_BMCR);
	if (bmcr < 0)
		return bmcr;
	bmcr |= BMCR_RESET;
	bmcr = phy_write(phydev, MII_BMCR, bmcr);
	if (bmcr < 0)
		return bmcr;

	do {
		bmcr = phy_read(phydev, MII_BMCR);
		if (bmcr < 0)
			return bmcr;
	} while (bmcr & BMCR_RESET);

	return 0;
}

static int ip1001_config_init(struct phy_device *phydev)
{
	int c;

	c = ip1xx_reset(phydev);
	if (c < 0)
		return c;

	/* Enable Auto Power Saving mode */
	c = phy_read(phydev, IP1001_SPEC_CTRL_STATUS_2);
	if (c < 0)
		return c;
	c |= IP1001_APS_ON;
	c = phy_write(phydev, IP1001_SPEC_CTRL_STATUS_2, c);
	if (c < 0)
		return c;

	if (phy_interface_is_rgmii(phydev)) {

		c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
		if (c < 0)
			return c;

		c &= ~(IP1001_RXPHASE_SEL | IP1001_TXPHASE_SEL);

		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
			c |= (IP1001_RXPHASE_SEL | IP1001_TXPHASE_SEL);
		else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
			c |= IP1001_RXPHASE_SEL;
		else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
			c |= IP1001_TXPHASE_SEL;

		c = phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
		if (c < 0)
			return c;
	}

	return 0;
}

static int ip101a_g_config_init(struct phy_device *phydev)
{
	int c;

	c = ip1xx_reset(phydev);
	if (c < 0)
		return c;

	/* INTR pin used: speed/link/duplex will cause an interrupt */
	c = phy_write(phydev, IP101A_G_IRQ_CONF_STATUS, IP101A_G_IRQ_DEFAULT);
	if (c < 0)
		return c;

	/* Enable Auto Power Saving mode */
	c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
	c |= IP101A_G_APS_ON;

	return phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
}

static int ip175c_read_status(struct phy_device *phydev)
{
	if (phydev->mdio.addr == 4) /* WAN port */
		genphy_read_status(phydev);
	else
		/* Don't need to read status for switch ports */
		phydev->irq = PHY_IGNORE_INTERRUPT;

	return 0;
}

static int ip175c_config_aneg(struct phy_device *phydev)
{
	if (phydev->mdio.addr == 4) /* WAN port */
		genphy_config_aneg(phydev);

	return 0;
}

static int ip101a_g_ack_interrupt(struct phy_device *phydev)
{
	int err = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS);
	if (err < 0)
		return err;

	return 0;
}

static struct phy_driver icplus_driver[] = {
{
	.phy_id		= 0x02430d80,
	.name		= "ICPlus IP175C",
	.phy_id_mask	= 0x0ffffff0,
	.features	= PHY_BASIC_FEATURES,
	.config_init	= &ip175c_config_init,
	.config_aneg	= &ip175c_config_aneg,
	.read_status	= &ip175c_read_status,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
}, {
	.phy_id		= 0x02430d90,
	.name		= "ICPlus IP1001",
	.phy_id_mask	= 0x0ffffff0,
	.features	= PHY_GBIT_FEATURES,
	.config_init	= &ip1001_config_init,
	.config_aneg	= &genphy_config_aneg,
	.read_status	= &genphy_read_status,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
}, {
	.phy_id		= 0x02430c54,
	.name		= "ICPlus IP101A/G",
	.phy_id_mask	= 0x0ffffff0,
	.features	= PHY_BASIC_FEATURES,
	.flags		= PHY_HAS_INTERRUPT,
	.ack_interrupt	= ip101a_g_ack_interrupt,
	.config_init	= &ip101a_g_config_init,
	.config_aneg	= &genphy_config_aneg,
	.read_status	= &genphy_read_status,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
} };

module_phy_driver(icplus_driver);

static struct mdio_device_id __maybe_unused icplus_tbl[] = {
	{ 0x02430d80, 0x0ffffff0 },
	{ 0x02430d90, 0x0ffffff0 },
	{ 0x02430c54, 0x0ffffff0 },
	{ }
};

MODULE_DEVICE_TABLE(mdio, icplus_tbl);
Commit	Line	Data
0cefeeba MB	1	/*
	2	* Driver for ICPlus PHYs
	3	*
	4	* Copyright (c) 2007 Freescale Semiconductor, Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*
	11	*/
	12	#include <linux/kernel.h>
	13	#include <linux/string.h>
	14	#include <linux/errno.h>
	15	#include <linux/unistd.h>
0cefeeba MB	16	#include <linux/interrupt.h>
	17	#include <linux/init.h>
	18	#include <linux/delay.h>
	19	#include <linux/netdevice.h>
	20	#include <linux/etherdevice.h>
	21	#include <linux/skbuff.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/mm.h>
	24	#include <linux/module.h>
	25	#include <linux/mii.h>
	26	#include <linux/ethtool.h>
	27	#include <linux/phy.h>
	28
	29	#include <asm/io.h>
	30	#include <asm/irq.h>
7c0f6ba6	31	#include <linux/uaccess.h>
0cefeeba	32
e3e09f26	33	MODULE_DESCRIPTION("ICPlus IP175C/IP101A/IP101G/IC1001 PHY drivers");
0cefeeba MB	34	MODULE_AUTHOR("Michael Barkowski");
	35	MODULE_LICENSE("GPL");
	36
e3e09f26 GC	37	/* IP101A/G - IP1001 */
e3e09f26 GC	38	#define IP10XX_SPEC_CTRL_STATUS 16 /* Spec. Control Register */
b4a49631 SM	39	#define IP1001_RXPHASE_SEL (1<<0) /* Add delay on RX_CLK */
b4a49631 SM	40	#define IP1001_TXPHASE_SEL (1<<1) /* Add delay on TX_CLK */
e3e09f26	41	#define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */
e3e09f26 GC	42	#define IP1001_APS_ON 11 /* IP1001 APS Mode bit */
e3e09f26 GC	43	#define IP101A_G_APS_ON 2 /* IP101A/G APS Mode bit */
996f7393	44	#define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */
9ec0db71 GC	45	#define IP101A_G_IRQ_PIN_USED (1<<15) /* INTR pin used */
9ec0db71 GC	46	#define IP101A_G_IRQ_DEFAULT IP101A_G_IRQ_PIN_USED
9c9b1f24	47
0cefeeba MB	48	static int ip175c_config_init(struct phy_device *phydev)
	49	{
	50	int err, i;
9ed66cb5	51	static int full_reset_performed;
0cefeeba MB	52
	53	if (full_reset_performed == 0) {
	54
	55	/* master reset */
e5a03bfd	56	err = mdiobus_write(phydev->mdio.bus, 30, 0, 0x175c);
0cefeeba MB	57	if (err < 0)
	58	return err;
	59
	60	/* ensure no bus delays overlap reset period */
e5a03bfd	61	err = mdiobus_read(phydev->mdio.bus, 30, 0);
0cefeeba MB	62
	63	/* data sheet specifies reset period is 2 msec */
	64	mdelay(2);
	65
	66	/* enable IP175C mode */
e5a03bfd	67	err = mdiobus_write(phydev->mdio.bus, 29, 31, 0x175c);
0cefeeba MB	68	if (err < 0)
	69	return err;
	70
	71	/* Set MII0 speed and duplex (in PHY mode) */
e5a03bfd	72	err = mdiobus_write(phydev->mdio.bus, 29, 22, 0x420);
0cefeeba MB	73	if (err < 0)
	74	return err;
	75
	76	/* reset switch ports */
	77	for (i = 0; i < 5; i++) {
e5a03bfd	78	err = mdiobus_write(phydev->mdio.bus, i,
76231e02	79	MII_BMCR, BMCR_RESET);
0cefeeba MB	80	if (err < 0)
	81	return err;
	82	}
	83
	84	for (i = 0; i < 5; i++)
e5a03bfd	85	err = mdiobus_read(phydev->mdio.bus, i, MII_BMCR);
0cefeeba MB	86
	87	mdelay(2);
	88
	89	full_reset_performed = 1;
	90	}
	91
e5a03bfd	92	if (phydev->mdio.addr != 4) {
0cefeeba MB	93	phydev->state = PHY_RUNNING;
	94	phydev->speed = SPEED_100;
	95	phydev->duplex = DUPLEX_FULL;
	96	phydev->link = 1;
	97	netif_carrier_on(phydev->attached_dev);
	98	}
	99
	100	return 0;
	101	}
	102
9c9b1f24	103	static int ip1xx_reset(struct phy_device *phydev)
377ecca9	104	{
b8e3995a	105	int bmcr;
377ecca9 GC	106
377ecca9 GC	107	/* Software Reset PHY */
9c9b1f24	108	bmcr = phy_read(phydev, MII_BMCR);
b8e3995a DM	109	if (bmcr < 0)
b8e3995a DM	110	return bmcr;
9c9b1f24	111	bmcr \|= BMCR_RESET;
b8e3995a DM	112	bmcr = phy_write(phydev, MII_BMCR, bmcr);
	113	if (bmcr < 0)
	114	return bmcr;
377ecca9 GC	115
377ecca9 GC	116	do {
9c9b1f24	117	bmcr = phy_read(phydev, MII_BMCR);
b8e3995a DM	118	if (bmcr < 0)
b8e3995a DM	119	return bmcr;
9c9b1f24 GC	120	} while (bmcr & BMCR_RESET);
9c9b1f24 GC	121
b8e3995a	122	return 0;
9c9b1f24 GC	123	}
	124
	125	static int ip1001_config_init(struct phy_device *phydev)
	126	{
	127	int c;
	128
	129	c = ip1xx_reset(phydev);
	130	if (c < 0)
	131	return c;
	132
	133	/* Enable Auto Power Saving mode */
	134	c = phy_read(phydev, IP1001_SPEC_CTRL_STATUS_2);
b8e3995a DM	135	if (c < 0)
b8e3995a DM	136	return c;
9c9b1f24	137	c \|= IP1001_APS_ON;
b8e3995a	138	c = phy_write(phydev, IP1001_SPEC_CTRL_STATUS_2, c);
9c9b1f24 GC	139	if (c < 0)
9c9b1f24 GC	140	return c;
377ecca9	141
32a64161	142	if (phy_interface_is_rgmii(phydev)) {
b4a49631	143
a4886d52	144	c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
b8e3995a DM	145	if (c < 0)
	146	return c;
	147
b4a49631 SM	148	c &= ~(IP1001_RXPHASE_SEL \| IP1001_TXPHASE_SEL);
	149
	150	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
	151	c \|= (IP1001_RXPHASE_SEL \| IP1001_TXPHASE_SEL);
	152	else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
	153	c \|= IP1001_RXPHASE_SEL;
	154	else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
	155	c \|= IP1001_TXPHASE_SEL;
	156
a4886d52	157	c = phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
b8e3995a DM	158	if (c < 0)
b8e3995a DM	159	return c;
a4886d52	160	}
9c9b1f24	161
b8e3995a	162	return 0;
9c9b1f24 GC	163	}
9c9b1f24 GC	164
e3e09f26	165	static int ip101a_g_config_init(struct phy_device *phydev)
9c9b1f24 GC	166	{
9c9b1f24 GC	167	int c;
377ecca9	168
9c9b1f24 GC	169	c = ip1xx_reset(phydev);
	170	if (c < 0)
	171	return c;
	172
014f2ffd GC	173	/* INTR pin used: speed/link/duplex will cause an interrupt */
	174	c = phy_write(phydev, IP101A_G_IRQ_CONF_STATUS, IP101A_G_IRQ_DEFAULT);
	175	if (c < 0)
	176	return c;
	177
9c9b1f24 GC	178	/* Enable Auto Power Saving mode */
9c9b1f24 GC	179	c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
e3e09f26	180	c \|= IP101A_G_APS_ON;
b3300146 SK	181
b3300146 SK	182	return phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
377ecca9 GC	183	}
377ecca9 GC	184
0cefeeba MB	185	static int ip175c_read_status(struct phy_device *phydev)
0cefeeba MB	186	{
e5a03bfd	187	if (phydev->mdio.addr == 4) /* WAN port */
0cefeeba MB	188	genphy_read_status(phydev);
	189	else
	190	/* Don't need to read status for switch ports */
	191	phydev->irq = PHY_IGNORE_INTERRUPT;
	192
	193	return 0;
	194	}
	195
	196	static int ip175c_config_aneg(struct phy_device *phydev)
	197	{
e5a03bfd	198	if (phydev->mdio.addr == 4) /* WAN port */
0cefeeba MB	199	genphy_config_aneg(phydev);
	200
	201	return 0;
	202	}
	203
996f7393 GC	204	static int ip101a_g_ack_interrupt(struct phy_device *phydev)
	205	{
	206	int err = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS);
	207	if (err < 0)
	208	return err;
	209
	210	return 0;
	211	}
	212
d5bf9071 CH	213	static struct phy_driver icplus_driver[] = {
d5bf9071 CH	214	{
0cefeeba MB	215	.phy_id = 0x02430d80,
	216	.name = "ICPlus IP175C",
	217	.phy_id_mask = 0x0ffffff0,
	218	.features = PHY_BASIC_FEATURES,
	219	.config_init = &ip175c_config_init,
	220	.config_aneg = &ip175c_config_aneg,
	221	.read_status = &ip175c_read_status,
dab10863 GC	222	.suspend = genphy_suspend,
dab10863 GC	223	.resume = genphy_resume,
d5bf9071	224	}, {
377ecca9 GC	225	.phy_id = 0x02430d90,
	226	.name = "ICPlus IP1001",
	227	.phy_id_mask = 0x0ffffff0,
529ed127	228	.features = PHY_GBIT_FEATURES,
377ecca9 GC	229	.config_init = &ip1001_config_init,
	230	.config_aneg = &genphy_config_aneg,
	231	.read_status = &genphy_read_status,
	232	.suspend = genphy_suspend,
	233	.resume = genphy_resume,
d5bf9071	234	}, {
9c9b1f24	235	.phy_id = 0x02430c54,
e3e09f26	236	.name = "ICPlus IP101A/G",
9c9b1f24	237	.phy_id_mask = 0x0ffffff0,
529ed127	238	.features = PHY_BASIC_FEATURES,
e3e09f26	239	.flags = PHY_HAS_INTERRUPT,
996f7393	240	.ack_interrupt = ip101a_g_ack_interrupt,
e3e09f26	241	.config_init = &ip101a_g_config_init,
9c9b1f24 GC	242	.config_aneg = &genphy_config_aneg,
	243	.read_status = &genphy_read_status,
	244	.suspend = genphy_suspend,
	245	.resume = genphy_resume,
d5bf9071	246	} };
9c9b1f24	247
50fd7150	248	module_phy_driver(icplus_driver);
4e4f10f6	249
cf93c945	250	static struct mdio_device_id __maybe_unused icplus_tbl[] = {
4e4f10f6	251	{ 0x02430d80, 0x0ffffff0 },
377ecca9	252	{ 0x02430d90, 0x0ffffff0 },
e3e09f26	253	{ 0x02430c54, 0x0ffffff0 },
4e4f10f6 DW	254	{ }
	255	};
	256
	257	MODULE_DEVICE_TABLE(mdio, icplus_tbl);