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[people/ms/linux.git] / drivers / net / phy / marvell.c
CommitLineData
00db8189
AF		 1/*
2 * drivers/net/phy/marvell.c
3 *
4 * Driver for Marvell PHYs
5 *
6 * Author: Andy Fleming
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
9 *
3871c387
MS		 10 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
11 *
00db8189
AF		 12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 */
00db8189 18#include <linux/kernel.h>
00db8189 19#include <linux/string.h>
0b04680f 20#include <linux/ctype.h>
00db8189
AF		 21#include <linux/errno.h>
22#include <linux/unistd.h>
0b04680f 23#include <linux/hwmon.h>
00db8189
AF		 24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/netdevice.h>
28#include <linux/etherdevice.h>
29#include <linux/skbuff.h>
30#include <linux/spinlock.h>
31#include <linux/mm.h>
32#include <linux/module.h>
00db8189
AF		 33#include <linux/mii.h>
34#include <linux/ethtool.h>
35#include <linux/phy.h>
2f495c39 36#include <linux/marvell_phy.h>
cf41a51d 37#include <linux/of.h>
00db8189 38
eea3b201 39#include <linux/io.h>
00db8189 40#include <asm/irq.h>
eea3b201 41#include <linux/uaccess.h>
00db8189 42
27d916d6
DD		 43#define MII_MARVELL_PHY_PAGE 22
44
00db8189
AF		 45#define MII_M1011_IEVENT 0x13
46#define MII_M1011_IEVENT_CLEAR 0x0000
47
48#define MII_M1011_IMASK 0x12
49#define MII_M1011_IMASK_INIT 0x6400
50#define MII_M1011_IMASK_CLEAR 0x0000
51
76884679 52#define MII_M1011_PHY_SCR 0x10
239aa55b
DT		 53#define MII_M1011_PHY_SCR_MDI 0x0000
54#define MII_M1011_PHY_SCR_MDI_X 0x0020
76884679
AF		 55#define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
56
07151bc9 57#define MII_M1145_PHY_EXT_ADDR_PAGE 0x16
b0224175 58#define MII_M1145_PHY_EXT_SR 0x1b
76884679
AF		 59#define MII_M1145_PHY_EXT_CR 0x14
60#define MII_M1145_RGMII_RX_DELAY 0x0080
61#define MII_M1145_RGMII_TX_DELAY 0x0002
b0224175
VND		 62#define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
63#define MII_M1145_HWCFG_MODE_MASK 0xf
64#define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
76884679 65
99d881f9
VB		 66#define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
67#define MII_M1145_HWCFG_MODE_MASK 0xf
68#define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
69
76884679
AF		 70#define MII_M1111_PHY_LED_CONTROL 0x18
71#define MII_M1111_PHY_LED_DIRECT 0x4100
72#define MII_M1111_PHY_LED_COMBINE 0x411c
895ee682
KP		 73#define MII_M1111_PHY_EXT_CR 0x14
74#define MII_M1111_RX_DELAY 0x80
75#define MII_M1111_TX_DELAY 0x2
76#define MII_M1111_PHY_EXT_SR 0x1b
be937f1f
AS		 77
78#define MII_M1111_HWCFG_MODE_MASK 0xf
79#define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
80#define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
4117b5be 81#define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
5f8cbc13 82#define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
be937f1f
AS		 83#define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
84#define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
85
86#define MII_M1111_COPPER 0
87#define MII_M1111_FIBER 1
88
c477d044
CC		 89#define MII_88E1121_PHY_MSCR_PAGE 2
90#define MII_88E1121_PHY_MSCR_REG 21
91#define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
92#define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
93#define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
94
0b04680f
AL		 95#define MII_88E1121_MISC_TEST 0x1a
96#define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK 0x1f00
97#define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT 8
98#define MII_88E1510_MISC_TEST_TEMP_IRQ_EN BIT(7)
99#define MII_88E1510_MISC_TEST_TEMP_IRQ BIT(6)
100#define MII_88E1121_MISC_TEST_TEMP_SENSOR_EN BIT(5)
101#define MII_88E1121_MISC_TEST_TEMP_MASK 0x1f
102
103#define MII_88E1510_TEMP_SENSOR 0x1b
104#define MII_88E1510_TEMP_SENSOR_MASK 0xff
105
337ac9d5
CC		 106#define MII_88E1318S_PHY_MSCR1_REG 16
107#define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
3ff1c259 108
3871c387
MS		 109/* Copper Specific Interrupt Enable Register */
110#define MII_88E1318S_PHY_CSIER 0x12
111/* WOL Event Interrupt Enable */
112#define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
113
114/* LED Timer Control Register */
115#define MII_88E1318S_PHY_LED_PAGE 0x03
116#define MII_88E1318S_PHY_LED_TCR 0x12
117#define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
118#define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
119#define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
120
121/* Magic Packet MAC address registers */
122#define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
123#define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
124#define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
125
126#define MII_88E1318S_PHY_WOL_PAGE 0x11
127#define MII_88E1318S_PHY_WOL_CTRL 0x10
128#define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
129#define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
130
140bc929
SP		 131#define MII_88E1121_PHY_LED_CTRL 16
132#define MII_88E1121_PHY_LED_PAGE 3
133#define MII_88E1121_PHY_LED_DEF 0x0030
140bc929 134
be937f1f
AS		 135#define MII_M1011_PHY_STATUS 0x11
136#define MII_M1011_PHY_STATUS_1000 0x8000
137#define MII_M1011_PHY_STATUS_100 0x4000
138#define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
139#define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
140#define MII_M1011_PHY_STATUS_RESOLVED 0x0800
141#define MII_M1011_PHY_STATUS_LINK 0x0400
142
3da09a51
MS		 143#define MII_M1116R_CONTROL_REG_MAC 21
144
6b358aed
SH		 145#define MII_88E3016_PHY_SPEC_CTRL 0x10
146#define MII_88E3016_DISABLE_SCRAMBLER 0x0200
147#define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
76884679 148
930b37ee
SR		 149#define MII_88E1510_GEN_CTRL_REG_1 0x14
150#define MII_88E1510_GEN_CTRL_REG_1_MODE_MASK 0x7
151#define MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII 0x1 /* SGMII to copper */
152#define MII_88E1510_GEN_CTRL_REG_1_RESET 0x8000 /* Soft reset */
153
6cfb3bcc
CAC		 154#define LPA_FIBER_1000HALF 0x40
155#define LPA_FIBER_1000FULL 0x20
156
157#define LPA_PAUSE_FIBER 0x180
158#define LPA_PAUSE_ASYM_FIBER 0x100
159
160#define ADVERTISE_FIBER_1000HALF 0x40
161#define ADVERTISE_FIBER_1000FULL 0x20
162
163#define ADVERTISE_PAUSE_FIBER 0x180
164#define ADVERTISE_PAUSE_ASYM_FIBER 0x100
165
166#define REGISTER_LINK_STATUS 0x400
2170fef7 167#define NB_FIBER_STATS 1
6cfb3bcc 168
00db8189
AF		 169MODULE_DESCRIPTION("Marvell PHY driver");
170MODULE_AUTHOR("Andy Fleming");
171MODULE_LICENSE("GPL");
172
d2fa47d9
AL		 173struct marvell_hw_stat {
174 const char *string;
175 u8 page;
176 u8 reg;
177 u8 bits;
178};
179
180static struct marvell_hw_stat marvell_hw_stats[] = {
2170fef7 181 { "phy_receive_errors_copper", 0, 21, 16},
d2fa47d9 182 { "phy_idle_errors", 0, 10, 8 },
2170fef7 183 { "phy_receive_errors_fiber", 1, 21, 16},
d2fa47d9
AL		 184};
185
186struct marvell_priv {
187 u64 stats[ARRAY_SIZE(marvell_hw_stats)];
0b04680f
AL		 188 char *hwmon_name;
189 struct device *hwmon_dev;
d2fa47d9
AL		 190};
191
00db8189
AF		 192static int marvell_ack_interrupt(struct phy_device *phydev)
193{
194 int err;
195
196 /* Clear the interrupts by reading the reg */
197 err = phy_read(phydev, MII_M1011_IEVENT);
198
199 if (err < 0)
200 return err;
201
202 return 0;
203}
204
205static int marvell_config_intr(struct phy_device *phydev)
206{
207 int err;
208
76884679 209 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
00db8189
AF		 210 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
211 else
212 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
213
214 return err;
215}
216
239aa55b
DT		 217static int marvell_set_polarity(struct phy_device *phydev, int polarity)
218{
219 int reg;
220 int err;
221 int val;
222
223 /* get the current settings */
224 reg = phy_read(phydev, MII_M1011_PHY_SCR);
225 if (reg < 0)
226 return reg;
227
228 val = reg;
229 val &= ~MII_M1011_PHY_SCR_AUTO_CROSS;
230 switch (polarity) {
231 case ETH_TP_MDI:
232 val |= MII_M1011_PHY_SCR_MDI;
233 break;
234 case ETH_TP_MDI_X:
235 val |= MII_M1011_PHY_SCR_MDI_X;
236 break;
237 case ETH_TP_MDI_AUTO:
238 case ETH_TP_MDI_INVALID:
239 default:
240 val |= MII_M1011_PHY_SCR_AUTO_CROSS;
241 break;
242 }
243
244 if (val != reg) {
245 /* Set the new polarity value in the register */
246 err = phy_write(phydev, MII_M1011_PHY_SCR, val);
247 if (err)
248 return err;
249 }
250
251 return 0;
252}
253
00db8189
AF		 254static int marvell_config_aneg(struct phy_device *phydev)
255{
256 int err;
257
258 /* The Marvell PHY has an errata which requires
259 * that certain registers get written in order
0c3439bc
AL		 260 * to restart autonegotiation
261 */
00db8189
AF		 262 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
263
264 if (err < 0)
265 return err;
266
267 err = phy_write(phydev, 0x1d, 0x1f);
268 if (err < 0)
269 return err;
270
271 err = phy_write(phydev, 0x1e, 0x200c);
272 if (err < 0)
273 return err;
274
275 err = phy_write(phydev, 0x1d, 0x5);
276 if (err < 0)
277 return err;
278
279 err = phy_write(phydev, 0x1e, 0);
280 if (err < 0)
281 return err;
282
283 err = phy_write(phydev, 0x1e, 0x100);
284 if (err < 0)
285 return err;
286
4e26c5c3 287 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
76884679
AF		 288 if (err < 0)
289 return err;
290
291 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
292 MII_M1111_PHY_LED_DIRECT);
293 if (err < 0)
294 return err;
00db8189
AF		 295
296 err = genphy_config_aneg(phydev);
8ff44985
AV		 297 if (err < 0)
298 return err;
00db8189 299
8ff44985
AV		 300 if (phydev->autoneg != AUTONEG_ENABLE) {
301 int bmcr;
302
0c3439bc 303 /* A write to speed/duplex bits (that is performed by
8ff44985
AV		 304 * genphy_config_aneg() call above) must be followed by
305 * a software reset. Otherwise, the write has no effect.
306 */
307 bmcr = phy_read(phydev, MII_BMCR);
308 if (bmcr < 0)
309 return bmcr;
310
311 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
312 if (err < 0)
313 return err;
314 }
315
316 return 0;
00db8189
AF		 317}
318
3ec0a0f1
HK		 319static int m88e1111_config_aneg(struct phy_device *phydev)
320{
321 int err;
322
323 /* The Marvell PHY has an errata which requires
324 * that certain registers get written in order
325 * to restart autonegotiation
326 */
327 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
328
4e26c5c3 329 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
3ec0a0f1
HK		 330 if (err < 0)
331 return err;
332
333 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
334 MII_M1111_PHY_LED_DIRECT);
335 if (err < 0)
336 return err;
337
338 err = genphy_config_aneg(phydev);
339 if (err < 0)
340 return err;
341
342 if (phydev->autoneg != AUTONEG_ENABLE) {
343 int bmcr;
344
345 /* A write to speed/duplex bits (that is performed by
346 * genphy_config_aneg() call above) must be followed by
347 * a software reset. Otherwise, the write has no effect.
348 */
349 bmcr = phy_read(phydev, MII_BMCR);
350 if (bmcr < 0)
351 return bmcr;
352
353 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
354 if (err < 0)
355 return err;
356 }
357
358 return 0;
359}
360
cf41a51d 361#ifdef CONFIG_OF_MDIO
0c3439bc 362/* Set and/or override some configuration registers based on the
cf41a51d
DD		 363 * marvell,reg-init property stored in the of_node for the phydev.
364 *
365 * marvell,reg-init = <reg-page reg mask value>,...;
366 *
367 * There may be one or more sets of <reg-page reg mask value>:
368 *
369 * reg-page: which register bank to use.
370 * reg: the register.
371 * mask: if non-zero, ANDed with existing register value.
372 * value: ORed with the masked value and written to the regiser.
373 *
374 */
375static int marvell_of_reg_init(struct phy_device *phydev)
376{
377 const __be32 *paddr;
b5718b5a 378 int len, i, saved_page, current_page, ret;
cf41a51d 379
e5a03bfd 380 if (!phydev->mdio.dev.of_node)
cf41a51d
DD		 381 return 0;
382
e5a03bfd
AL		 383 paddr = of_get_property(phydev->mdio.dev.of_node,
384 "marvell,reg-init", &len);
cf41a51d
DD		 385 if (!paddr || len < (4 * sizeof(*paddr)))
386 return 0;
387
388 saved_page = phy_read(phydev, MII_MARVELL_PHY_PAGE);
389 if (saved_page < 0)
390 return saved_page;
cf41a51d
DD		 391 current_page = saved_page;
392
393 ret = 0;
394 len /= sizeof(*paddr);
395 for (i = 0; i < len - 3; i += 4) {
396 u16 reg_page = be32_to_cpup(paddr + i);
397 u16 reg = be32_to_cpup(paddr + i + 1);
398 u16 mask = be32_to_cpup(paddr + i + 2);
399 u16 val_bits = be32_to_cpup(paddr + i + 3);
400 int val;
401
402 if (reg_page != current_page) {
403 current_page = reg_page;
cf41a51d
DD		 404 ret = phy_write(phydev, MII_MARVELL_PHY_PAGE, reg_page);
405 if (ret < 0)
406 goto err;
407 }
408
409 val = 0;
410 if (mask) {
411 val = phy_read(phydev, reg);
412 if (val < 0) {
413 ret = val;
414 goto err;
415 }
416 val &= mask;
417 }
418 val |= val_bits;
419
420 ret = phy_write(phydev, reg, val);
421 if (ret < 0)
422 goto err;
cf41a51d
DD		 423 }
424err:
b5718b5a 425 if (current_page != saved_page) {
cf41a51d
DD		 426 i = phy_write(phydev, MII_MARVELL_PHY_PAGE, saved_page);
427 if (ret == 0)
428 ret = i;
429 }
430 return ret;
431}
432#else
433static int marvell_of_reg_init(struct phy_device *phydev)
434{
435 return 0;
436}
437#endif /* CONFIG_OF_MDIO */
438
140bc929
SP		 439static int m88e1121_config_aneg(struct phy_device *phydev)
440{
c477d044
CC		 441 int err, oldpage, mscr;
442
27d916d6 443 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
c477d044 444
27d916d6 445 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
c477d044
CC		 446 MII_88E1121_PHY_MSCR_PAGE);
447 if (err < 0)
448 return err;
be8c6480 449
32a64161 450 if (phy_interface_is_rgmii(phydev)) {
be8c6480
AP		 451 mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) &
452 MII_88E1121_PHY_MSCR_DELAY_MASK;
453
454 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
455 mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY |
456 MII_88E1121_PHY_MSCR_TX_DELAY);
457 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
458 mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
459 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
460 mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
461
462 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
463 if (err < 0)
464 return err;
465 }
c477d044 466
27d916d6 467 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
140bc929
SP		 468
469 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
470 if (err < 0)
471 return err;
472
473 err = phy_write(phydev, MII_M1011_PHY_SCR,
474 MII_M1011_PHY_SCR_AUTO_CROSS);
475 if (err < 0)
476 return err;
477
fdecf36f 478 return genphy_config_aneg(phydev);
140bc929
SP		 479}
480
337ac9d5 481static int m88e1318_config_aneg(struct phy_device *phydev)
3ff1c259
CC		 482{
483 int err, oldpage, mscr;
484
27d916d6 485 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
3ff1c259 486
27d916d6 487 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
3ff1c259
CC		 488 MII_88E1121_PHY_MSCR_PAGE);
489 if (err < 0)
490 return err;
491
337ac9d5
CC		 492 mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG);
493 mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD;
3ff1c259 494
337ac9d5 495 err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr);
3ff1c259
CC		 496 if (err < 0)
497 return err;
498
27d916d6 499 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
3ff1c259
CC		 500 if (err < 0)
501 return err;
502
503 return m88e1121_config_aneg(phydev);
504}
505
78301ebe
CAC		 506/**
507 * ethtool_adv_to_fiber_adv_t
508 * @ethadv: the ethtool advertisement settings
509 *
510 * A small helper function that translates ethtool advertisement
511 * settings to phy autonegotiation advertisements for the
512 * MII_ADV register for fiber link.
513 */
514static inline u32 ethtool_adv_to_fiber_adv_t(u32 ethadv)
515{
516 u32 result = 0;
517
518 if (ethadv & ADVERTISED_1000baseT_Half)
519 result |= ADVERTISE_FIBER_1000HALF;
520 if (ethadv & ADVERTISED_1000baseT_Full)
521 result |= ADVERTISE_FIBER_1000FULL;
522
523 if ((ethadv & ADVERTISE_PAUSE_ASYM) && (ethadv & ADVERTISE_PAUSE_CAP))
524 result |= LPA_PAUSE_ASYM_FIBER;
525 else if (ethadv & ADVERTISE_PAUSE_CAP)
526 result |= (ADVERTISE_PAUSE_FIBER
527 & (~ADVERTISE_PAUSE_ASYM_FIBER));
528
529 return result;
530}
531
532/**
533 * marvell_config_aneg_fiber - restart auto-negotiation or write BMCR
534 * @phydev: target phy_device struct
535 *
536 * Description: If auto-negotiation is enabled, we configure the
537 * advertising, and then restart auto-negotiation. If it is not
538 * enabled, then we write the BMCR. Adapted for fiber link in
539 * some Marvell's devices.
540 */
541static int marvell_config_aneg_fiber(struct phy_device *phydev)
542{
543 int changed = 0;
544 int err;
545 int adv, oldadv;
546 u32 advertise;
547
548 if (phydev->autoneg != AUTONEG_ENABLE)
549 return genphy_setup_forced(phydev);
550
551 /* Only allow advertising what this PHY supports */
552 phydev->advertising &= phydev->supported;
553 advertise = phydev->advertising;
554
555 /* Setup fiber advertisement */
556 adv = phy_read(phydev, MII_ADVERTISE);
557 if (adv < 0)
558 return adv;
559
560 oldadv = adv;
561 adv &= ~(ADVERTISE_FIBER_1000HALF | ADVERTISE_FIBER_1000FULL
562 | LPA_PAUSE_FIBER);
563 adv |= ethtool_adv_to_fiber_adv_t(advertise);
564
565 if (adv != oldadv) {
566 err = phy_write(phydev, MII_ADVERTISE, adv);
567 if (err < 0)
568 return err;
569
570 changed = 1;
571 }
572
573 if (changed == 0) {
574 /* Advertisement hasn't changed, but maybe aneg was never on to
575 * begin with? Or maybe phy was isolated?
576 */
577 int ctl = phy_read(phydev, MII_BMCR);
578
579 if (ctl < 0)
580 return ctl;
581
582 if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE))
583 changed = 1; /* do restart aneg */
584 }
585
586 /* Only restart aneg if we are advertising something different
587 * than we were before.
588 */
589 if (changed > 0)
590 changed = genphy_restart_aneg(phydev);
591
592 return changed;
593}
594
10e24caa
MS		 595static int m88e1510_config_aneg(struct phy_device *phydev)
596{
597 int err;
598
78301ebe
CAC		 599 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
600 if (err < 0)
601 goto error;
602
603 /* Configure the copper link first */
10e24caa
MS		 604 err = m88e1318_config_aneg(phydev);
605 if (err < 0)
78301ebe 606 goto error;
10e24caa 607
78301ebe
CAC		 608 /* Then the fiber link */
609 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER);
610 if (err < 0)
611 goto error;
612
613 err = marvell_config_aneg_fiber(phydev);
614 if (err < 0)
615 goto error;
616
617 return phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
618
619error:
620 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
621 return err;
79be1a1c
CG		 622}
623
624static int marvell_config_init(struct phy_device *phydev)
625{
626 /* Set registers from marvell,reg-init DT property */
10e24caa
MS		 627 return marvell_of_reg_init(phydev);
628}
629
3da09a51
MS		 630static int m88e1116r_config_init(struct phy_device *phydev)
631{
632 int temp;
633 int err;
634
635 temp = phy_read(phydev, MII_BMCR);
636 temp |= BMCR_RESET;
637 err = phy_write(phydev, MII_BMCR, temp);
638 if (err < 0)
639 return err;
640
641 mdelay(500);
642
643 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
644 if (err < 0)
645 return err;
646
647 temp = phy_read(phydev, MII_M1011_PHY_SCR);
648 temp |= (7 << 12); /* max number of gigabit attempts */
649 temp |= (1 << 11); /* enable downshift */
650 temp |= MII_M1011_PHY_SCR_AUTO_CROSS;
651 err = phy_write(phydev, MII_M1011_PHY_SCR, temp);
652 if (err < 0)
653 return err;
654
655 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 2);
656 if (err < 0)
657 return err;
658 temp = phy_read(phydev, MII_M1116R_CONTROL_REG_MAC);
659 temp |= (1 << 5);
660 temp |= (1 << 4);
661 err = phy_write(phydev, MII_M1116R_CONTROL_REG_MAC, temp);
662 if (err < 0)
663 return err;
664 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
665 if (err < 0)
666 return err;
667
668 temp = phy_read(phydev, MII_BMCR);
669 temp |= BMCR_RESET;
670 err = phy_write(phydev, MII_BMCR, temp);
671 if (err < 0)
672 return err;
673
674 mdelay(500);
675
79be1a1c 676 return marvell_config_init(phydev);
3da09a51
MS		 677}
678
6b358aed
SH		 679static int m88e3016_config_init(struct phy_device *phydev)
680{
681 int reg;
682
683 /* Enable Scrambler and Auto-Crossover */
684 reg = phy_read(phydev, MII_88E3016_PHY_SPEC_CTRL);
685 if (reg < 0)
686 return reg;
687
688 reg &= ~MII_88E3016_DISABLE_SCRAMBLER;
689 reg |= MII_88E3016_AUTO_MDIX_CROSSOVER;
690
691 reg = phy_write(phydev, MII_88E3016_PHY_SPEC_CTRL, reg);
692 if (reg < 0)
693 return reg;
694
79be1a1c 695 return marvell_config_init(phydev);
6b358aed
SH		 696}
697
895ee682
KP		 698static int m88e1111_config_init(struct phy_device *phydev)
699{
700 int err;
be937f1f 701 int temp;
be937f1f 702
32a64161 703 if (phy_interface_is_rgmii(phydev)) {
9daf5a76
KP		 704 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
705 if (temp < 0)
706 return temp;
895ee682 707
9daf5a76 708 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
895ee682 709 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
9daf5a76
KP		 710 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
711 temp &= ~MII_M1111_TX_DELAY;
712 temp |= MII_M1111_RX_DELAY;
713 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
714 temp &= ~MII_M1111_RX_DELAY;
715 temp |= MII_M1111_TX_DELAY;
895ee682
KP		 716 }
717
9daf5a76
KP		 718 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
719 if (err < 0)
720 return err;
721
895ee682
KP		 722 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
723 if (temp < 0)
724 return temp;
725
726 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
be937f1f 727
7239016d 728 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
be937f1f
AS		 729 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
730 else
731 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
895ee682
KP		 732
733 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
734 if (err < 0)
735 return err;
736 }
737
4117b5be 738 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
4117b5be
KJ		 739 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
740 if (temp < 0)
741 return temp;
742
743 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
744 temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
32d0c1e1 745 temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
4117b5be
KJ		 746
747 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
748 if (err < 0)
749 return err;
07151bc9
MB		 750
751 /* make sure copper is selected */
752 err = phy_read(phydev, MII_M1145_PHY_EXT_ADDR_PAGE);
753 if (err < 0)
754 return err;
755
756 err = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE,
757 err & (~0xff));
758 if (err < 0)
759 return err;
4117b5be
KJ		 760 }
761
5f8cbc13
LYB		 762 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
763 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
764 if (temp < 0)
765 return temp;
766 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
767 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
768 if (err < 0)
769 return err;
770
771 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
772 if (temp < 0)
773 return temp;
774 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
775 temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
776 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
777 if (err < 0)
778 return err;
779
780 /* soft reset */
781 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
782 if (err < 0)
783 return err;
784 do
785 temp = phy_read(phydev, MII_BMCR);
786 while (temp & BMCR_RESET);
787
788 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
789 if (temp < 0)
790 return temp;
791 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
792 temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
793 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
794 if (err < 0)
795 return err;
796 }
797
cf41a51d
DD		 798 err = marvell_of_reg_init(phydev);
799 if (err < 0)
800 return err;
5f8cbc13 801
cc90cb3b 802 return phy_write(phydev, MII_BMCR, BMCR_RESET);
895ee682
KP		 803}
804
fdecf36f
CG		 805static int m88e1121_config_init(struct phy_device *phydev)
806{
807 int err, oldpage;
808
809 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
810
811 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
812 if (err < 0)
813 return err;
814
815 /* Default PHY LED config: LED[0] .. Link, LED[1] .. Activity */
816 err = phy_write(phydev, MII_88E1121_PHY_LED_CTRL,
817 MII_88E1121_PHY_LED_DEF);
818 if (err < 0)
819 return err;
820
821 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
822
823 /* Set marvell,reg-init configuration from device tree */
824 return marvell_config_init(phydev);
825}
826
407353ec
CG		 827static int m88e1510_config_init(struct phy_device *phydev)
828{
829 int err;
830 int temp;
831
832 /* SGMII-to-Copper mode initialization */
833 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
834 /* Select page 18 */
835 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 18);
836 if (err < 0)
837 return err;
838
839 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
840 temp = phy_read(phydev, MII_88E1510_GEN_CTRL_REG_1);
841 temp &= ~MII_88E1510_GEN_CTRL_REG_1_MODE_MASK;
842 temp |= MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII;
843 err = phy_write(phydev, MII_88E1510_GEN_CTRL_REG_1, temp);
844 if (err < 0)
845 return err;
846
847 /* PHY reset is necessary after changing MODE[2:0] */
848 temp |= MII_88E1510_GEN_CTRL_REG_1_RESET;
849 err = phy_write(phydev, MII_88E1510_GEN_CTRL_REG_1, temp);
850 if (err < 0)
851 return err;
852
853 /* Reset page selection */
854 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
855 if (err < 0)
856 return err;
857 }
858
fdecf36f 859 return m88e1121_config_init(phydev);
407353ec
CG		 860}
861
605f196e
RM		 862static int m88e1118_config_aneg(struct phy_device *phydev)
863{
864 int err;
865
866 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
867 if (err < 0)
868 return err;
869
870 err = phy_write(phydev, MII_M1011_PHY_SCR,
871 MII_M1011_PHY_SCR_AUTO_CROSS);
872 if (err < 0)
873 return err;
874
875 err = genphy_config_aneg(phydev);
876 return 0;
877}
878
879static int m88e1118_config_init(struct phy_device *phydev)
880{
881 int err;
882
883 /* Change address */
27d916d6 884 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
605f196e
RM		 885 if (err < 0)
886 return err;
887
888 /* Enable 1000 Mbit */
889 err = phy_write(phydev, 0x15, 0x1070);
890 if (err < 0)
891 return err;
892
893 /* Change address */
27d916d6 894 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0003);
605f196e
RM		 895 if (err < 0)
896 return err;
897
898 /* Adjust LED Control */
2f495c39
BH		 899 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
900 err = phy_write(phydev, 0x10, 0x1100);
901 else
902 err = phy_write(phydev, 0x10, 0x021e);
605f196e
RM		 903 if (err < 0)
904 return err;
905
cf41a51d
DD		 906 err = marvell_of_reg_init(phydev);
907 if (err < 0)
908 return err;
909
605f196e 910 /* Reset address */
27d916d6 911 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
605f196e
RM		 912 if (err < 0)
913 return err;
914
cc90cb3b 915 return phy_write(phydev, MII_BMCR, BMCR_RESET);
605f196e
RM		 916}
917
90600732
DD		 918static int m88e1149_config_init(struct phy_device *phydev)
919{
920 int err;
921
922 /* Change address */
923 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
924 if (err < 0)
925 return err;
926
927 /* Enable 1000 Mbit */
928 err = phy_write(phydev, 0x15, 0x1048);
929 if (err < 0)
930 return err;
931
cf41a51d
DD		 932 err = marvell_of_reg_init(phydev);
933 if (err < 0)
934 return err;
935
90600732
DD		 936 /* Reset address */
937 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
938 if (err < 0)
939 return err;
940
cc90cb3b 941 return phy_write(phydev, MII_BMCR, BMCR_RESET);
90600732
DD		 942}
943
76884679
AF		 944static int m88e1145_config_init(struct phy_device *phydev)
945{
946 int err;
b0224175 947 int temp;
76884679
AF		 948
949 /* Take care of errata E0 & E1 */
950 err = phy_write(phydev, 0x1d, 0x001b);
951 if (err < 0)
952 return err;
953
954 err = phy_write(phydev, 0x1e, 0x418f);
955 if (err < 0)
956 return err;
957
958 err = phy_write(phydev, 0x1d, 0x0016);
959 if (err < 0)
960 return err;
961
962 err = phy_write(phydev, 0x1e, 0xa2da);
963 if (err < 0)
964 return err;
965
895ee682 966 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
76884679 967 int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
e69d9ed4 968
76884679
AF		 969 if (temp < 0)
970 return temp;
971
972 temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
973
974 err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
975 if (err < 0)
976 return err;
977
2f495c39 978 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
76884679
AF		 979 err = phy_write(phydev, 0x1d, 0x0012);
980 if (err < 0)
981 return err;
982
983 temp = phy_read(phydev, 0x1e);
984 if (temp < 0)
985 return temp;
986
987 temp &= 0xf03f;
988 temp |= 2 << 9; /* 36 ohm */
989 temp |= 2 << 6; /* 39 ohm */
990
991 err = phy_write(phydev, 0x1e, temp);
992 if (err < 0)
993 return err;
994
995 err = phy_write(phydev, 0x1d, 0x3);
996 if (err < 0)
997 return err;
998
999 err = phy_write(phydev, 0x1e, 0x8000);
1000 if (err < 0)
1001 return err;
1002 }
1003 }
1004
b0224175
VND		 1005 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1006 temp = phy_read(phydev, MII_M1145_PHY_EXT_SR);
1007 if (temp < 0)
1008 return temp;
1009
99d881f9 1010 temp &= ~MII_M1145_HWCFG_MODE_MASK;
b0224175
VND		 1011 temp |= MII_M1145_HWCFG_MODE_SGMII_NO_CLK;
1012 temp |= MII_M1145_HWCFG_FIBER_COPPER_AUTO;
1013
1014 err = phy_write(phydev, MII_M1145_PHY_EXT_SR, temp);
1015 if (err < 0)
1016 return err;
1017 }
1018
cf41a51d
DD		 1019 err = marvell_of_reg_init(phydev);
1020 if (err < 0)
1021 return err;
1022
76884679
AF		 1023 return 0;
1024}
00db8189 1025
6cfb3bcc
CAC		 1026/**
1027 * fiber_lpa_to_ethtool_lpa_t
1028 * @lpa: value of the MII_LPA register for fiber link
1029 *
1030 * A small helper function that translates MII_LPA
1031 * bits to ethtool LP advertisement settings.
1032 */
1033static u32 fiber_lpa_to_ethtool_lpa_t(u32 lpa)
1034{
1035 u32 result = 0;
1036
1037 if (lpa & LPA_FIBER_1000HALF)
1038 result |= ADVERTISED_1000baseT_Half;
1039 if (lpa & LPA_FIBER_1000FULL)
1040 result |= ADVERTISED_1000baseT_Full;
1041
1042 return result;
1043}
1044
1045/**
1046 * marvell_update_link - update link status in real time in @phydev
1047 * @phydev: target phy_device struct
1048 *
1049 * Description: Update the value in phydev->link to reflect the
1050 * current link value.
1051 */
1052static int marvell_update_link(struct phy_device *phydev, int fiber)
1053{
1054 int status;
1055
1056 /* Use the generic register for copper link, or specific
0c3439bc
AL		 1057 * register for fiber case
1058 */
6cfb3bcc
CAC		 1059 if (fiber) {
1060 status = phy_read(phydev, MII_M1011_PHY_STATUS);
1061 if (status < 0)
1062 return status;
1063
1064 if ((status & REGISTER_LINK_STATUS) == 0)
1065 phydev->link = 0;
1066 else
1067 phydev->link = 1;
1068 } else {
1069 return genphy_update_link(phydev);
1070 }
1071
1072 return 0;
1073}
1074
1075/* marvell_read_status_page
be937f1f 1076 *
f0c88f9c 1077 * Description:
be937f1f
AS		 1078 * Check the link, then figure out the current state
1079 * by comparing what we advertise with what the link partner
1080 * advertises. Start by checking the gigabit possibilities,
1081 * then move on to 10/100.
1082 */
6cfb3bcc 1083static int marvell_read_status_page(struct phy_device *phydev, int page)
be937f1f
AS		 1084{
1085 int adv;
1086 int err;
1087 int lpa;
357cd64c 1088 int lpagb;
be937f1f 1089 int status = 0;
6cfb3bcc 1090 int fiber;
be937f1f 1091
6cfb3bcc 1092 /* Detect and update the link, but return if there
0c3439bc
AL		 1093 * was an error
1094 */
6cfb3bcc
CAC		 1095 if (page == MII_M1111_FIBER)
1096 fiber = 1;
1097 else
1098 fiber = 0;
1099
1100 err = marvell_update_link(phydev, fiber);
be937f1f
AS		 1101 if (err)
1102 return err;
1103
4f48ed32 1104 if (phydev->autoneg == AUTONEG_ENABLE) {
be937f1f
AS		 1105 status = phy_read(phydev, MII_M1011_PHY_STATUS);
1106 if (status < 0)
1107 return status;
1108
1109 lpa = phy_read(phydev, MII_LPA);
1110 if (lpa < 0)
1111 return lpa;
1112
357cd64c
RK		 1113 lpagb = phy_read(phydev, MII_STAT1000);
1114 if (lpagb < 0)
1115 return lpagb;
1116
be937f1f
AS		 1117 adv = phy_read(phydev, MII_ADVERTISE);
1118 if (adv < 0)
1119 return adv;
1120
1121 lpa &= adv;
1122
1123 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
1124 phydev->duplex = DUPLEX_FULL;
1125 else
1126 phydev->duplex = DUPLEX_HALF;
1127
1128 status = status & MII_M1011_PHY_STATUS_SPD_MASK;
4f48ed32
AL		 1129 phydev->pause = 0;
1130 phydev->asym_pause = 0;
be937f1f
AS		 1131
1132 switch (status) {
1133 case MII_M1011_PHY_STATUS_1000:
1134 phydev->speed = SPEED_1000;
1135 break;
1136
1137 case MII_M1011_PHY_STATUS_100:
1138 phydev->speed = SPEED_100;
1139 break;
1140
1141 default:
1142 phydev->speed = SPEED_10;
1143 break;
1144 }
1145
6cfb3bcc
CAC		 1146 if (!fiber) {
1147 phydev->lp_advertising = mii_stat1000_to_ethtool_lpa_t(lpagb) |
1148 mii_lpa_to_ethtool_lpa_t(lpa);
1149
1150 if (phydev->duplex == DUPLEX_FULL) {
1151 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
1152 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
1153 }
1154 } else {
1155 /* The fiber link is only 1000M capable */
1156 phydev->lp_advertising = fiber_lpa_to_ethtool_lpa_t(lpa);
1157
1158 if (phydev->duplex == DUPLEX_FULL) {
1159 if (!(lpa & LPA_PAUSE_FIBER)) {
1160 phydev->pause = 0;
1161 phydev->asym_pause = 0;
1162 } else if ((lpa & LPA_PAUSE_ASYM_FIBER)) {
1163 phydev->pause = 1;
1164 phydev->asym_pause = 1;
1165 } else {
1166 phydev->pause = 1;
1167 phydev->asym_pause = 0;
1168 }
1169 }
be937f1f
AS		 1170 }
1171 } else {
1172 int bmcr = phy_read(phydev, MII_BMCR);
1173
1174 if (bmcr < 0)
1175 return bmcr;
1176
1177 if (bmcr & BMCR_FULLDPLX)
1178 phydev->duplex = DUPLEX_FULL;
1179 else
1180 phydev->duplex = DUPLEX_HALF;
1181
1182 if (bmcr & BMCR_SPEED1000)
1183 phydev->speed = SPEED_1000;
1184 else if (bmcr & BMCR_SPEED100)
1185 phydev->speed = SPEED_100;
1186 else
1187 phydev->speed = SPEED_10;
1188
4f48ed32
AL		 1189 phydev->pause = 0;
1190 phydev->asym_pause = 0;
357cd64c 1191 phydev->lp_advertising = 0;
be937f1f
AS		 1192 }
1193
1194 return 0;
1195}
1196
6cfb3bcc
CAC		 1197/* marvell_read_status
1198 *
1199 * Some Marvell's phys have two modes: fiber and copper.
1200 * Both need status checked.
1201 * Description:
1202 * First, check the fiber link and status.
1203 * If the fiber link is down, check the copper link and status which
1204 * will be the default value if both link are down.
1205 */
1206static int marvell_read_status(struct phy_device *phydev)
1207{
1208 int err;
1209
1210 /* Check the fiber mode first */
a13c0652
RK		 1211 if (phydev->supported & SUPPORTED_FIBRE &&
1212 phydev->interface != PHY_INTERFACE_MODE_SGMII) {
6cfb3bcc
CAC		 1213 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER);
1214 if (err < 0)
1215 goto error;
1216
1217 err = marvell_read_status_page(phydev, MII_M1111_FIBER);
1218 if (err < 0)
1219 goto error;
1220
0c3439bc
AL		 1221 /* If the fiber link is up, it is the selected and
1222 * used link. In this case, we need to stay in the
1223 * fiber page. Please to be careful about that, avoid
1224 * to restore Copper page in other functions which
1225 * could break the behaviour for some fiber phy like
1226 * 88E1512.
1227 */
6cfb3bcc
CAC		 1228 if (phydev->link)
1229 return 0;
1230
1231 /* If fiber link is down, check and save copper mode state */
1232 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1233 if (err < 0)
1234 goto error;
1235 }
1236
1237 return marvell_read_status_page(phydev, MII_M1111_COPPER);
1238
1239error:
1240 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1241 return err;
1242}
3758be3d
CAC		 1243
1244/* marvell_suspend
1245 *
1246 * Some Marvell's phys have two modes: fiber and copper.
1247 * Both need to be suspended
1248 */
1249static int marvell_suspend(struct phy_device *phydev)
1250{
1251 int err;
1252
1253 /* Suspend the fiber mode first */
1254 if (!(phydev->supported & SUPPORTED_FIBRE)) {
1255 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER);
1256 if (err < 0)
1257 goto error;
1258
1259 /* With the page set, use the generic suspend */
1260 err = genphy_suspend(phydev);
1261 if (err < 0)
1262 goto error;
1263
1264 /* Then, the copper link */
1265 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1266 if (err < 0)
1267 goto error;
1268 }
1269
1270 /* With the page set, use the generic suspend */
1271 return genphy_suspend(phydev);
1272
1273error:
1274 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1275 return err;
1276}
1277
1278/* marvell_resume
1279 *
1280 * Some Marvell's phys have two modes: fiber and copper.
1281 * Both need to be resumed
1282 */
1283static int marvell_resume(struct phy_device *phydev)
1284{
1285 int err;
1286
1287 /* Resume the fiber mode first */
1288 if (!(phydev->supported & SUPPORTED_FIBRE)) {
1289 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER);
1290 if (err < 0)
1291 goto error;
1292
1293 /* With the page set, use the generic resume */
1294 err = genphy_resume(phydev);
1295 if (err < 0)
1296 goto error;
1297
1298 /* Then, the copper link */
1299 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1300 if (err < 0)
1301 goto error;
1302 }
1303
1304 /* With the page set, use the generic resume */
1305 return genphy_resume(phydev);
1306
1307error:
1308 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1309 return err;
1310}
1311
6b358aed
SH		 1312static int marvell_aneg_done(struct phy_device *phydev)
1313{
1314 int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
e69d9ed4 1315
6b358aed
SH		 1316 return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
1317}
1318
dcd07be3
AG		 1319static int m88e1121_did_interrupt(struct phy_device *phydev)
1320{
1321 int imask;
1322
1323 imask = phy_read(phydev, MII_M1011_IEVENT);
1324
1325 if (imask & MII_M1011_IMASK_INIT)
1326 return 1;
1327
1328 return 0;
1329}
1330
3871c387
MS		 1331static void m88e1318_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
1332{
1333 wol->supported = WAKE_MAGIC;
1334 wol->wolopts = 0;
1335
1336 if (phy_write(phydev, MII_MARVELL_PHY_PAGE,
1337 MII_88E1318S_PHY_WOL_PAGE) < 0)
1338 return;
1339
1340 if (phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL) &
1341 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
1342 wol->wolopts |= WAKE_MAGIC;
1343
1344 if (phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00) < 0)
1345 return;
1346}
1347
1348static int m88e1318_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
1349{
1350 int err, oldpage, temp;
1351
1352 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
1353
1354 if (wol->wolopts & WAKE_MAGIC) {
1355 /* Explicitly switch to page 0x00, just to be sure */
1356 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00);
1357 if (err < 0)
1358 return err;
1359
1360 /* Enable the WOL interrupt */
1361 temp = phy_read(phydev, MII_88E1318S_PHY_CSIER);
1362 temp |= MII_88E1318S_PHY_CSIER_WOL_EIE;
1363 err = phy_write(phydev, MII_88E1318S_PHY_CSIER, temp);
1364 if (err < 0)
1365 return err;
1366
1367 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1368 MII_88E1318S_PHY_LED_PAGE);
1369 if (err < 0)
1370 return err;
1371
1372 /* Setup LED[2] as interrupt pin (active low) */
1373 temp = phy_read(phydev, MII_88E1318S_PHY_LED_TCR);
1374 temp &= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT;
1375 temp |= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE;
1376 temp |= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW;
1377 err = phy_write(phydev, MII_88E1318S_PHY_LED_TCR, temp);
1378 if (err < 0)
1379 return err;
1380
1381 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1382 MII_88E1318S_PHY_WOL_PAGE);
1383 if (err < 0)
1384 return err;
1385
1386 /* Store the device address for the magic packet */
1387 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
1388 ((phydev->attached_dev->dev_addr[5] << 8) |
1389 phydev->attached_dev->dev_addr[4]));
1390 if (err < 0)
1391 return err;
1392 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
1393 ((phydev->attached_dev->dev_addr[3] << 8) |
1394 phydev->attached_dev->dev_addr[2]));
1395 if (err < 0)
1396 return err;
1397 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
1398 ((phydev->attached_dev->dev_addr[1] << 8) |
1399 phydev->attached_dev->dev_addr[0]));
1400 if (err < 0)
1401 return err;
1402
1403 /* Clear WOL status and enable magic packet matching */
1404 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
1405 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
1406 temp |= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
1407 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
1408 if (err < 0)
1409 return err;
1410 } else {
1411 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1412 MII_88E1318S_PHY_WOL_PAGE);
1413 if (err < 0)
1414 return err;
1415
1416 /* Clear WOL status and disable magic packet matching */
1417 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
1418 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
1419 temp &= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
1420 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
1421 if (err < 0)
1422 return err;
1423 }
1424
1425 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
1426 if (err < 0)
1427 return err;
1428
1429 return 0;
1430}
1431
d2fa47d9
AL		 1432static int marvell_get_sset_count(struct phy_device *phydev)
1433{
2170fef7
CAC		 1434 if (phydev->supported & SUPPORTED_FIBRE)
1435 return ARRAY_SIZE(marvell_hw_stats);
1436 else
1437 return ARRAY_SIZE(marvell_hw_stats) - NB_FIBER_STATS;
d2fa47d9
AL		 1438}
1439
1440static void marvell_get_strings(struct phy_device *phydev, u8 *data)
1441{
1442 int i;
1443
1444 for (i = 0; i < ARRAY_SIZE(marvell_hw_stats); i++) {
1445 memcpy(data + i * ETH_GSTRING_LEN,
1446 marvell_hw_stats[i].string, ETH_GSTRING_LEN);
1447 }
1448}
1449
1450#ifndef UINT64_MAX
1451#define UINT64_MAX (u64)(~((u64)0))
1452#endif
1453static u64 marvell_get_stat(struct phy_device *phydev, int i)
1454{
1455 struct marvell_hw_stat stat = marvell_hw_stats[i];
1456 struct marvell_priv *priv = phydev->priv;
321b4d4b
AL		 1457 int err, oldpage, val;
1458 u64 ret;
d2fa47d9
AL		 1459
1460 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
1461 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1462 stat.page);
1463 if (err < 0)
1464 return UINT64_MAX;
1465
1466 val = phy_read(phydev, stat.reg);
1467 if (val < 0) {
321b4d4b 1468 ret = UINT64_MAX;
d2fa47d9
AL		 1469 } else {
1470 val = val & ((1 << stat.bits) - 1);
1471 priv->stats[i] += val;
321b4d4b 1472 ret = priv->stats[i];
d2fa47d9
AL		 1473 }
1474
1475 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
1476
321b4d4b 1477 return ret;
d2fa47d9
AL		 1478}
1479
1480static void marvell_get_stats(struct phy_device *phydev,
1481 struct ethtool_stats *stats, u64 *data)
1482{
1483 int i;
1484
1485 for (i = 0; i < ARRAY_SIZE(marvell_hw_stats); i++)
1486 data[i] = marvell_get_stat(phydev, i);
1487}
1488
0b04680f
AL		 1489#ifdef CONFIG_HWMON
1490static int m88e1121_get_temp(struct phy_device *phydev, long *temp)
1491{
1492 int ret;
1493 int val;
1494
1495 *temp = 0;
1496
1497 mutex_lock(&phydev->lock);
1498
1499 ret = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x6);
1500 if (ret < 0)
1501 goto error;
1502
1503 /* Enable temperature sensor */
1504 ret = phy_read(phydev, MII_88E1121_MISC_TEST);
1505 if (ret < 0)
1506 goto error;
1507
1508 ret = phy_write(phydev, MII_88E1121_MISC_TEST,
1509 ret | MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
1510 if (ret < 0)
1511 goto error;
1512
1513 /* Wait for temperature to stabilize */
1514 usleep_range(10000, 12000);
1515
1516 val = phy_read(phydev, MII_88E1121_MISC_TEST);
1517 if (val < 0) {
1518 ret = val;
1519 goto error;
1520 }
1521
1522 /* Disable temperature sensor */
1523 ret = phy_write(phydev, MII_88E1121_MISC_TEST,
1524 ret & ~MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
1525 if (ret < 0)
1526 goto error;
1527
1528 *temp = ((val & MII_88E1121_MISC_TEST_TEMP_MASK) - 5) * 5000;
1529
1530error:
1531 phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x0);
1532 mutex_unlock(&phydev->lock);
1533
1534 return ret;
1535}
1536
1537static int m88e1121_hwmon_read(struct device *dev,
1538 enum hwmon_sensor_types type,
1539 u32 attr, int channel, long *temp)
1540{
1541 struct phy_device *phydev = dev_get_drvdata(dev);
1542 int err;
1543
1544 switch (attr) {
1545 case hwmon_temp_input:
1546 err = m88e1121_get_temp(phydev, temp);
1547 break;
1548 default:
1549 return -EOPNOTSUPP;
1550 }
1551
1552 return err;
1553}
1554
1555static umode_t m88e1121_hwmon_is_visible(const void *data,
1556 enum hwmon_sensor_types type,
1557 u32 attr, int channel)
1558{
1559 if (type != hwmon_temp)
1560 return 0;
1561
1562 switch (attr) {
1563 case hwmon_temp_input:
1564 return 0444;
1565 default:
1566 return 0;
1567 }
1568}
1569
1570static u32 m88e1121_hwmon_chip_config[] = {
1571 HWMON_C_REGISTER_TZ,
1572 0
1573};
1574
1575static const struct hwmon_channel_info m88e1121_hwmon_chip = {
1576 .type = hwmon_chip,
1577 .config = m88e1121_hwmon_chip_config,
1578};
1579
1580static u32 m88e1121_hwmon_temp_config[] = {
1581 HWMON_T_INPUT,
1582 0
1583};
1584
1585static const struct hwmon_channel_info m88e1121_hwmon_temp = {
1586 .type = hwmon_temp,
1587 .config = m88e1121_hwmon_temp_config,
1588};
1589
1590static const struct hwmon_channel_info *m88e1121_hwmon_info[] = {
1591 &m88e1121_hwmon_chip,
1592 &m88e1121_hwmon_temp,
1593 NULL
1594};
1595
1596static const struct hwmon_ops m88e1121_hwmon_hwmon_ops = {
1597 .is_visible = m88e1121_hwmon_is_visible,
1598 .read = m88e1121_hwmon_read,
1599};
1600
1601static const struct hwmon_chip_info m88e1121_hwmon_chip_info = {
1602 .ops = &m88e1121_hwmon_hwmon_ops,
1603 .info = m88e1121_hwmon_info,
1604};
1605
1606static int m88e1510_get_temp(struct phy_device *phydev, long *temp)
1607{
1608 int ret;
1609
1610 *temp = 0;
1611
1612 mutex_lock(&phydev->lock);
1613
1614 ret = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x6);
1615 if (ret < 0)
1616 goto error;
1617
1618 ret = phy_read(phydev, MII_88E1510_TEMP_SENSOR);
1619 if (ret < 0)
1620 goto error;
1621
1622 *temp = ((ret & MII_88E1510_TEMP_SENSOR_MASK) - 25) * 1000;
1623
1624error:
1625 phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x0);
1626 mutex_unlock(&phydev->lock);
1627
1628 return ret;
1629}
1630
1631int m88e1510_get_temp_critical(struct phy_device *phydev, long *temp)
1632{
1633 int ret;
1634
1635 *temp = 0;
1636
1637 mutex_lock(&phydev->lock);
1638
1639 ret = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x6);
1640 if (ret < 0)
1641 goto error;
1642
1643 ret = phy_read(phydev, MII_88E1121_MISC_TEST);
1644 if (ret < 0)
1645 goto error;
1646
1647 *temp = (((ret & MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK) >>
1648 MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT) * 5) - 25;
1649 /* convert to mC */
1650 *temp *= 1000;
1651
1652error:
1653 phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x0);
1654 mutex_unlock(&phydev->lock);
1655
1656 return ret;
1657}
1658
1659int m88e1510_set_temp_critical(struct phy_device *phydev, long temp)
1660{
1661 int ret;
1662
1663 mutex_lock(&phydev->lock);
1664
1665 ret = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x6);
1666 if (ret < 0)
1667 goto error;
1668
1669 ret = phy_read(phydev, MII_88E1121_MISC_TEST);
1670 if (ret < 0)
1671 goto error;
1672
1673 temp = temp / 1000;
1674 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
1675 ret = phy_write(phydev, MII_88E1121_MISC_TEST,
1676 (ret & ~MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK) |
1677 (temp << MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT));
1678
1679error:
1680 phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x0);
1681 mutex_unlock(&phydev->lock);
1682
1683 return ret;
1684}
1685
1686int m88e1510_get_temp_alarm(struct phy_device *phydev, long *alarm)
1687{
1688 int ret;
1689
1690 *alarm = false;
1691
1692 mutex_lock(&phydev->lock);
1693
1694 ret = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x6);
1695 if (ret < 0)
1696 goto error;
1697
1698 ret = phy_read(phydev, MII_88E1121_MISC_TEST);
1699 if (ret < 0)
1700 goto error;
1701 *alarm = !!(ret & MII_88E1510_MISC_TEST_TEMP_IRQ);
1702
1703error:
1704 phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x0);
1705 mutex_unlock(&phydev->lock);
1706
1707 return ret;
1708}
1709
1710static int m88e1510_hwmon_read(struct device *dev,
1711 enum hwmon_sensor_types type,
1712 u32 attr, int channel, long *temp)
1713{
1714 struct phy_device *phydev = dev_get_drvdata(dev);
1715 int err;
1716
1717 switch (attr) {
1718 case hwmon_temp_input:
1719 err = m88e1510_get_temp(phydev, temp);
1720 break;
1721 case hwmon_temp_crit:
1722 err = m88e1510_get_temp_critical(phydev, temp);
1723 break;
1724 case hwmon_temp_max_alarm:
1725 err = m88e1510_get_temp_alarm(phydev, temp);
1726 break;
1727 default:
1728 return -EOPNOTSUPP;
1729 }
1730
1731 return err;
1732}
1733
1734static int m88e1510_hwmon_write(struct device *dev,
1735 enum hwmon_sensor_types type,
1736 u32 attr, int channel, long temp)
1737{
1738 struct phy_device *phydev = dev_get_drvdata(dev);
1739 int err;
1740
1741 switch (attr) {
1742 case hwmon_temp_crit:
1743 err = m88e1510_set_temp_critical(phydev, temp);
1744 break;
1745 default:
1746 return -EOPNOTSUPP;
1747 }
1748 return err;
1749}
1750
1751static umode_t m88e1510_hwmon_is_visible(const void *data,
1752 enum hwmon_sensor_types type,
1753 u32 attr, int channel)
1754{
1755 if (type != hwmon_temp)
1756 return 0;
1757
1758 switch (attr) {
1759 case hwmon_temp_input:
1760 case hwmon_temp_max_alarm:
1761 return 0444;
1762 case hwmon_temp_crit:
1763 return 0644;
1764 default:
1765 return 0;
1766 }
1767}
1768
1769static u32 m88e1510_hwmon_temp_config[] = {
1770 HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_MAX_ALARM,
1771 0
1772};
1773
1774static const struct hwmon_channel_info m88e1510_hwmon_temp = {
1775 .type = hwmon_temp,
1776 .config = m88e1510_hwmon_temp_config,
1777};
1778
1779static const struct hwmon_channel_info *m88e1510_hwmon_info[] = {
1780 &m88e1121_hwmon_chip,
1781 &m88e1510_hwmon_temp,
1782 NULL
1783};
1784
1785static const struct hwmon_ops m88e1510_hwmon_hwmon_ops = {
1786 .is_visible = m88e1510_hwmon_is_visible,
1787 .read = m88e1510_hwmon_read,
1788 .write = m88e1510_hwmon_write,
1789};
1790
1791static const struct hwmon_chip_info m88e1510_hwmon_chip_info = {
1792 .ops = &m88e1510_hwmon_hwmon_ops,
1793 .info = m88e1510_hwmon_info,
1794};
1795
1796static int marvell_hwmon_name(struct phy_device *phydev)
1797{
1798 struct marvell_priv *priv = phydev->priv;
1799 struct device *dev = &phydev->mdio.dev;
1800 const char *devname = dev_name(dev);
1801 size_t len = strlen(devname);
1802 int i, j;
1803
1804 priv->hwmon_name = devm_kzalloc(dev, len, GFP_KERNEL);
1805 if (!priv->hwmon_name)
1806 return -ENOMEM;
1807
1808 for (i = j = 0; i < len && devname[i]; i++) {
1809 if (isalnum(devname[i]))
1810 priv->hwmon_name[j++] = devname[i];
1811 }
1812
1813 return 0;
1814}
1815
1816static int marvell_hwmon_probe(struct phy_device *phydev,
1817 const struct hwmon_chip_info *chip)
1818{
1819 struct marvell_priv *priv = phydev->priv;
1820 struct device *dev = &phydev->mdio.dev;
1821 int err;
1822
1823 err = marvell_hwmon_name(phydev);
1824 if (err)
1825 return err;
1826
1827 priv->hwmon_dev = devm_hwmon_device_register_with_info(
1828 dev, priv->hwmon_name, phydev, chip, NULL);
1829
1830 return PTR_ERR_OR_ZERO(priv->hwmon_dev);
1831}
1832
1833static int m88e1121_hwmon_probe(struct phy_device *phydev)
1834{
1835 return marvell_hwmon_probe(phydev, &m88e1121_hwmon_chip_info);
1836}
1837
1838static int m88e1510_hwmon_probe(struct phy_device *phydev)
1839{
1840 return marvell_hwmon_probe(phydev, &m88e1510_hwmon_chip_info);
1841}
1842#else
1843static int m88e1121_hwmon_probe(struct phy_device *phydev)
1844{
1845 return 0;
1846}
1847
1848static int m88e1510_hwmon_probe(struct phy_device *phydev)
1849{
1850 return 0;
1851}
1852#endif
1853
d2fa47d9
AL		 1854static int marvell_probe(struct phy_device *phydev)
1855{
1856 struct marvell_priv *priv;
1857
e5a03bfd 1858 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
d2fa47d9
AL		 1859 if (!priv)
1860 return -ENOMEM;
1861
1862 phydev->priv = priv;
1863
1864 return 0;
1865}
1866
0b04680f
AL		 1867static int m88e1121_probe(struct phy_device *phydev)
1868{
1869 int err;
1870
1871 err = marvell_probe(phydev);
1872 if (err)
1873 return err;
1874
1875 return m88e1121_hwmon_probe(phydev);
1876}
1877
1878static int m88e1510_probe(struct phy_device *phydev)
1879{
1880 int err;
1881
1882 err = marvell_probe(phydev);
1883 if (err)
1884 return err;
1885
1886 return m88e1510_hwmon_probe(phydev);
1887}
1888
e5479239
OJ		 1889static struct phy_driver marvell_drivers[] = {
1890 {
2f495c39
BH		 1891 .phy_id = MARVELL_PHY_ID_88E1101,
1892 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 1893 .name = "Marvell 88E1101",
1894 .features = PHY_GBIT_FEATURES,
1895 .flags = PHY_HAS_INTERRUPT,
18702414 1896 .probe = marvell_probe,
79be1a1c 1897 .config_init = &marvell_config_init,
e5479239
OJ		 1898 .config_aneg = &marvell_config_aneg,
1899 .read_status = &genphy_read_status,
1900 .ack_interrupt = &marvell_ack_interrupt,
1901 .config_intr = &marvell_config_intr,
0898b448
SH		 1902 .resume = &genphy_resume,
1903 .suspend = &genphy_suspend,
d2fa47d9
AL		 1904 .get_sset_count = marvell_get_sset_count,
1905 .get_strings = marvell_get_strings,
1906 .get_stats = marvell_get_stats,
e5479239 1907 },
85cfb534 1908 {
2f495c39
BH		 1909 .phy_id = MARVELL_PHY_ID_88E1112,
1910 .phy_id_mask = MARVELL_PHY_ID_MASK,
85cfb534
OJ		 1911 .name = "Marvell 88E1112",
1912 .features = PHY_GBIT_FEATURES,
1913 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1914 .probe = marvell_probe,
85cfb534
OJ		 1915 .config_init = &m88e1111_config_init,
1916 .config_aneg = &marvell_config_aneg,
1917 .read_status = &genphy_read_status,
1918 .ack_interrupt = &marvell_ack_interrupt,
1919 .config_intr = &marvell_config_intr,
0898b448
SH		 1920 .resume = &genphy_resume,
1921 .suspend = &genphy_suspend,
d2fa47d9
AL		 1922 .get_sset_count = marvell_get_sset_count,
1923 .get_strings = marvell_get_strings,
1924 .get_stats = marvell_get_stats,
85cfb534 1925 },
e5479239 1926 {
2f495c39
BH		 1927 .phy_id = MARVELL_PHY_ID_88E1111,
1928 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 1929 .name = "Marvell 88E1111",
1930 .features = PHY_GBIT_FEATURES,
1931 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1932 .probe = marvell_probe,
e5479239 1933 .config_init = &m88e1111_config_init,
3ec0a0f1 1934 .config_aneg = &m88e1111_config_aneg,
be937f1f 1935 .read_status = &marvell_read_status,
e5479239
OJ		 1936 .ack_interrupt = &marvell_ack_interrupt,
1937 .config_intr = &marvell_config_intr,
0898b448
SH		 1938 .resume = &genphy_resume,
1939 .suspend = &genphy_suspend,
d2fa47d9
AL		 1940 .get_sset_count = marvell_get_sset_count,
1941 .get_strings = marvell_get_strings,
1942 .get_stats = marvell_get_stats,
e5479239 1943 },
605f196e 1944 {
2f495c39
BH		 1945 .phy_id = MARVELL_PHY_ID_88E1118,
1946 .phy_id_mask = MARVELL_PHY_ID_MASK,
605f196e
RM		 1947 .name = "Marvell 88E1118",
1948 .features = PHY_GBIT_FEATURES,
1949 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1950 .probe = marvell_probe,
605f196e
RM		 1951 .config_init = &m88e1118_config_init,
1952 .config_aneg = &m88e1118_config_aneg,
1953 .read_status = &genphy_read_status,
1954 .ack_interrupt = &marvell_ack_interrupt,
1955 .config_intr = &marvell_config_intr,
0898b448
SH		 1956 .resume = &genphy_resume,
1957 .suspend = &genphy_suspend,
d2fa47d9
AL		 1958 .get_sset_count = marvell_get_sset_count,
1959 .get_strings = marvell_get_strings,
1960 .get_stats = marvell_get_stats,
605f196e 1961 },
140bc929 1962 {
2f495c39
BH		 1963 .phy_id = MARVELL_PHY_ID_88E1121R,
1964 .phy_id_mask = MARVELL_PHY_ID_MASK,
140bc929
SP		 1965 .name = "Marvell 88E1121R",
1966 .features = PHY_GBIT_FEATURES,
1967 .flags = PHY_HAS_INTERRUPT,
18702414 1968 .probe = &m88e1121_probe,
fdecf36f 1969 .config_init = &m88e1121_config_init,
140bc929
SP		 1970 .config_aneg = &m88e1121_config_aneg,
1971 .read_status = &marvell_read_status,
1972 .ack_interrupt = &marvell_ack_interrupt,
1973 .config_intr = &marvell_config_intr,
dcd07be3 1974 .did_interrupt = &m88e1121_did_interrupt,
0898b448
SH		 1975 .resume = &genphy_resume,
1976 .suspend = &genphy_suspend,
d2fa47d9
AL		 1977 .get_sset_count = marvell_get_sset_count,
1978 .get_strings = marvell_get_strings,
1979 .get_stats = marvell_get_stats,
140bc929 1980 },
3ff1c259 1981 {
337ac9d5 1982 .phy_id = MARVELL_PHY_ID_88E1318S,
6ba74014 1983 .phy_id_mask = MARVELL_PHY_ID_MASK,
337ac9d5 1984 .name = "Marvell 88E1318S",
3ff1c259
CC		 1985 .features = PHY_GBIT_FEATURES,
1986 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1987 .probe = marvell_probe,
fdecf36f 1988 .config_init = &m88e1121_config_init,
337ac9d5 1989 .config_aneg = &m88e1318_config_aneg,
3ff1c259
CC		 1990 .read_status = &marvell_read_status,
1991 .ack_interrupt = &marvell_ack_interrupt,
1992 .config_intr = &marvell_config_intr,
1993 .did_interrupt = &m88e1121_did_interrupt,
3871c387
MS		 1994 .get_wol = &m88e1318_get_wol,
1995 .set_wol = &m88e1318_set_wol,
0898b448
SH		 1996 .resume = &genphy_resume,
1997 .suspend = &genphy_suspend,
d2fa47d9
AL		 1998 .get_sset_count = marvell_get_sset_count,
1999 .get_strings = marvell_get_strings,
2000 .get_stats = marvell_get_stats,
3ff1c259 2001 },
e5479239 2002 {
2f495c39
BH		 2003 .phy_id = MARVELL_PHY_ID_88E1145,
2004 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 2005 .name = "Marvell 88E1145",
2006 .features = PHY_GBIT_FEATURES,
2007 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 2008 .probe = marvell_probe,
e5479239
OJ		 2009 .config_init = &m88e1145_config_init,
2010 .config_aneg = &marvell_config_aneg,
2011 .read_status = &genphy_read_status,
2012 .ack_interrupt = &marvell_ack_interrupt,
2013 .config_intr = &marvell_config_intr,
0898b448
SH		 2014 .resume = &genphy_resume,
2015 .suspend = &genphy_suspend,
d2fa47d9
AL		 2016 .get_sset_count = marvell_get_sset_count,
2017 .get_strings = marvell_get_strings,
2018 .get_stats = marvell_get_stats,
ac8c635a 2019 },
90600732
DD		 2020 {
2021 .phy_id = MARVELL_PHY_ID_88E1149R,
2022 .phy_id_mask = MARVELL_PHY_ID_MASK,
2023 .name = "Marvell 88E1149R",
2024 .features = PHY_GBIT_FEATURES,
2025 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 2026 .probe = marvell_probe,
90600732
DD		 2027 .config_init = &m88e1149_config_init,
2028 .config_aneg = &m88e1118_config_aneg,
2029 .read_status = &genphy_read_status,
2030 .ack_interrupt = &marvell_ack_interrupt,
2031 .config_intr = &marvell_config_intr,
0898b448
SH		 2032 .resume = &genphy_resume,
2033 .suspend = &genphy_suspend,
d2fa47d9
AL		 2034 .get_sset_count = marvell_get_sset_count,
2035 .get_strings = marvell_get_strings,
2036 .get_stats = marvell_get_stats,
90600732 2037 },
ac8c635a 2038 {
2f495c39
BH		 2039 .phy_id = MARVELL_PHY_ID_88E1240,
2040 .phy_id_mask = MARVELL_PHY_ID_MASK,
ac8c635a
OJ		 2041 .name = "Marvell 88E1240",
2042 .features = PHY_GBIT_FEATURES,
2043 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 2044 .probe = marvell_probe,
ac8c635a
OJ		 2045 .config_init = &m88e1111_config_init,
2046 .config_aneg = &marvell_config_aneg,
2047 .read_status = &genphy_read_status,
2048 .ack_interrupt = &marvell_ack_interrupt,
2049 .config_intr = &marvell_config_intr,
0898b448
SH		 2050 .resume = &genphy_resume,
2051 .suspend = &genphy_suspend,
d2fa47d9
AL		 2052 .get_sset_count = marvell_get_sset_count,
2053 .get_strings = marvell_get_strings,
2054 .get_stats = marvell_get_stats,
ac8c635a 2055 },
3da09a51
MS		 2056 {
2057 .phy_id = MARVELL_PHY_ID_88E1116R,
2058 .phy_id_mask = MARVELL_PHY_ID_MASK,
2059 .name = "Marvell 88E1116R",
2060 .features = PHY_GBIT_FEATURES,
2061 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 2062 .probe = marvell_probe,
3da09a51
MS		 2063 .config_init = &m88e1116r_config_init,
2064 .config_aneg = &genphy_config_aneg,
2065 .read_status = &genphy_read_status,
2066 .ack_interrupt = &marvell_ack_interrupt,
2067 .config_intr = &marvell_config_intr,
0898b448
SH		 2068 .resume = &genphy_resume,
2069 .suspend = &genphy_suspend,
d2fa47d9
AL		 2070 .get_sset_count = marvell_get_sset_count,
2071 .get_strings = marvell_get_strings,
2072 .get_stats = marvell_get_stats,
3da09a51 2073 },
10e24caa
MS		 2074 {
2075 .phy_id = MARVELL_PHY_ID_88E1510,
2076 .phy_id_mask = MARVELL_PHY_ID_MASK,
2077 .name = "Marvell 88E1510",
6cfb3bcc 2078 .features = PHY_GBIT_FEATURES | SUPPORTED_FIBRE,
18702414 2079 .flags = PHY_HAS_INTERRUPT,
0b04680f 2080 .probe = &m88e1510_probe,
930b37ee 2081 .config_init = &m88e1510_config_init,
10e24caa
MS		 2082 .config_aneg = &m88e1510_config_aneg,
2083 .read_status = &marvell_read_status,
2084 .ack_interrupt = &marvell_ack_interrupt,
2085 .config_intr = &marvell_config_intr,
2086 .did_interrupt = &m88e1121_did_interrupt,
f39aac7e
JH		 2087 .get_wol = &m88e1318_get_wol,
2088 .set_wol = &m88e1318_set_wol,
3758be3d
CAC		 2089 .resume = &marvell_resume,
2090 .suspend = &marvell_suspend,
d2fa47d9
AL		 2091 .get_sset_count = marvell_get_sset_count,
2092 .get_strings = marvell_get_strings,
2093 .get_stats = marvell_get_stats,
10e24caa 2094 },
819ec8e1
AL		 2095 {
2096 .phy_id = MARVELL_PHY_ID_88E1540,
2097 .phy_id_mask = MARVELL_PHY_ID_MASK,
2098 .name = "Marvell 88E1540",
2099 .features = PHY_GBIT_FEATURES,
2100 .flags = PHY_HAS_INTERRUPT,
18702414 2101 .probe = m88e1510_probe,
79be1a1c 2102 .config_init = &marvell_config_init,
819ec8e1
AL		 2103 .config_aneg = &m88e1510_config_aneg,
2104 .read_status = &marvell_read_status,
2105 .ack_interrupt = &marvell_ack_interrupt,
2106 .config_intr = &marvell_config_intr,
2107 .did_interrupt = &m88e1121_did_interrupt,
2108 .resume = &genphy_resume,
2109 .suspend = &genphy_suspend,
d2fa47d9
AL		 2110 .get_sset_count = marvell_get_sset_count,
2111 .get_strings = marvell_get_strings,
2112 .get_stats = marvell_get_stats,
819ec8e1 2113 },
60f06fde
AL		 2114 {
2115 .phy_id = MARVELL_PHY_ID_88E1545,
2116 .phy_id_mask = MARVELL_PHY_ID_MASK,
2117 .name = "Marvell 88E1545",
2118 .probe = m88e1510_probe,
60f06fde
AL		 2119 .features = PHY_GBIT_FEATURES,
2120 .flags = PHY_HAS_INTERRUPT,
2121 .config_init = &marvell_config_init,
2122 .config_aneg = &m88e1510_config_aneg,
2123 .read_status = &marvell_read_status,
2124 .ack_interrupt = &marvell_ack_interrupt,
2125 .config_intr = &marvell_config_intr,
2126 .did_interrupt = &m88e1121_did_interrupt,
2127 .resume = &genphy_resume,
2128 .suspend = &genphy_suspend,
2129 .get_sset_count = marvell_get_sset_count,
2130 .get_strings = marvell_get_strings,
2131 .get_stats = marvell_get_stats,
2132 },
6b358aed
SH		 2133 {
2134 .phy_id = MARVELL_PHY_ID_88E3016,
2135 .phy_id_mask = MARVELL_PHY_ID_MASK,
2136 .name = "Marvell 88E3016",
2137 .features = PHY_BASIC_FEATURES,
2138 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 2139 .probe = marvell_probe,
6b358aed
SH		 2140 .config_aneg = &genphy_config_aneg,
2141 .config_init = &m88e3016_config_init,
2142 .aneg_done = &marvell_aneg_done,
2143 .read_status = &marvell_read_status,
2144 .ack_interrupt = &marvell_ack_interrupt,
2145 .config_intr = &marvell_config_intr,
2146 .did_interrupt = &m88e1121_did_interrupt,
2147 .resume = &genphy_resume,
2148 .suspend = &genphy_suspend,
d2fa47d9
AL		 2149 .get_sset_count = marvell_get_sset_count,
2150 .get_strings = marvell_get_strings,
2151 .get_stats = marvell_get_stats,
6b358aed 2152 },
e4cf8a38
AL		 2153 {
2154 .phy_id = MARVELL_PHY_ID_88E6390,
2155 .phy_id_mask = MARVELL_PHY_ID_MASK,
2156 .name = "Marvell 88E6390",
2157 .features = PHY_GBIT_FEATURES,
2158 .flags = PHY_HAS_INTERRUPT,
2159 .probe = m88e1510_probe,
2160 .config_init = &marvell_config_init,
2161 .config_aneg = &m88e1510_config_aneg,
2162 .read_status = &marvell_read_status,
2163 .ack_interrupt = &marvell_ack_interrupt,
2164 .config_intr = &marvell_config_intr,
2165 .did_interrupt = &m88e1121_did_interrupt,
2166 .resume = &genphy_resume,
2167 .suspend = &genphy_suspend,
2168 .get_sset_count = marvell_get_sset_count,
2169 .get_strings = marvell_get_strings,
2170 .get_stats = marvell_get_stats,
2171 },
00db8189
AF		 2172};
2173
50fd7150 2174module_phy_driver(marvell_drivers);
4e4f10f6 2175
cf93c945 2176static struct mdio_device_id __maybe_unused marvell_tbl[] = {
f5e1cabf
MS		 2177 { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
2178 { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
2179 { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
2180 { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
2181 { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
2182 { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
2183 { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
2184 { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
2185 { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
3da09a51 2186 { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
10e24caa 2187 { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
819ec8e1 2188 { MARVELL_PHY_ID_88E1540, MARVELL_PHY_ID_MASK },
60f06fde 2189 { MARVELL_PHY_ID_88E1545, MARVELL_PHY_ID_MASK },
6b358aed 2190 { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
e4cf8a38 2191 { MARVELL_PHY_ID_88E6390, MARVELL_PHY_ID_MASK },
4e4f10f6
DW		 2192 { }
2193};
2194
2195MODULE_DEVICE_TABLE(mdio, marvell_tbl);
Michael's Linux tree.