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net: phy: Pass mdix ethtool setting through to phy driver
[people/ms/linux.git] / drivers / net / phy / marvell.c
CommitLineData
00db8189
AF		 1/*
2 * drivers/net/phy/marvell.c
3 *
4 * Driver for Marvell PHYs
5 *
6 * Author: Andy Fleming
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
9 *
3871c387
MS		 10 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
11 *
00db8189
AF		 12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 */
00db8189 18#include <linux/kernel.h>
00db8189
AF		 19#include <linux/string.h>
20#include <linux/errno.h>
21#include <linux/unistd.h>
00db8189
AF		 22#include <linux/interrupt.h>
23#include <linux/init.h>
24#include <linux/delay.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/skbuff.h>
28#include <linux/spinlock.h>
29#include <linux/mm.h>
30#include <linux/module.h>
00db8189
AF		 31#include <linux/mii.h>
32#include <linux/ethtool.h>
33#include <linux/phy.h>
2f495c39 34#include <linux/marvell_phy.h>
cf41a51d 35#include <linux/of.h>
00db8189 36
eea3b201 37#include <linux/io.h>
00db8189 38#include <asm/irq.h>
eea3b201 39#include <linux/uaccess.h>
00db8189 40
27d916d6
DD		 41#define MII_MARVELL_PHY_PAGE 22
42
00db8189
AF		 43#define MII_M1011_IEVENT 0x13
44#define MII_M1011_IEVENT_CLEAR 0x0000
45
46#define MII_M1011_IMASK 0x12
47#define MII_M1011_IMASK_INIT 0x6400
48#define MII_M1011_IMASK_CLEAR 0x0000
49
76884679
AF		 50#define MII_M1011_PHY_SCR 0x10
51#define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
52
b0224175 53#define MII_M1145_PHY_EXT_SR 0x1b
76884679
AF		 54#define MII_M1145_PHY_EXT_CR 0x14
55#define MII_M1145_RGMII_RX_DELAY 0x0080
56#define MII_M1145_RGMII_TX_DELAY 0x0002
b0224175
VND		 57#define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
58#define MII_M1145_HWCFG_MODE_MASK 0xf
59#define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
76884679 60
99d881f9
VB		 61#define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
62#define MII_M1145_HWCFG_MODE_MASK 0xf
63#define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
64
76884679
AF		 65#define MII_M1111_PHY_LED_CONTROL 0x18
66#define MII_M1111_PHY_LED_DIRECT 0x4100
67#define MII_M1111_PHY_LED_COMBINE 0x411c
895ee682
KP		 68#define MII_M1111_PHY_EXT_CR 0x14
69#define MII_M1111_RX_DELAY 0x80
70#define MII_M1111_TX_DELAY 0x2
71#define MII_M1111_PHY_EXT_SR 0x1b
be937f1f
AS		 72
73#define MII_M1111_HWCFG_MODE_MASK 0xf
74#define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
75#define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
4117b5be 76#define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
5f8cbc13 77#define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
be937f1f
AS		 78#define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
79#define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
80
81#define MII_M1111_COPPER 0
82#define MII_M1111_FIBER 1
83
c477d044
CC		 84#define MII_88E1121_PHY_MSCR_PAGE 2
85#define MII_88E1121_PHY_MSCR_REG 21
86#define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
87#define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
88#define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
89
337ac9d5
CC		 90#define MII_88E1318S_PHY_MSCR1_REG 16
91#define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
3ff1c259 92
3871c387
MS		 93/* Copper Specific Interrupt Enable Register */
94#define MII_88E1318S_PHY_CSIER 0x12
95/* WOL Event Interrupt Enable */
96#define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
97
98/* LED Timer Control Register */
99#define MII_88E1318S_PHY_LED_PAGE 0x03
100#define MII_88E1318S_PHY_LED_TCR 0x12
101#define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
102#define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
103#define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
104
105/* Magic Packet MAC address registers */
106#define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
107#define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
108#define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
109
110#define MII_88E1318S_PHY_WOL_PAGE 0x11
111#define MII_88E1318S_PHY_WOL_CTRL 0x10
112#define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
113#define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
114
140bc929
SP		 115#define MII_88E1121_PHY_LED_CTRL 16
116#define MII_88E1121_PHY_LED_PAGE 3
117#define MII_88E1121_PHY_LED_DEF 0x0030
140bc929 118
be937f1f
AS		 119#define MII_M1011_PHY_STATUS 0x11
120#define MII_M1011_PHY_STATUS_1000 0x8000
121#define MII_M1011_PHY_STATUS_100 0x4000
122#define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
123#define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
124#define MII_M1011_PHY_STATUS_RESOLVED 0x0800
125#define MII_M1011_PHY_STATUS_LINK 0x0400
126
3da09a51
MS		 127#define MII_M1116R_CONTROL_REG_MAC 21
128
6b358aed
SH		 129#define MII_88E3016_PHY_SPEC_CTRL 0x10
130#define MII_88E3016_DISABLE_SCRAMBLER 0x0200
131#define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
76884679 132
00db8189
AF		 133MODULE_DESCRIPTION("Marvell PHY driver");
134MODULE_AUTHOR("Andy Fleming");
135MODULE_LICENSE("GPL");
136
137static int marvell_ack_interrupt(struct phy_device *phydev)
138{
139 int err;
140
141 /* Clear the interrupts by reading the reg */
142 err = phy_read(phydev, MII_M1011_IEVENT);
143
144 if (err < 0)
145 return err;
146
147 return 0;
148}
149
150static int marvell_config_intr(struct phy_device *phydev)
151{
152 int err;
153
76884679 154 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
00db8189
AF		 155 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
156 else
157 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
158
159 return err;
160}
161
162static int marvell_config_aneg(struct phy_device *phydev)
163{
164 int err;
165
166 /* The Marvell PHY has an errata which requires
167 * that certain registers get written in order
168 * to restart autonegotiation */
169 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
170
171 if (err < 0)
172 return err;
173
174 err = phy_write(phydev, 0x1d, 0x1f);
175 if (err < 0)
176 return err;
177
178 err = phy_write(phydev, 0x1e, 0x200c);
179 if (err < 0)
180 return err;
181
182 err = phy_write(phydev, 0x1d, 0x5);
183 if (err < 0)
184 return err;
185
186 err = phy_write(phydev, 0x1e, 0);
187 if (err < 0)
188 return err;
189
190 err = phy_write(phydev, 0x1e, 0x100);
191 if (err < 0)
192 return err;
193
76884679
AF		 194 err = phy_write(phydev, MII_M1011_PHY_SCR,
195 MII_M1011_PHY_SCR_AUTO_CROSS);
196 if (err < 0)
197 return err;
198
199 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
200 MII_M1111_PHY_LED_DIRECT);
201 if (err < 0)
202 return err;
00db8189
AF		 203
204 err = genphy_config_aneg(phydev);
8ff44985
AV		 205 if (err < 0)
206 return err;
00db8189 207
8ff44985
AV		 208 if (phydev->autoneg != AUTONEG_ENABLE) {
209 int bmcr;
210
211 /*
212 * A write to speed/duplex bits (that is performed by
213 * genphy_config_aneg() call above) must be followed by
214 * a software reset. Otherwise, the write has no effect.
215 */
216 bmcr = phy_read(phydev, MII_BMCR);
217 if (bmcr < 0)
218 return bmcr;
219
220 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
221 if (err < 0)
222 return err;
223 }
224
225 return 0;
00db8189
AF		 226}
227
cf41a51d
DD		 228#ifdef CONFIG_OF_MDIO
229/*
230 * Set and/or override some configuration registers based on the
231 * marvell,reg-init property stored in the of_node for the phydev.
232 *
233 * marvell,reg-init = <reg-page reg mask value>,...;
234 *
235 * There may be one or more sets of <reg-page reg mask value>:
236 *
237 * reg-page: which register bank to use.
238 * reg: the register.
239 * mask: if non-zero, ANDed with existing register value.
240 * value: ORed with the masked value and written to the regiser.
241 *
242 */
243static int marvell_of_reg_init(struct phy_device *phydev)
244{
245 const __be32 *paddr;
246 int len, i, saved_page, current_page, page_changed, ret;
247
248 if (!phydev->dev.of_node)
249 return 0;
250
251 paddr = of_get_property(phydev->dev.of_node, "marvell,reg-init", &len);
252 if (!paddr || len < (4 * sizeof(*paddr)))
253 return 0;
254
255 saved_page = phy_read(phydev, MII_MARVELL_PHY_PAGE);
256 if (saved_page < 0)
257 return saved_page;
258 page_changed = 0;
259 current_page = saved_page;
260
261 ret = 0;
262 len /= sizeof(*paddr);
263 for (i = 0; i < len - 3; i += 4) {
264 u16 reg_page = be32_to_cpup(paddr + i);
265 u16 reg = be32_to_cpup(paddr + i + 1);
266 u16 mask = be32_to_cpup(paddr + i + 2);
267 u16 val_bits = be32_to_cpup(paddr + i + 3);
268 int val;
269
270 if (reg_page != current_page) {
271 current_page = reg_page;
272 page_changed = 1;
273 ret = phy_write(phydev, MII_MARVELL_PHY_PAGE, reg_page);
274 if (ret < 0)
275 goto err;
276 }
277
278 val = 0;
279 if (mask) {
280 val = phy_read(phydev, reg);
281 if (val < 0) {
282 ret = val;
283 goto err;
284 }
285 val &= mask;
286 }
287 val |= val_bits;
288
289 ret = phy_write(phydev, reg, val);
290 if (ret < 0)
291 goto err;
292
293 }
294err:
295 if (page_changed) {
296 i = phy_write(phydev, MII_MARVELL_PHY_PAGE, saved_page);
297 if (ret == 0)
298 ret = i;
299 }
300 return ret;
301}
302#else
303static int marvell_of_reg_init(struct phy_device *phydev)
304{
305 return 0;
306}
307#endif /* CONFIG_OF_MDIO */
308
140bc929
SP		 309static int m88e1121_config_aneg(struct phy_device *phydev)
310{
c477d044
CC		 311 int err, oldpage, mscr;
312
27d916d6 313 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
c477d044 314
27d916d6 315 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
c477d044
CC		 316 MII_88E1121_PHY_MSCR_PAGE);
317 if (err < 0)
318 return err;
be8c6480 319
32a64161 320 if (phy_interface_is_rgmii(phydev)) {
be8c6480
AP		 321
322 mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) &
323 MII_88E1121_PHY_MSCR_DELAY_MASK;
324
325 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
326 mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY |
327 MII_88E1121_PHY_MSCR_TX_DELAY);
328 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
329 mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
330 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
331 mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
332
333 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
334 if (err < 0)
335 return err;
336 }
c477d044 337
27d916d6 338 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
140bc929
SP		 339
340 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
341 if (err < 0)
342 return err;
343
344 err = phy_write(phydev, MII_M1011_PHY_SCR,
345 MII_M1011_PHY_SCR_AUTO_CROSS);
346 if (err < 0)
347 return err;
348
27d916d6 349 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
140bc929 350
27d916d6 351 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
140bc929 352 phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF);
27d916d6 353 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
140bc929
SP		 354
355 err = genphy_config_aneg(phydev);
356
357 return err;
358}
359
337ac9d5 360static int m88e1318_config_aneg(struct phy_device *phydev)
3ff1c259
CC		 361{
362 int err, oldpage, mscr;
363
27d916d6 364 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
3ff1c259 365
27d916d6 366 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
3ff1c259
CC		 367 MII_88E1121_PHY_MSCR_PAGE);
368 if (err < 0)
369 return err;
370
337ac9d5
CC		 371 mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG);
372 mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD;
3ff1c259 373
337ac9d5 374 err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr);
3ff1c259
CC		 375 if (err < 0)
376 return err;
377
27d916d6 378 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
3ff1c259
CC		 379 if (err < 0)
380 return err;
381
382 return m88e1121_config_aneg(phydev);
383}
384
10e24caa
MS		 385static int m88e1510_config_aneg(struct phy_device *phydev)
386{
387 int err;
388
389 err = m88e1318_config_aneg(phydev);
390 if (err < 0)
391 return err;
392
393 return marvell_of_reg_init(phydev);
394}
395
3da09a51
MS		 396static int m88e1116r_config_init(struct phy_device *phydev)
397{
398 int temp;
399 int err;
400
401 temp = phy_read(phydev, MII_BMCR);
402 temp |= BMCR_RESET;
403 err = phy_write(phydev, MII_BMCR, temp);
404 if (err < 0)
405 return err;
406
407 mdelay(500);
408
409 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
410 if (err < 0)
411 return err;
412
413 temp = phy_read(phydev, MII_M1011_PHY_SCR);
414 temp |= (7 << 12); /* max number of gigabit attempts */
415 temp |= (1 << 11); /* enable downshift */
416 temp |= MII_M1011_PHY_SCR_AUTO_CROSS;
417 err = phy_write(phydev, MII_M1011_PHY_SCR, temp);
418 if (err < 0)
419 return err;
420
421 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 2);
422 if (err < 0)
423 return err;
424 temp = phy_read(phydev, MII_M1116R_CONTROL_REG_MAC);
425 temp |= (1 << 5);
426 temp |= (1 << 4);
427 err = phy_write(phydev, MII_M1116R_CONTROL_REG_MAC, temp);
428 if (err < 0)
429 return err;
430 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
431 if (err < 0)
432 return err;
433
434 temp = phy_read(phydev, MII_BMCR);
435 temp |= BMCR_RESET;
436 err = phy_write(phydev, MII_BMCR, temp);
437 if (err < 0)
438 return err;
439
440 mdelay(500);
441
442 return 0;
443}
444
6b358aed
SH		 445static int m88e3016_config_init(struct phy_device *phydev)
446{
447 int reg;
448
449 /* Enable Scrambler and Auto-Crossover */
450 reg = phy_read(phydev, MII_88E3016_PHY_SPEC_CTRL);
451 if (reg < 0)
452 return reg;
453
454 reg &= ~MII_88E3016_DISABLE_SCRAMBLER;
455 reg |= MII_88E3016_AUTO_MDIX_CROSSOVER;
456
457 reg = phy_write(phydev, MII_88E3016_PHY_SPEC_CTRL, reg);
458 if (reg < 0)
459 return reg;
460
461 return 0;
462}
463
895ee682
KP		 464static int m88e1111_config_init(struct phy_device *phydev)
465{
466 int err;
be937f1f 467 int temp;
be937f1f 468
32a64161 469 if (phy_interface_is_rgmii(phydev)) {
895ee682 470
9daf5a76
KP		 471 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
472 if (temp < 0)
473 return temp;
895ee682 474
9daf5a76 475 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
895ee682 476 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
9daf5a76
KP		 477 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
478 temp &= ~MII_M1111_TX_DELAY;
479 temp |= MII_M1111_RX_DELAY;
480 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
481 temp &= ~MII_M1111_RX_DELAY;
482 temp |= MII_M1111_TX_DELAY;
895ee682
KP		 483 }
484
9daf5a76
KP		 485 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
486 if (err < 0)
487 return err;
488
895ee682
KP		 489 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
490 if (temp < 0)
491 return temp;
492
493 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
be937f1f 494
7239016d 495 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
be937f1f
AS		 496 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
497 else
498 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
895ee682
KP		 499
500 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
501 if (err < 0)
502 return err;
503 }
504
4117b5be 505 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
4117b5be
KJ		 506 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
507 if (temp < 0)
508 return temp;
509
510 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
511 temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
32d0c1e1 512 temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
4117b5be
KJ		 513
514 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
515 if (err < 0)
516 return err;
517 }
518
5f8cbc13
LYB		 519 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
520 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
521 if (temp < 0)
522 return temp;
523 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
524 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
525 if (err < 0)
526 return err;
527
528 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
529 if (temp < 0)
530 return temp;
531 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
532 temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
533 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
534 if (err < 0)
535 return err;
536
537 /* soft reset */
538 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
539 if (err < 0)
540 return err;
541 do
542 temp = phy_read(phydev, MII_BMCR);
543 while (temp & BMCR_RESET);
544
545 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
546 if (temp < 0)
547 return temp;
548 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
549 temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
550 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
551 if (err < 0)
552 return err;
553 }
554
cf41a51d
DD		 555 err = marvell_of_reg_init(phydev);
556 if (err < 0)
557 return err;
5f8cbc13 558
cc90cb3b 559 return phy_write(phydev, MII_BMCR, BMCR_RESET);
895ee682
KP		 560}
561
605f196e
RM		 562static int m88e1118_config_aneg(struct phy_device *phydev)
563{
564 int err;
565
566 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
567 if (err < 0)
568 return err;
569
570 err = phy_write(phydev, MII_M1011_PHY_SCR,
571 MII_M1011_PHY_SCR_AUTO_CROSS);
572 if (err < 0)
573 return err;
574
575 err = genphy_config_aneg(phydev);
576 return 0;
577}
578
579static int m88e1118_config_init(struct phy_device *phydev)
580{
581 int err;
582
583 /* Change address */
27d916d6 584 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
605f196e
RM		 585 if (err < 0)
586 return err;
587
588 /* Enable 1000 Mbit */
589 err = phy_write(phydev, 0x15, 0x1070);
590 if (err < 0)
591 return err;
592
593 /* Change address */
27d916d6 594 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0003);
605f196e
RM		 595 if (err < 0)
596 return err;
597
598 /* Adjust LED Control */
2f495c39
BH		 599 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
600 err = phy_write(phydev, 0x10, 0x1100);
601 else
602 err = phy_write(phydev, 0x10, 0x021e);
605f196e
RM		 603 if (err < 0)
604 return err;
605
cf41a51d
DD		 606 err = marvell_of_reg_init(phydev);
607 if (err < 0)
608 return err;
609
605f196e 610 /* Reset address */
27d916d6 611 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
605f196e
RM		 612 if (err < 0)
613 return err;
614
cc90cb3b 615 return phy_write(phydev, MII_BMCR, BMCR_RESET);
605f196e
RM		 616}
617
90600732
DD		 618static int m88e1149_config_init(struct phy_device *phydev)
619{
620 int err;
621
622 /* Change address */
623 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
624 if (err < 0)
625 return err;
626
627 /* Enable 1000 Mbit */
628 err = phy_write(phydev, 0x15, 0x1048);
629 if (err < 0)
630 return err;
631
cf41a51d
DD		 632 err = marvell_of_reg_init(phydev);
633 if (err < 0)
634 return err;
635
90600732
DD		 636 /* Reset address */
637 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
638 if (err < 0)
639 return err;
640
cc90cb3b 641 return phy_write(phydev, MII_BMCR, BMCR_RESET);
90600732
DD		 642}
643
76884679
AF		 644static int m88e1145_config_init(struct phy_device *phydev)
645{
646 int err;
b0224175 647 int temp;
76884679
AF		 648
649 /* Take care of errata E0 & E1 */
650 err = phy_write(phydev, 0x1d, 0x001b);
651 if (err < 0)
652 return err;
653
654 err = phy_write(phydev, 0x1e, 0x418f);
655 if (err < 0)
656 return err;
657
658 err = phy_write(phydev, 0x1d, 0x0016);
659 if (err < 0)
660 return err;
661
662 err = phy_write(phydev, 0x1e, 0xa2da);
663 if (err < 0)
664 return err;
665
895ee682 666 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
76884679
AF		 667 int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
668 if (temp < 0)
669 return temp;
670
671 temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
672
673 err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
674 if (err < 0)
675 return err;
676
2f495c39 677 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
76884679
AF		 678 err = phy_write(phydev, 0x1d, 0x0012);
679 if (err < 0)
680 return err;
681
682 temp = phy_read(phydev, 0x1e);
683 if (temp < 0)
684 return temp;
685
686 temp &= 0xf03f;
687 temp |= 2 << 9; /* 36 ohm */
688 temp |= 2 << 6; /* 39 ohm */
689
690 err = phy_write(phydev, 0x1e, temp);
691 if (err < 0)
692 return err;
693
694 err = phy_write(phydev, 0x1d, 0x3);
695 if (err < 0)
696 return err;
697
698 err = phy_write(phydev, 0x1e, 0x8000);
699 if (err < 0)
700 return err;
701 }
702 }
703
b0224175
VND		 704 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
705 temp = phy_read(phydev, MII_M1145_PHY_EXT_SR);
706 if (temp < 0)
707 return temp;
708
99d881f9 709 temp &= ~MII_M1145_HWCFG_MODE_MASK;
b0224175
VND		 710 temp |= MII_M1145_HWCFG_MODE_SGMII_NO_CLK;
711 temp |= MII_M1145_HWCFG_FIBER_COPPER_AUTO;
712
713 err = phy_write(phydev, MII_M1145_PHY_EXT_SR, temp);
714 if (err < 0)
715 return err;
716 }
717
cf41a51d
DD		 718 err = marvell_of_reg_init(phydev);
719 if (err < 0)
720 return err;
721
76884679
AF		 722 return 0;
723}
00db8189 724
be937f1f
AS		 725/* marvell_read_status
726 *
727 * Generic status code does not detect Fiber correctly!
f0c88f9c 728 * Description:
be937f1f
AS		 729 * Check the link, then figure out the current state
730 * by comparing what we advertise with what the link partner
731 * advertises. Start by checking the gigabit possibilities,
732 * then move on to 10/100.
733 */
734static int marvell_read_status(struct phy_device *phydev)
735{
736 int adv;
737 int err;
738 int lpa;
739 int status = 0;
740
741 /* Update the link, but return if there
742 * was an error */
743 err = genphy_update_link(phydev);
744 if (err)
745 return err;
746
747 if (AUTONEG_ENABLE == phydev->autoneg) {
748 status = phy_read(phydev, MII_M1011_PHY_STATUS);
749 if (status < 0)
750 return status;
751
752 lpa = phy_read(phydev, MII_LPA);
753 if (lpa < 0)
754 return lpa;
755
756 adv = phy_read(phydev, MII_ADVERTISE);
757 if (adv < 0)
758 return adv;
759
760 lpa &= adv;
761
762 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
763 phydev->duplex = DUPLEX_FULL;
764 else
765 phydev->duplex = DUPLEX_HALF;
766
767 status = status & MII_M1011_PHY_STATUS_SPD_MASK;
768 phydev->pause = phydev->asym_pause = 0;
769
770 switch (status) {
771 case MII_M1011_PHY_STATUS_1000:
772 phydev->speed = SPEED_1000;
773 break;
774
775 case MII_M1011_PHY_STATUS_100:
776 phydev->speed = SPEED_100;
777 break;
778
779 default:
780 phydev->speed = SPEED_10;
781 break;
782 }
783
784 if (phydev->duplex == DUPLEX_FULL) {
785 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
786 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
787 }
788 } else {
789 int bmcr = phy_read(phydev, MII_BMCR);
790
791 if (bmcr < 0)
792 return bmcr;
793
794 if (bmcr & BMCR_FULLDPLX)
795 phydev->duplex = DUPLEX_FULL;
796 else
797 phydev->duplex = DUPLEX_HALF;
798
799 if (bmcr & BMCR_SPEED1000)
800 phydev->speed = SPEED_1000;
801 else if (bmcr & BMCR_SPEED100)
802 phydev->speed = SPEED_100;
803 else
804 phydev->speed = SPEED_10;
805
806 phydev->pause = phydev->asym_pause = 0;
807 }
808
809 return 0;
810}
811
6b358aed
SH		 812static int marvell_aneg_done(struct phy_device *phydev)
813{
814 int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
815 return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
816}
817
dcd07be3
AG		 818static int m88e1121_did_interrupt(struct phy_device *phydev)
819{
820 int imask;
821
822 imask = phy_read(phydev, MII_M1011_IEVENT);
823
824 if (imask & MII_M1011_IMASK_INIT)
825 return 1;
826
827 return 0;
828}
829
3871c387
MS		 830static void m88e1318_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
831{
832 wol->supported = WAKE_MAGIC;
833 wol->wolopts = 0;
834
835 if (phy_write(phydev, MII_MARVELL_PHY_PAGE,
836 MII_88E1318S_PHY_WOL_PAGE) < 0)
837 return;
838
839 if (phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL) &
840 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
841 wol->wolopts |= WAKE_MAGIC;
842
843 if (phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00) < 0)
844 return;
845}
846
847static int m88e1318_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
848{
849 int err, oldpage, temp;
850
851 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
852
853 if (wol->wolopts & WAKE_MAGIC) {
854 /* Explicitly switch to page 0x00, just to be sure */
855 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00);
856 if (err < 0)
857 return err;
858
859 /* Enable the WOL interrupt */
860 temp = phy_read(phydev, MII_88E1318S_PHY_CSIER);
861 temp |= MII_88E1318S_PHY_CSIER_WOL_EIE;
862 err = phy_write(phydev, MII_88E1318S_PHY_CSIER, temp);
863 if (err < 0)
864 return err;
865
866 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
867 MII_88E1318S_PHY_LED_PAGE);
868 if (err < 0)
869 return err;
870
871 /* Setup LED[2] as interrupt pin (active low) */
872 temp = phy_read(phydev, MII_88E1318S_PHY_LED_TCR);
873 temp &= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT;
874 temp |= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE;
875 temp |= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW;
876 err = phy_write(phydev, MII_88E1318S_PHY_LED_TCR, temp);
877 if (err < 0)
878 return err;
879
880 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
881 MII_88E1318S_PHY_WOL_PAGE);
882 if (err < 0)
883 return err;
884
885 /* Store the device address for the magic packet */
886 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
887 ((phydev->attached_dev->dev_addr[5] << 8) |
888 phydev->attached_dev->dev_addr[4]));
889 if (err < 0)
890 return err;
891 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
892 ((phydev->attached_dev->dev_addr[3] << 8) |
893 phydev->attached_dev->dev_addr[2]));
894 if (err < 0)
895 return err;
896 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
897 ((phydev->attached_dev->dev_addr[1] << 8) |
898 phydev->attached_dev->dev_addr[0]));
899 if (err < 0)
900 return err;
901
902 /* Clear WOL status and enable magic packet matching */
903 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
904 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
905 temp |= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
906 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
907 if (err < 0)
908 return err;
909 } else {
910 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
911 MII_88E1318S_PHY_WOL_PAGE);
912 if (err < 0)
913 return err;
914
915 /* Clear WOL status and disable magic packet matching */
916 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
917 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
918 temp &= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
919 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
920 if (err < 0)
921 return err;
922 }
923
924 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
925 if (err < 0)
926 return err;
927
928 return 0;
929}
930
e5479239
OJ		 931static struct phy_driver marvell_drivers[] = {
932 {
2f495c39
BH		 933 .phy_id = MARVELL_PHY_ID_88E1101,
934 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 935 .name = "Marvell 88E1101",
936 .features = PHY_GBIT_FEATURES,
937 .flags = PHY_HAS_INTERRUPT,
938 .config_aneg = &marvell_config_aneg,
939 .read_status = &genphy_read_status,
940 .ack_interrupt = &marvell_ack_interrupt,
941 .config_intr = &marvell_config_intr,
0898b448
SH		 942 .resume = &genphy_resume,
943 .suspend = &genphy_suspend,
ac8c635a 944 .driver = { .owner = THIS_MODULE },
e5479239 945 },
85cfb534 946 {
2f495c39
BH		 947 .phy_id = MARVELL_PHY_ID_88E1112,
948 .phy_id_mask = MARVELL_PHY_ID_MASK,
85cfb534
OJ		 949 .name = "Marvell 88E1112",
950 .features = PHY_GBIT_FEATURES,
951 .flags = PHY_HAS_INTERRUPT,
952 .config_init = &m88e1111_config_init,
953 .config_aneg = &marvell_config_aneg,
954 .read_status = &genphy_read_status,
955 .ack_interrupt = &marvell_ack_interrupt,
956 .config_intr = &marvell_config_intr,
0898b448
SH		 957 .resume = &genphy_resume,
958 .suspend = &genphy_suspend,
ac8c635a 959 .driver = { .owner = THIS_MODULE },
85cfb534 960 },
e5479239 961 {
2f495c39
BH		 962 .phy_id = MARVELL_PHY_ID_88E1111,
963 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 964 .name = "Marvell 88E1111",
965 .features = PHY_GBIT_FEATURES,
966 .flags = PHY_HAS_INTERRUPT,
967 .config_init = &m88e1111_config_init,
968 .config_aneg = &marvell_config_aneg,
be937f1f 969 .read_status = &marvell_read_status,
e5479239
OJ		 970 .ack_interrupt = &marvell_ack_interrupt,
971 .config_intr = &marvell_config_intr,
0898b448
SH		 972 .resume = &genphy_resume,
973 .suspend = &genphy_suspend,
ac8c635a 974 .driver = { .owner = THIS_MODULE },
e5479239 975 },
605f196e 976 {
2f495c39
BH		 977 .phy_id = MARVELL_PHY_ID_88E1118,
978 .phy_id_mask = MARVELL_PHY_ID_MASK,
605f196e
RM		 979 .name = "Marvell 88E1118",
980 .features = PHY_GBIT_FEATURES,
981 .flags = PHY_HAS_INTERRUPT,
982 .config_init = &m88e1118_config_init,
983 .config_aneg = &m88e1118_config_aneg,
984 .read_status = &genphy_read_status,
985 .ack_interrupt = &marvell_ack_interrupt,
986 .config_intr = &marvell_config_intr,
0898b448
SH		 987 .resume = &genphy_resume,
988 .suspend = &genphy_suspend,
605f196e
RM		 989 .driver = {.owner = THIS_MODULE,},
990 },
140bc929 991 {
2f495c39
BH		 992 .phy_id = MARVELL_PHY_ID_88E1121R,
993 .phy_id_mask = MARVELL_PHY_ID_MASK,
140bc929
SP		 994 .name = "Marvell 88E1121R",
995 .features = PHY_GBIT_FEATURES,
996 .flags = PHY_HAS_INTERRUPT,
997 .config_aneg = &m88e1121_config_aneg,
998 .read_status = &marvell_read_status,
999 .ack_interrupt = &marvell_ack_interrupt,
1000 .config_intr = &marvell_config_intr,
dcd07be3 1001 .did_interrupt = &m88e1121_did_interrupt,
0898b448
SH		 1002 .resume = &genphy_resume,
1003 .suspend = &genphy_suspend,
140bc929
SP		 1004 .driver = { .owner = THIS_MODULE },
1005 },
3ff1c259 1006 {
337ac9d5 1007 .phy_id = MARVELL_PHY_ID_88E1318S,
6ba74014 1008 .phy_id_mask = MARVELL_PHY_ID_MASK,
337ac9d5 1009 .name = "Marvell 88E1318S",
3ff1c259
CC		 1010 .features = PHY_GBIT_FEATURES,
1011 .flags = PHY_HAS_INTERRUPT,
337ac9d5 1012 .config_aneg = &m88e1318_config_aneg,
3ff1c259
CC		 1013 .read_status = &marvell_read_status,
1014 .ack_interrupt = &marvell_ack_interrupt,
1015 .config_intr = &marvell_config_intr,
1016 .did_interrupt = &m88e1121_did_interrupt,
3871c387
MS		 1017 .get_wol = &m88e1318_get_wol,
1018 .set_wol = &m88e1318_set_wol,
0898b448
SH		 1019 .resume = &genphy_resume,
1020 .suspend = &genphy_suspend,
3ff1c259
CC		 1021 .driver = { .owner = THIS_MODULE },
1022 },
e5479239 1023 {
2f495c39
BH		 1024 .phy_id = MARVELL_PHY_ID_88E1145,
1025 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 1026 .name = "Marvell 88E1145",
1027 .features = PHY_GBIT_FEATURES,
1028 .flags = PHY_HAS_INTERRUPT,
1029 .config_init = &m88e1145_config_init,
1030 .config_aneg = &marvell_config_aneg,
1031 .read_status = &genphy_read_status,
1032 .ack_interrupt = &marvell_ack_interrupt,
1033 .config_intr = &marvell_config_intr,
0898b448
SH		 1034 .resume = &genphy_resume,
1035 .suspend = &genphy_suspend,
ac8c635a
OJ		 1036 .driver = { .owner = THIS_MODULE },
1037 },
90600732
DD		 1038 {
1039 .phy_id = MARVELL_PHY_ID_88E1149R,
1040 .phy_id_mask = MARVELL_PHY_ID_MASK,
1041 .name = "Marvell 88E1149R",
1042 .features = PHY_GBIT_FEATURES,
1043 .flags = PHY_HAS_INTERRUPT,
1044 .config_init = &m88e1149_config_init,
1045 .config_aneg = &m88e1118_config_aneg,
1046 .read_status = &genphy_read_status,
1047 .ack_interrupt = &marvell_ack_interrupt,
1048 .config_intr = &marvell_config_intr,
0898b448
SH		 1049 .resume = &genphy_resume,
1050 .suspend = &genphy_suspend,
90600732
DD		 1051 .driver = { .owner = THIS_MODULE },
1052 },
ac8c635a 1053 {
2f495c39
BH		 1054 .phy_id = MARVELL_PHY_ID_88E1240,
1055 .phy_id_mask = MARVELL_PHY_ID_MASK,
ac8c635a
OJ		 1056 .name = "Marvell 88E1240",
1057 .features = PHY_GBIT_FEATURES,
1058 .flags = PHY_HAS_INTERRUPT,
1059 .config_init = &m88e1111_config_init,
1060 .config_aneg = &marvell_config_aneg,
1061 .read_status = &genphy_read_status,
1062 .ack_interrupt = &marvell_ack_interrupt,
1063 .config_intr = &marvell_config_intr,
0898b448
SH		 1064 .resume = &genphy_resume,
1065 .suspend = &genphy_suspend,
ac8c635a
OJ		 1066 .driver = { .owner = THIS_MODULE },
1067 },
3da09a51
MS		 1068 {
1069 .phy_id = MARVELL_PHY_ID_88E1116R,
1070 .phy_id_mask = MARVELL_PHY_ID_MASK,
1071 .name = "Marvell 88E1116R",
1072 .features = PHY_GBIT_FEATURES,
1073 .flags = PHY_HAS_INTERRUPT,
1074 .config_init = &m88e1116r_config_init,
1075 .config_aneg = &genphy_config_aneg,
1076 .read_status = &genphy_read_status,
1077 .ack_interrupt = &marvell_ack_interrupt,
1078 .config_intr = &marvell_config_intr,
0898b448
SH		 1079 .resume = &genphy_resume,
1080 .suspend = &genphy_suspend,
3da09a51
MS		 1081 .driver = { .owner = THIS_MODULE },
1082 },
10e24caa
MS		 1083 {
1084 .phy_id = MARVELL_PHY_ID_88E1510,
1085 .phy_id_mask = MARVELL_PHY_ID_MASK,
1086 .name = "Marvell 88E1510",
1087 .features = PHY_GBIT_FEATURES,
1088 .flags = PHY_HAS_INTERRUPT,
1089 .config_aneg = &m88e1510_config_aneg,
1090 .read_status = &marvell_read_status,
1091 .ack_interrupt = &marvell_ack_interrupt,
1092 .config_intr = &marvell_config_intr,
1093 .did_interrupt = &m88e1121_did_interrupt,
0898b448
SH		 1094 .resume = &genphy_resume,
1095 .suspend = &genphy_suspend,
10e24caa
MS		 1096 .driver = { .owner = THIS_MODULE },
1097 },
6b358aed
SH		 1098 {
1099 .phy_id = MARVELL_PHY_ID_88E3016,
1100 .phy_id_mask = MARVELL_PHY_ID_MASK,
1101 .name = "Marvell 88E3016",
1102 .features = PHY_BASIC_FEATURES,
1103 .flags = PHY_HAS_INTERRUPT,
1104 .config_aneg = &genphy_config_aneg,
1105 .config_init = &m88e3016_config_init,
1106 .aneg_done = &marvell_aneg_done,
1107 .read_status = &marvell_read_status,
1108 .ack_interrupt = &marvell_ack_interrupt,
1109 .config_intr = &marvell_config_intr,
1110 .did_interrupt = &m88e1121_did_interrupt,
1111 .resume = &genphy_resume,
1112 .suspend = &genphy_suspend,
1113 .driver = { .owner = THIS_MODULE },
1114 },
00db8189
AF		 1115};
1116
50fd7150 1117module_phy_driver(marvell_drivers);
4e4f10f6 1118
cf93c945 1119static struct mdio_device_id __maybe_unused marvell_tbl[] = {
f5e1cabf
MS		 1120 { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
1121 { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
1122 { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
1123 { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
1124 { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
1125 { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
1126 { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
1127 { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
1128 { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
3da09a51 1129 { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
10e24caa 1130 { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
6b358aed 1131 { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
4e4f10f6
DW		 1132 { }
1133};
1134
1135MODULE_DEVICE_TABLE(mdio, marvell_tbl);
Michael's Linux tree.