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Marvell phy: check link status in case of fiber link.
[people/ms/linux.git] / drivers / net / phy / marvell.c
CommitLineData
00db8189
AF		 1/*
2 * drivers/net/phy/marvell.c
3 *
4 * Driver for Marvell PHYs
5 *
6 * Author: Andy Fleming
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
9 *
3871c387
MS		 10 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
11 *
00db8189
AF		 12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 */
00db8189 18#include <linux/kernel.h>
00db8189
AF		 19#include <linux/string.h>
20#include <linux/errno.h>
21#include <linux/unistd.h>
00db8189
AF		 22#include <linux/interrupt.h>
23#include <linux/init.h>
24#include <linux/delay.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/skbuff.h>
28#include <linux/spinlock.h>
29#include <linux/mm.h>
30#include <linux/module.h>
00db8189
AF		 31#include <linux/mii.h>
32#include <linux/ethtool.h>
33#include <linux/phy.h>
2f495c39 34#include <linux/marvell_phy.h>
cf41a51d 35#include <linux/of.h>
00db8189 36
eea3b201 37#include <linux/io.h>
00db8189 38#include <asm/irq.h>
eea3b201 39#include <linux/uaccess.h>
00db8189 40
27d916d6
DD		 41#define MII_MARVELL_PHY_PAGE 22
42
00db8189
AF		 43#define MII_M1011_IEVENT 0x13
44#define MII_M1011_IEVENT_CLEAR 0x0000
45
46#define MII_M1011_IMASK 0x12
47#define MII_M1011_IMASK_INIT 0x6400
48#define MII_M1011_IMASK_CLEAR 0x0000
49
76884679 50#define MII_M1011_PHY_SCR 0x10
239aa55b
DT		 51#define MII_M1011_PHY_SCR_MDI 0x0000
52#define MII_M1011_PHY_SCR_MDI_X 0x0020
76884679
AF		 53#define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
54
07151bc9 55#define MII_M1145_PHY_EXT_ADDR_PAGE 0x16
b0224175 56#define MII_M1145_PHY_EXT_SR 0x1b
76884679
AF		 57#define MII_M1145_PHY_EXT_CR 0x14
58#define MII_M1145_RGMII_RX_DELAY 0x0080
59#define MII_M1145_RGMII_TX_DELAY 0x0002
b0224175
VND		 60#define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
61#define MII_M1145_HWCFG_MODE_MASK 0xf
62#define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
76884679 63
99d881f9
VB		 64#define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
65#define MII_M1145_HWCFG_MODE_MASK 0xf
66#define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
67
76884679
AF		 68#define MII_M1111_PHY_LED_CONTROL 0x18
69#define MII_M1111_PHY_LED_DIRECT 0x4100
70#define MII_M1111_PHY_LED_COMBINE 0x411c
895ee682
KP		 71#define MII_M1111_PHY_EXT_CR 0x14
72#define MII_M1111_RX_DELAY 0x80
73#define MII_M1111_TX_DELAY 0x2
74#define MII_M1111_PHY_EXT_SR 0x1b
be937f1f
AS		 75
76#define MII_M1111_HWCFG_MODE_MASK 0xf
77#define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
78#define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
4117b5be 79#define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
5f8cbc13 80#define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
be937f1f
AS		 81#define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
82#define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
83
84#define MII_M1111_COPPER 0
85#define MII_M1111_FIBER 1
86
c477d044
CC		 87#define MII_88E1121_PHY_MSCR_PAGE 2
88#define MII_88E1121_PHY_MSCR_REG 21
89#define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
90#define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
91#define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
92
337ac9d5
CC		 93#define MII_88E1318S_PHY_MSCR1_REG 16
94#define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
3ff1c259 95
3871c387
MS		 96/* Copper Specific Interrupt Enable Register */
97#define MII_88E1318S_PHY_CSIER 0x12
98/* WOL Event Interrupt Enable */
99#define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
100
101/* LED Timer Control Register */
102#define MII_88E1318S_PHY_LED_PAGE 0x03
103#define MII_88E1318S_PHY_LED_TCR 0x12
104#define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
105#define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
106#define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
107
108/* Magic Packet MAC address registers */
109#define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
110#define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
111#define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
112
113#define MII_88E1318S_PHY_WOL_PAGE 0x11
114#define MII_88E1318S_PHY_WOL_CTRL 0x10
115#define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
116#define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
117
140bc929
SP		 118#define MII_88E1121_PHY_LED_CTRL 16
119#define MII_88E1121_PHY_LED_PAGE 3
120#define MII_88E1121_PHY_LED_DEF 0x0030
140bc929 121
be937f1f
AS		 122#define MII_M1011_PHY_STATUS 0x11
123#define MII_M1011_PHY_STATUS_1000 0x8000
124#define MII_M1011_PHY_STATUS_100 0x4000
125#define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
126#define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
127#define MII_M1011_PHY_STATUS_RESOLVED 0x0800
128#define MII_M1011_PHY_STATUS_LINK 0x0400
129
3da09a51
MS		 130#define MII_M1116R_CONTROL_REG_MAC 21
131
6b358aed
SH		 132#define MII_88E3016_PHY_SPEC_CTRL 0x10
133#define MII_88E3016_DISABLE_SCRAMBLER 0x0200
134#define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
76884679 135
930b37ee
SR		 136#define MII_88E1510_GEN_CTRL_REG_1 0x14
137#define MII_88E1510_GEN_CTRL_REG_1_MODE_MASK 0x7
138#define MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII 0x1 /* SGMII to copper */
139#define MII_88E1510_GEN_CTRL_REG_1_RESET 0x8000 /* Soft reset */
140
6cfb3bcc
CAC		 141#define LPA_FIBER_1000HALF 0x40
142#define LPA_FIBER_1000FULL 0x20
143
144#define LPA_PAUSE_FIBER 0x180
145#define LPA_PAUSE_ASYM_FIBER 0x100
146
147#define ADVERTISE_FIBER_1000HALF 0x40
148#define ADVERTISE_FIBER_1000FULL 0x20
149
150#define ADVERTISE_PAUSE_FIBER 0x180
151#define ADVERTISE_PAUSE_ASYM_FIBER 0x100
152
153#define REGISTER_LINK_STATUS 0x400
154
00db8189
AF		 155MODULE_DESCRIPTION("Marvell PHY driver");
156MODULE_AUTHOR("Andy Fleming");
157MODULE_LICENSE("GPL");
158
d2fa47d9
AL		 159struct marvell_hw_stat {
160 const char *string;
161 u8 page;
162 u8 reg;
163 u8 bits;
164};
165
166static struct marvell_hw_stat marvell_hw_stats[] = {
167 { "phy_receive_errors", 0, 21, 16},
168 { "phy_idle_errors", 0, 10, 8 },
169};
170
171struct marvell_priv {
172 u64 stats[ARRAY_SIZE(marvell_hw_stats)];
173};
174
00db8189
AF		 175static int marvell_ack_interrupt(struct phy_device *phydev)
176{
177 int err;
178
179 /* Clear the interrupts by reading the reg */
180 err = phy_read(phydev, MII_M1011_IEVENT);
181
182 if (err < 0)
183 return err;
184
185 return 0;
186}
187
188static int marvell_config_intr(struct phy_device *phydev)
189{
190 int err;
191
76884679 192 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
00db8189
AF		 193 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
194 else
195 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
196
197 return err;
198}
199
239aa55b
DT		 200static int marvell_set_polarity(struct phy_device *phydev, int polarity)
201{
202 int reg;
203 int err;
204 int val;
205
206 /* get the current settings */
207 reg = phy_read(phydev, MII_M1011_PHY_SCR);
208 if (reg < 0)
209 return reg;
210
211 val = reg;
212 val &= ~MII_M1011_PHY_SCR_AUTO_CROSS;
213 switch (polarity) {
214 case ETH_TP_MDI:
215 val |= MII_M1011_PHY_SCR_MDI;
216 break;
217 case ETH_TP_MDI_X:
218 val |= MII_M1011_PHY_SCR_MDI_X;
219 break;
220 case ETH_TP_MDI_AUTO:
221 case ETH_TP_MDI_INVALID:
222 default:
223 val |= MII_M1011_PHY_SCR_AUTO_CROSS;
224 break;
225 }
226
227 if (val != reg) {
228 /* Set the new polarity value in the register */
229 err = phy_write(phydev, MII_M1011_PHY_SCR, val);
230 if (err)
231 return err;
232 }
233
234 return 0;
235}
236
00db8189
AF		 237static int marvell_config_aneg(struct phy_device *phydev)
238{
239 int err;
240
241 /* The Marvell PHY has an errata which requires
242 * that certain registers get written in order
243 * to restart autonegotiation */
244 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
245
246 if (err < 0)
247 return err;
248
249 err = phy_write(phydev, 0x1d, 0x1f);
250 if (err < 0)
251 return err;
252
253 err = phy_write(phydev, 0x1e, 0x200c);
254 if (err < 0)
255 return err;
256
257 err = phy_write(phydev, 0x1d, 0x5);
258 if (err < 0)
259 return err;
260
261 err = phy_write(phydev, 0x1e, 0);
262 if (err < 0)
263 return err;
264
265 err = phy_write(phydev, 0x1e, 0x100);
266 if (err < 0)
267 return err;
268
239aa55b 269 err = marvell_set_polarity(phydev, phydev->mdix);
76884679
AF		 270 if (err < 0)
271 return err;
272
273 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
274 MII_M1111_PHY_LED_DIRECT);
275 if (err < 0)
276 return err;
00db8189
AF		 277
278 err = genphy_config_aneg(phydev);
8ff44985
AV		 279 if (err < 0)
280 return err;
00db8189 281
8ff44985
AV		 282 if (phydev->autoneg != AUTONEG_ENABLE) {
283 int bmcr;
284
285 /*
286 * A write to speed/duplex bits (that is performed by
287 * genphy_config_aneg() call above) must be followed by
288 * a software reset. Otherwise, the write has no effect.
289 */
290 bmcr = phy_read(phydev, MII_BMCR);
291 if (bmcr < 0)
292 return bmcr;
293
294 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
295 if (err < 0)
296 return err;
297 }
298
299 return 0;
00db8189
AF		 300}
301
3ec0a0f1
HK		 302static int m88e1111_config_aneg(struct phy_device *phydev)
303{
304 int err;
305
306 /* The Marvell PHY has an errata which requires
307 * that certain registers get written in order
308 * to restart autonegotiation
309 */
310 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
311
312 err = marvell_set_polarity(phydev, phydev->mdix);
313 if (err < 0)
314 return err;
315
316 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
317 MII_M1111_PHY_LED_DIRECT);
318 if (err < 0)
319 return err;
320
321 err = genphy_config_aneg(phydev);
322 if (err < 0)
323 return err;
324
325 if (phydev->autoneg != AUTONEG_ENABLE) {
326 int bmcr;
327
328 /* A write to speed/duplex bits (that is performed by
329 * genphy_config_aneg() call above) must be followed by
330 * a software reset. Otherwise, the write has no effect.
331 */
332 bmcr = phy_read(phydev, MII_BMCR);
333 if (bmcr < 0)
334 return bmcr;
335
336 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
337 if (err < 0)
338 return err;
339 }
340
341 return 0;
342}
343
cf41a51d
DD		 344#ifdef CONFIG_OF_MDIO
345/*
346 * Set and/or override some configuration registers based on the
347 * marvell,reg-init property stored in the of_node for the phydev.
348 *
349 * marvell,reg-init = <reg-page reg mask value>,...;
350 *
351 * There may be one or more sets of <reg-page reg mask value>:
352 *
353 * reg-page: which register bank to use.
354 * reg: the register.
355 * mask: if non-zero, ANDed with existing register value.
356 * value: ORed with the masked value and written to the regiser.
357 *
358 */
359static int marvell_of_reg_init(struct phy_device *phydev)
360{
361 const __be32 *paddr;
362 int len, i, saved_page, current_page, page_changed, ret;
363
e5a03bfd 364 if (!phydev->mdio.dev.of_node)
cf41a51d
DD		 365 return 0;
366
e5a03bfd
AL		 367 paddr = of_get_property(phydev->mdio.dev.of_node,
368 "marvell,reg-init", &len);
cf41a51d
DD		 369 if (!paddr || len < (4 * sizeof(*paddr)))
370 return 0;
371
372 saved_page = phy_read(phydev, MII_MARVELL_PHY_PAGE);
373 if (saved_page < 0)
374 return saved_page;
375 page_changed = 0;
376 current_page = saved_page;
377
378 ret = 0;
379 len /= sizeof(*paddr);
380 for (i = 0; i < len - 3; i += 4) {
381 u16 reg_page = be32_to_cpup(paddr + i);
382 u16 reg = be32_to_cpup(paddr + i + 1);
383 u16 mask = be32_to_cpup(paddr + i + 2);
384 u16 val_bits = be32_to_cpup(paddr + i + 3);
385 int val;
386
387 if (reg_page != current_page) {
388 current_page = reg_page;
389 page_changed = 1;
390 ret = phy_write(phydev, MII_MARVELL_PHY_PAGE, reg_page);
391 if (ret < 0)
392 goto err;
393 }
394
395 val = 0;
396 if (mask) {
397 val = phy_read(phydev, reg);
398 if (val < 0) {
399 ret = val;
400 goto err;
401 }
402 val &= mask;
403 }
404 val |= val_bits;
405
406 ret = phy_write(phydev, reg, val);
407 if (ret < 0)
408 goto err;
409
410 }
411err:
412 if (page_changed) {
413 i = phy_write(phydev, MII_MARVELL_PHY_PAGE, saved_page);
414 if (ret == 0)
415 ret = i;
416 }
417 return ret;
418}
419#else
420static int marvell_of_reg_init(struct phy_device *phydev)
421{
422 return 0;
423}
424#endif /* CONFIG_OF_MDIO */
425
140bc929
SP		 426static int m88e1121_config_aneg(struct phy_device *phydev)
427{
c477d044
CC		 428 int err, oldpage, mscr;
429
27d916d6 430 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
c477d044 431
27d916d6 432 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
c477d044
CC		 433 MII_88E1121_PHY_MSCR_PAGE);
434 if (err < 0)
435 return err;
be8c6480 436
32a64161 437 if (phy_interface_is_rgmii(phydev)) {
be8c6480
AP		 438
439 mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) &
440 MII_88E1121_PHY_MSCR_DELAY_MASK;
441
442 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
443 mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY |
444 MII_88E1121_PHY_MSCR_TX_DELAY);
445 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
446 mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
447 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
448 mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
449
450 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
451 if (err < 0)
452 return err;
453 }
c477d044 454
27d916d6 455 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
140bc929
SP		 456
457 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
458 if (err < 0)
459 return err;
460
461 err = phy_write(phydev, MII_M1011_PHY_SCR,
462 MII_M1011_PHY_SCR_AUTO_CROSS);
463 if (err < 0)
464 return err;
465
fdecf36f 466 return genphy_config_aneg(phydev);
140bc929
SP		 467}
468
337ac9d5 469static int m88e1318_config_aneg(struct phy_device *phydev)
3ff1c259
CC		 470{
471 int err, oldpage, mscr;
472
27d916d6 473 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
3ff1c259 474
27d916d6 475 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
3ff1c259
CC		 476 MII_88E1121_PHY_MSCR_PAGE);
477 if (err < 0)
478 return err;
479
337ac9d5
CC		 480 mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG);
481 mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD;
3ff1c259 482
337ac9d5 483 err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr);
3ff1c259
CC		 484 if (err < 0)
485 return err;
486
27d916d6 487 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
3ff1c259
CC		 488 if (err < 0)
489 return err;
490
491 return m88e1121_config_aneg(phydev);
492}
493
10e24caa
MS		 494static int m88e1510_config_aneg(struct phy_device *phydev)
495{
496 int err;
497
498 err = m88e1318_config_aneg(phydev);
499 if (err < 0)
500 return err;
501
79be1a1c
CG		 502 return 0;
503}
504
505static int marvell_config_init(struct phy_device *phydev)
506{
507 /* Set registers from marvell,reg-init DT property */
10e24caa
MS		 508 return marvell_of_reg_init(phydev);
509}
510
3da09a51
MS		 511static int m88e1116r_config_init(struct phy_device *phydev)
512{
513 int temp;
514 int err;
515
516 temp = phy_read(phydev, MII_BMCR);
517 temp |= BMCR_RESET;
518 err = phy_write(phydev, MII_BMCR, temp);
519 if (err < 0)
520 return err;
521
522 mdelay(500);
523
524 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
525 if (err < 0)
526 return err;
527
528 temp = phy_read(phydev, MII_M1011_PHY_SCR);
529 temp |= (7 << 12); /* max number of gigabit attempts */
530 temp |= (1 << 11); /* enable downshift */
531 temp |= MII_M1011_PHY_SCR_AUTO_CROSS;
532 err = phy_write(phydev, MII_M1011_PHY_SCR, temp);
533 if (err < 0)
534 return err;
535
536 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 2);
537 if (err < 0)
538 return err;
539 temp = phy_read(phydev, MII_M1116R_CONTROL_REG_MAC);
540 temp |= (1 << 5);
541 temp |= (1 << 4);
542 err = phy_write(phydev, MII_M1116R_CONTROL_REG_MAC, temp);
543 if (err < 0)
544 return err;
545 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
546 if (err < 0)
547 return err;
548
549 temp = phy_read(phydev, MII_BMCR);
550 temp |= BMCR_RESET;
551 err = phy_write(phydev, MII_BMCR, temp);
552 if (err < 0)
553 return err;
554
555 mdelay(500);
556
79be1a1c 557 return marvell_config_init(phydev);
3da09a51
MS		 558}
559
6b358aed
SH		 560static int m88e3016_config_init(struct phy_device *phydev)
561{
562 int reg;
563
564 /* Enable Scrambler and Auto-Crossover */
565 reg = phy_read(phydev, MII_88E3016_PHY_SPEC_CTRL);
566 if (reg < 0)
567 return reg;
568
569 reg &= ~MII_88E3016_DISABLE_SCRAMBLER;
570 reg |= MII_88E3016_AUTO_MDIX_CROSSOVER;
571
572 reg = phy_write(phydev, MII_88E3016_PHY_SPEC_CTRL, reg);
573 if (reg < 0)
574 return reg;
575
79be1a1c 576 return marvell_config_init(phydev);
6b358aed
SH		 577}
578
895ee682
KP		 579static int m88e1111_config_init(struct phy_device *phydev)
580{
581 int err;
be937f1f 582 int temp;
be937f1f 583
32a64161 584 if (phy_interface_is_rgmii(phydev)) {
895ee682 585
9daf5a76
KP		 586 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
587 if (temp < 0)
588 return temp;
895ee682 589
9daf5a76 590 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
895ee682 591 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
9daf5a76
KP		 592 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
593 temp &= ~MII_M1111_TX_DELAY;
594 temp |= MII_M1111_RX_DELAY;
595 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
596 temp &= ~MII_M1111_RX_DELAY;
597 temp |= MII_M1111_TX_DELAY;
895ee682
KP		 598 }
599
9daf5a76
KP		 600 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
601 if (err < 0)
602 return err;
603
895ee682
KP		 604 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
605 if (temp < 0)
606 return temp;
607
608 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
be937f1f 609
7239016d 610 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
be937f1f
AS		 611 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
612 else
613 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
895ee682
KP		 614
615 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
616 if (err < 0)
617 return err;
618 }
619
4117b5be 620 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
4117b5be
KJ		 621 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
622 if (temp < 0)
623 return temp;
624
625 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
626 temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
32d0c1e1 627 temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
4117b5be
KJ		 628
629 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
630 if (err < 0)
631 return err;
07151bc9
MB		 632
633 /* make sure copper is selected */
634 err = phy_read(phydev, MII_M1145_PHY_EXT_ADDR_PAGE);
635 if (err < 0)
636 return err;
637
638 err = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE,
639 err & (~0xff));
640 if (err < 0)
641 return err;
4117b5be
KJ		 642 }
643
5f8cbc13
LYB		 644 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
645 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
646 if (temp < 0)
647 return temp;
648 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
649 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
650 if (err < 0)
651 return err;
652
653 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
654 if (temp < 0)
655 return temp;
656 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
657 temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
658 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
659 if (err < 0)
660 return err;
661
662 /* soft reset */
663 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
664 if (err < 0)
665 return err;
666 do
667 temp = phy_read(phydev, MII_BMCR);
668 while (temp & BMCR_RESET);
669
670 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
671 if (temp < 0)
672 return temp;
673 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
674 temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
675 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
676 if (err < 0)
677 return err;
678 }
679
cf41a51d
DD		 680 err = marvell_of_reg_init(phydev);
681 if (err < 0)
682 return err;
5f8cbc13 683
cc90cb3b 684 return phy_write(phydev, MII_BMCR, BMCR_RESET);
895ee682
KP		 685}
686
fdecf36f
CG		 687static int m88e1121_config_init(struct phy_device *phydev)
688{
689 int err, oldpage;
690
691 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
692
693 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
694 if (err < 0)
695 return err;
696
697 /* Default PHY LED config: LED[0] .. Link, LED[1] .. Activity */
698 err = phy_write(phydev, MII_88E1121_PHY_LED_CTRL,
699 MII_88E1121_PHY_LED_DEF);
700 if (err < 0)
701 return err;
702
703 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
704
705 /* Set marvell,reg-init configuration from device tree */
706 return marvell_config_init(phydev);
707}
708
407353ec
CG		 709static int m88e1510_config_init(struct phy_device *phydev)
710{
711 int err;
712 int temp;
713
714 /* SGMII-to-Copper mode initialization */
715 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
716 /* Select page 18 */
717 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 18);
718 if (err < 0)
719 return err;
720
721 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
722 temp = phy_read(phydev, MII_88E1510_GEN_CTRL_REG_1);
723 temp &= ~MII_88E1510_GEN_CTRL_REG_1_MODE_MASK;
724 temp |= MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII;
725 err = phy_write(phydev, MII_88E1510_GEN_CTRL_REG_1, temp);
726 if (err < 0)
727 return err;
728
729 /* PHY reset is necessary after changing MODE[2:0] */
730 temp |= MII_88E1510_GEN_CTRL_REG_1_RESET;
731 err = phy_write(phydev, MII_88E1510_GEN_CTRL_REG_1, temp);
732 if (err < 0)
733 return err;
734
735 /* Reset page selection */
736 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
737 if (err < 0)
738 return err;
739 }
740
fdecf36f 741 return m88e1121_config_init(phydev);
407353ec
CG		 742}
743
605f196e
RM		 744static int m88e1118_config_aneg(struct phy_device *phydev)
745{
746 int err;
747
748 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
749 if (err < 0)
750 return err;
751
752 err = phy_write(phydev, MII_M1011_PHY_SCR,
753 MII_M1011_PHY_SCR_AUTO_CROSS);
754 if (err < 0)
755 return err;
756
757 err = genphy_config_aneg(phydev);
758 return 0;
759}
760
761static int m88e1118_config_init(struct phy_device *phydev)
762{
763 int err;
764
765 /* Change address */
27d916d6 766 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
605f196e
RM		 767 if (err < 0)
768 return err;
769
770 /* Enable 1000 Mbit */
771 err = phy_write(phydev, 0x15, 0x1070);
772 if (err < 0)
773 return err;
774
775 /* Change address */
27d916d6 776 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0003);
605f196e
RM		 777 if (err < 0)
778 return err;
779
780 /* Adjust LED Control */
2f495c39
BH		 781 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
782 err = phy_write(phydev, 0x10, 0x1100);
783 else
784 err = phy_write(phydev, 0x10, 0x021e);
605f196e
RM		 785 if (err < 0)
786 return err;
787
cf41a51d
DD		 788 err = marvell_of_reg_init(phydev);
789 if (err < 0)
790 return err;
791
605f196e 792 /* Reset address */
27d916d6 793 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
605f196e
RM		 794 if (err < 0)
795 return err;
796
cc90cb3b 797 return phy_write(phydev, MII_BMCR, BMCR_RESET);
605f196e
RM		 798}
799
90600732
DD		 800static int m88e1149_config_init(struct phy_device *phydev)
801{
802 int err;
803
804 /* Change address */
805 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
806 if (err < 0)
807 return err;
808
809 /* Enable 1000 Mbit */
810 err = phy_write(phydev, 0x15, 0x1048);
811 if (err < 0)
812 return err;
813
cf41a51d
DD		 814 err = marvell_of_reg_init(phydev);
815 if (err < 0)
816 return err;
817
90600732
DD		 818 /* Reset address */
819 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
820 if (err < 0)
821 return err;
822
cc90cb3b 823 return phy_write(phydev, MII_BMCR, BMCR_RESET);
90600732
DD		 824}
825
76884679
AF		 826static int m88e1145_config_init(struct phy_device *phydev)
827{
828 int err;
b0224175 829 int temp;
76884679
AF		 830
831 /* Take care of errata E0 & E1 */
832 err = phy_write(phydev, 0x1d, 0x001b);
833 if (err < 0)
834 return err;
835
836 err = phy_write(phydev, 0x1e, 0x418f);
837 if (err < 0)
838 return err;
839
840 err = phy_write(phydev, 0x1d, 0x0016);
841 if (err < 0)
842 return err;
843
844 err = phy_write(phydev, 0x1e, 0xa2da);
845 if (err < 0)
846 return err;
847
895ee682 848 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
76884679
AF		 849 int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
850 if (temp < 0)
851 return temp;
852
853 temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
854
855 err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
856 if (err < 0)
857 return err;
858
2f495c39 859 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
76884679
AF		 860 err = phy_write(phydev, 0x1d, 0x0012);
861 if (err < 0)
862 return err;
863
864 temp = phy_read(phydev, 0x1e);
865 if (temp < 0)
866 return temp;
867
868 temp &= 0xf03f;
869 temp |= 2 << 9; /* 36 ohm */
870 temp |= 2 << 6; /* 39 ohm */
871
872 err = phy_write(phydev, 0x1e, temp);
873 if (err < 0)
874 return err;
875
876 err = phy_write(phydev, 0x1d, 0x3);
877 if (err < 0)
878 return err;
879
880 err = phy_write(phydev, 0x1e, 0x8000);
881 if (err < 0)
882 return err;
883 }
884 }
885
b0224175
VND		 886 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
887 temp = phy_read(phydev, MII_M1145_PHY_EXT_SR);
888 if (temp < 0)
889 return temp;
890
99d881f9 891 temp &= ~MII_M1145_HWCFG_MODE_MASK;
b0224175
VND		 892 temp |= MII_M1145_HWCFG_MODE_SGMII_NO_CLK;
893 temp |= MII_M1145_HWCFG_FIBER_COPPER_AUTO;
894
895 err = phy_write(phydev, MII_M1145_PHY_EXT_SR, temp);
896 if (err < 0)
897 return err;
898 }
899
cf41a51d
DD		 900 err = marvell_of_reg_init(phydev);
901 if (err < 0)
902 return err;
903
76884679
AF		 904 return 0;
905}
00db8189 906
6cfb3bcc
CAC		 907/**
908 * fiber_lpa_to_ethtool_lpa_t
909 * @lpa: value of the MII_LPA register for fiber link
910 *
911 * A small helper function that translates MII_LPA
912 * bits to ethtool LP advertisement settings.
913 */
914static u32 fiber_lpa_to_ethtool_lpa_t(u32 lpa)
915{
916 u32 result = 0;
917
918 if (lpa & LPA_FIBER_1000HALF)
919 result |= ADVERTISED_1000baseT_Half;
920 if (lpa & LPA_FIBER_1000FULL)
921 result |= ADVERTISED_1000baseT_Full;
922
923 return result;
924}
925
926/**
927 * marvell_update_link - update link status in real time in @phydev
928 * @phydev: target phy_device struct
929 *
930 * Description: Update the value in phydev->link to reflect the
931 * current link value.
932 */
933static int marvell_update_link(struct phy_device *phydev, int fiber)
934{
935 int status;
936
937 /* Use the generic register for copper link, or specific
938 * register for fiber case */
939 if (fiber) {
940 status = phy_read(phydev, MII_M1011_PHY_STATUS);
941 if (status < 0)
942 return status;
943
944 if ((status & REGISTER_LINK_STATUS) == 0)
945 phydev->link = 0;
946 else
947 phydev->link = 1;
948 } else {
949 return genphy_update_link(phydev);
950 }
951
952 return 0;
953}
954
955/* marvell_read_status_page
be937f1f 956 *
f0c88f9c 957 * Description:
be937f1f
AS		 958 * Check the link, then figure out the current state
959 * by comparing what we advertise with what the link partner
960 * advertises. Start by checking the gigabit possibilities,
961 * then move on to 10/100.
962 */
6cfb3bcc 963static int marvell_read_status_page(struct phy_device *phydev, int page)
be937f1f
AS		 964{
965 int adv;
966 int err;
967 int lpa;
357cd64c 968 int lpagb;
be937f1f 969 int status = 0;
6cfb3bcc 970 int fiber;
be937f1f 971
6cfb3bcc 972 /* Detect and update the link, but return if there
be937f1f 973 * was an error */
6cfb3bcc
CAC		 974 if (page == MII_M1111_FIBER)
975 fiber = 1;
976 else
977 fiber = 0;
978
979 err = marvell_update_link(phydev, fiber);
be937f1f
AS		 980 if (err)
981 return err;
982
983 if (AUTONEG_ENABLE == phydev->autoneg) {
984 status = phy_read(phydev, MII_M1011_PHY_STATUS);
985 if (status < 0)
986 return status;
987
988 lpa = phy_read(phydev, MII_LPA);
989 if (lpa < 0)
990 return lpa;
991
357cd64c
RK		 992 lpagb = phy_read(phydev, MII_STAT1000);
993 if (lpagb < 0)
994 return lpagb;
995
be937f1f
AS		 996 adv = phy_read(phydev, MII_ADVERTISE);
997 if (adv < 0)
998 return adv;
999
1000 lpa &= adv;
1001
1002 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
1003 phydev->duplex = DUPLEX_FULL;
1004 else
1005 phydev->duplex = DUPLEX_HALF;
1006
1007 status = status & MII_M1011_PHY_STATUS_SPD_MASK;
1008 phydev->pause = phydev->asym_pause = 0;
1009
1010 switch (status) {
1011 case MII_M1011_PHY_STATUS_1000:
1012 phydev->speed = SPEED_1000;
1013 break;
1014
1015 case MII_M1011_PHY_STATUS_100:
1016 phydev->speed = SPEED_100;
1017 break;
1018
1019 default:
1020 phydev->speed = SPEED_10;
1021 break;
1022 }
1023
6cfb3bcc
CAC		 1024 if (!fiber) {
1025 phydev->lp_advertising = mii_stat1000_to_ethtool_lpa_t(lpagb) |
1026 mii_lpa_to_ethtool_lpa_t(lpa);
1027
1028 if (phydev->duplex == DUPLEX_FULL) {
1029 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
1030 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
1031 }
1032 } else {
1033 /* The fiber link is only 1000M capable */
1034 phydev->lp_advertising = fiber_lpa_to_ethtool_lpa_t(lpa);
1035
1036 if (phydev->duplex == DUPLEX_FULL) {
1037 if (!(lpa & LPA_PAUSE_FIBER)) {
1038 phydev->pause = 0;
1039 phydev->asym_pause = 0;
1040 } else if ((lpa & LPA_PAUSE_ASYM_FIBER)) {
1041 phydev->pause = 1;
1042 phydev->asym_pause = 1;
1043 } else {
1044 phydev->pause = 1;
1045 phydev->asym_pause = 0;
1046 }
1047 }
be937f1f
AS		 1048 }
1049 } else {
1050 int bmcr = phy_read(phydev, MII_BMCR);
1051
1052 if (bmcr < 0)
1053 return bmcr;
1054
1055 if (bmcr & BMCR_FULLDPLX)
1056 phydev->duplex = DUPLEX_FULL;
1057 else
1058 phydev->duplex = DUPLEX_HALF;
1059
1060 if (bmcr & BMCR_SPEED1000)
1061 phydev->speed = SPEED_1000;
1062 else if (bmcr & BMCR_SPEED100)
1063 phydev->speed = SPEED_100;
1064 else
1065 phydev->speed = SPEED_10;
1066
1067 phydev->pause = phydev->asym_pause = 0;
357cd64c 1068 phydev->lp_advertising = 0;
be937f1f
AS		 1069 }
1070
1071 return 0;
1072}
1073
6cfb3bcc
CAC		 1074/* marvell_read_status
1075 *
1076 * Some Marvell's phys have two modes: fiber and copper.
1077 * Both need status checked.
1078 * Description:
1079 * First, check the fiber link and status.
1080 * If the fiber link is down, check the copper link and status which
1081 * will be the default value if both link are down.
1082 */
1083static int marvell_read_status(struct phy_device *phydev)
1084{
1085 int err;
1086
1087 /* Check the fiber mode first */
1088 if (phydev->supported & SUPPORTED_FIBRE) {
1089 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER);
1090 if (err < 0)
1091 goto error;
1092
1093 err = marvell_read_status_page(phydev, MII_M1111_FIBER);
1094 if (err < 0)
1095 goto error;
1096
1097 /* If the fiber link is up, it is the selected and used link.
1098 * In this case, we need to stay in the fiber page.
1099 * Please to be careful about that, avoid to restore Copper page
1100 * in other functions which could break the behaviour
1101 * for some fiber phy like 88E1512.
1102 * */
1103 if (phydev->link)
1104 return 0;
1105
1106 /* If fiber link is down, check and save copper mode state */
1107 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1108 if (err < 0)
1109 goto error;
1110 }
1111
1112 return marvell_read_status_page(phydev, MII_M1111_COPPER);
1113
1114error:
1115 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1116 return err;
1117}
6b358aed
SH		 1118static int marvell_aneg_done(struct phy_device *phydev)
1119{
1120 int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
1121 return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
1122}
1123
dcd07be3
AG		 1124static int m88e1121_did_interrupt(struct phy_device *phydev)
1125{
1126 int imask;
1127
1128 imask = phy_read(phydev, MII_M1011_IEVENT);
1129
1130 if (imask & MII_M1011_IMASK_INIT)
1131 return 1;
1132
1133 return 0;
1134}
1135
3871c387
MS		 1136static void m88e1318_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
1137{
1138 wol->supported = WAKE_MAGIC;
1139 wol->wolopts = 0;
1140
1141 if (phy_write(phydev, MII_MARVELL_PHY_PAGE,
1142 MII_88E1318S_PHY_WOL_PAGE) < 0)
1143 return;
1144
1145 if (phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL) &
1146 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
1147 wol->wolopts |= WAKE_MAGIC;
1148
1149 if (phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00) < 0)
1150 return;
1151}
1152
1153static int m88e1318_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
1154{
1155 int err, oldpage, temp;
1156
1157 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
1158
1159 if (wol->wolopts & WAKE_MAGIC) {
1160 /* Explicitly switch to page 0x00, just to be sure */
1161 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00);
1162 if (err < 0)
1163 return err;
1164
1165 /* Enable the WOL interrupt */
1166 temp = phy_read(phydev, MII_88E1318S_PHY_CSIER);
1167 temp |= MII_88E1318S_PHY_CSIER_WOL_EIE;
1168 err = phy_write(phydev, MII_88E1318S_PHY_CSIER, temp);
1169 if (err < 0)
1170 return err;
1171
1172 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1173 MII_88E1318S_PHY_LED_PAGE);
1174 if (err < 0)
1175 return err;
1176
1177 /* Setup LED[2] as interrupt pin (active low) */
1178 temp = phy_read(phydev, MII_88E1318S_PHY_LED_TCR);
1179 temp &= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT;
1180 temp |= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE;
1181 temp |= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW;
1182 err = phy_write(phydev, MII_88E1318S_PHY_LED_TCR, temp);
1183 if (err < 0)
1184 return err;
1185
1186 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1187 MII_88E1318S_PHY_WOL_PAGE);
1188 if (err < 0)
1189 return err;
1190
1191 /* Store the device address for the magic packet */
1192 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
1193 ((phydev->attached_dev->dev_addr[5] << 8) |
1194 phydev->attached_dev->dev_addr[4]));
1195 if (err < 0)
1196 return err;
1197 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
1198 ((phydev->attached_dev->dev_addr[3] << 8) |
1199 phydev->attached_dev->dev_addr[2]));
1200 if (err < 0)
1201 return err;
1202 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
1203 ((phydev->attached_dev->dev_addr[1] << 8) |
1204 phydev->attached_dev->dev_addr[0]));
1205 if (err < 0)
1206 return err;
1207
1208 /* Clear WOL status and enable magic packet matching */
1209 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
1210 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
1211 temp |= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
1212 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
1213 if (err < 0)
1214 return err;
1215 } else {
1216 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1217 MII_88E1318S_PHY_WOL_PAGE);
1218 if (err < 0)
1219 return err;
1220
1221 /* Clear WOL status and disable magic packet matching */
1222 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
1223 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
1224 temp &= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
1225 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
1226 if (err < 0)
1227 return err;
1228 }
1229
1230 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
1231 if (err < 0)
1232 return err;
1233
1234 return 0;
1235}
1236
d2fa47d9
AL		 1237static int marvell_get_sset_count(struct phy_device *phydev)
1238{
1239 return ARRAY_SIZE(marvell_hw_stats);
1240}
1241
1242static void marvell_get_strings(struct phy_device *phydev, u8 *data)
1243{
1244 int i;
1245
1246 for (i = 0; i < ARRAY_SIZE(marvell_hw_stats); i++) {
1247 memcpy(data + i * ETH_GSTRING_LEN,
1248 marvell_hw_stats[i].string, ETH_GSTRING_LEN);
1249 }
1250}
1251
1252#ifndef UINT64_MAX
1253#define UINT64_MAX (u64)(~((u64)0))
1254#endif
1255static u64 marvell_get_stat(struct phy_device *phydev, int i)
1256{
1257 struct marvell_hw_stat stat = marvell_hw_stats[i];
1258 struct marvell_priv *priv = phydev->priv;
321b4d4b
AL		 1259 int err, oldpage, val;
1260 u64 ret;
d2fa47d9
AL		 1261
1262 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
1263 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1264 stat.page);
1265 if (err < 0)
1266 return UINT64_MAX;
1267
1268 val = phy_read(phydev, stat.reg);
1269 if (val < 0) {
321b4d4b 1270 ret = UINT64_MAX;
d2fa47d9
AL		 1271 } else {
1272 val = val & ((1 << stat.bits) - 1);
1273 priv->stats[i] += val;
321b4d4b 1274 ret = priv->stats[i];
d2fa47d9
AL		 1275 }
1276
1277 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
1278
321b4d4b 1279 return ret;
d2fa47d9
AL		 1280}
1281
1282static void marvell_get_stats(struct phy_device *phydev,
1283 struct ethtool_stats *stats, u64 *data)
1284{
1285 int i;
1286
1287 for (i = 0; i < ARRAY_SIZE(marvell_hw_stats); i++)
1288 data[i] = marvell_get_stat(phydev, i);
1289}
1290
1291static int marvell_probe(struct phy_device *phydev)
1292{
1293 struct marvell_priv *priv;
1294
e5a03bfd 1295 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
d2fa47d9
AL		 1296 if (!priv)
1297 return -ENOMEM;
1298
1299 phydev->priv = priv;
1300
1301 return 0;
1302}
1303
e5479239
OJ		 1304static struct phy_driver marvell_drivers[] = {
1305 {
2f495c39
BH		 1306 .phy_id = MARVELL_PHY_ID_88E1101,
1307 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 1308 .name = "Marvell 88E1101",
1309 .features = PHY_GBIT_FEATURES,
d2fa47d9 1310 .probe = marvell_probe,
e5479239 1311 .flags = PHY_HAS_INTERRUPT,
79be1a1c 1312 .config_init = &marvell_config_init,
e5479239
OJ		 1313 .config_aneg = &marvell_config_aneg,
1314 .read_status = &genphy_read_status,
1315 .ack_interrupt = &marvell_ack_interrupt,
1316 .config_intr = &marvell_config_intr,
0898b448
SH		 1317 .resume = &genphy_resume,
1318 .suspend = &genphy_suspend,
d2fa47d9
AL		 1319 .get_sset_count = marvell_get_sset_count,
1320 .get_strings = marvell_get_strings,
1321 .get_stats = marvell_get_stats,
e5479239 1322 },
85cfb534 1323 {
2f495c39
BH		 1324 .phy_id = MARVELL_PHY_ID_88E1112,
1325 .phy_id_mask = MARVELL_PHY_ID_MASK,
85cfb534
OJ		 1326 .name = "Marvell 88E1112",
1327 .features = PHY_GBIT_FEATURES,
1328 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1329 .probe = marvell_probe,
85cfb534
OJ		 1330 .config_init = &m88e1111_config_init,
1331 .config_aneg = &marvell_config_aneg,
1332 .read_status = &genphy_read_status,
1333 .ack_interrupt = &marvell_ack_interrupt,
1334 .config_intr = &marvell_config_intr,
0898b448
SH		 1335 .resume = &genphy_resume,
1336 .suspend = &genphy_suspend,
d2fa47d9
AL		 1337 .get_sset_count = marvell_get_sset_count,
1338 .get_strings = marvell_get_strings,
1339 .get_stats = marvell_get_stats,
85cfb534 1340 },
e5479239 1341 {
2f495c39
BH		 1342 .phy_id = MARVELL_PHY_ID_88E1111,
1343 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 1344 .name = "Marvell 88E1111",
1345 .features = PHY_GBIT_FEATURES,
1346 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1347 .probe = marvell_probe,
e5479239 1348 .config_init = &m88e1111_config_init,
3ec0a0f1 1349 .config_aneg = &m88e1111_config_aneg,
be937f1f 1350 .read_status = &marvell_read_status,
e5479239
OJ		 1351 .ack_interrupt = &marvell_ack_interrupt,
1352 .config_intr = &marvell_config_intr,
0898b448
SH		 1353 .resume = &genphy_resume,
1354 .suspend = &genphy_suspend,
d2fa47d9
AL		 1355 .get_sset_count = marvell_get_sset_count,
1356 .get_strings = marvell_get_strings,
1357 .get_stats = marvell_get_stats,
e5479239 1358 },
605f196e 1359 {
2f495c39
BH		 1360 .phy_id = MARVELL_PHY_ID_88E1118,
1361 .phy_id_mask = MARVELL_PHY_ID_MASK,
605f196e
RM		 1362 .name = "Marvell 88E1118",
1363 .features = PHY_GBIT_FEATURES,
1364 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1365 .probe = marvell_probe,
605f196e
RM		 1366 .config_init = &m88e1118_config_init,
1367 .config_aneg = &m88e1118_config_aneg,
1368 .read_status = &genphy_read_status,
1369 .ack_interrupt = &marvell_ack_interrupt,
1370 .config_intr = &marvell_config_intr,
0898b448
SH		 1371 .resume = &genphy_resume,
1372 .suspend = &genphy_suspend,
d2fa47d9
AL		 1373 .get_sset_count = marvell_get_sset_count,
1374 .get_strings = marvell_get_strings,
1375 .get_stats = marvell_get_stats,
605f196e 1376 },
140bc929 1377 {
2f495c39
BH		 1378 .phy_id = MARVELL_PHY_ID_88E1121R,
1379 .phy_id_mask = MARVELL_PHY_ID_MASK,
140bc929
SP		 1380 .name = "Marvell 88E1121R",
1381 .features = PHY_GBIT_FEATURES,
1382 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1383 .probe = marvell_probe,
fdecf36f 1384 .config_init = &m88e1121_config_init,
140bc929
SP		 1385 .config_aneg = &m88e1121_config_aneg,
1386 .read_status = &marvell_read_status,
1387 .ack_interrupt = &marvell_ack_interrupt,
1388 .config_intr = &marvell_config_intr,
dcd07be3 1389 .did_interrupt = &m88e1121_did_interrupt,
0898b448
SH		 1390 .resume = &genphy_resume,
1391 .suspend = &genphy_suspend,
d2fa47d9
AL		 1392 .get_sset_count = marvell_get_sset_count,
1393 .get_strings = marvell_get_strings,
1394 .get_stats = marvell_get_stats,
140bc929 1395 },
3ff1c259 1396 {
337ac9d5 1397 .phy_id = MARVELL_PHY_ID_88E1318S,
6ba74014 1398 .phy_id_mask = MARVELL_PHY_ID_MASK,
337ac9d5 1399 .name = "Marvell 88E1318S",
3ff1c259
CC		 1400 .features = PHY_GBIT_FEATURES,
1401 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1402 .probe = marvell_probe,
fdecf36f 1403 .config_init = &m88e1121_config_init,
337ac9d5 1404 .config_aneg = &m88e1318_config_aneg,
3ff1c259
CC		 1405 .read_status = &marvell_read_status,
1406 .ack_interrupt = &marvell_ack_interrupt,
1407 .config_intr = &marvell_config_intr,
1408 .did_interrupt = &m88e1121_did_interrupt,
3871c387
MS		 1409 .get_wol = &m88e1318_get_wol,
1410 .set_wol = &m88e1318_set_wol,
0898b448
SH		 1411 .resume = &genphy_resume,
1412 .suspend = &genphy_suspend,
d2fa47d9
AL		 1413 .get_sset_count = marvell_get_sset_count,
1414 .get_strings = marvell_get_strings,
1415 .get_stats = marvell_get_stats,
3ff1c259 1416 },
e5479239 1417 {
2f495c39
BH		 1418 .phy_id = MARVELL_PHY_ID_88E1145,
1419 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 1420 .name = "Marvell 88E1145",
1421 .features = PHY_GBIT_FEATURES,
1422 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1423 .probe = marvell_probe,
e5479239
OJ		 1424 .config_init = &m88e1145_config_init,
1425 .config_aneg = &marvell_config_aneg,
1426 .read_status = &genphy_read_status,
1427 .ack_interrupt = &marvell_ack_interrupt,
1428 .config_intr = &marvell_config_intr,
0898b448
SH		 1429 .resume = &genphy_resume,
1430 .suspend = &genphy_suspend,
d2fa47d9
AL		 1431 .get_sset_count = marvell_get_sset_count,
1432 .get_strings = marvell_get_strings,
1433 .get_stats = marvell_get_stats,
ac8c635a 1434 },
90600732
DD		 1435 {
1436 .phy_id = MARVELL_PHY_ID_88E1149R,
1437 .phy_id_mask = MARVELL_PHY_ID_MASK,
1438 .name = "Marvell 88E1149R",
1439 .features = PHY_GBIT_FEATURES,
1440 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1441 .probe = marvell_probe,
90600732
DD		 1442 .config_init = &m88e1149_config_init,
1443 .config_aneg = &m88e1118_config_aneg,
1444 .read_status = &genphy_read_status,
1445 .ack_interrupt = &marvell_ack_interrupt,
1446 .config_intr = &marvell_config_intr,
0898b448
SH		 1447 .resume = &genphy_resume,
1448 .suspend = &genphy_suspend,
d2fa47d9
AL		 1449 .get_sset_count = marvell_get_sset_count,
1450 .get_strings = marvell_get_strings,
1451 .get_stats = marvell_get_stats,
90600732 1452 },
ac8c635a 1453 {
2f495c39
BH		 1454 .phy_id = MARVELL_PHY_ID_88E1240,
1455 .phy_id_mask = MARVELL_PHY_ID_MASK,
ac8c635a
OJ		 1456 .name = "Marvell 88E1240",
1457 .features = PHY_GBIT_FEATURES,
1458 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1459 .probe = marvell_probe,
ac8c635a
OJ		 1460 .config_init = &m88e1111_config_init,
1461 .config_aneg = &marvell_config_aneg,
1462 .read_status = &genphy_read_status,
1463 .ack_interrupt = &marvell_ack_interrupt,
1464 .config_intr = &marvell_config_intr,
0898b448
SH		 1465 .resume = &genphy_resume,
1466 .suspend = &genphy_suspend,
d2fa47d9
AL		 1467 .get_sset_count = marvell_get_sset_count,
1468 .get_strings = marvell_get_strings,
1469 .get_stats = marvell_get_stats,
ac8c635a 1470 },
3da09a51
MS		 1471 {
1472 .phy_id = MARVELL_PHY_ID_88E1116R,
1473 .phy_id_mask = MARVELL_PHY_ID_MASK,
1474 .name = "Marvell 88E1116R",
1475 .features = PHY_GBIT_FEATURES,
1476 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1477 .probe = marvell_probe,
3da09a51
MS		 1478 .config_init = &m88e1116r_config_init,
1479 .config_aneg = &genphy_config_aneg,
1480 .read_status = &genphy_read_status,
1481 .ack_interrupt = &marvell_ack_interrupt,
1482 .config_intr = &marvell_config_intr,
0898b448
SH		 1483 .resume = &genphy_resume,
1484 .suspend = &genphy_suspend,
d2fa47d9
AL		 1485 .get_sset_count = marvell_get_sset_count,
1486 .get_strings = marvell_get_strings,
1487 .get_stats = marvell_get_stats,
3da09a51 1488 },
10e24caa
MS		 1489 {
1490 .phy_id = MARVELL_PHY_ID_88E1510,
1491 .phy_id_mask = MARVELL_PHY_ID_MASK,
1492 .name = "Marvell 88E1510",
6cfb3bcc 1493 .features = PHY_GBIT_FEATURES | SUPPORTED_FIBRE,
10e24caa 1494 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1495 .probe = marvell_probe,
930b37ee 1496 .config_init = &m88e1510_config_init,
10e24caa
MS		 1497 .config_aneg = &m88e1510_config_aneg,
1498 .read_status = &marvell_read_status,
1499 .ack_interrupt = &marvell_ack_interrupt,
1500 .config_intr = &marvell_config_intr,
1501 .did_interrupt = &m88e1121_did_interrupt,
0898b448
SH		 1502 .resume = &genphy_resume,
1503 .suspend = &genphy_suspend,
d2fa47d9
AL		 1504 .get_sset_count = marvell_get_sset_count,
1505 .get_strings = marvell_get_strings,
1506 .get_stats = marvell_get_stats,
10e24caa 1507 },
819ec8e1
AL		 1508 {
1509 .phy_id = MARVELL_PHY_ID_88E1540,
1510 .phy_id_mask = MARVELL_PHY_ID_MASK,
1511 .name = "Marvell 88E1540",
1512 .features = PHY_GBIT_FEATURES,
1513 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1514 .probe = marvell_probe,
79be1a1c 1515 .config_init = &marvell_config_init,
819ec8e1
AL		 1516 .config_aneg = &m88e1510_config_aneg,
1517 .read_status = &marvell_read_status,
1518 .ack_interrupt = &marvell_ack_interrupt,
1519 .config_intr = &marvell_config_intr,
1520 .did_interrupt = &m88e1121_did_interrupt,
1521 .resume = &genphy_resume,
1522 .suspend = &genphy_suspend,
d2fa47d9
AL		 1523 .get_sset_count = marvell_get_sset_count,
1524 .get_strings = marvell_get_strings,
1525 .get_stats = marvell_get_stats,
819ec8e1 1526 },
6b358aed
SH		 1527 {
1528 .phy_id = MARVELL_PHY_ID_88E3016,
1529 .phy_id_mask = MARVELL_PHY_ID_MASK,
1530 .name = "Marvell 88E3016",
1531 .features = PHY_BASIC_FEATURES,
1532 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1533 .probe = marvell_probe,
6b358aed
SH		 1534 .config_aneg = &genphy_config_aneg,
1535 .config_init = &m88e3016_config_init,
1536 .aneg_done = &marvell_aneg_done,
1537 .read_status = &marvell_read_status,
1538 .ack_interrupt = &marvell_ack_interrupt,
1539 .config_intr = &marvell_config_intr,
1540 .did_interrupt = &m88e1121_did_interrupt,
1541 .resume = &genphy_resume,
1542 .suspend = &genphy_suspend,
d2fa47d9
AL		 1543 .get_sset_count = marvell_get_sset_count,
1544 .get_strings = marvell_get_strings,
1545 .get_stats = marvell_get_stats,
6b358aed 1546 },
00db8189
AF		 1547};
1548
50fd7150 1549module_phy_driver(marvell_drivers);
4e4f10f6 1550
cf93c945 1551static struct mdio_device_id __maybe_unused marvell_tbl[] = {
f5e1cabf
MS		 1552 { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
1553 { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
1554 { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
1555 { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
1556 { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
1557 { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
1558 { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
1559 { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
1560 { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
3da09a51 1561 { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
10e24caa 1562 { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
819ec8e1 1563 { MARVELL_PHY_ID_88E1540, MARVELL_PHY_ID_MASK },
6b358aed 1564 { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
4e4f10f6
DW		 1565 { }
1566};
1567
1568MODULE_DEVICE_TABLE(mdio, marvell_tbl);
Michael's Linux tree.