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netxen: remove writeq/readq function definitions
[people/ms/linux.git] / drivers / net / phy / marvell.c
CommitLineData
00db8189
AF		 1/*
2 * drivers/net/phy/marvell.c
3 *
4 * Driver for Marvell PHYs
5 *
6 * Author: Andy Fleming
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
9 *
3871c387
MS		 10 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
11 *
00db8189
AF		 12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 */
00db8189 18#include <linux/kernel.h>
00db8189 19#include <linux/string.h>
0b04680f 20#include <linux/ctype.h>
00db8189
AF		 21#include <linux/errno.h>
22#include <linux/unistd.h>
0b04680f 23#include <linux/hwmon.h>
00db8189
AF		 24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/netdevice.h>
28#include <linux/etherdevice.h>
29#include <linux/skbuff.h>
30#include <linux/spinlock.h>
31#include <linux/mm.h>
32#include <linux/module.h>
00db8189
AF		 33#include <linux/mii.h>
34#include <linux/ethtool.h>
35#include <linux/phy.h>
2f495c39 36#include <linux/marvell_phy.h>
cf41a51d 37#include <linux/of.h>
00db8189 38
eea3b201 39#include <linux/io.h>
00db8189 40#include <asm/irq.h>
eea3b201 41#include <linux/uaccess.h>
00db8189 42
27d916d6 43#define MII_MARVELL_PHY_PAGE 22
52295666
AL		 44#define MII_MARVELL_COPPER_PAGE 0x00
45#define MII_MARVELL_FIBER_PAGE 0x01
46#define MII_MARVELL_MSCR_PAGE 0x02
47#define MII_MARVELL_LED_PAGE 0x03
48#define MII_MARVELL_MISC_TEST_PAGE 0x06
49#define MII_MARVELL_WOL_PAGE 0x11
27d916d6 50
00db8189
AF		 51#define MII_M1011_IEVENT 0x13
52#define MII_M1011_IEVENT_CLEAR 0x0000
53
54#define MII_M1011_IMASK 0x12
55#define MII_M1011_IMASK_INIT 0x6400
56#define MII_M1011_IMASK_CLEAR 0x0000
57
76884679 58#define MII_M1011_PHY_SCR 0x10
239aa55b
DT		 59#define MII_M1011_PHY_SCR_MDI 0x0000
60#define MII_M1011_PHY_SCR_MDI_X 0x0020
76884679
AF		 61#define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
62
b0224175 63#define MII_M1145_PHY_EXT_SR 0x1b
76884679
AF		 64#define MII_M1145_PHY_EXT_CR 0x14
65#define MII_M1145_RGMII_RX_DELAY 0x0080
66#define MII_M1145_RGMII_TX_DELAY 0x0002
b0224175
VND		 67#define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
68#define MII_M1145_HWCFG_MODE_MASK 0xf
69#define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
76884679 70
99d881f9
VB		 71#define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
72#define MII_M1145_HWCFG_MODE_MASK 0xf
73#define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
74
76884679
AF		 75#define MII_M1111_PHY_LED_CONTROL 0x18
76#define MII_M1111_PHY_LED_DIRECT 0x4100
77#define MII_M1111_PHY_LED_COMBINE 0x411c
895ee682
KP		 78#define MII_M1111_PHY_EXT_CR 0x14
79#define MII_M1111_RX_DELAY 0x80
80#define MII_M1111_TX_DELAY 0x2
81#define MII_M1111_PHY_EXT_SR 0x1b
be937f1f
AS		 82
83#define MII_M1111_HWCFG_MODE_MASK 0xf
84#define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
85#define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
4117b5be 86#define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
5f8cbc13 87#define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
be937f1f
AS		 88#define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
89#define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
90
c477d044
CC		 91#define MII_88E1121_PHY_MSCR_REG 21
92#define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
93#define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
94#define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
95
0b04680f
AL		 96#define MII_88E1121_MISC_TEST 0x1a
97#define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK 0x1f00
98#define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT 8
99#define MII_88E1510_MISC_TEST_TEMP_IRQ_EN BIT(7)
100#define MII_88E1510_MISC_TEST_TEMP_IRQ BIT(6)
101#define MII_88E1121_MISC_TEST_TEMP_SENSOR_EN BIT(5)
102#define MII_88E1121_MISC_TEST_TEMP_MASK 0x1f
103
104#define MII_88E1510_TEMP_SENSOR 0x1b
105#define MII_88E1510_TEMP_SENSOR_MASK 0xff
106
337ac9d5
CC		 107#define MII_88E1318S_PHY_MSCR1_REG 16
108#define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
3ff1c259 109
3871c387
MS		 110/* Copper Specific Interrupt Enable Register */
111#define MII_88E1318S_PHY_CSIER 0x12
112/* WOL Event Interrupt Enable */
113#define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
114
115/* LED Timer Control Register */
3871c387
MS		 116#define MII_88E1318S_PHY_LED_TCR 0x12
117#define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
118#define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
119#define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
120
121/* Magic Packet MAC address registers */
122#define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
123#define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
124#define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
125
3871c387
MS		 126#define MII_88E1318S_PHY_WOL_CTRL 0x10
127#define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
128#define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
129
140bc929 130#define MII_88E1121_PHY_LED_CTRL 16
140bc929 131#define MII_88E1121_PHY_LED_DEF 0x0030
140bc929 132
be937f1f
AS		 133#define MII_M1011_PHY_STATUS 0x11
134#define MII_M1011_PHY_STATUS_1000 0x8000
135#define MII_M1011_PHY_STATUS_100 0x4000
136#define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
137#define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
138#define MII_M1011_PHY_STATUS_RESOLVED 0x0800
139#define MII_M1011_PHY_STATUS_LINK 0x0400
140
3da09a51
MS		 141#define MII_M1116R_CONTROL_REG_MAC 21
142
6b358aed
SH		 143#define MII_88E3016_PHY_SPEC_CTRL 0x10
144#define MII_88E3016_DISABLE_SCRAMBLER 0x0200
145#define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
76884679 146
930b37ee
SR		 147#define MII_88E1510_GEN_CTRL_REG_1 0x14
148#define MII_88E1510_GEN_CTRL_REG_1_MODE_MASK 0x7
149#define MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII 0x1 /* SGMII to copper */
150#define MII_88E1510_GEN_CTRL_REG_1_RESET 0x8000 /* Soft reset */
151
6cfb3bcc
CAC		 152#define LPA_FIBER_1000HALF 0x40
153#define LPA_FIBER_1000FULL 0x20
154
155#define LPA_PAUSE_FIBER 0x180
156#define LPA_PAUSE_ASYM_FIBER 0x100
157
158#define ADVERTISE_FIBER_1000HALF 0x40
159#define ADVERTISE_FIBER_1000FULL 0x20
160
161#define ADVERTISE_PAUSE_FIBER 0x180
162#define ADVERTISE_PAUSE_ASYM_FIBER 0x100
163
164#define REGISTER_LINK_STATUS 0x400
2170fef7 165#define NB_FIBER_STATS 1
6cfb3bcc 166
00db8189
AF		 167MODULE_DESCRIPTION("Marvell PHY driver");
168MODULE_AUTHOR("Andy Fleming");
169MODULE_LICENSE("GPL");
170
d2fa47d9
AL		 171struct marvell_hw_stat {
172 const char *string;
173 u8 page;
174 u8 reg;
175 u8 bits;
176};
177
178static struct marvell_hw_stat marvell_hw_stats[] = {
2170fef7 179 { "phy_receive_errors_copper", 0, 21, 16},
d2fa47d9 180 { "phy_idle_errors", 0, 10, 8 },
2170fef7 181 { "phy_receive_errors_fiber", 1, 21, 16},
d2fa47d9
AL		 182};
183
184struct marvell_priv {
185 u64 stats[ARRAY_SIZE(marvell_hw_stats)];
0b04680f
AL		 186 char *hwmon_name;
187 struct device *hwmon_dev;
d2fa47d9
AL		 188};
189
6427bb2d
AL		 190static int marvell_get_page(struct phy_device *phydev)
191{
192 return phy_read(phydev, MII_MARVELL_PHY_PAGE);
193}
194
195static int marvell_set_page(struct phy_device *phydev, int page)
196{
197 return phy_write(phydev, MII_MARVELL_PHY_PAGE, page);
198}
199
53798328
AL		 200static int marvell_get_set_page(struct phy_device *phydev, int page)
201{
202 int oldpage = marvell_get_page(phydev);
203
204 if (oldpage < 0)
205 return oldpage;
206
207 if (page != oldpage)
208 return marvell_set_page(phydev, page);
209
210 return 0;
211}
212
00db8189
AF		 213static int marvell_ack_interrupt(struct phy_device *phydev)
214{
215 int err;
216
217 /* Clear the interrupts by reading the reg */
218 err = phy_read(phydev, MII_M1011_IEVENT);
219
220 if (err < 0)
221 return err;
222
223 return 0;
224}
225
226static int marvell_config_intr(struct phy_device *phydev)
227{
228 int err;
229
76884679 230 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
23beb38f
AL		 231 err = phy_write(phydev, MII_M1011_IMASK,
232 MII_M1011_IMASK_INIT);
00db8189 233 else
23beb38f
AL		 234 err = phy_write(phydev, MII_M1011_IMASK,
235 MII_M1011_IMASK_CLEAR);
00db8189
AF		 236
237 return err;
238}
239
239aa55b
DT		 240static int marvell_set_polarity(struct phy_device *phydev, int polarity)
241{
242 int reg;
243 int err;
244 int val;
245
246 /* get the current settings */
247 reg = phy_read(phydev, MII_M1011_PHY_SCR);
248 if (reg < 0)
249 return reg;
250
251 val = reg;
252 val &= ~MII_M1011_PHY_SCR_AUTO_CROSS;
253 switch (polarity) {
254 case ETH_TP_MDI:
255 val |= MII_M1011_PHY_SCR_MDI;
256 break;
257 case ETH_TP_MDI_X:
258 val |= MII_M1011_PHY_SCR_MDI_X;
259 break;
260 case ETH_TP_MDI_AUTO:
261 case ETH_TP_MDI_INVALID:
262 default:
263 val |= MII_M1011_PHY_SCR_AUTO_CROSS;
264 break;
265 }
266
267 if (val != reg) {
268 /* Set the new polarity value in the register */
269 err = phy_write(phydev, MII_M1011_PHY_SCR, val);
270 if (err)
271 return err;
272 }
273
274 return 0;
275}
276
00db8189
AF		 277static int marvell_config_aneg(struct phy_device *phydev)
278{
279 int err;
280
4e26c5c3 281 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
76884679
AF		 282 if (err < 0)
283 return err;
284
285 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
286 MII_M1111_PHY_LED_DIRECT);
287 if (err < 0)
288 return err;
00db8189
AF		 289
290 err = genphy_config_aneg(phydev);
8ff44985
AV		 291 if (err < 0)
292 return err;
00db8189 293
8ff44985
AV		 294 if (phydev->autoneg != AUTONEG_ENABLE) {
295 int bmcr;
296
0c3439bc 297 /* A write to speed/duplex bits (that is performed by
8ff44985
AV		 298 * genphy_config_aneg() call above) must be followed by
299 * a software reset. Otherwise, the write has no effect.
300 */
301 bmcr = phy_read(phydev, MII_BMCR);
302 if (bmcr < 0)
303 return bmcr;
304
305 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
306 if (err < 0)
307 return err;
308 }
309
310 return 0;
00db8189
AF		 311}
312
f2899788
AL		 313static int m88e1101_config_aneg(struct phy_device *phydev)
314{
315 int err;
316
317 /* This Marvell PHY has an errata which requires
318 * that certain registers get written in order
319 * to restart autonegotiation
320 */
321 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
322
323 if (err < 0)
324 return err;
325
326 err = phy_write(phydev, 0x1d, 0x1f);
327 if (err < 0)
328 return err;
329
330 err = phy_write(phydev, 0x1e, 0x200c);
331 if (err < 0)
332 return err;
333
334 err = phy_write(phydev, 0x1d, 0x5);
335 if (err < 0)
336 return err;
337
338 err = phy_write(phydev, 0x1e, 0);
339 if (err < 0)
340 return err;
341
342 err = phy_write(phydev, 0x1e, 0x100);
343 if (err < 0)
344 return err;
345
346 return marvell_config_aneg(phydev);
347}
348
3ec0a0f1
HK		 349static int m88e1111_config_aneg(struct phy_device *phydev)
350{
351 int err;
352
353 /* The Marvell PHY has an errata which requires
354 * that certain registers get written in order
355 * to restart autonegotiation
356 */
357 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
358
4e26c5c3 359 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
3ec0a0f1
HK		 360 if (err < 0)
361 return err;
362
363 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
364 MII_M1111_PHY_LED_DIRECT);
365 if (err < 0)
366 return err;
367
368 err = genphy_config_aneg(phydev);
369 if (err < 0)
370 return err;
371
372 if (phydev->autoneg != AUTONEG_ENABLE) {
373 int bmcr;
374
375 /* A write to speed/duplex bits (that is performed by
376 * genphy_config_aneg() call above) must be followed by
377 * a software reset. Otherwise, the write has no effect.
378 */
379 bmcr = phy_read(phydev, MII_BMCR);
380 if (bmcr < 0)
381 return bmcr;
382
383 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
384 if (err < 0)
385 return err;
386 }
387
388 return 0;
389}
390
cf41a51d 391#ifdef CONFIG_OF_MDIO
0c3439bc 392/* Set and/or override some configuration registers based on the
cf41a51d
DD		 393 * marvell,reg-init property stored in the of_node for the phydev.
394 *
395 * marvell,reg-init = <reg-page reg mask value>,...;
396 *
397 * There may be one or more sets of <reg-page reg mask value>:
398 *
399 * reg-page: which register bank to use.
400 * reg: the register.
401 * mask: if non-zero, ANDed with existing register value.
402 * value: ORed with the masked value and written to the regiser.
403 *
404 */
405static int marvell_of_reg_init(struct phy_device *phydev)
406{
407 const __be32 *paddr;
b5718b5a 408 int len, i, saved_page, current_page, ret;
cf41a51d 409
e5a03bfd 410 if (!phydev->mdio.dev.of_node)
cf41a51d
DD		 411 return 0;
412
e5a03bfd
AL		 413 paddr = of_get_property(phydev->mdio.dev.of_node,
414 "marvell,reg-init", &len);
cf41a51d
DD		 415 if (!paddr || len < (4 * sizeof(*paddr)))
416 return 0;
417
6427bb2d 418 saved_page = marvell_get_page(phydev);
cf41a51d
DD		 419 if (saved_page < 0)
420 return saved_page;
cf41a51d
DD		 421 current_page = saved_page;
422
423 ret = 0;
424 len /= sizeof(*paddr);
425 for (i = 0; i < len - 3; i += 4) {
6427bb2d 426 u16 page = be32_to_cpup(paddr + i);
cf41a51d
DD		 427 u16 reg = be32_to_cpup(paddr + i + 1);
428 u16 mask = be32_to_cpup(paddr + i + 2);
429 u16 val_bits = be32_to_cpup(paddr + i + 3);
430 int val;
431
6427bb2d
AL		 432 if (page != current_page) {
433 current_page = page;
434 ret = marvell_set_page(phydev, page);
cf41a51d
DD		 435 if (ret < 0)
436 goto err;
437 }
438
439 val = 0;
440 if (mask) {
441 val = phy_read(phydev, reg);
442 if (val < 0) {
443 ret = val;
444 goto err;
445 }
446 val &= mask;
447 }
448 val |= val_bits;
449
450 ret = phy_write(phydev, reg, val);
451 if (ret < 0)
452 goto err;
cf41a51d
DD		 453 }
454err:
b5718b5a 455 if (current_page != saved_page) {
6427bb2d 456 i = marvell_set_page(phydev, saved_page);
cf41a51d
DD		 457 if (ret == 0)
458 ret = i;
459 }
460 return ret;
461}
462#else
463static int marvell_of_reg_init(struct phy_device *phydev)
464{
465 return 0;
466}
467#endif /* CONFIG_OF_MDIO */
468
140bc929
SP		 469static int m88e1121_config_aneg(struct phy_device *phydev)
470{
c477d044
CC		 471 int err, oldpage, mscr;
472
52295666 473 oldpage = marvell_get_set_page(phydev, MII_MARVELL_MSCR_PAGE);
53798328
AL		 474 if (oldpage < 0)
475 return oldpage;
be8c6480 476
32a64161 477 if (phy_interface_is_rgmii(phydev)) {
be8c6480
AP		 478 mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) &
479 MII_88E1121_PHY_MSCR_DELAY_MASK;
480
481 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
482 mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY |
483 MII_88E1121_PHY_MSCR_TX_DELAY);
484 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
485 mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
486 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
487 mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
488
489 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
490 if (err < 0)
491 return err;
492 }
c477d044 493
6427bb2d 494 marvell_set_page(phydev, oldpage);
140bc929
SP		 495
496 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
497 if (err < 0)
498 return err;
499
500 err = phy_write(phydev, MII_M1011_PHY_SCR,
501 MII_M1011_PHY_SCR_AUTO_CROSS);
502 if (err < 0)
503 return err;
504
fdecf36f 505 return genphy_config_aneg(phydev);
140bc929
SP		 506}
507
337ac9d5 508static int m88e1318_config_aneg(struct phy_device *phydev)
3ff1c259
CC		 509{
510 int err, oldpage, mscr;
511
52295666 512 oldpage = marvell_get_set_page(phydev, MII_MARVELL_MSCR_PAGE);
53798328
AL		 513 if (oldpage < 0)
514 return oldpage;
3ff1c259 515
337ac9d5
CC		 516 mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG);
517 mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD;
3ff1c259 518
337ac9d5 519 err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr);
3ff1c259
CC		 520 if (err < 0)
521 return err;
522
6427bb2d 523 err = marvell_set_page(phydev, oldpage);
3ff1c259
CC		 524 if (err < 0)
525 return err;
526
527 return m88e1121_config_aneg(phydev);
528}
529
78301ebe
CAC		 530/**
531 * ethtool_adv_to_fiber_adv_t
532 * @ethadv: the ethtool advertisement settings
533 *
534 * A small helper function that translates ethtool advertisement
535 * settings to phy autonegotiation advertisements for the
536 * MII_ADV register for fiber link.
537 */
538static inline u32 ethtool_adv_to_fiber_adv_t(u32 ethadv)
539{
540 u32 result = 0;
541
542 if (ethadv & ADVERTISED_1000baseT_Half)
543 result |= ADVERTISE_FIBER_1000HALF;
544 if (ethadv & ADVERTISED_1000baseT_Full)
545 result |= ADVERTISE_FIBER_1000FULL;
546
547 if ((ethadv & ADVERTISE_PAUSE_ASYM) && (ethadv & ADVERTISE_PAUSE_CAP))
548 result |= LPA_PAUSE_ASYM_FIBER;
549 else if (ethadv & ADVERTISE_PAUSE_CAP)
550 result |= (ADVERTISE_PAUSE_FIBER
551 & (~ADVERTISE_PAUSE_ASYM_FIBER));
552
553 return result;
554}
555
556/**
557 * marvell_config_aneg_fiber - restart auto-negotiation or write BMCR
558 * @phydev: target phy_device struct
559 *
560 * Description: If auto-negotiation is enabled, we configure the
561 * advertising, and then restart auto-negotiation. If it is not
562 * enabled, then we write the BMCR. Adapted for fiber link in
563 * some Marvell's devices.
564 */
565static int marvell_config_aneg_fiber(struct phy_device *phydev)
566{
567 int changed = 0;
568 int err;
569 int adv, oldadv;
570 u32 advertise;
571
572 if (phydev->autoneg != AUTONEG_ENABLE)
573 return genphy_setup_forced(phydev);
574
575 /* Only allow advertising what this PHY supports */
576 phydev->advertising &= phydev->supported;
577 advertise = phydev->advertising;
578
579 /* Setup fiber advertisement */
580 adv = phy_read(phydev, MII_ADVERTISE);
581 if (adv < 0)
582 return adv;
583
584 oldadv = adv;
585 adv &= ~(ADVERTISE_FIBER_1000HALF | ADVERTISE_FIBER_1000FULL
586 | LPA_PAUSE_FIBER);
587 adv |= ethtool_adv_to_fiber_adv_t(advertise);
588
589 if (adv != oldadv) {
590 err = phy_write(phydev, MII_ADVERTISE, adv);
591 if (err < 0)
592 return err;
593
594 changed = 1;
595 }
596
597 if (changed == 0) {
598 /* Advertisement hasn't changed, but maybe aneg was never on to
599 * begin with? Or maybe phy was isolated?
600 */
601 int ctl = phy_read(phydev, MII_BMCR);
602
603 if (ctl < 0)
604 return ctl;
605
606 if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE))
607 changed = 1; /* do restart aneg */
608 }
609
610 /* Only restart aneg if we are advertising something different
611 * than we were before.
612 */
613 if (changed > 0)
614 changed = genphy_restart_aneg(phydev);
615
616 return changed;
617}
618
10e24caa
MS		 619static int m88e1510_config_aneg(struct phy_device *phydev)
620{
621 int err;
622
52295666 623 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
78301ebe
CAC		 624 if (err < 0)
625 goto error;
626
627 /* Configure the copper link first */
10e24caa
MS		 628 err = m88e1318_config_aneg(phydev);
629 if (err < 0)
78301ebe 630 goto error;
10e24caa 631
78301ebe 632 /* Then the fiber link */
52295666 633 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
78301ebe
CAC		 634 if (err < 0)
635 goto error;
636
637 err = marvell_config_aneg_fiber(phydev);
638 if (err < 0)
639 goto error;
640
52295666 641 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
78301ebe
CAC		 642
643error:
52295666 644 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
78301ebe 645 return err;
79be1a1c
CG		 646}
647
648static int marvell_config_init(struct phy_device *phydev)
649{
650 /* Set registers from marvell,reg-init DT property */
10e24caa
MS		 651 return marvell_of_reg_init(phydev);
652}
653
3da09a51
MS		 654static int m88e1116r_config_init(struct phy_device *phydev)
655{
656 int temp;
657 int err;
658
659 temp = phy_read(phydev, MII_BMCR);
660 temp |= BMCR_RESET;
661 err = phy_write(phydev, MII_BMCR, temp);
662 if (err < 0)
663 return err;
664
665 mdelay(500);
666
52295666 667 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
3da09a51
MS		 668 if (err < 0)
669 return err;
670
671 temp = phy_read(phydev, MII_M1011_PHY_SCR);
672 temp |= (7 << 12); /* max number of gigabit attempts */
673 temp |= (1 << 11); /* enable downshift */
674 temp |= MII_M1011_PHY_SCR_AUTO_CROSS;
675 err = phy_write(phydev, MII_M1011_PHY_SCR, temp);
676 if (err < 0)
677 return err;
678
52295666 679 err = marvell_set_page(phydev, MII_MARVELL_MSCR_PAGE);
3da09a51
MS		 680 if (err < 0)
681 return err;
682 temp = phy_read(phydev, MII_M1116R_CONTROL_REG_MAC);
683 temp |= (1 << 5);
684 temp |= (1 << 4);
685 err = phy_write(phydev, MII_M1116R_CONTROL_REG_MAC, temp);
686 if (err < 0)
687 return err;
52295666 688 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
3da09a51
MS		 689 if (err < 0)
690 return err;
691
692 temp = phy_read(phydev, MII_BMCR);
693 temp |= BMCR_RESET;
694 err = phy_write(phydev, MII_BMCR, temp);
695 if (err < 0)
696 return err;
697
698 mdelay(500);
699
79be1a1c 700 return marvell_config_init(phydev);
3da09a51
MS		 701}
702
6b358aed
SH		 703static int m88e3016_config_init(struct phy_device *phydev)
704{
705 int reg;
706
707 /* Enable Scrambler and Auto-Crossover */
708 reg = phy_read(phydev, MII_88E3016_PHY_SPEC_CTRL);
709 if (reg < 0)
710 return reg;
711
712 reg &= ~MII_88E3016_DISABLE_SCRAMBLER;
713 reg |= MII_88E3016_AUTO_MDIX_CROSSOVER;
714
715 reg = phy_write(phydev, MII_88E3016_PHY_SPEC_CTRL, reg);
716 if (reg < 0)
717 return reg;
718
79be1a1c 719 return marvell_config_init(phydev);
6b358aed
SH		 720}
721
e1dde8dc 722static int m88e1111_config_init_rgmii(struct phy_device *phydev)
895ee682
KP		 723{
724 int err;
be937f1f 725 int temp;
be937f1f 726
e1dde8dc
AL		 727 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
728 if (temp < 0)
729 return temp;
895ee682 730
e1dde8dc
AL		 731 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
732 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
733 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
734 temp &= ~MII_M1111_TX_DELAY;
735 temp |= MII_M1111_RX_DELAY;
736 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
737 temp &= ~MII_M1111_RX_DELAY;
738 temp |= MII_M1111_TX_DELAY;
739 }
895ee682 740
e1dde8dc
AL		 741 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
742 if (err < 0)
743 return err;
9daf5a76 744
e1dde8dc
AL		 745 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
746 if (temp < 0)
747 return temp;
895ee682 748
e1dde8dc 749 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
be937f1f 750
e1dde8dc
AL		 751 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
752 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
753 else
754 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
895ee682 755
e1dde8dc
AL		 756 return phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
757}
895ee682 758
e1dde8dc
AL		 759static int m88e1111_config_init_sgmii(struct phy_device *phydev)
760{
761 int err;
762 int temp;
4117b5be 763
e1dde8dc
AL		 764 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
765 if (temp < 0)
766 return temp;
4117b5be 767
e1dde8dc
AL		 768 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
769 temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
770 temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
07151bc9 771
e1dde8dc
AL		 772 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
773 if (err < 0)
774 return err;
07151bc9 775
e1dde8dc 776 /* make sure copper is selected */
52295666 777 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
e1dde8dc 778}
5f8cbc13 779
e1dde8dc
AL		 780static int m88e1111_config_init_rtbi(struct phy_device *phydev)
781{
782 int err;
783 int temp;
784
785 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
786 if (temp < 0)
787 return temp;
788
789 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
790 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
791 if (err < 0)
792 return err;
793
794 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
795 if (temp < 0)
796 return temp;
797
798 temp &= ~(MII_M1111_HWCFG_MODE_MASK |
799 MII_M1111_HWCFG_FIBER_COPPER_RES);
800 temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
801
802 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
803 if (err < 0)
804 return err;
805
806 /* soft reset */
807 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
808 if (err < 0)
809 return err;
810
811 do
812 temp = phy_read(phydev, MII_BMCR);
813 while (temp & BMCR_RESET);
814
815 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
816 if (temp < 0)
817 return temp;
818
819 temp &= ~(MII_M1111_HWCFG_MODE_MASK |
820 MII_M1111_HWCFG_FIBER_COPPER_RES);
821 temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI |
822 MII_M1111_HWCFG_FIBER_COPPER_AUTO;
823
824 return phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
825}
826
827static int m88e1111_config_init(struct phy_device *phydev)
828{
829 int err;
830
831 if (phy_interface_is_rgmii(phydev)) {
832 err = m88e1111_config_init_rgmii(phydev);
833 if (err)
5f8cbc13 834 return err;
e1dde8dc 835 }
5f8cbc13 836
e1dde8dc
AL		 837 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
838 err = m88e1111_config_init_sgmii(phydev);
5f8cbc13
LYB		 839 if (err < 0)
840 return err;
e1dde8dc 841 }
5f8cbc13 842
e1dde8dc
AL		 843 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
844 err = m88e1111_config_init_rtbi(phydev);
5f8cbc13
LYB		 845 if (err < 0)
846 return err;
847 }
848
cf41a51d
DD		 849 err = marvell_of_reg_init(phydev);
850 if (err < 0)
851 return err;
5f8cbc13 852
cc90cb3b 853 return phy_write(phydev, MII_BMCR, BMCR_RESET);
895ee682
KP		 854}
855
fdecf36f
CG		 856static int m88e1121_config_init(struct phy_device *phydev)
857{
858 int err, oldpage;
859
52295666 860 oldpage = marvell_get_set_page(phydev, MII_MARVELL_LED_PAGE);
53798328
AL		 861 if (oldpage < 0)
862 return oldpage;
fdecf36f
CG		 863
864 /* Default PHY LED config: LED[0] .. Link, LED[1] .. Activity */
865 err = phy_write(phydev, MII_88E1121_PHY_LED_CTRL,
866 MII_88E1121_PHY_LED_DEF);
867 if (err < 0)
868 return err;
869
6427bb2d 870 marvell_set_page(phydev, oldpage);
fdecf36f
CG		 871
872 /* Set marvell,reg-init configuration from device tree */
873 return marvell_config_init(phydev);
874}
875
407353ec
CG		 876static int m88e1510_config_init(struct phy_device *phydev)
877{
878 int err;
879 int temp;
880
881 /* SGMII-to-Copper mode initialization */
882 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
883 /* Select page 18 */
6427bb2d 884 err = marvell_set_page(phydev, 18);
407353ec
CG		 885 if (err < 0)
886 return err;
887
888 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
889 temp = phy_read(phydev, MII_88E1510_GEN_CTRL_REG_1);
890 temp &= ~MII_88E1510_GEN_CTRL_REG_1_MODE_MASK;
891 temp |= MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII;
892 err = phy_write(phydev, MII_88E1510_GEN_CTRL_REG_1, temp);
893 if (err < 0)
894 return err;
895
896 /* PHY reset is necessary after changing MODE[2:0] */
897 temp |= MII_88E1510_GEN_CTRL_REG_1_RESET;
898 err = phy_write(phydev, MII_88E1510_GEN_CTRL_REG_1, temp);
899 if (err < 0)
900 return err;
901
902 /* Reset page selection */
52295666 903 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
407353ec
CG		 904 if (err < 0)
905 return err;
906 }
907
fdecf36f 908 return m88e1121_config_init(phydev);
407353ec
CG		 909}
910
605f196e
RM		 911static int m88e1118_config_aneg(struct phy_device *phydev)
912{
913 int err;
914
915 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
916 if (err < 0)
917 return err;
918
919 err = phy_write(phydev, MII_M1011_PHY_SCR,
920 MII_M1011_PHY_SCR_AUTO_CROSS);
921 if (err < 0)
922 return err;
923
924 err = genphy_config_aneg(phydev);
925 return 0;
926}
927
928static int m88e1118_config_init(struct phy_device *phydev)
929{
930 int err;
931
932 /* Change address */
52295666 933 err = marvell_set_page(phydev, MII_MARVELL_MSCR_PAGE);
605f196e
RM		 934 if (err < 0)
935 return err;
936
937 /* Enable 1000 Mbit */
938 err = phy_write(phydev, 0x15, 0x1070);
939 if (err < 0)
940 return err;
941
942 /* Change address */
52295666 943 err = marvell_set_page(phydev, MII_MARVELL_LED_PAGE);
605f196e
RM		 944 if (err < 0)
945 return err;
946
947 /* Adjust LED Control */
2f495c39
BH		 948 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
949 err = phy_write(phydev, 0x10, 0x1100);
950 else
951 err = phy_write(phydev, 0x10, 0x021e);
605f196e
RM		 952 if (err < 0)
953 return err;
954
cf41a51d
DD		 955 err = marvell_of_reg_init(phydev);
956 if (err < 0)
957 return err;
958
605f196e 959 /* Reset address */
52295666 960 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
605f196e
RM		 961 if (err < 0)
962 return err;
963
cc90cb3b 964 return phy_write(phydev, MII_BMCR, BMCR_RESET);
605f196e
RM		 965}
966
90600732
DD		 967static int m88e1149_config_init(struct phy_device *phydev)
968{
969 int err;
970
971 /* Change address */
52295666 972 err = marvell_set_page(phydev, MII_MARVELL_MSCR_PAGE);
90600732
DD		 973 if (err < 0)
974 return err;
975
976 /* Enable 1000 Mbit */
977 err = phy_write(phydev, 0x15, 0x1048);
978 if (err < 0)
979 return err;
980
cf41a51d
DD		 981 err = marvell_of_reg_init(phydev);
982 if (err < 0)
983 return err;
984
90600732 985 /* Reset address */
52295666 986 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
90600732
DD		 987 if (err < 0)
988 return err;
989
cc90cb3b 990 return phy_write(phydev, MII_BMCR, BMCR_RESET);
90600732
DD		 991}
992
e1dde8dc
AL		 993static int m88e1145_config_init_rgmii(struct phy_device *phydev)
994{
995 int err;
996 int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
997
998 if (temp < 0)
999 return temp;
1000
1001 temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
1002
1003 err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
1004 if (err < 0)
1005 return err;
1006
1007 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
1008 err = phy_write(phydev, 0x1d, 0x0012);
1009 if (err < 0)
1010 return err;
1011
1012 temp = phy_read(phydev, 0x1e);
1013 if (temp < 0)
1014 return temp;
1015
1016 temp &= 0xf03f;
1017 temp |= 2 << 9; /* 36 ohm */
1018 temp |= 2 << 6; /* 39 ohm */
1019
1020 err = phy_write(phydev, 0x1e, temp);
1021 if (err < 0)
1022 return err;
1023
1024 err = phy_write(phydev, 0x1d, 0x3);
1025 if (err < 0)
1026 return err;
1027
1028 err = phy_write(phydev, 0x1e, 0x8000);
1029 }
1030 return err;
1031}
1032
1033static int m88e1145_config_init_sgmii(struct phy_device *phydev)
1034{
1035 int temp = phy_read(phydev, MII_M1145_PHY_EXT_SR);
1036
1037 if (temp < 0)
1038 return temp;
1039
1040 temp &= ~MII_M1145_HWCFG_MODE_MASK;
1041 temp |= MII_M1145_HWCFG_MODE_SGMII_NO_CLK;
1042 temp |= MII_M1145_HWCFG_FIBER_COPPER_AUTO;
1043
1044 return phy_write(phydev, MII_M1145_PHY_EXT_SR, temp);
1045}
1046
76884679
AF		 1047static int m88e1145_config_init(struct phy_device *phydev)
1048{
1049 int err;
1050
1051 /* Take care of errata E0 & E1 */
1052 err = phy_write(phydev, 0x1d, 0x001b);
1053 if (err < 0)
1054 return err;
1055
1056 err = phy_write(phydev, 0x1e, 0x418f);
1057 if (err < 0)
1058 return err;
1059
1060 err = phy_write(phydev, 0x1d, 0x0016);
1061 if (err < 0)
1062 return err;
1063
1064 err = phy_write(phydev, 0x1e, 0xa2da);
1065 if (err < 0)
1066 return err;
1067
895ee682 1068 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
e1dde8dc 1069 err = m88e1145_config_init_rgmii(phydev);
76884679
AF		 1070 if (err < 0)
1071 return err;
76884679
AF		 1072 }
1073
b0224175 1074 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
e1dde8dc 1075 err = m88e1145_config_init_sgmii(phydev);
b0224175
VND		 1076 if (err < 0)
1077 return err;
1078 }
1079
cf41a51d
DD		 1080 err = marvell_of_reg_init(phydev);
1081 if (err < 0)
1082 return err;
1083
76884679
AF		 1084 return 0;
1085}
00db8189 1086
6cfb3bcc
CAC		 1087/**
1088 * fiber_lpa_to_ethtool_lpa_t
1089 * @lpa: value of the MII_LPA register for fiber link
1090 *
1091 * A small helper function that translates MII_LPA
1092 * bits to ethtool LP advertisement settings.
1093 */
1094static u32 fiber_lpa_to_ethtool_lpa_t(u32 lpa)
1095{
1096 u32 result = 0;
1097
1098 if (lpa & LPA_FIBER_1000HALF)
1099 result |= ADVERTISED_1000baseT_Half;
1100 if (lpa & LPA_FIBER_1000FULL)
1101 result |= ADVERTISED_1000baseT_Full;
1102
1103 return result;
1104}
1105
1106/**
1107 * marvell_update_link - update link status in real time in @phydev
1108 * @phydev: target phy_device struct
1109 *
1110 * Description: Update the value in phydev->link to reflect the
1111 * current link value.
1112 */
1113static int marvell_update_link(struct phy_device *phydev, int fiber)
1114{
1115 int status;
1116
1117 /* Use the generic register for copper link, or specific
0c3439bc
AL		 1118 * register for fiber case
1119 */
6cfb3bcc
CAC		 1120 if (fiber) {
1121 status = phy_read(phydev, MII_M1011_PHY_STATUS);
1122 if (status < 0)
1123 return status;
1124
1125 if ((status & REGISTER_LINK_STATUS) == 0)
1126 phydev->link = 0;
1127 else
1128 phydev->link = 1;
1129 } else {
1130 return genphy_update_link(phydev);
1131 }
1132
1133 return 0;
1134}
1135
e1dde8dc
AL		 1136static int marvell_read_status_page_an(struct phy_device *phydev,
1137 int fiber)
1138{
1139 int status;
1140 int lpa;
1141 int lpagb;
1142 int adv;
1143
1144 status = phy_read(phydev, MII_M1011_PHY_STATUS);
1145 if (status < 0)
1146 return status;
1147
1148 lpa = phy_read(phydev, MII_LPA);
1149 if (lpa < 0)
1150 return lpa;
1151
1152 lpagb = phy_read(phydev, MII_STAT1000);
1153 if (lpagb < 0)
1154 return lpagb;
1155
1156 adv = phy_read(phydev, MII_ADVERTISE);
1157 if (adv < 0)
1158 return adv;
1159
1160 lpa &= adv;
1161
1162 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
1163 phydev->duplex = DUPLEX_FULL;
1164 else
1165 phydev->duplex = DUPLEX_HALF;
1166
1167 status = status & MII_M1011_PHY_STATUS_SPD_MASK;
1168 phydev->pause = 0;
1169 phydev->asym_pause = 0;
1170
1171 switch (status) {
1172 case MII_M1011_PHY_STATUS_1000:
1173 phydev->speed = SPEED_1000;
1174 break;
1175
1176 case MII_M1011_PHY_STATUS_100:
1177 phydev->speed = SPEED_100;
1178 break;
1179
1180 default:
1181 phydev->speed = SPEED_10;
1182 break;
1183 }
1184
1185 if (!fiber) {
1186 phydev->lp_advertising =
1187 mii_stat1000_to_ethtool_lpa_t(lpagb) |
1188 mii_lpa_to_ethtool_lpa_t(lpa);
1189
1190 if (phydev->duplex == DUPLEX_FULL) {
1191 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
1192 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
1193 }
1194 } else {
1195 /* The fiber link is only 1000M capable */
1196 phydev->lp_advertising = fiber_lpa_to_ethtool_lpa_t(lpa);
1197
1198 if (phydev->duplex == DUPLEX_FULL) {
1199 if (!(lpa & LPA_PAUSE_FIBER)) {
1200 phydev->pause = 0;
1201 phydev->asym_pause = 0;
1202 } else if ((lpa & LPA_PAUSE_ASYM_FIBER)) {
1203 phydev->pause = 1;
1204 phydev->asym_pause = 1;
1205 } else {
1206 phydev->pause = 1;
1207 phydev->asym_pause = 0;
1208 }
1209 }
1210 }
1211 return 0;
1212}
1213
1214static int marvell_read_status_page_fixed(struct phy_device *phydev)
1215{
1216 int bmcr = phy_read(phydev, MII_BMCR);
1217
1218 if (bmcr < 0)
1219 return bmcr;
1220
1221 if (bmcr & BMCR_FULLDPLX)
1222 phydev->duplex = DUPLEX_FULL;
1223 else
1224 phydev->duplex = DUPLEX_HALF;
1225
1226 if (bmcr & BMCR_SPEED1000)
1227 phydev->speed = SPEED_1000;
1228 else if (bmcr & BMCR_SPEED100)
1229 phydev->speed = SPEED_100;
1230 else
1231 phydev->speed = SPEED_10;
1232
1233 phydev->pause = 0;
1234 phydev->asym_pause = 0;
1235 phydev->lp_advertising = 0;
1236
1237 return 0;
1238}
1239
6cfb3bcc 1240/* marvell_read_status_page
be937f1f 1241 *
f0c88f9c 1242 * Description:
be937f1f
AS		 1243 * Check the link, then figure out the current state
1244 * by comparing what we advertise with what the link partner
1245 * advertises. Start by checking the gigabit possibilities,
1246 * then move on to 10/100.
1247 */
6cfb3bcc 1248static int marvell_read_status_page(struct phy_device *phydev, int page)
be937f1f 1249{
6cfb3bcc 1250 int fiber;
e1dde8dc 1251 int err;
be937f1f 1252
6cfb3bcc 1253 /* Detect and update the link, but return if there
0c3439bc
AL		 1254 * was an error
1255 */
52295666 1256 if (page == MII_MARVELL_FIBER_PAGE)
6cfb3bcc
CAC		 1257 fiber = 1;
1258 else
1259 fiber = 0;
1260
1261 err = marvell_update_link(phydev, fiber);
be937f1f
AS		 1262 if (err)
1263 return err;
1264
e1dde8dc
AL		 1265 if (phydev->autoneg == AUTONEG_ENABLE)
1266 err = marvell_read_status_page_an(phydev, fiber);
1267 else
1268 err = marvell_read_status_page_fixed(phydev);
be937f1f 1269
e1dde8dc 1270 return err;
be937f1f
AS		 1271}
1272
6cfb3bcc
CAC		 1273/* marvell_read_status
1274 *
1275 * Some Marvell's phys have two modes: fiber and copper.
1276 * Both need status checked.
1277 * Description:
1278 * First, check the fiber link and status.
1279 * If the fiber link is down, check the copper link and status which
1280 * will be the default value if both link are down.
1281 */
1282static int marvell_read_status(struct phy_device *phydev)
1283{
1284 int err;
1285
1286 /* Check the fiber mode first */
a13c0652
RK		 1287 if (phydev->supported & SUPPORTED_FIBRE &&
1288 phydev->interface != PHY_INTERFACE_MODE_SGMII) {
52295666 1289 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
6cfb3bcc
CAC		 1290 if (err < 0)
1291 goto error;
1292
52295666 1293 err = marvell_read_status_page(phydev, MII_MARVELL_FIBER_PAGE);
6cfb3bcc
CAC		 1294 if (err < 0)
1295 goto error;
1296
0c3439bc
AL		 1297 /* If the fiber link is up, it is the selected and
1298 * used link. In this case, we need to stay in the
1299 * fiber page. Please to be careful about that, avoid
1300 * to restore Copper page in other functions which
1301 * could break the behaviour for some fiber phy like
1302 * 88E1512.
1303 */
6cfb3bcc
CAC		 1304 if (phydev->link)
1305 return 0;
1306
1307 /* If fiber link is down, check and save copper mode state */
52295666 1308 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
6cfb3bcc
CAC		 1309 if (err < 0)
1310 goto error;
1311 }
1312
52295666 1313 return marvell_read_status_page(phydev, MII_MARVELL_COPPER_PAGE);
6cfb3bcc
CAC		 1314
1315error:
52295666 1316 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
6cfb3bcc
CAC		 1317 return err;
1318}
3758be3d
CAC		 1319
1320/* marvell_suspend
1321 *
1322 * Some Marvell's phys have two modes: fiber and copper.
1323 * Both need to be suspended
1324 */
1325static int marvell_suspend(struct phy_device *phydev)
1326{
1327 int err;
1328
1329 /* Suspend the fiber mode first */
1330 if (!(phydev->supported & SUPPORTED_FIBRE)) {
52295666 1331 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
3758be3d
CAC		 1332 if (err < 0)
1333 goto error;
1334
1335 /* With the page set, use the generic suspend */
1336 err = genphy_suspend(phydev);
1337 if (err < 0)
1338 goto error;
1339
1340 /* Then, the copper link */
52295666 1341 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
3758be3d
CAC		 1342 if (err < 0)
1343 goto error;
1344 }
1345
1346 /* With the page set, use the generic suspend */
1347 return genphy_suspend(phydev);
1348
1349error:
52295666 1350 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
3758be3d
CAC		 1351 return err;
1352}
1353
1354/* marvell_resume
1355 *
1356 * Some Marvell's phys have two modes: fiber and copper.
1357 * Both need to be resumed
1358 */
1359static int marvell_resume(struct phy_device *phydev)
1360{
1361 int err;
1362
1363 /* Resume the fiber mode first */
1364 if (!(phydev->supported & SUPPORTED_FIBRE)) {
52295666 1365 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
3758be3d
CAC		 1366 if (err < 0)
1367 goto error;
1368
1369 /* With the page set, use the generic resume */
1370 err = genphy_resume(phydev);
1371 if (err < 0)
1372 goto error;
1373
1374 /* Then, the copper link */
52295666 1375 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
3758be3d
CAC		 1376 if (err < 0)
1377 goto error;
1378 }
1379
1380 /* With the page set, use the generic resume */
1381 return genphy_resume(phydev);
1382
1383error:
52295666 1384 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
3758be3d
CAC		 1385 return err;
1386}
1387
6b358aed
SH		 1388static int marvell_aneg_done(struct phy_device *phydev)
1389{
1390 int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
e69d9ed4 1391
6b358aed
SH		 1392 return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
1393}
1394
dcd07be3
AG		 1395static int m88e1121_did_interrupt(struct phy_device *phydev)
1396{
1397 int imask;
1398
1399 imask = phy_read(phydev, MII_M1011_IEVENT);
1400
1401 if (imask & MII_M1011_IMASK_INIT)
1402 return 1;
1403
1404 return 0;
1405}
1406
23beb38f
AL		 1407static void m88e1318_get_wol(struct phy_device *phydev,
1408 struct ethtool_wolinfo *wol)
3871c387
MS		 1409{
1410 wol->supported = WAKE_MAGIC;
1411 wol->wolopts = 0;
1412
52295666 1413 if (marvell_set_page(phydev, MII_MARVELL_WOL_PAGE) < 0)
3871c387
MS		 1414 return;
1415
1416 if (phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL) &
1417 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
1418 wol->wolopts |= WAKE_MAGIC;
1419
52295666 1420 if (marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE) < 0)
3871c387
MS		 1421 return;
1422}
1423
23beb38f
AL		 1424static int m88e1318_set_wol(struct phy_device *phydev,
1425 struct ethtool_wolinfo *wol)
3871c387
MS		 1426{
1427 int err, oldpage, temp;
1428
6427bb2d 1429 oldpage = marvell_get_page(phydev);
3871c387
MS		 1430
1431 if (wol->wolopts & WAKE_MAGIC) {
1432 /* Explicitly switch to page 0x00, just to be sure */
52295666 1433 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
3871c387
MS		 1434 if (err < 0)
1435 return err;
1436
1437 /* Enable the WOL interrupt */
1438 temp = phy_read(phydev, MII_88E1318S_PHY_CSIER);
1439 temp |= MII_88E1318S_PHY_CSIER_WOL_EIE;
1440 err = phy_write(phydev, MII_88E1318S_PHY_CSIER, temp);
1441 if (err < 0)
1442 return err;
1443
52295666 1444 err = marvell_set_page(phydev, MII_MARVELL_LED_PAGE);
3871c387
MS		 1445 if (err < 0)
1446 return err;
1447
1448 /* Setup LED[2] as interrupt pin (active low) */
1449 temp = phy_read(phydev, MII_88E1318S_PHY_LED_TCR);
1450 temp &= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT;
1451 temp |= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE;
1452 temp |= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW;
1453 err = phy_write(phydev, MII_88E1318S_PHY_LED_TCR, temp);
1454 if (err < 0)
1455 return err;
1456
52295666 1457 err = marvell_set_page(phydev, MII_MARVELL_WOL_PAGE);
3871c387
MS		 1458 if (err < 0)
1459 return err;
1460
1461 /* Store the device address for the magic packet */
1462 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
1463 ((phydev->attached_dev->dev_addr[5] << 8) |
1464 phydev->attached_dev->dev_addr[4]));
1465 if (err < 0)
1466 return err;
1467 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
1468 ((phydev->attached_dev->dev_addr[3] << 8) |
1469 phydev->attached_dev->dev_addr[2]));
1470 if (err < 0)
1471 return err;
1472 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
1473 ((phydev->attached_dev->dev_addr[1] << 8) |
1474 phydev->attached_dev->dev_addr[0]));
1475 if (err < 0)
1476 return err;
1477
1478 /* Clear WOL status and enable magic packet matching */
1479 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
1480 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
1481 temp |= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
1482 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
1483 if (err < 0)
1484 return err;
1485 } else {
52295666 1486 err = marvell_set_page(phydev, MII_MARVELL_WOL_PAGE);
3871c387
MS		 1487 if (err < 0)
1488 return err;
1489
1490 /* Clear WOL status and disable magic packet matching */
1491 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
1492 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
1493 temp &= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
1494 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
1495 if (err < 0)
1496 return err;
1497 }
1498
6427bb2d 1499 err = marvell_set_page(phydev, oldpage);
3871c387
MS		 1500 if (err < 0)
1501 return err;
1502
1503 return 0;
1504}
1505
d2fa47d9
AL		 1506static int marvell_get_sset_count(struct phy_device *phydev)
1507{
2170fef7
CAC		 1508 if (phydev->supported & SUPPORTED_FIBRE)
1509 return ARRAY_SIZE(marvell_hw_stats);
1510 else
1511 return ARRAY_SIZE(marvell_hw_stats) - NB_FIBER_STATS;
d2fa47d9
AL		 1512}
1513
1514static void marvell_get_strings(struct phy_device *phydev, u8 *data)
1515{
1516 int i;
1517
1518 for (i = 0; i < ARRAY_SIZE(marvell_hw_stats); i++) {
1519 memcpy(data + i * ETH_GSTRING_LEN,
1520 marvell_hw_stats[i].string, ETH_GSTRING_LEN);
1521 }
1522}
1523
1524#ifndef UINT64_MAX
1525#define UINT64_MAX (u64)(~((u64)0))
1526#endif
1527static u64 marvell_get_stat(struct phy_device *phydev, int i)
1528{
1529 struct marvell_hw_stat stat = marvell_hw_stats[i];
1530 struct marvell_priv *priv = phydev->priv;
53798328 1531 int oldpage, val;
321b4d4b 1532 u64 ret;
d2fa47d9 1533
53798328
AL		 1534 oldpage = marvell_get_set_page(phydev, stat.page);
1535 if (oldpage < 0)
d2fa47d9
AL		 1536 return UINT64_MAX;
1537
1538 val = phy_read(phydev, stat.reg);
1539 if (val < 0) {
321b4d4b 1540 ret = UINT64_MAX;
d2fa47d9
AL		 1541 } else {
1542 val = val & ((1 << stat.bits) - 1);
1543 priv->stats[i] += val;
321b4d4b 1544 ret = priv->stats[i];
d2fa47d9
AL		 1545 }
1546
6427bb2d 1547 marvell_set_page(phydev, oldpage);
d2fa47d9 1548
321b4d4b 1549 return ret;
d2fa47d9
AL		 1550}
1551
1552static void marvell_get_stats(struct phy_device *phydev,
1553 struct ethtool_stats *stats, u64 *data)
1554{
1555 int i;
1556
1557 for (i = 0; i < ARRAY_SIZE(marvell_hw_stats); i++)
1558 data[i] = marvell_get_stat(phydev, i);
1559}
1560
0b04680f
AL		 1561#ifdef CONFIG_HWMON
1562static int m88e1121_get_temp(struct phy_device *phydev, long *temp)
1563{
975b388c 1564 int oldpage;
0b04680f
AL		 1565 int ret;
1566 int val;
1567
1568 *temp = 0;
1569
1570 mutex_lock(&phydev->lock);
1571
52295666 1572 oldpage = marvell_get_set_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
975b388c
AL		 1573 if (oldpage < 0) {
1574 mutex_unlock(&phydev->lock);
1575 return oldpage;
1576 }
1577
0b04680f
AL		 1578 /* Enable temperature sensor */
1579 ret = phy_read(phydev, MII_88E1121_MISC_TEST);
1580 if (ret < 0)
1581 goto error;
1582
1583 ret = phy_write(phydev, MII_88E1121_MISC_TEST,
1584 ret | MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
1585 if (ret < 0)
1586 goto error;
1587
1588 /* Wait for temperature to stabilize */
1589 usleep_range(10000, 12000);
1590
1591 val = phy_read(phydev, MII_88E1121_MISC_TEST);
1592 if (val < 0) {
1593 ret = val;
1594 goto error;
1595 }
1596
1597 /* Disable temperature sensor */
1598 ret = phy_write(phydev, MII_88E1121_MISC_TEST,
1599 ret & ~MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
1600 if (ret < 0)
1601 goto error;
1602
1603 *temp = ((val & MII_88E1121_MISC_TEST_TEMP_MASK) - 5) * 5000;
1604
1605error:
975b388c 1606 marvell_set_page(phydev, oldpage);
0b04680f
AL		 1607 mutex_unlock(&phydev->lock);
1608
1609 return ret;
1610}
1611
1612static int m88e1121_hwmon_read(struct device *dev,
1613 enum hwmon_sensor_types type,
1614 u32 attr, int channel, long *temp)
1615{
1616 struct phy_device *phydev = dev_get_drvdata(dev);
1617 int err;
1618
1619 switch (attr) {
1620 case hwmon_temp_input:
1621 err = m88e1121_get_temp(phydev, temp);
1622 break;
1623 default:
1624 return -EOPNOTSUPP;
1625 }
1626
1627 return err;
1628}
1629
1630static umode_t m88e1121_hwmon_is_visible(const void *data,
1631 enum hwmon_sensor_types type,
1632 u32 attr, int channel)
1633{
1634 if (type != hwmon_temp)
1635 return 0;
1636
1637 switch (attr) {
1638 case hwmon_temp_input:
1639 return 0444;
1640 default:
1641 return 0;
1642 }
1643}
1644
1645static u32 m88e1121_hwmon_chip_config[] = {
1646 HWMON_C_REGISTER_TZ,
1647 0
1648};
1649
1650static const struct hwmon_channel_info m88e1121_hwmon_chip = {
1651 .type = hwmon_chip,
1652 .config = m88e1121_hwmon_chip_config,
1653};
1654
1655static u32 m88e1121_hwmon_temp_config[] = {
1656 HWMON_T_INPUT,
1657 0
1658};
1659
1660static const struct hwmon_channel_info m88e1121_hwmon_temp = {
1661 .type = hwmon_temp,
1662 .config = m88e1121_hwmon_temp_config,
1663};
1664
1665static const struct hwmon_channel_info *m88e1121_hwmon_info[] = {
1666 &m88e1121_hwmon_chip,
1667 &m88e1121_hwmon_temp,
1668 NULL
1669};
1670
1671static const struct hwmon_ops m88e1121_hwmon_hwmon_ops = {
1672 .is_visible = m88e1121_hwmon_is_visible,
1673 .read = m88e1121_hwmon_read,
1674};
1675
1676static const struct hwmon_chip_info m88e1121_hwmon_chip_info = {
1677 .ops = &m88e1121_hwmon_hwmon_ops,
1678 .info = m88e1121_hwmon_info,
1679};
1680
1681static int m88e1510_get_temp(struct phy_device *phydev, long *temp)
1682{
975b388c 1683 int oldpage;
0b04680f
AL		 1684 int ret;
1685
1686 *temp = 0;
1687
1688 mutex_lock(&phydev->lock);
1689
52295666 1690 oldpage = marvell_get_set_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
975b388c
AL		 1691 if (oldpage < 0) {
1692 mutex_unlock(&phydev->lock);
1693 return oldpage;
1694 }
1695
0b04680f
AL		 1696 ret = phy_read(phydev, MII_88E1510_TEMP_SENSOR);
1697 if (ret < 0)
1698 goto error;
1699
1700 *temp = ((ret & MII_88E1510_TEMP_SENSOR_MASK) - 25) * 1000;
1701
1702error:
975b388c 1703 marvell_set_page(phydev, oldpage);
0b04680f
AL		 1704 mutex_unlock(&phydev->lock);
1705
1706 return ret;
1707}
1708
1709int m88e1510_get_temp_critical(struct phy_device *phydev, long *temp)
1710{
975b388c 1711 int oldpage;
0b04680f
AL		 1712 int ret;
1713
1714 *temp = 0;
1715
1716 mutex_lock(&phydev->lock);
53798328 1717
52295666 1718 oldpage = marvell_get_set_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
975b388c
AL		 1719 if (oldpage < 0) {
1720 mutex_unlock(&phydev->lock);
1721 return oldpage;
1722 }
0b04680f 1723
0b04680f
AL		 1724 ret = phy_read(phydev, MII_88E1121_MISC_TEST);
1725 if (ret < 0)
1726 goto error;
1727
1728 *temp = (((ret & MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK) >>
1729 MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT) * 5) - 25;
1730 /* convert to mC */
1731 *temp *= 1000;
1732
1733error:
975b388c 1734 marvell_set_page(phydev, oldpage);
0b04680f
AL		 1735 mutex_unlock(&phydev->lock);
1736
1737 return ret;
1738}
1739
1740int m88e1510_set_temp_critical(struct phy_device *phydev, long temp)
1741{
975b388c 1742 int oldpage;
0b04680f
AL		 1743 int ret;
1744
1745 mutex_lock(&phydev->lock);
1746
52295666 1747 oldpage = marvell_get_set_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
975b388c
AL		 1748 if (oldpage < 0) {
1749 mutex_unlock(&phydev->lock);
1750 return oldpage;
1751 }
1752
0b04680f
AL		 1753 ret = phy_read(phydev, MII_88E1121_MISC_TEST);
1754 if (ret < 0)
1755 goto error;
1756
1757 temp = temp / 1000;
1758 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
1759 ret = phy_write(phydev, MII_88E1121_MISC_TEST,
1760 (ret & ~MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK) |
1761 (temp << MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT));
1762
1763error:
975b388c 1764 marvell_set_page(phydev, oldpage);
0b04680f
AL		 1765 mutex_unlock(&phydev->lock);
1766
1767 return ret;
1768}
1769
1770int m88e1510_get_temp_alarm(struct phy_device *phydev, long *alarm)
1771{
975b388c 1772 int oldpage;
0b04680f
AL		 1773 int ret;
1774
1775 *alarm = false;
1776
1777 mutex_lock(&phydev->lock);
1778
52295666 1779 oldpage = marvell_get_set_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
975b388c
AL		 1780 if (oldpage < 0) {
1781 mutex_unlock(&phydev->lock);
1782 return oldpage;
1783 }
1784
0b04680f
AL		 1785 ret = phy_read(phydev, MII_88E1121_MISC_TEST);
1786 if (ret < 0)
1787 goto error;
1788 *alarm = !!(ret & MII_88E1510_MISC_TEST_TEMP_IRQ);
1789
1790error:
975b388c 1791 marvell_set_page(phydev, oldpage);
0b04680f
AL		 1792 mutex_unlock(&phydev->lock);
1793
1794 return ret;
1795}
1796
1797static int m88e1510_hwmon_read(struct device *dev,
1798 enum hwmon_sensor_types type,
1799 u32 attr, int channel, long *temp)
1800{
1801 struct phy_device *phydev = dev_get_drvdata(dev);
1802 int err;
1803
1804 switch (attr) {
1805 case hwmon_temp_input:
1806 err = m88e1510_get_temp(phydev, temp);
1807 break;
1808 case hwmon_temp_crit:
1809 err = m88e1510_get_temp_critical(phydev, temp);
1810 break;
1811 case hwmon_temp_max_alarm:
1812 err = m88e1510_get_temp_alarm(phydev, temp);
1813 break;
1814 default:
1815 return -EOPNOTSUPP;
1816 }
1817
1818 return err;
1819}
1820
1821static int m88e1510_hwmon_write(struct device *dev,
1822 enum hwmon_sensor_types type,
1823 u32 attr, int channel, long temp)
1824{
1825 struct phy_device *phydev = dev_get_drvdata(dev);
1826 int err;
1827
1828 switch (attr) {
1829 case hwmon_temp_crit:
1830 err = m88e1510_set_temp_critical(phydev, temp);
1831 break;
1832 default:
1833 return -EOPNOTSUPP;
1834 }
1835 return err;
1836}
1837
1838static umode_t m88e1510_hwmon_is_visible(const void *data,
1839 enum hwmon_sensor_types type,
1840 u32 attr, int channel)
1841{
1842 if (type != hwmon_temp)
1843 return 0;
1844
1845 switch (attr) {
1846 case hwmon_temp_input:
1847 case hwmon_temp_max_alarm:
1848 return 0444;
1849 case hwmon_temp_crit:
1850 return 0644;
1851 default:
1852 return 0;
1853 }
1854}
1855
1856static u32 m88e1510_hwmon_temp_config[] = {
1857 HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_MAX_ALARM,
1858 0
1859};
1860
1861static const struct hwmon_channel_info m88e1510_hwmon_temp = {
1862 .type = hwmon_temp,
1863 .config = m88e1510_hwmon_temp_config,
1864};
1865
1866static const struct hwmon_channel_info *m88e1510_hwmon_info[] = {
1867 &m88e1121_hwmon_chip,
1868 &m88e1510_hwmon_temp,
1869 NULL
1870};
1871
1872static const struct hwmon_ops m88e1510_hwmon_hwmon_ops = {
1873 .is_visible = m88e1510_hwmon_is_visible,
1874 .read = m88e1510_hwmon_read,
1875 .write = m88e1510_hwmon_write,
1876};
1877
1878static const struct hwmon_chip_info m88e1510_hwmon_chip_info = {
1879 .ops = &m88e1510_hwmon_hwmon_ops,
1880 .info = m88e1510_hwmon_info,
1881};
1882
1883static int marvell_hwmon_name(struct phy_device *phydev)
1884{
1885 struct marvell_priv *priv = phydev->priv;
1886 struct device *dev = &phydev->mdio.dev;
1887 const char *devname = dev_name(dev);
1888 size_t len = strlen(devname);
1889 int i, j;
1890
1891 priv->hwmon_name = devm_kzalloc(dev, len, GFP_KERNEL);
1892 if (!priv->hwmon_name)
1893 return -ENOMEM;
1894
1895 for (i = j = 0; i < len && devname[i]; i++) {
1896 if (isalnum(devname[i]))
1897 priv->hwmon_name[j++] = devname[i];
1898 }
1899
1900 return 0;
1901}
1902
1903static int marvell_hwmon_probe(struct phy_device *phydev,
1904 const struct hwmon_chip_info *chip)
1905{
1906 struct marvell_priv *priv = phydev->priv;
1907 struct device *dev = &phydev->mdio.dev;
1908 int err;
1909
1910 err = marvell_hwmon_name(phydev);
1911 if (err)
1912 return err;
1913
1914 priv->hwmon_dev = devm_hwmon_device_register_with_info(
1915 dev, priv->hwmon_name, phydev, chip, NULL);
1916
1917 return PTR_ERR_OR_ZERO(priv->hwmon_dev);
1918}
1919
1920static int m88e1121_hwmon_probe(struct phy_device *phydev)
1921{
1922 return marvell_hwmon_probe(phydev, &m88e1121_hwmon_chip_info);
1923}
1924
1925static int m88e1510_hwmon_probe(struct phy_device *phydev)
1926{
1927 return marvell_hwmon_probe(phydev, &m88e1510_hwmon_chip_info);
1928}
1929#else
1930static int m88e1121_hwmon_probe(struct phy_device *phydev)
1931{
1932 return 0;
1933}
1934
1935static int m88e1510_hwmon_probe(struct phy_device *phydev)
1936{
1937 return 0;
1938}
1939#endif
1940
d2fa47d9
AL		 1941static int marvell_probe(struct phy_device *phydev)
1942{
1943 struct marvell_priv *priv;
1944
e5a03bfd 1945 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
d2fa47d9
AL		 1946 if (!priv)
1947 return -ENOMEM;
1948
1949 phydev->priv = priv;
1950
1951 return 0;
1952}
1953
0b04680f
AL		 1954static int m88e1121_probe(struct phy_device *phydev)
1955{
1956 int err;
1957
1958 err = marvell_probe(phydev);
1959 if (err)
1960 return err;
1961
1962 return m88e1121_hwmon_probe(phydev);
1963}
1964
1965static int m88e1510_probe(struct phy_device *phydev)
1966{
1967 int err;
1968
1969 err = marvell_probe(phydev);
1970 if (err)
1971 return err;
1972
1973 return m88e1510_hwmon_probe(phydev);
1974}
1975
e5479239
OJ		 1976static struct phy_driver marvell_drivers[] = {
1977 {
2f495c39
BH		 1978 .phy_id = MARVELL_PHY_ID_88E1101,
1979 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 1980 .name = "Marvell 88E1101",
1981 .features = PHY_GBIT_FEATURES,
1982 .flags = PHY_HAS_INTERRUPT,
18702414 1983 .probe = marvell_probe,
79be1a1c 1984 .config_init = &marvell_config_init,
f2899788 1985 .config_aneg = &m88e1101_config_aneg,
e5479239
OJ		 1986 .read_status = &genphy_read_status,
1987 .ack_interrupt = &marvell_ack_interrupt,
1988 .config_intr = &marvell_config_intr,
0898b448
SH		 1989 .resume = &genphy_resume,
1990 .suspend = &genphy_suspend,
d2fa47d9
AL		 1991 .get_sset_count = marvell_get_sset_count,
1992 .get_strings = marvell_get_strings,
1993 .get_stats = marvell_get_stats,
e5479239 1994 },
85cfb534 1995 {
2f495c39
BH		 1996 .phy_id = MARVELL_PHY_ID_88E1112,
1997 .phy_id_mask = MARVELL_PHY_ID_MASK,
85cfb534
OJ		 1998 .name = "Marvell 88E1112",
1999 .features = PHY_GBIT_FEATURES,
2000 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 2001 .probe = marvell_probe,
85cfb534
OJ		 2002 .config_init = &m88e1111_config_init,
2003 .config_aneg = &marvell_config_aneg,
2004 .read_status = &genphy_read_status,
2005 .ack_interrupt = &marvell_ack_interrupt,
2006 .config_intr = &marvell_config_intr,
0898b448
SH		 2007 .resume = &genphy_resume,
2008 .suspend = &genphy_suspend,
d2fa47d9
AL		 2009 .get_sset_count = marvell_get_sset_count,
2010 .get_strings = marvell_get_strings,
2011 .get_stats = marvell_get_stats,
85cfb534 2012 },
e5479239 2013 {
2f495c39
BH		 2014 .phy_id = MARVELL_PHY_ID_88E1111,
2015 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 2016 .name = "Marvell 88E1111",
2017 .features = PHY_GBIT_FEATURES,
2018 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 2019 .probe = marvell_probe,
e5479239 2020 .config_init = &m88e1111_config_init,
3ec0a0f1 2021 .config_aneg = &m88e1111_config_aneg,
be937f1f 2022 .read_status = &marvell_read_status,
e5479239
OJ		 2023 .ack_interrupt = &marvell_ack_interrupt,
2024 .config_intr = &marvell_config_intr,
0898b448
SH		 2025 .resume = &genphy_resume,
2026 .suspend = &genphy_suspend,
d2fa47d9
AL		 2027 .get_sset_count = marvell_get_sset_count,
2028 .get_strings = marvell_get_strings,
2029 .get_stats = marvell_get_stats,
e5479239 2030 },
605f196e 2031 {
2f495c39
BH		 2032 .phy_id = MARVELL_PHY_ID_88E1118,
2033 .phy_id_mask = MARVELL_PHY_ID_MASK,
605f196e
RM		 2034 .name = "Marvell 88E1118",
2035 .features = PHY_GBIT_FEATURES,
2036 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 2037 .probe = marvell_probe,
605f196e
RM		 2038 .config_init = &m88e1118_config_init,
2039 .config_aneg = &m88e1118_config_aneg,
2040 .read_status = &genphy_read_status,
2041 .ack_interrupt = &marvell_ack_interrupt,
2042 .config_intr = &marvell_config_intr,
0898b448
SH		 2043 .resume = &genphy_resume,
2044 .suspend = &genphy_suspend,
d2fa47d9
AL		 2045 .get_sset_count = marvell_get_sset_count,
2046 .get_strings = marvell_get_strings,
2047 .get_stats = marvell_get_stats,
605f196e 2048 },
140bc929 2049 {
2f495c39
BH		 2050 .phy_id = MARVELL_PHY_ID_88E1121R,
2051 .phy_id_mask = MARVELL_PHY_ID_MASK,
140bc929
SP		 2052 .name = "Marvell 88E1121R",
2053 .features = PHY_GBIT_FEATURES,
2054 .flags = PHY_HAS_INTERRUPT,
18702414 2055 .probe = &m88e1121_probe,
fdecf36f 2056 .config_init = &m88e1121_config_init,
140bc929
SP		 2057 .config_aneg = &m88e1121_config_aneg,
2058 .read_status = &marvell_read_status,
2059 .ack_interrupt = &marvell_ack_interrupt,
2060 .config_intr = &marvell_config_intr,
dcd07be3 2061 .did_interrupt = &m88e1121_did_interrupt,
0898b448
SH		 2062 .resume = &genphy_resume,
2063 .suspend = &genphy_suspend,
d2fa47d9
AL		 2064 .get_sset_count = marvell_get_sset_count,
2065 .get_strings = marvell_get_strings,
2066 .get_stats = marvell_get_stats,
140bc929 2067 },
3ff1c259 2068 {
337ac9d5 2069 .phy_id = MARVELL_PHY_ID_88E1318S,
6ba74014 2070 .phy_id_mask = MARVELL_PHY_ID_MASK,
337ac9d5 2071 .name = "Marvell 88E1318S",
3ff1c259
CC		 2072 .features = PHY_GBIT_FEATURES,
2073 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 2074 .probe = marvell_probe,
fdecf36f 2075 .config_init = &m88e1121_config_init,
337ac9d5 2076 .config_aneg = &m88e1318_config_aneg,
3ff1c259
CC		 2077 .read_status = &marvell_read_status,
2078 .ack_interrupt = &marvell_ack_interrupt,
2079 .config_intr = &marvell_config_intr,
2080 .did_interrupt = &m88e1121_did_interrupt,
3871c387
MS		 2081 .get_wol = &m88e1318_get_wol,
2082 .set_wol = &m88e1318_set_wol,
0898b448
SH		 2083 .resume = &genphy_resume,
2084 .suspend = &genphy_suspend,
d2fa47d9
AL		 2085 .get_sset_count = marvell_get_sset_count,
2086 .get_strings = marvell_get_strings,
2087 .get_stats = marvell_get_stats,
3ff1c259 2088 },
e5479239 2089 {
2f495c39
BH		 2090 .phy_id = MARVELL_PHY_ID_88E1145,
2091 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 2092 .name = "Marvell 88E1145",
2093 .features = PHY_GBIT_FEATURES,
2094 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 2095 .probe = marvell_probe,
e5479239
OJ		 2096 .config_init = &m88e1145_config_init,
2097 .config_aneg = &marvell_config_aneg,
2098 .read_status = &genphy_read_status,
2099 .ack_interrupt = &marvell_ack_interrupt,
2100 .config_intr = &marvell_config_intr,
0898b448
SH		 2101 .resume = &genphy_resume,
2102 .suspend = &genphy_suspend,
d2fa47d9
AL		 2103 .get_sset_count = marvell_get_sset_count,
2104 .get_strings = marvell_get_strings,
2105 .get_stats = marvell_get_stats,
ac8c635a 2106 },
90600732
DD		 2107 {
2108 .phy_id = MARVELL_PHY_ID_88E1149R,
2109 .phy_id_mask = MARVELL_PHY_ID_MASK,
2110 .name = "Marvell 88E1149R",
2111 .features = PHY_GBIT_FEATURES,
2112 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 2113 .probe = marvell_probe,
90600732
DD		 2114 .config_init = &m88e1149_config_init,
2115 .config_aneg = &m88e1118_config_aneg,
2116 .read_status = &genphy_read_status,
2117 .ack_interrupt = &marvell_ack_interrupt,
2118 .config_intr = &marvell_config_intr,
0898b448
SH		 2119 .resume = &genphy_resume,
2120 .suspend = &genphy_suspend,
d2fa47d9
AL		 2121 .get_sset_count = marvell_get_sset_count,
2122 .get_strings = marvell_get_strings,
2123 .get_stats = marvell_get_stats,
90600732 2124 },
ac8c635a 2125 {
2f495c39
BH		 2126 .phy_id = MARVELL_PHY_ID_88E1240,
2127 .phy_id_mask = MARVELL_PHY_ID_MASK,
ac8c635a
OJ		 2128 .name = "Marvell 88E1240",
2129 .features = PHY_GBIT_FEATURES,
2130 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 2131 .probe = marvell_probe,
ac8c635a
OJ		 2132 .config_init = &m88e1111_config_init,
2133 .config_aneg = &marvell_config_aneg,
2134 .read_status = &genphy_read_status,
2135 .ack_interrupt = &marvell_ack_interrupt,
2136 .config_intr = &marvell_config_intr,
0898b448
SH		 2137 .resume = &genphy_resume,
2138 .suspend = &genphy_suspend,
d2fa47d9
AL		 2139 .get_sset_count = marvell_get_sset_count,
2140 .get_strings = marvell_get_strings,
2141 .get_stats = marvell_get_stats,
ac8c635a 2142 },
3da09a51
MS		 2143 {
2144 .phy_id = MARVELL_PHY_ID_88E1116R,
2145 .phy_id_mask = MARVELL_PHY_ID_MASK,
2146 .name = "Marvell 88E1116R",
2147 .features = PHY_GBIT_FEATURES,
2148 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 2149 .probe = marvell_probe,
3da09a51
MS		 2150 .config_init = &m88e1116r_config_init,
2151 .config_aneg = &genphy_config_aneg,
2152 .read_status = &genphy_read_status,
2153 .ack_interrupt = &marvell_ack_interrupt,
2154 .config_intr = &marvell_config_intr,
0898b448
SH		 2155 .resume = &genphy_resume,
2156 .suspend = &genphy_suspend,
d2fa47d9
AL		 2157 .get_sset_count = marvell_get_sset_count,
2158 .get_strings = marvell_get_strings,
2159 .get_stats = marvell_get_stats,
3da09a51 2160 },
10e24caa
MS		 2161 {
2162 .phy_id = MARVELL_PHY_ID_88E1510,
2163 .phy_id_mask = MARVELL_PHY_ID_MASK,
2164 .name = "Marvell 88E1510",
6cfb3bcc 2165 .features = PHY_GBIT_FEATURES | SUPPORTED_FIBRE,
18702414 2166 .flags = PHY_HAS_INTERRUPT,
0b04680f 2167 .probe = &m88e1510_probe,
930b37ee 2168 .config_init = &m88e1510_config_init,
10e24caa
MS		 2169 .config_aneg = &m88e1510_config_aneg,
2170 .read_status = &marvell_read_status,
2171 .ack_interrupt = &marvell_ack_interrupt,
2172 .config_intr = &marvell_config_intr,
2173 .did_interrupt = &m88e1121_did_interrupt,
f39aac7e
JH		 2174 .get_wol = &m88e1318_get_wol,
2175 .set_wol = &m88e1318_set_wol,
3758be3d
CAC		 2176 .resume = &marvell_resume,
2177 .suspend = &marvell_suspend,
d2fa47d9
AL		 2178 .get_sset_count = marvell_get_sset_count,
2179 .get_strings = marvell_get_strings,
2180 .get_stats = marvell_get_stats,
10e24caa 2181 },
819ec8e1
AL		 2182 {
2183 .phy_id = MARVELL_PHY_ID_88E1540,
2184 .phy_id_mask = MARVELL_PHY_ID_MASK,
2185 .name = "Marvell 88E1540",
2186 .features = PHY_GBIT_FEATURES,
2187 .flags = PHY_HAS_INTERRUPT,
18702414 2188 .probe = m88e1510_probe,
79be1a1c 2189 .config_init = &marvell_config_init,
819ec8e1
AL		 2190 .config_aneg = &m88e1510_config_aneg,
2191 .read_status = &marvell_read_status,
2192 .ack_interrupt = &marvell_ack_interrupt,
2193 .config_intr = &marvell_config_intr,
2194 .did_interrupt = &m88e1121_did_interrupt,
2195 .resume = &genphy_resume,
2196 .suspend = &genphy_suspend,
d2fa47d9
AL		 2197 .get_sset_count = marvell_get_sset_count,
2198 .get_strings = marvell_get_strings,
2199 .get_stats = marvell_get_stats,
819ec8e1 2200 },
60f06fde
AL		 2201 {
2202 .phy_id = MARVELL_PHY_ID_88E1545,
2203 .phy_id_mask = MARVELL_PHY_ID_MASK,
2204 .name = "Marvell 88E1545",
2205 .probe = m88e1510_probe,
60f06fde
AL		 2206 .features = PHY_GBIT_FEATURES,
2207 .flags = PHY_HAS_INTERRUPT,
2208 .config_init = &marvell_config_init,
2209 .config_aneg = &m88e1510_config_aneg,
2210 .read_status = &marvell_read_status,
2211 .ack_interrupt = &marvell_ack_interrupt,
2212 .config_intr = &marvell_config_intr,
2213 .did_interrupt = &m88e1121_did_interrupt,
2214 .resume = &genphy_resume,
2215 .suspend = &genphy_suspend,
2216 .get_sset_count = marvell_get_sset_count,
2217 .get_strings = marvell_get_strings,
2218 .get_stats = marvell_get_stats,
2219 },
6b358aed
SH		 2220 {
2221 .phy_id = MARVELL_PHY_ID_88E3016,
2222 .phy_id_mask = MARVELL_PHY_ID_MASK,
2223 .name = "Marvell 88E3016",
2224 .features = PHY_BASIC_FEATURES,
2225 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 2226 .probe = marvell_probe,
6b358aed
SH		 2227 .config_aneg = &genphy_config_aneg,
2228 .config_init = &m88e3016_config_init,
2229 .aneg_done = &marvell_aneg_done,
2230 .read_status = &marvell_read_status,
2231 .ack_interrupt = &marvell_ack_interrupt,
2232 .config_intr = &marvell_config_intr,
2233 .did_interrupt = &m88e1121_did_interrupt,
2234 .resume = &genphy_resume,
2235 .suspend = &genphy_suspend,
d2fa47d9
AL		 2236 .get_sset_count = marvell_get_sset_count,
2237 .get_strings = marvell_get_strings,
2238 .get_stats = marvell_get_stats,
6b358aed 2239 },
e4cf8a38
AL		 2240 {
2241 .phy_id = MARVELL_PHY_ID_88E6390,
2242 .phy_id_mask = MARVELL_PHY_ID_MASK,
2243 .name = "Marvell 88E6390",
2244 .features = PHY_GBIT_FEATURES,
2245 .flags = PHY_HAS_INTERRUPT,
2246 .probe = m88e1510_probe,
2247 .config_init = &marvell_config_init,
2248 .config_aneg = &m88e1510_config_aneg,
2249 .read_status = &marvell_read_status,
2250 .ack_interrupt = &marvell_ack_interrupt,
2251 .config_intr = &marvell_config_intr,
2252 .did_interrupt = &m88e1121_did_interrupt,
2253 .resume = &genphy_resume,
2254 .suspend = &genphy_suspend,
2255 .get_sset_count = marvell_get_sset_count,
2256 .get_strings = marvell_get_strings,
2257 .get_stats = marvell_get_stats,
2258 },
00db8189
AF		 2259};
2260
50fd7150 2261module_phy_driver(marvell_drivers);
4e4f10f6 2262
cf93c945 2263static struct mdio_device_id __maybe_unused marvell_tbl[] = {
f5e1cabf
MS		 2264 { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
2265 { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
2266 { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
2267 { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
2268 { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
2269 { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
2270 { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
2271 { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
2272 { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
3da09a51 2273 { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
10e24caa 2274 { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
819ec8e1 2275 { MARVELL_PHY_ID_88E1540, MARVELL_PHY_ID_MASK },
60f06fde 2276 { MARVELL_PHY_ID_88E1545, MARVELL_PHY_ID_MASK },
6b358aed 2277 { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
e4cf8a38 2278 { MARVELL_PHY_ID_88E6390, MARVELL_PHY_ID_MASK },
4e4f10f6
DW		 2279 { }
2280};
2281
2282MODULE_DEVICE_TABLE(mdio, marvell_tbl);
Michael's Linux tree.