[people/ms/u-boot.git] / drivers / net / phy / micrel.c

/*
 * Micrel PHY drivers
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * Copyright 2010-2011 Freescale Semiconductor, Inc.
 * author Andy Fleming
 * (C) 2012 NetModule AG, David Andrey, added KSZ9031
 */
#include <config.h>
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
#include <micrel.h>
#include <phy.h>

DECLARE_GLOBAL_DATA_PTR;

static struct phy_driver KSZ804_driver = {
	.name = "Micrel KSZ804",
	.uid = 0x221510,
	.mask = 0xfffff0,
	.features = PHY_BASIC_FEATURES,
	.config = &genphy_config,
	.startup = &genphy_startup,
	.shutdown = &genphy_shutdown,
};

#define MII_KSZPHY_OMSO		0x16
#define KSZPHY_OMSO_B_CAST_OFF	(1 << 9)

static int ksz_genconfig_bcastoff(struct phy_device *phydev)
{
	int ret;

	ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO);
	if (ret < 0)
		return ret;

	ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO,
			ret | KSZPHY_OMSO_B_CAST_OFF);
	if (ret < 0)
		return ret;

	return genphy_config(phydev);
}

static struct phy_driver KSZ8031_driver = {
	.name = "Micrel KSZ8021/KSZ8031",
	.uid = 0x221550,
	.mask = 0xfffff0,
	.features = PHY_BASIC_FEATURES,
	.config = &ksz_genconfig_bcastoff,
	.startup = &genphy_startup,
	.shutdown = &genphy_shutdown,
};

/**
 * KSZ8051
 */
#define MII_KSZ8051_PHY_OMSO			0x16
#define MII_KSZ8051_PHY_OMSO_NAND_TREE_ON	(1 << 5)

static int ksz8051_config(struct phy_device *phydev)
{
	unsigned val;

	/* Disable NAND-tree */
	val = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO);
	val &= ~MII_KSZ8051_PHY_OMSO_NAND_TREE_ON;
	phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO, val);

	return genphy_config(phydev);
}

static struct phy_driver KSZ8051_driver = {
	.name = "Micrel KSZ8051",
	.uid = 0x221550,
	.mask = 0xfffff0,
	.features = PHY_BASIC_FEATURES,
	.config = &ksz8051_config,
	.startup = &genphy_startup,
	.shutdown = &genphy_shutdown,
};

static struct phy_driver KSZ8081_driver = {
	.name = "Micrel KSZ8081",
	.uid = 0x221560,
	.mask = 0xfffff0,
	.features = PHY_BASIC_FEATURES,
	.config = &ksz_genconfig_bcastoff,
	.startup = &genphy_startup,
	.shutdown = &genphy_shutdown,
};

/**
 * KSZ8895
 */

static unsigned short smireg_to_phy(unsigned short reg)
{
	return ((reg & 0xc0) >> 3) + 0x06 + ((reg & 0x20) >> 5);
}

static unsigned short smireg_to_reg(unsigned short reg)
{
	return reg & 0x1F;
}

static void ksz8895_write_smireg(struct phy_device *phydev, int smireg, int val)
{
	phydev->bus->write(phydev->bus, smireg_to_phy(smireg), MDIO_DEVAD_NONE,
						smireg_to_reg(smireg), val);
}

#if 0
static int ksz8895_read_smireg(struct phy_device *phydev, int smireg)
{
	return phydev->bus->read(phydev->bus, smireg_to_phy(smireg),
					MDIO_DEVAD_NONE, smireg_to_reg(smireg));
}
#endif

int ksz8895_config(struct phy_device *phydev)
{
	/* we are connected directly to the switch without
	 * dedicated PHY. SCONF1 == 001 */
	phydev->link = 1;
	phydev->duplex = DUPLEX_FULL;
	phydev->speed = SPEED_100;

	/* Force the switch to start */
	ksz8895_write_smireg(phydev, 1, 1);

	return 0;
}

static int ksz8895_startup(struct phy_device *phydev)
{
	return 0;
}

static struct phy_driver ksz8895_driver = {
	.name = "Micrel KSZ8895/KSZ8864",
	.uid  = 0x221450,
	.mask = 0xffffe1,
	.features = PHY_BASIC_FEATURES,
	.config   = &ksz8895_config,
	.startup  = &ksz8895_startup,
	.shutdown = &genphy_shutdown,
};

#ifndef CONFIG_PHY_MICREL_KSZ9021
/*
 * I can't believe Micrel used the exact same part number
 * for the KSZ9021. Shame Micrel, Shame!
 */
static struct phy_driver KS8721_driver = {
	.name = "Micrel KS8721BL",
	.uid = 0x221610,
	.mask = 0xfffff0,
	.features = PHY_BASIC_FEATURES,
	.config = &genphy_config,
	.startup = &genphy_startup,
	.shutdown = &genphy_shutdown,
};
#endif


/*
 * KSZ9021 - KSZ9031 common
 */

#define MII_KSZ90xx_PHY_CTL		0x1f
#define MIIM_KSZ90xx_PHYCTL_1000	(1 << 6)
#define MIIM_KSZ90xx_PHYCTL_100		(1 << 5)
#define MIIM_KSZ90xx_PHYCTL_10		(1 << 4)
#define MIIM_KSZ90xx_PHYCTL_DUPLEX	(1 << 3)

static int ksz90xx_startup(struct phy_device *phydev)
{
	unsigned phy_ctl;
	genphy_update_link(phydev);
	phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL);

	if (phy_ctl & MIIM_KSZ90xx_PHYCTL_DUPLEX)
		phydev->duplex = DUPLEX_FULL;
	else
		phydev->duplex = DUPLEX_HALF;

	if (phy_ctl & MIIM_KSZ90xx_PHYCTL_1000)
		phydev->speed = SPEED_1000;
	else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_100)
		phydev->speed = SPEED_100;
	else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_10)
		phydev->speed = SPEED_10;
	return 0;
}

/* Common OF config bits for KSZ9021 and KSZ9031 */
#if defined(CONFIG_PHY_MICREL_KSZ9021) || defined(CONFIG_PHY_MICREL_KSZ9031)
#ifdef CONFIG_DM_ETH
struct ksz90x1_reg_field {
	const char	*name;
	const u8	size;	/* Size of the bitfield, in bits */
	const u8	off;	/* Offset from bit 0 */
	const u8	dflt;	/* Default value */
};

struct ksz90x1_ofcfg {
	const u16			reg;
	const u16			devad;
	const struct ksz90x1_reg_field	*grp;
	const u16			grpsz;
};

static const struct ksz90x1_reg_field ksz90x1_rxd_grp[] = {
	{ "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 },
	{ "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 }
};

static const struct ksz90x1_reg_field ksz90x1_txd_grp[] = {
	{ "txd0-skew-ps", 4, 0, 0x7 }, { "txd1-skew-ps", 4, 4, 0x7 },
	{ "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 },
};

static int ksz90x1_of_config_group(struct phy_device *phydev,
				   struct ksz90x1_ofcfg *ofcfg)
{
	struct udevice *dev = phydev->dev;
	struct phy_driver *drv = phydev->drv;
	const int ps_to_regval = 200;
	int val[4];
	int i, changed = 0, offset, max;
	u16 regval = 0;

	if (!drv || !drv->writeext)
		return -EOPNOTSUPP;

	for (i = 0; i < ofcfg->grpsz; i++) {
		val[i] = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
					 ofcfg->grp[i].name, -1);
		offset = ofcfg->grp[i].off;
		if (val[i] == -1) {
			/* Default register value for KSZ9021 */
			regval |= ofcfg->grp[i].dflt << offset;
		} else {
			changed = 1;	/* Value was changed in OF */
			/* Calculate the register value and fix corner cases */
			if (val[i] > ps_to_regval * 0xf) {
				max = (1 << ofcfg->grp[i].size) - 1;
				regval |= max << offset;
			} else {
				regval |= (val[i] / ps_to_regval) << offset;
			}
		}
	}

	if (!changed)
		return 0;

	return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval);
}
#endif
#endif

#ifdef CONFIG_PHY_MICREL_KSZ9021
/*
 * KSZ9021
 */

/* PHY Registers */
#define MII_KSZ9021_EXTENDED_CTRL	0x0b
#define MII_KSZ9021_EXTENDED_DATAW	0x0c
#define MII_KSZ9021_EXTENDED_DATAR	0x0d

#define CTRL1000_PREFER_MASTER		(1 << 10)
#define CTRL1000_CONFIG_MASTER		(1 << 11)
#define CTRL1000_MANUAL_CONFIG		(1 << 12)

#ifdef CONFIG_DM_ETH
static const struct ksz90x1_reg_field ksz9021_clk_grp[] = {
	{ "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 },
	{ "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 },
};

static int ksz9021_of_config(struct phy_device *phydev)
{
	struct ksz90x1_ofcfg ofcfg[] = {
		{ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0, ksz90x1_rxd_grp, 4 },
		{ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0, ksz90x1_txd_grp, 4 },
		{ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0, ksz9021_clk_grp, 4 },
	};
	int i, ret = 0;

	for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
		ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
		if (ret)
			return ret;

	return 0;
}
#else
static int ksz9021_of_config(struct phy_device *phydev)
{
	return 0;
}
#endif

int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val)
{
	/* extended registers */
	phy_write(phydev, MDIO_DEVAD_NONE,
		MII_KSZ9021_EXTENDED_CTRL, regnum | 0x8000);
	return phy_write(phydev, MDIO_DEVAD_NONE,
		MII_KSZ9021_EXTENDED_DATAW, val);
}

int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum)
{
	/* extended registers */
	phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum);
	return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR);
}


static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr,
			      int regnum)
{
	return ksz9021_phy_extended_read(phydev, regnum);
}

static int ksz9021_phy_extwrite(struct phy_device *phydev, int addr,
			       int devaddr, int regnum, u16 val)
{
	return ksz9021_phy_extended_write(phydev, regnum, val);
}

/* Micrel ksz9021 */
static int ksz9021_config(struct phy_device *phydev)
{
	unsigned ctrl1000 = 0;
	const unsigned master = CTRL1000_PREFER_MASTER |
			CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG;
	unsigned features = phydev->drv->features;
	int ret;

	ret = ksz9021_of_config(phydev);
	if (ret)
		return ret;

	if (getenv("disable_giga"))
		features &= ~(SUPPORTED_1000baseT_Half |
				SUPPORTED_1000baseT_Full);
	/* force master mode for 1000BaseT due to chip errata */
	if (features & SUPPORTED_1000baseT_Half)
		ctrl1000 |= ADVERTISE_1000HALF | master;
	if (features & SUPPORTED_1000baseT_Full)
		ctrl1000 |= ADVERTISE_1000FULL | master;
	phydev->advertising = phydev->supported = features;
	phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000);
	genphy_config_aneg(phydev);
	genphy_restart_aneg(phydev);
	return 0;
}

static struct phy_driver ksz9021_driver = {
	.name = "Micrel ksz9021",
	.uid  = 0x221610,
	.mask = 0xfffff0,
	.features = PHY_GBIT_FEATURES,
	.config = &ksz9021_config,
	.startup = &ksz90xx_startup,
	.shutdown = &genphy_shutdown,
	.writeext = &ksz9021_phy_extwrite,
	.readext = &ksz9021_phy_extread,
};
#endif

/**
 * KSZ9031
 */
/* PHY Registers */
#define MII_KSZ9031_MMD_ACCES_CTRL	0x0d
#define MII_KSZ9031_MMD_REG_DATA	0x0e

#ifdef CONFIG_DM_ETH
static const struct ksz90x1_reg_field ksz9031_ctl_grp[] =
	{ { "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 } };
static const struct ksz90x1_reg_field ksz9031_clk_grp[] =
	{ { "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf } };

static int ksz9031_of_config(struct phy_device *phydev)
{
	struct ksz90x1_ofcfg ofcfg[] = {
		{ MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 },
		{ MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
		{ MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
		{ MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 },
	};
	int i, ret = 0;

	for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
		ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
		if (ret)
			return ret;

	return 0;
}
#else
static int ksz9031_of_config(struct phy_device *phydev)
{
	return 0;
}
#endif

/* Accessors to extended registers*/
int ksz9031_phy_extended_write(struct phy_device *phydev,
			       int devaddr, int regnum, u16 mode, u16 val)
{
	/*select register addr for mmd*/
	phy_write(phydev, MDIO_DEVAD_NONE,
		  MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
	/*select register for mmd*/
	phy_write(phydev, MDIO_DEVAD_NONE,
		  MII_KSZ9031_MMD_REG_DATA, regnum);
	/*setup mode*/
	phy_write(phydev, MDIO_DEVAD_NONE,
		  MII_KSZ9031_MMD_ACCES_CTRL, (mode | devaddr));
	/*write the value*/
	return	phy_write(phydev, MDIO_DEVAD_NONE,
		MII_KSZ9031_MMD_REG_DATA, val);
}

int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
			      int regnum, u16 mode)
{
	phy_write(phydev, MDIO_DEVAD_NONE,
		  MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
	phy_write(phydev, MDIO_DEVAD_NONE,
		  MII_KSZ9031_MMD_REG_DATA, regnum);
	phy_write(phydev, MDIO_DEVAD_NONE,
		  MII_KSZ9031_MMD_ACCES_CTRL, (devaddr | mode));
	return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9031_MMD_REG_DATA);
}

static int ksz9031_phy_extread(struct phy_device *phydev, int addr, int devaddr,
			       int regnum)
{
	return ksz9031_phy_extended_read(phydev, devaddr, regnum,
					 MII_KSZ9031_MOD_DATA_NO_POST_INC);
};

static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
				int devaddr, int regnum, u16 val)
{
	return ksz9031_phy_extended_write(phydev, devaddr, regnum,
					 MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
};

static int ksz9031_config(struct phy_device *phydev)
{
	int ret;
	ret = ksz9031_of_config(phydev);
	if (ret)
		return ret;
	return genphy_config(phydev);
}

static struct phy_driver ksz9031_driver = {
	.name = "Micrel ksz9031",
	.uid  = 0x221620,
	.mask = 0xfffff0,
	.features = PHY_GBIT_FEATURES,
	.config   = &ksz9031_config,
	.startup  = &ksz90xx_startup,
	.shutdown = &genphy_shutdown,
	.writeext = &ksz9031_phy_extwrite,
	.readext = &ksz9031_phy_extread,
};

int phy_micrel_init(void)
{
	phy_register(&KSZ804_driver);
	phy_register(&KSZ8031_driver);
	phy_register(&KSZ8051_driver);
	phy_register(&KSZ8081_driver);
#ifdef CONFIG_PHY_MICREL_KSZ9021
	phy_register(&ksz9021_driver);
#else
	phy_register(&KS8721_driver);
#endif
	phy_register(&ksz9031_driver);
	phy_register(&ksz8895_driver);
	return 0;
}
Commit	Line	Data
9082eeac AF	1	/*
	2	* Micrel PHY drivers
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
9082eeac AF	5	*
	6	* Copyright 2010-2011 Freescale Semiconductor, Inc.
	7	* author Andy Fleming
62d7dba7	8	* (C) 2012 NetModule AG, David Andrey, added KSZ9031
9082eeac	9	*/
8682aba7 TK	10	#include <config.h>
8682aba7 TK	11	#include <common.h>
22854bda MV	12	#include <dm.h>
	13	#include <errno.h>
	14	#include <fdtdec.h>
8682aba7	15	#include <micrel.h>
9082eeac AF	16	#include <phy.h>
9082eeac AF	17
22854bda MV	18	DECLARE_GLOBAL_DATA_PTR;
22854bda MV	19
9082eeac AF	20	static struct phy_driver KSZ804_driver = {
	21	.name = "Micrel KSZ804",
	22	.uid = 0x221510,
	23	.mask = 0xfffff0,
	24	.features = PHY_BASIC_FEATURES,
	25	.config = &genphy_config,
	26	.startup = &genphy_startup,
	27	.shutdown = &genphy_shutdown,
	28	};
	29
79e3efd5 AM	30	#define MII_KSZPHY_OMSO 0x16
	31	#define KSZPHY_OMSO_B_CAST_OFF (1 << 9)
	32
	33	static int ksz_genconfig_bcastoff(struct phy_device *phydev)
	34	{
	35	int ret;
	36
	37	ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO);
	38	if (ret < 0)
	39	return ret;
	40
	41	ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO,
	42	ret \| KSZPHY_OMSO_B_CAST_OFF);
	43	if (ret < 0)
	44	return ret;
	45
	46	return genphy_config(phydev);
	47	}
	48
6617f876 SL	49	static struct phy_driver KSZ8031_driver = {
	50	.name = "Micrel KSZ8021/KSZ8031",
	51	.uid = 0x221550,
	52	.mask = 0xfffff0,
	53	.features = PHY_BASIC_FEATURES,
79e3efd5	54	.config = &ksz_genconfig_bcastoff,
6617f876 SL	55	.startup = &genphy_startup,
	56	.shutdown = &genphy_shutdown,
	57	};
	58
4f485150 SR	59	/**
	60	* KSZ8051
	61	*/
	62	#define MII_KSZ8051_PHY_OMSO 0x16
	63	#define MII_KSZ8051_PHY_OMSO_NAND_TREE_ON (1 << 5)
	64
	65	static int ksz8051_config(struct phy_device *phydev)
	66	{
	67	unsigned val;
	68
	69	/* Disable NAND-tree */
	70	val = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO);
	71	val &= ~MII_KSZ8051_PHY_OMSO_NAND_TREE_ON;
	72	phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO, val);
	73
	74	return genphy_config(phydev);
	75	}
	76
	77	static struct phy_driver KSZ8051_driver = {
	78	.name = "Micrel KSZ8051",
	79	.uid = 0x221550,
	80	.mask = 0xfffff0,
	81	.features = PHY_BASIC_FEATURES,
	82	.config = &ksz8051_config,
	83	.startup = &genphy_startup,
	84	.shutdown = &genphy_shutdown,
	85	};
	86
c6a40f6e LE	87	static struct phy_driver KSZ8081_driver = {
	88	.name = "Micrel KSZ8081",
	89	.uid = 0x221560,
	90	.mask = 0xfffff0,
	91	.features = PHY_BASIC_FEATURES,
79e3efd5	92	.config = &ksz_genconfig_bcastoff,
c6a40f6e LE	93	.startup = &genphy_startup,
	94	.shutdown = &genphy_shutdown,
	95	};
	96
b7a5b084 PDM	97	/**
	98	* KSZ8895
	99	*/
	100
	101	static unsigned short smireg_to_phy(unsigned short reg)
	102	{
	103	return ((reg & 0xc0) >> 3) + 0x06 + ((reg & 0x20) >> 5);
	104	}
	105
	106	static unsigned short smireg_to_reg(unsigned short reg)
	107	{
	108	return reg & 0x1F;
	109	}
	110
	111	static void ksz8895_write_smireg(struct phy_device *phydev, int smireg, int val)
	112	{
	113	phydev->bus->write(phydev->bus, smireg_to_phy(smireg), MDIO_DEVAD_NONE,
	114	smireg_to_reg(smireg), val);
	115	}
	116
	117	#if 0
	118	static int ksz8895_read_smireg(struct phy_device *phydev, int smireg)
	119	{
	120	return phydev->bus->read(phydev->bus, smireg_to_phy(smireg),
	121	MDIO_DEVAD_NONE, smireg_to_reg(smireg));
	122	}
	123	#endif
	124
	125	int ksz8895_config(struct phy_device *phydev)
	126	{
	127	/* we are connected directly to the switch without
	128	* dedicated PHY. SCONF1 == 001 */
	129	phydev->link = 1;
	130	phydev->duplex = DUPLEX_FULL;
	131	phydev->speed = SPEED_100;
	132
	133	/* Force the switch to start */
	134	ksz8895_write_smireg(phydev, 1, 1);
	135
	136	return 0;
	137	}
	138
	139	static int ksz8895_startup(struct phy_device *phydev)
	140	{
	141	return 0;
	142	}
	143
	144	static struct phy_driver ksz8895_driver = {
	145	.name = "Micrel KSZ8895/KSZ8864",
	146	.uid = 0x221450,
	147	.mask = 0xffffe1,
	148	.features = PHY_BASIC_FEATURES,
	149	.config = &ksz8895_config,
	150	.startup = &ksz8895_startup,
	151	.shutdown = &genphy_shutdown,
	152	};
	153
cc5f5522 TK	154	#ifndef CONFIG_PHY_MICREL_KSZ9021
	155	/*
	156	* I can't believe Micrel used the exact same part number
58ec63d6	157	* for the KSZ9021. Shame Micrel, Shame!
cc5f5522	158	*/
fcc0c75d VZ	159	static struct phy_driver KS8721_driver = {
	160	.name = "Micrel KS8721BL",
	161	.uid = 0x221610,
	162	.mask = 0xfffff0,
	163	.features = PHY_BASIC_FEATURES,
	164	.config = &genphy_config,
	165	.startup = &genphy_startup,
	166	.shutdown = &genphy_shutdown,
	167	};
cc5f5522	168	#endif
fcc0c75d	169
62d7dba7	170
58ec63d6	171	/*
62d7dba7 DA	172	* KSZ9021 - KSZ9031 common
	173	*/
	174
	175	#define MII_KSZ90xx_PHY_CTL 0x1f
	176	#define MIIM_KSZ90xx_PHYCTL_1000 (1 << 6)
	177	#define MIIM_KSZ90xx_PHYCTL_100 (1 << 5)
	178	#define MIIM_KSZ90xx_PHYCTL_10 (1 << 4)
	179	#define MIIM_KSZ90xx_PHYCTL_DUPLEX (1 << 3)
	180
	181	static int ksz90xx_startup(struct phy_device *phydev)
	182	{
	183	unsigned phy_ctl;
	184	genphy_update_link(phydev);
	185	phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL);
	186
	187	if (phy_ctl & MIIM_KSZ90xx_PHYCTL_DUPLEX)
	188	phydev->duplex = DUPLEX_FULL;
	189	else
	190	phydev->duplex = DUPLEX_HALF;
	191
	192	if (phy_ctl & MIIM_KSZ90xx_PHYCTL_1000)
	193	phydev->speed = SPEED_1000;
	194	else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_100)
	195	phydev->speed = SPEED_100;
	196	else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_10)
	197	phydev->speed = SPEED_10;
	198	return 0;
	199	}
62d7dba7	200
22854bda MV	201	/* Common OF config bits for KSZ9021 and KSZ9031 */
	202	#if defined(CONFIG_PHY_MICREL_KSZ9021) \|\| defined(CONFIG_PHY_MICREL_KSZ9031)
	203	#ifdef CONFIG_DM_ETH
	204	struct ksz90x1_reg_field {
	205	const char *name;
	206	const u8 size; /* Size of the bitfield, in bits */
	207	const u8 off; /* Offset from bit 0 */
	208	const u8 dflt; /* Default value */
	209	};
	210
	211	struct ksz90x1_ofcfg {
	212	const u16 reg;
	213	const u16 devad;
	214	const struct ksz90x1_reg_field *grp;
	215	const u16 grpsz;
	216	};
	217
	218	static const struct ksz90x1_reg_field ksz90x1_rxd_grp[] = {
	219	{ "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 },
	220	{ "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 }
	221	};
	222
	223	static const struct ksz90x1_reg_field ksz90x1_txd_grp[] = {
	224	{ "txd0-skew-ps", 4, 0, 0x7 }, { "txd1-skew-ps", 4, 4, 0x7 },
	225	{ "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 },
	226	};
	227
	228	static int ksz90x1_of_config_group(struct phy_device *phydev,
	229	struct ksz90x1_ofcfg *ofcfg)
	230	{
	231	struct udevice *dev = phydev->dev;
	232	struct phy_driver *drv = phydev->drv;
	233	const int ps_to_regval = 200;
	234	int val[4];
	235	int i, changed = 0, offset, max;
	236	u16 regval = 0;
	237
	238	if (!drv \|\| !drv->writeext)
	239	return -EOPNOTSUPP;
	240
	241	for (i = 0; i < ofcfg->grpsz; i++) {
	242	val[i] = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
	243	ofcfg->grp[i].name, -1);
	244	offset = ofcfg->grp[i].off;
	245	if (val[i] == -1) {
	246	/* Default register value for KSZ9021 */
	247	regval \|= ofcfg->grp[i].dflt << offset;
	248	} else {
	249	changed = 1; /* Value was changed in OF */
	250	/* Calculate the register value and fix corner cases */
	251	if (val[i] > ps_to_regval * 0xf) {
	252	max = (1 << ofcfg->grp[i].size) - 1;
	253	regval \|= max << offset;
	254	} else {
	255	regval \|= (val[i] / ps_to_regval) << offset;
	256	}
	257	}
	258	}
	259
	260	if (!changed)
	261	return 0;
	262
	263	return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval);
	264	}
265	#endif
266	#endif
267
58ec63d6	268	#ifdef CONFIG_PHY_MICREL_KSZ9021
62d7dba7 DA	269	/*
	270	* KSZ9021
	271	*/
	272
	273	/* PHY Registers */
8682aba7 TK	274	#define MII_KSZ9021_EXTENDED_CTRL 0x0b
	275	#define MII_KSZ9021_EXTENDED_DATAW 0x0c
	276	#define MII_KSZ9021_EXTENDED_DATAR 0x0d
8682aba7 TK	277
	278	#define CTRL1000_PREFER_MASTER (1 << 10)
	279	#define CTRL1000_CONFIG_MASTER (1 << 11)
	280	#define CTRL1000_MANUAL_CONFIG (1 << 12)
	281
22854bda MV	282	#ifdef CONFIG_DM_ETH
	283	static const struct ksz90x1_reg_field ksz9021_clk_grp[] = {
	284	{ "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 },
	285	{ "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 },
	286	};
	287
	288	static int ksz9021_of_config(struct phy_device *phydev)
	289	{
	290	struct ksz90x1_ofcfg ofcfg[] = {
	291	{ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0, ksz90x1_rxd_grp, 4 },
	292	{ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0, ksz90x1_txd_grp, 4 },
	293	{ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0, ksz9021_clk_grp, 4 },
	294	};
	295	int i, ret = 0;
	296
	297	for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
	298	ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
	299	if (ret)
	300	return ret;
	301
	302	return 0;
	303	}
	304	#else
	305	static int ksz9021_of_config(struct phy_device *phydev)
	306	{
	307	return 0;
	308	}
	309	#endif
	310
8682aba7 TK	311	int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val)
	312	{
	313	/* extended registers */
	314	phy_write(phydev, MDIO_DEVAD_NONE,
	315	MII_KSZ9021_EXTENDED_CTRL, regnum \| 0x8000);
	316	return phy_write(phydev, MDIO_DEVAD_NONE,
	317	MII_KSZ9021_EXTENDED_DATAW, val);
	318	}
	319
	320	int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum)
	321	{
	322	/* extended registers */
	323	phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum);
	324	return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR);
	325	}
	326
9ced16fe SB	327
	328	static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr,
	329	int regnum)
	330	{
	331	return ksz9021_phy_extended_read(phydev, regnum);
	332	}
	333
	334	static int ksz9021_phy_extwrite(struct phy_device *phydev, int addr,
	335	int devaddr, int regnum, u16 val)
	336	{
	337	return ksz9021_phy_extended_write(phydev, regnum, val);
	338	}
	339
8682aba7 TK	340	/* Micrel ksz9021 */
	341	static int ksz9021_config(struct phy_device *phydev)
	342	{
	343	unsigned ctrl1000 = 0;
	344	const unsigned master = CTRL1000_PREFER_MASTER \|
	345	CTRL1000_CONFIG_MASTER \| CTRL1000_MANUAL_CONFIG;
	346	unsigned features = phydev->drv->features;
22854bda MV	347	int ret;
	348
	349	ret = ksz9021_of_config(phydev);
	350	if (ret)
	351	return ret;
8682aba7 TK	352
	353	if (getenv("disable_giga"))
	354	features &= ~(SUPPORTED_1000baseT_Half \|
	355	SUPPORTED_1000baseT_Full);
	356	/* force master mode for 1000BaseT due to chip errata */
	357	if (features & SUPPORTED_1000baseT_Half)
	358	ctrl1000 \|= ADVERTISE_1000HALF \| master;
	359	if (features & SUPPORTED_1000baseT_Full)
	360	ctrl1000 \|= ADVERTISE_1000FULL \| master;
	361	phydev->advertising = phydev->supported = features;
	362	phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000);
	363	genphy_config_aneg(phydev);
	364	genphy_restart_aneg(phydev);
	365	return 0;
	366	}
	367
8682aba7 TK	368	static struct phy_driver ksz9021_driver = {
	369	.name = "Micrel ksz9021",
	370	.uid = 0x221610,
	371	.mask = 0xfffff0,
	372	.features = PHY_GBIT_FEATURES,
	373	.config = &ksz9021_config,
62d7dba7	374	.startup = &ksz90xx_startup,
8682aba7	375	.shutdown = &genphy_shutdown,
9ced16fe SB	376	.writeext = &ksz9021_phy_extwrite,
9ced16fe SB	377	.readext = &ksz9021_phy_extread,
8682aba7	378	};
cc5f5522	379	#endif
8682aba7	380
42a7cb50	381	/**
62d7dba7 DA	382	* KSZ9031
62d7dba7 DA	383	*/
42a7cb50 SL	384	/* PHY Registers */
	385	#define MII_KSZ9031_MMD_ACCES_CTRL 0x0d
	386	#define MII_KSZ9031_MMD_REG_DATA 0x0e
	387
22854bda MV	388	#ifdef CONFIG_DM_ETH
	389	static const struct ksz90x1_reg_field ksz9031_ctl_grp[] =
	390	{ { "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 } };
	391	static const struct ksz90x1_reg_field ksz9031_clk_grp[] =
	392	{ { "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf } };
	393
	394	static int ksz9031_of_config(struct phy_device *phydev)
	395	{
	396	struct ksz90x1_ofcfg ofcfg[] = {
	397	{ MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 },
	398	{ MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
	399	{ MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
	400	{ MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 },
	401	};
	402	int i, ret = 0;
	403
	404	for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
	405	ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
	406	if (ret)
	407	return ret;
	408
	409	return 0;
	410	}
	411	#else
	412	static int ksz9031_of_config(struct phy_device *phydev)
	413	{
	414	return 0;
	415	}
	416	#endif
	417
42a7cb50 SL	418	/* Accessors to extended registers*/
	419	int ksz9031_phy_extended_write(struct phy_device *phydev,
	420	int devaddr, int regnum, u16 mode, u16 val)
	421	{
	422	/select register addr for mmd/
	423	phy_write(phydev, MDIO_DEVAD_NONE,
	424	MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
	425	/select register for mmd/
	426	phy_write(phydev, MDIO_DEVAD_NONE,
	427	MII_KSZ9031_MMD_REG_DATA, regnum);
	428	/setup mode/
	429	phy_write(phydev, MDIO_DEVAD_NONE,
	430	MII_KSZ9031_MMD_ACCES_CTRL, (mode \| devaddr));
	431	/write the value/
	432	return phy_write(phydev, MDIO_DEVAD_NONE,
	433	MII_KSZ9031_MMD_REG_DATA, val);
	434	}
	435
	436	int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
	437	int regnum, u16 mode)
	438	{
	439	phy_write(phydev, MDIO_DEVAD_NONE,
	440	MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
	441	phy_write(phydev, MDIO_DEVAD_NONE,
	442	MII_KSZ9031_MMD_REG_DATA, regnum);
	443	phy_write(phydev, MDIO_DEVAD_NONE,
	444	MII_KSZ9031_MMD_ACCES_CTRL, (devaddr \| mode));
	445	return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9031_MMD_REG_DATA);
	446	}
	447
9ced16fe SB	448	static int ksz9031_phy_extread(struct phy_device *phydev, int addr, int devaddr,
	449	int regnum)
	450	{
	451	return ksz9031_phy_extended_read(phydev, devaddr, regnum,
	452	MII_KSZ9031_MOD_DATA_NO_POST_INC);
	453	};
	454
	455	static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
	456	int devaddr, int regnum, u16 val)
	457	{
	458	return ksz9031_phy_extended_write(phydev, devaddr, regnum,
	459	MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
	460	};
	461
22854bda MV	462	static int ksz9031_config(struct phy_device *phydev)
	463	{
	464	int ret;
	465	ret = ksz9031_of_config(phydev);
	466	if (ret)
	467	return ret;
	468	return genphy_config(phydev);
	469	}
9ced16fe	470
62d7dba7 DA	471	static struct phy_driver ksz9031_driver = {
	472	.name = "Micrel ksz9031",
	473	.uid = 0x221620,
e8194d58	474	.mask = 0xfffff0,
62d7dba7	475	.features = PHY_GBIT_FEATURES,
22854bda	476	.config = &ksz9031_config,
62d7dba7 DA	477	.startup = &ksz90xx_startup,
62d7dba7 DA	478	.shutdown = &genphy_shutdown,
9ced16fe SB	479	.writeext = &ksz9031_phy_extwrite,
9ced16fe SB	480	.readext = &ksz9031_phy_extread,
62d7dba7 DA	481	};
62d7dba7 DA	482
9082eeac AF	483	int phy_micrel_init(void)
	484	{
	485	phy_register(&KSZ804_driver);
6617f876	486	phy_register(&KSZ8031_driver);
4f485150	487	phy_register(&KSZ8051_driver);
c6a40f6e	488	phy_register(&KSZ8081_driver);
cc5f5522	489	#ifdef CONFIG_PHY_MICREL_KSZ9021
8682aba7	490	phy_register(&ksz9021_driver);
cc5f5522 TK	491	#else
	492	phy_register(&KS8721_driver);
	493	#endif
62d7dba7	494	phy_register(&ksz9031_driver);
b7a5b084	495	phy_register(&ksz8895_driver);
9082eeac AF	496	return 0;
9082eeac AF	497	}