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Commit | Line | Data |
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9082eeac AF |
1 | /* |
2 | * Micrel PHY drivers | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
9082eeac AF |
5 | * |
6 | * Copyright 2010-2011 Freescale Semiconductor, Inc. | |
7 | * author Andy Fleming | |
62d7dba7 | 8 | * (C) 2012 NetModule AG, David Andrey, added KSZ9031 |
9082eeac | 9 | */ |
8682aba7 TK |
10 | #include <config.h> |
11 | #include <common.h> | |
22854bda MV |
12 | #include <dm.h> |
13 | #include <errno.h> | |
14 | #include <fdtdec.h> | |
8682aba7 | 15 | #include <micrel.h> |
9082eeac AF |
16 | #include <phy.h> |
17 | ||
22854bda MV |
18 | DECLARE_GLOBAL_DATA_PTR; |
19 | ||
9082eeac AF |
20 | static struct phy_driver KSZ804_driver = { |
21 | .name = "Micrel KSZ804", | |
22 | .uid = 0x221510, | |
23 | .mask = 0xfffff0, | |
24 | .features = PHY_BASIC_FEATURES, | |
25 | .config = &genphy_config, | |
26 | .startup = &genphy_startup, | |
27 | .shutdown = &genphy_shutdown, | |
28 | }; | |
29 | ||
79e3efd5 AM |
30 | #define MII_KSZPHY_OMSO 0x16 |
31 | #define KSZPHY_OMSO_B_CAST_OFF (1 << 9) | |
32 | ||
33 | static int ksz_genconfig_bcastoff(struct phy_device *phydev) | |
34 | { | |
35 | int ret; | |
36 | ||
37 | ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO); | |
38 | if (ret < 0) | |
39 | return ret; | |
40 | ||
41 | ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO, | |
42 | ret | KSZPHY_OMSO_B_CAST_OFF); | |
43 | if (ret < 0) | |
44 | return ret; | |
45 | ||
46 | return genphy_config(phydev); | |
47 | } | |
48 | ||
6617f876 SL |
49 | static struct phy_driver KSZ8031_driver = { |
50 | .name = "Micrel KSZ8021/KSZ8031", | |
51 | .uid = 0x221550, | |
52 | .mask = 0xfffff0, | |
53 | .features = PHY_BASIC_FEATURES, | |
79e3efd5 | 54 | .config = &ksz_genconfig_bcastoff, |
6617f876 SL |
55 | .startup = &genphy_startup, |
56 | .shutdown = &genphy_shutdown, | |
57 | }; | |
58 | ||
4f485150 SR |
59 | /** |
60 | * KSZ8051 | |
61 | */ | |
62 | #define MII_KSZ8051_PHY_OMSO 0x16 | |
63 | #define MII_KSZ8051_PHY_OMSO_NAND_TREE_ON (1 << 5) | |
64 | ||
65 | static int ksz8051_config(struct phy_device *phydev) | |
66 | { | |
67 | unsigned val; | |
68 | ||
69 | /* Disable NAND-tree */ | |
70 | val = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO); | |
71 | val &= ~MII_KSZ8051_PHY_OMSO_NAND_TREE_ON; | |
72 | phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO, val); | |
73 | ||
74 | return genphy_config(phydev); | |
75 | } | |
76 | ||
77 | static struct phy_driver KSZ8051_driver = { | |
78 | .name = "Micrel KSZ8051", | |
79 | .uid = 0x221550, | |
80 | .mask = 0xfffff0, | |
81 | .features = PHY_BASIC_FEATURES, | |
82 | .config = &ksz8051_config, | |
83 | .startup = &genphy_startup, | |
84 | .shutdown = &genphy_shutdown, | |
85 | }; | |
86 | ||
c6a40f6e LE |
87 | static struct phy_driver KSZ8081_driver = { |
88 | .name = "Micrel KSZ8081", | |
89 | .uid = 0x221560, | |
90 | .mask = 0xfffff0, | |
91 | .features = PHY_BASIC_FEATURES, | |
79e3efd5 | 92 | .config = &ksz_genconfig_bcastoff, |
c6a40f6e LE |
93 | .startup = &genphy_startup, |
94 | .shutdown = &genphy_shutdown, | |
95 | }; | |
96 | ||
b7a5b084 PDM |
97 | /** |
98 | * KSZ8895 | |
99 | */ | |
100 | ||
101 | static unsigned short smireg_to_phy(unsigned short reg) | |
102 | { | |
103 | return ((reg & 0xc0) >> 3) + 0x06 + ((reg & 0x20) >> 5); | |
104 | } | |
105 | ||
106 | static unsigned short smireg_to_reg(unsigned short reg) | |
107 | { | |
108 | return reg & 0x1F; | |
109 | } | |
110 | ||
111 | static void ksz8895_write_smireg(struct phy_device *phydev, int smireg, int val) | |
112 | { | |
113 | phydev->bus->write(phydev->bus, smireg_to_phy(smireg), MDIO_DEVAD_NONE, | |
114 | smireg_to_reg(smireg), val); | |
115 | } | |
116 | ||
117 | #if 0 | |
118 | static int ksz8895_read_smireg(struct phy_device *phydev, int smireg) | |
119 | { | |
120 | return phydev->bus->read(phydev->bus, smireg_to_phy(smireg), | |
121 | MDIO_DEVAD_NONE, smireg_to_reg(smireg)); | |
122 | } | |
123 | #endif | |
124 | ||
125 | int ksz8895_config(struct phy_device *phydev) | |
126 | { | |
127 | /* we are connected directly to the switch without | |
128 | * dedicated PHY. SCONF1 == 001 */ | |
129 | phydev->link = 1; | |
130 | phydev->duplex = DUPLEX_FULL; | |
131 | phydev->speed = SPEED_100; | |
132 | ||
133 | /* Force the switch to start */ | |
134 | ksz8895_write_smireg(phydev, 1, 1); | |
135 | ||
136 | return 0; | |
137 | } | |
138 | ||
139 | static int ksz8895_startup(struct phy_device *phydev) | |
140 | { | |
141 | return 0; | |
142 | } | |
143 | ||
144 | static struct phy_driver ksz8895_driver = { | |
145 | .name = "Micrel KSZ8895/KSZ8864", | |
146 | .uid = 0x221450, | |
147 | .mask = 0xffffe1, | |
148 | .features = PHY_BASIC_FEATURES, | |
149 | .config = &ksz8895_config, | |
150 | .startup = &ksz8895_startup, | |
151 | .shutdown = &genphy_shutdown, | |
152 | }; | |
153 | ||
cc5f5522 TK |
154 | #ifndef CONFIG_PHY_MICREL_KSZ9021 |
155 | /* | |
156 | * I can't believe Micrel used the exact same part number | |
58ec63d6 | 157 | * for the KSZ9021. Shame Micrel, Shame! |
cc5f5522 | 158 | */ |
fcc0c75d VZ |
159 | static struct phy_driver KS8721_driver = { |
160 | .name = "Micrel KS8721BL", | |
161 | .uid = 0x221610, | |
162 | .mask = 0xfffff0, | |
163 | .features = PHY_BASIC_FEATURES, | |
164 | .config = &genphy_config, | |
165 | .startup = &genphy_startup, | |
166 | .shutdown = &genphy_shutdown, | |
167 | }; | |
cc5f5522 | 168 | #endif |
fcc0c75d | 169 | |
62d7dba7 | 170 | |
58ec63d6 | 171 | /* |
62d7dba7 DA |
172 | * KSZ9021 - KSZ9031 common |
173 | */ | |
174 | ||
175 | #define MII_KSZ90xx_PHY_CTL 0x1f | |
176 | #define MIIM_KSZ90xx_PHYCTL_1000 (1 << 6) | |
177 | #define MIIM_KSZ90xx_PHYCTL_100 (1 << 5) | |
178 | #define MIIM_KSZ90xx_PHYCTL_10 (1 << 4) | |
179 | #define MIIM_KSZ90xx_PHYCTL_DUPLEX (1 << 3) | |
180 | ||
181 | static int ksz90xx_startup(struct phy_device *phydev) | |
182 | { | |
183 | unsigned phy_ctl; | |
184 | genphy_update_link(phydev); | |
185 | phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL); | |
186 | ||
187 | if (phy_ctl & MIIM_KSZ90xx_PHYCTL_DUPLEX) | |
188 | phydev->duplex = DUPLEX_FULL; | |
189 | else | |
190 | phydev->duplex = DUPLEX_HALF; | |
191 | ||
192 | if (phy_ctl & MIIM_KSZ90xx_PHYCTL_1000) | |
193 | phydev->speed = SPEED_1000; | |
194 | else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_100) | |
195 | phydev->speed = SPEED_100; | |
196 | else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_10) | |
197 | phydev->speed = SPEED_10; | |
198 | return 0; | |
199 | } | |
62d7dba7 | 200 | |
22854bda MV |
201 | /* Common OF config bits for KSZ9021 and KSZ9031 */ |
202 | #if defined(CONFIG_PHY_MICREL_KSZ9021) || defined(CONFIG_PHY_MICREL_KSZ9031) | |
203 | #ifdef CONFIG_DM_ETH | |
204 | struct ksz90x1_reg_field { | |
205 | const char *name; | |
206 | const u8 size; /* Size of the bitfield, in bits */ | |
207 | const u8 off; /* Offset from bit 0 */ | |
208 | const u8 dflt; /* Default value */ | |
209 | }; | |
210 | ||
211 | struct ksz90x1_ofcfg { | |
212 | const u16 reg; | |
213 | const u16 devad; | |
214 | const struct ksz90x1_reg_field *grp; | |
215 | const u16 grpsz; | |
216 | }; | |
217 | ||
218 | static const struct ksz90x1_reg_field ksz90x1_rxd_grp[] = { | |
219 | { "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 }, | |
220 | { "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 } | |
221 | }; | |
222 | ||
223 | static const struct ksz90x1_reg_field ksz90x1_txd_grp[] = { | |
224 | { "txd0-skew-ps", 4, 0, 0x7 }, { "txd1-skew-ps", 4, 4, 0x7 }, | |
225 | { "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 }, | |
226 | }; | |
227 | ||
228 | static int ksz90x1_of_config_group(struct phy_device *phydev, | |
229 | struct ksz90x1_ofcfg *ofcfg) | |
230 | { | |
231 | struct udevice *dev = phydev->dev; | |
232 | struct phy_driver *drv = phydev->drv; | |
ff7bd212 | 233 | const int ps_to_regval = 60; |
22854bda MV |
234 | int val[4]; |
235 | int i, changed = 0, offset, max; | |
236 | u16 regval = 0; | |
237 | ||
238 | if (!drv || !drv->writeext) | |
239 | return -EOPNOTSUPP; | |
240 | ||
241 | for (i = 0; i < ofcfg->grpsz; i++) { | |
242 | val[i] = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, | |
243 | ofcfg->grp[i].name, -1); | |
244 | offset = ofcfg->grp[i].off; | |
245 | if (val[i] == -1) { | |
246 | /* Default register value for KSZ9021 */ | |
247 | regval |= ofcfg->grp[i].dflt << offset; | |
248 | } else { | |
249 | changed = 1; /* Value was changed in OF */ | |
250 | /* Calculate the register value and fix corner cases */ | |
251 | if (val[i] > ps_to_regval * 0xf) { | |
252 | max = (1 << ofcfg->grp[i].size) - 1; | |
253 | regval |= max << offset; | |
254 | } else { | |
255 | regval |= (val[i] / ps_to_regval) << offset; | |
256 | } | |
257 | } | |
258 | } | |
259 | ||
260 | if (!changed) | |
261 | return 0; | |
262 | ||
263 | return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval); | |
264 | } | |
265 | #endif | |
266 | #endif | |
267 | ||
58ec63d6 | 268 | #ifdef CONFIG_PHY_MICREL_KSZ9021 |
62d7dba7 DA |
269 | /* |
270 | * KSZ9021 | |
271 | */ | |
272 | ||
273 | /* PHY Registers */ | |
8682aba7 TK |
274 | #define MII_KSZ9021_EXTENDED_CTRL 0x0b |
275 | #define MII_KSZ9021_EXTENDED_DATAW 0x0c | |
276 | #define MII_KSZ9021_EXTENDED_DATAR 0x0d | |
8682aba7 TK |
277 | |
278 | #define CTRL1000_PREFER_MASTER (1 << 10) | |
279 | #define CTRL1000_CONFIG_MASTER (1 << 11) | |
280 | #define CTRL1000_MANUAL_CONFIG (1 << 12) | |
281 | ||
347348f9 M |
282 | #if defined(CONFIG_DM_ETH) && (defined(CONFIG_PHY_MICREL_KSZ9021) || \ |
283 | defined(CONFIG_PHY_MICREL_KSZ9031)) | |
22854bda MV |
284 | static const struct ksz90x1_reg_field ksz9021_clk_grp[] = { |
285 | { "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 }, | |
286 | { "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 }, | |
287 | }; | |
288 | ||
289 | static int ksz9021_of_config(struct phy_device *phydev) | |
290 | { | |
291 | struct ksz90x1_ofcfg ofcfg[] = { | |
292 | { MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0, ksz90x1_rxd_grp, 4 }, | |
293 | { MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0, ksz90x1_txd_grp, 4 }, | |
294 | { MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0, ksz9021_clk_grp, 4 }, | |
295 | }; | |
296 | int i, ret = 0; | |
297 | ||
298 | for (i = 0; i < ARRAY_SIZE(ofcfg); i++) | |
299 | ret = ksz90x1_of_config_group(phydev, &(ofcfg[i])); | |
300 | if (ret) | |
301 | return ret; | |
302 | ||
303 | return 0; | |
304 | } | |
305 | #else | |
306 | static int ksz9021_of_config(struct phy_device *phydev) | |
307 | { | |
308 | return 0; | |
309 | } | |
310 | #endif | |
311 | ||
8682aba7 TK |
312 | int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val) |
313 | { | |
314 | /* extended registers */ | |
315 | phy_write(phydev, MDIO_DEVAD_NONE, | |
316 | MII_KSZ9021_EXTENDED_CTRL, regnum | 0x8000); | |
317 | return phy_write(phydev, MDIO_DEVAD_NONE, | |
318 | MII_KSZ9021_EXTENDED_DATAW, val); | |
319 | } | |
320 | ||
321 | int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum) | |
322 | { | |
323 | /* extended registers */ | |
324 | phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum); | |
325 | return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR); | |
326 | } | |
327 | ||
9ced16fe SB |
328 | |
329 | static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr, | |
330 | int regnum) | |
331 | { | |
332 | return ksz9021_phy_extended_read(phydev, regnum); | |
333 | } | |
334 | ||
335 | static int ksz9021_phy_extwrite(struct phy_device *phydev, int addr, | |
336 | int devaddr, int regnum, u16 val) | |
337 | { | |
338 | return ksz9021_phy_extended_write(phydev, regnum, val); | |
339 | } | |
340 | ||
8682aba7 TK |
341 | /* Micrel ksz9021 */ |
342 | static int ksz9021_config(struct phy_device *phydev) | |
343 | { | |
344 | unsigned ctrl1000 = 0; | |
345 | const unsigned master = CTRL1000_PREFER_MASTER | | |
346 | CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG; | |
347 | unsigned features = phydev->drv->features; | |
22854bda MV |
348 | int ret; |
349 | ||
350 | ret = ksz9021_of_config(phydev); | |
351 | if (ret) | |
352 | return ret; | |
8682aba7 TK |
353 | |
354 | if (getenv("disable_giga")) | |
355 | features &= ~(SUPPORTED_1000baseT_Half | | |
356 | SUPPORTED_1000baseT_Full); | |
357 | /* force master mode for 1000BaseT due to chip errata */ | |
358 | if (features & SUPPORTED_1000baseT_Half) | |
359 | ctrl1000 |= ADVERTISE_1000HALF | master; | |
360 | if (features & SUPPORTED_1000baseT_Full) | |
361 | ctrl1000 |= ADVERTISE_1000FULL | master; | |
362 | phydev->advertising = phydev->supported = features; | |
363 | phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000); | |
364 | genphy_config_aneg(phydev); | |
365 | genphy_restart_aneg(phydev); | |
366 | return 0; | |
367 | } | |
368 | ||
8682aba7 TK |
369 | static struct phy_driver ksz9021_driver = { |
370 | .name = "Micrel ksz9021", | |
371 | .uid = 0x221610, | |
372 | .mask = 0xfffff0, | |
373 | .features = PHY_GBIT_FEATURES, | |
374 | .config = &ksz9021_config, | |
62d7dba7 | 375 | .startup = &ksz90xx_startup, |
8682aba7 | 376 | .shutdown = &genphy_shutdown, |
9ced16fe SB |
377 | .writeext = &ksz9021_phy_extwrite, |
378 | .readext = &ksz9021_phy_extread, | |
8682aba7 | 379 | }; |
cc5f5522 | 380 | #endif |
8682aba7 | 381 | |
42a7cb50 | 382 | /** |
62d7dba7 DA |
383 | * KSZ9031 |
384 | */ | |
42a7cb50 SL |
385 | /* PHY Registers */ |
386 | #define MII_KSZ9031_MMD_ACCES_CTRL 0x0d | |
387 | #define MII_KSZ9031_MMD_REG_DATA 0x0e | |
388 | ||
347348f9 M |
389 | #if defined(CONFIG_DM_ETH) && (defined(CONFIG_PHY_MICREL_KSZ9021) || \ |
390 | defined(CONFIG_PHY_MICREL_KSZ9031)) | |
22854bda MV |
391 | static const struct ksz90x1_reg_field ksz9031_ctl_grp[] = |
392 | { { "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 } }; | |
393 | static const struct ksz90x1_reg_field ksz9031_clk_grp[] = | |
394 | { { "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf } }; | |
395 | ||
396 | static int ksz9031_of_config(struct phy_device *phydev) | |
397 | { | |
398 | struct ksz90x1_ofcfg ofcfg[] = { | |
399 | { MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 }, | |
400 | { MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 }, | |
401 | { MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 }, | |
402 | { MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 }, | |
403 | }; | |
404 | int i, ret = 0; | |
405 | ||
406 | for (i = 0; i < ARRAY_SIZE(ofcfg); i++) | |
407 | ret = ksz90x1_of_config_group(phydev, &(ofcfg[i])); | |
408 | if (ret) | |
409 | return ret; | |
410 | ||
411 | return 0; | |
412 | } | |
413 | #else | |
414 | static int ksz9031_of_config(struct phy_device *phydev) | |
415 | { | |
416 | return 0; | |
417 | } | |
418 | #endif | |
419 | ||
42a7cb50 SL |
420 | /* Accessors to extended registers*/ |
421 | int ksz9031_phy_extended_write(struct phy_device *phydev, | |
422 | int devaddr, int regnum, u16 mode, u16 val) | |
423 | { | |
424 | /*select register addr for mmd*/ | |
425 | phy_write(phydev, MDIO_DEVAD_NONE, | |
426 | MII_KSZ9031_MMD_ACCES_CTRL, devaddr); | |
427 | /*select register for mmd*/ | |
428 | phy_write(phydev, MDIO_DEVAD_NONE, | |
429 | MII_KSZ9031_MMD_REG_DATA, regnum); | |
430 | /*setup mode*/ | |
431 | phy_write(phydev, MDIO_DEVAD_NONE, | |
432 | MII_KSZ9031_MMD_ACCES_CTRL, (mode | devaddr)); | |
433 | /*write the value*/ | |
434 | return phy_write(phydev, MDIO_DEVAD_NONE, | |
435 | MII_KSZ9031_MMD_REG_DATA, val); | |
436 | } | |
437 | ||
438 | int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr, | |
439 | int regnum, u16 mode) | |
440 | { | |
441 | phy_write(phydev, MDIO_DEVAD_NONE, | |
442 | MII_KSZ9031_MMD_ACCES_CTRL, devaddr); | |
443 | phy_write(phydev, MDIO_DEVAD_NONE, | |
444 | MII_KSZ9031_MMD_REG_DATA, regnum); | |
445 | phy_write(phydev, MDIO_DEVAD_NONE, | |
446 | MII_KSZ9031_MMD_ACCES_CTRL, (devaddr | mode)); | |
447 | return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9031_MMD_REG_DATA); | |
448 | } | |
449 | ||
9ced16fe SB |
450 | static int ksz9031_phy_extread(struct phy_device *phydev, int addr, int devaddr, |
451 | int regnum) | |
452 | { | |
453 | return ksz9031_phy_extended_read(phydev, devaddr, regnum, | |
454 | MII_KSZ9031_MOD_DATA_NO_POST_INC); | |
455 | }; | |
456 | ||
457 | static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr, | |
458 | int devaddr, int regnum, u16 val) | |
459 | { | |
460 | return ksz9031_phy_extended_write(phydev, devaddr, regnum, | |
461 | MII_KSZ9031_MOD_DATA_POST_INC_RW, val); | |
462 | }; | |
463 | ||
22854bda MV |
464 | static int ksz9031_config(struct phy_device *phydev) |
465 | { | |
466 | int ret; | |
467 | ret = ksz9031_of_config(phydev); | |
468 | if (ret) | |
469 | return ret; | |
470 | return genphy_config(phydev); | |
471 | } | |
9ced16fe | 472 | |
62d7dba7 DA |
473 | static struct phy_driver ksz9031_driver = { |
474 | .name = "Micrel ksz9031", | |
475 | .uid = 0x221620, | |
e8194d58 | 476 | .mask = 0xfffff0, |
62d7dba7 | 477 | .features = PHY_GBIT_FEATURES, |
22854bda | 478 | .config = &ksz9031_config, |
62d7dba7 DA |
479 | .startup = &ksz90xx_startup, |
480 | .shutdown = &genphy_shutdown, | |
9ced16fe SB |
481 | .writeext = &ksz9031_phy_extwrite, |
482 | .readext = &ksz9031_phy_extread, | |
62d7dba7 DA |
483 | }; |
484 | ||
9082eeac AF |
485 | int phy_micrel_init(void) |
486 | { | |
487 | phy_register(&KSZ804_driver); | |
6617f876 | 488 | phy_register(&KSZ8031_driver); |
4f485150 | 489 | phy_register(&KSZ8051_driver); |
c6a40f6e | 490 | phy_register(&KSZ8081_driver); |
cc5f5522 | 491 | #ifdef CONFIG_PHY_MICREL_KSZ9021 |
8682aba7 | 492 | phy_register(&ksz9021_driver); |
cc5f5522 TK |
493 | #else |
494 | phy_register(&KS8721_driver); | |
495 | #endif | |
62d7dba7 | 496 | phy_register(&ksz9031_driver); |
b7a5b084 | 497 | phy_register(&ksz8895_driver); |
9082eeac AF |
498 | return 0; |
499 | } |