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r8169: support control of advertising.
[thirdparty/kernel/stable.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
bca03d5f 27#include <linux/firmware.h>
1da177e4 28
99f252b0 29#include <asm/system.h>
1da177e4
LT		 30#include <asm/io.h>
31#include <asm/irq.h>
32
865c652d 33#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 34#define MODULENAME "r8169"
35#define PFX MODULENAME ": "
36
bca03d5f 37#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
38#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
5a5e4443 39#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
bca03d5f 40
1da177e4
LT		 41#ifdef RTL8169_DEBUG
42#define assert(expr) \
5b0384f4
FR		 43 if (!(expr)) { \
44 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 45 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 46 }
06fa7358
JP		 47#define dprintk(fmt, args...) \
48 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 49#else
50#define assert(expr) do {} while (0)
51#define dprintk(fmt, args...) do {} while (0)
52#endif /* RTL8169_DEBUG */
53
b57b7e5a 54#define R8169_MSG_DEFAULT \
f0e837d9 55 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 56
1da177e4
LT		 57#define TX_BUFFS_AVAIL(tp) \
58 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
59
1da177e4
LT		 60/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
61 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 62static const int multicast_filter_limit = 32;
1da177e4
LT		 63
64/* MAC address length */
65#define MAC_ADDR_LEN 6
66
9c14ceaf 67#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 68#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
69#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
70#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
1da177e4
LT		 71#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
72#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
73
74#define R8169_REGS_SIZE 256
75#define R8169_NAPI_WEIGHT 64
76#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
77#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
78#define RX_BUF_SIZE 1536 /* Rx Buffer size */
79#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
80#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
81
82#define RTL8169_TX_TIMEOUT (6*HZ)
83#define RTL8169_PHY_TIMEOUT (10*HZ)
84
ea8dbdd1 85#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
86#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 87#define RTL_EEPROM_SIG_ADDR 0x0000
88
1da177e4
LT		 89/* write/read MMIO register */
90#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
91#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
92#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
93#define RTL_R8(reg) readb (ioaddr + (reg))
94#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 95#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 96
97enum mac_version {
f21b75e9 98 RTL_GIGA_MAC_NONE = 0x00,
ba6eb6ee
FR		 99 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
100 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
101 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
102 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
103 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 104 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2857ffb7
FR		 105 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
106 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
107 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
108 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
2dd99530 109 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 110 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
111 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
112 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
113 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
114 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
115 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
116 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
117 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
197ff761 118 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
6fb07058 119 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
ef3386f0 120 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
7f3e3d3a 121 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
5b538df9 122 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
daf9df6d 123 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
124 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
e6de30d6 125 RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP
126 RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP
5a5e4443
HW		 127 RTL_GIGA_MAC_VER_29 = 0x1d, // 8105E
128 RTL_GIGA_MAC_VER_30 = 0x1e, // 8105E
1da177e4
LT		 129};
130
1da177e4
LT		 131#define _R(NAME,MAC,MASK) \
132 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
133
3c6bee1d 134static const struct {
1da177e4
LT		 135 const char *name;
136 u8 mac_version;
137 u32 RxConfigMask; /* Clears the bits supported by this chip */
138} rtl_chip_info[] = {
ba6eb6ee
FR		 139 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
140 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
141 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
142 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
143 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 144 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
2857ffb7
FR		 145 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
146 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
147 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
148 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
bcf0bf90
FR		 149 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
150 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
151 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
152 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 153 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
154 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
155 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
156 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
157 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
197ff761 158 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
6fb07058 159 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
ef3386f0 160 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
7f3e3d3a 161 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
5b538df9 162 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
daf9df6d 163 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
164 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
e6de30d6 165 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880), // PCI-E
5a5e4443
HW		 166 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_28, 0xff7e1880), // PCI-E
167 _R("RTL8105e", RTL_GIGA_MAC_VER_29, 0xff7e1880), // PCI-E
168 _R("RTL8105e", RTL_GIGA_MAC_VER_30, 0xff7e1880) // PCI-E
1da177e4
LT		 169};
170#undef _R
171
bcf0bf90
FR		 172enum cfg_version {
173 RTL_CFG_0 = 0x00,
174 RTL_CFG_1,
175 RTL_CFG_2
176};
177
07ce4064
FR		 178static void rtl_hw_start_8169(struct net_device *);
179static void rtl_hw_start_8168(struct net_device *);
180static void rtl_hw_start_8101(struct net_device *);
181
a3aa1884 182static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 183 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 184 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 185 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 186 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 187 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
188 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 189 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 190 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
191 { PCI_VENDOR_ID_LINKSYS, 0x1032,
192 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 193 { 0x0001, 0x8168,
194 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 195 {0,},
196};
197
198MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
199
6f0333b8 200static int rx_buf_sz = 16383;
4300e8c7 201static int use_dac;
b57b7e5a
SH		 202static struct {
203 u32 msg_enable;
204} debug = { -1 };
1da177e4 205
07d3f51f
FR		 206enum rtl_registers {
207 MAC0 = 0, /* Ethernet hardware address. */
773d2021 208 MAC4 = 4,
07d3f51f
FR		 209 MAR0 = 8, /* Multicast filter. */
210 CounterAddrLow = 0x10,
211 CounterAddrHigh = 0x14,
212 TxDescStartAddrLow = 0x20,
213 TxDescStartAddrHigh = 0x24,
214 TxHDescStartAddrLow = 0x28,
215 TxHDescStartAddrHigh = 0x2c,
216 FLASH = 0x30,
217 ERSR = 0x36,
218 ChipCmd = 0x37,
219 TxPoll = 0x38,
220 IntrMask = 0x3c,
221 IntrStatus = 0x3e,
222 TxConfig = 0x40,
223 RxConfig = 0x44,
224 RxMissed = 0x4c,
225 Cfg9346 = 0x50,
226 Config0 = 0x51,
227 Config1 = 0x52,
228 Config2 = 0x53,
229 Config3 = 0x54,
230 Config4 = 0x55,
231 Config5 = 0x56,
232 MultiIntr = 0x5c,
233 PHYAR = 0x60,
07d3f51f
FR		 234 PHYstatus = 0x6c,
235 RxMaxSize = 0xda,
236 CPlusCmd = 0xe0,
237 IntrMitigate = 0xe2,
238 RxDescAddrLow = 0xe4,
239 RxDescAddrHigh = 0xe8,
f0298f81 240 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
241
242#define NoEarlyTx 0x3f /* Max value : no early transmit. */
243
244 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
245
246#define TxPacketMax (8064 >> 7)
247
07d3f51f
FR		 248 FuncEvent = 0xf0,
249 FuncEventMask = 0xf4,
250 FuncPresetState = 0xf8,
251 FuncForceEvent = 0xfc,
1da177e4
LT		 252};
253
f162a5d1
FR		 254enum rtl8110_registers {
255 TBICSR = 0x64,
256 TBI_ANAR = 0x68,
257 TBI_LPAR = 0x6a,
258};
259
260enum rtl8168_8101_registers {
261 CSIDR = 0x64,
262 CSIAR = 0x68,
263#define CSIAR_FLAG 0x80000000
264#define CSIAR_WRITE_CMD 0x80000000
265#define CSIAR_BYTE_ENABLE 0x0f
266#define CSIAR_BYTE_ENABLE_SHIFT 12
267#define CSIAR_ADDR_MASK 0x0fff
065c27c1 268 PMCH = 0x6f,
f162a5d1
FR		 269 EPHYAR = 0x80,
270#define EPHYAR_FLAG 0x80000000
271#define EPHYAR_WRITE_CMD 0x80000000
272#define EPHYAR_REG_MASK 0x1f
273#define EPHYAR_REG_SHIFT 16
274#define EPHYAR_DATA_MASK 0xffff
5a5e4443
HW		 275 DLLPR = 0xd0,
276#define PM_SWITCH (1 << 6)
f162a5d1
FR		 277 DBG_REG = 0xd1,
278#define FIX_NAK_1 (1 << 4)
279#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 280 TWSI = 0xd2,
281 MCU = 0xd3,
282#define EN_NDP (1 << 3)
283#define EN_OOB_RESET (1 << 2)
daf9df6d 284 EFUSEAR = 0xdc,
285#define EFUSEAR_FLAG 0x80000000
286#define EFUSEAR_WRITE_CMD 0x80000000
287#define EFUSEAR_READ_CMD 0x00000000
288#define EFUSEAR_REG_MASK 0x03ff
289#define EFUSEAR_REG_SHIFT 8
290#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 291};
292
c0e45c1c 293enum rtl8168_registers {
b646d900 294 ERIDR = 0x70,
295 ERIAR = 0x74,
296#define ERIAR_FLAG 0x80000000
297#define ERIAR_WRITE_CMD 0x80000000
298#define ERIAR_READ_CMD 0x00000000
299#define ERIAR_ADDR_BYTE_ALIGN 4
300#define ERIAR_EXGMAC 0
301#define ERIAR_MSIX 1
302#define ERIAR_ASF 2
303#define ERIAR_TYPE_SHIFT 16
304#define ERIAR_BYTEEN 0x0f
305#define ERIAR_BYTEEN_SHIFT 12
c0e45c1c 306 EPHY_RXER_NUM = 0x7c,
307 OCPDR = 0xb0, /* OCP GPHY access */
308#define OCPDR_WRITE_CMD 0x80000000
309#define OCPDR_READ_CMD 0x00000000
310#define OCPDR_REG_MASK 0x7f
311#define OCPDR_GPHY_REG_SHIFT 16
312#define OCPDR_DATA_MASK 0xffff
313 OCPAR = 0xb4,
314#define OCPAR_FLAG 0x80000000
315#define OCPAR_GPHY_WRITE_CMD 0x8000f060
316#define OCPAR_GPHY_READ_CMD 0x0000f060
e6de30d6 317 RDSAR1 = 0xd0 /* 8168c only. Undocumented on 8168dp */
c0e45c1c 318};
319
07d3f51f 320enum rtl_register_content {
1da177e4 321 /* InterruptStatusBits */
07d3f51f
FR		 322 SYSErr = 0x8000,
323 PCSTimeout = 0x4000,
324 SWInt = 0x0100,
325 TxDescUnavail = 0x0080,
326 RxFIFOOver = 0x0040,
327 LinkChg = 0x0020,
328 RxOverflow = 0x0010,
329 TxErr = 0x0008,
330 TxOK = 0x0004,
331 RxErr = 0x0002,
332 RxOK = 0x0001,
1da177e4
LT		 333
334 /* RxStatusDesc */
9dccf611
FR		 335 RxFOVF = (1 << 23),
336 RxRWT = (1 << 22),
337 RxRES = (1 << 21),
338 RxRUNT = (1 << 20),
339 RxCRC = (1 << 19),
1da177e4
LT		 340
341 /* ChipCmdBits */
07d3f51f
FR		 342 CmdReset = 0x10,
343 CmdRxEnb = 0x08,
344 CmdTxEnb = 0x04,
345 RxBufEmpty = 0x01,
1da177e4 346
275391a4
FR		 347 /* TXPoll register p.5 */
348 HPQ = 0x80, /* Poll cmd on the high prio queue */
349 NPQ = 0x40, /* Poll cmd on the low prio queue */
350 FSWInt = 0x01, /* Forced software interrupt */
351
1da177e4 352 /* Cfg9346Bits */
07d3f51f
FR		 353 Cfg9346_Lock = 0x00,
354 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 355
356 /* rx_mode_bits */
07d3f51f
FR		 357 AcceptErr = 0x20,
358 AcceptRunt = 0x10,
359 AcceptBroadcast = 0x08,
360 AcceptMulticast = 0x04,
361 AcceptMyPhys = 0x02,
362 AcceptAllPhys = 0x01,
1da177e4
LT		 363
364 /* RxConfigBits */
07d3f51f
FR		 365 RxCfgFIFOShift = 13,
366 RxCfgDMAShift = 8,
1da177e4
LT		 367
368 /* TxConfigBits */
369 TxInterFrameGapShift = 24,
370 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
371
5d06a99f 372 /* Config1 register p.24 */
f162a5d1
FR		 373 LEDS1 = (1 << 7),
374 LEDS0 = (1 << 6),
fbac58fc 375 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 376 Speed_down = (1 << 4),
377 MEMMAP = (1 << 3),
378 IOMAP = (1 << 2),
379 VPD = (1 << 1),
5d06a99f
FR		 380 PMEnable = (1 << 0), /* Power Management Enable */
381
6dccd16b
FR		 382 /* Config2 register p. 25 */
383 PCI_Clock_66MHz = 0x01,
384 PCI_Clock_33MHz = 0x00,
385
61a4dcc2
FR		 386 /* Config3 register p.25 */
387 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
388 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 389 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 390
5d06a99f 391 /* Config5 register p.27 */
61a4dcc2
FR		 392 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
393 MWF = (1 << 5), /* Accept Multicast wakeup frame */
394 UWF = (1 << 4), /* Accept Unicast wakeup frame */
395 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 396 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
397
1da177e4
LT		 398 /* TBICSR p.28 */
399 TBIReset = 0x80000000,
400 TBILoopback = 0x40000000,
401 TBINwEnable = 0x20000000,
402 TBINwRestart = 0x10000000,
403 TBILinkOk = 0x02000000,
404 TBINwComplete = 0x01000000,
405
406 /* CPlusCmd p.31 */
f162a5d1
FR		 407 EnableBist = (1 << 15), // 8168 8101
408 Mac_dbgo_oe = (1 << 14), // 8168 8101
409 Normal_mode = (1 << 13), // unused
410 Force_half_dup = (1 << 12), // 8168 8101
411 Force_rxflow_en = (1 << 11), // 8168 8101
412 Force_txflow_en = (1 << 10), // 8168 8101
413 Cxpl_dbg_sel = (1 << 9), // 8168 8101
414 ASF = (1 << 8), // 8168 8101
415 PktCntrDisable = (1 << 7), // 8168 8101
416 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 417 RxVlan = (1 << 6),
418 RxChkSum = (1 << 5),
419 PCIDAC = (1 << 4),
420 PCIMulRW = (1 << 3),
0e485150
FR		 421 INTT_0 = 0x0000, // 8168
422 INTT_1 = 0x0001, // 8168
423 INTT_2 = 0x0002, // 8168
424 INTT_3 = 0x0003, // 8168
1da177e4
LT		 425
426 /* rtl8169_PHYstatus */
07d3f51f
FR		 427 TBI_Enable = 0x80,
428 TxFlowCtrl = 0x40,
429 RxFlowCtrl = 0x20,
430 _1000bpsF = 0x10,
431 _100bps = 0x08,
432 _10bps = 0x04,
433 LinkStatus = 0x02,
434 FullDup = 0x01,
1da177e4 435
1da177e4 436 /* _TBICSRBit */
07d3f51f 437 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 438
439 /* DumpCounterCommand */
07d3f51f 440 CounterDump = 0x8,
1da177e4
LT		 441};
442
07d3f51f 443enum desc_status_bit {
1da177e4
LT		 444 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
445 RingEnd = (1 << 30), /* End of descriptor ring */
446 FirstFrag = (1 << 29), /* First segment of a packet */
447 LastFrag = (1 << 28), /* Final segment of a packet */
448
449 /* Tx private */
450 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
451 MSSShift = 16, /* MSS value position */
452 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
453 IPCS = (1 << 18), /* Calculate IP checksum */
454 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
455 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
456 TxVlanTag = (1 << 17), /* Add VLAN tag */
457
458 /* Rx private */
459 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
460 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
461
462#define RxProtoUDP (PID1)
463#define RxProtoTCP (PID0)
464#define RxProtoIP (PID1 | PID0)
465#define RxProtoMask RxProtoIP
466
467 IPFail = (1 << 16), /* IP checksum failed */
468 UDPFail = (1 << 15), /* UDP/IP checksum failed */
469 TCPFail = (1 << 14), /* TCP/IP checksum failed */
470 RxVlanTag = (1 << 16), /* VLAN tag available */
471};
472
473#define RsvdMask 0x3fffc000
474
475struct TxDesc {
6cccd6e7
REB		 476 __le32 opts1;
477 __le32 opts2;
478 __le64 addr;
1da177e4
LT		 479};
480
481struct RxDesc {
6cccd6e7
REB		 482 __le32 opts1;
483 __le32 opts2;
484 __le64 addr;
1da177e4
LT		 485};
486
487struct ring_info {
488 struct sk_buff *skb;
489 u32 len;
490 u8 __pad[sizeof(void *) - sizeof(u32)];
491};
492
f23e7fda 493enum features {
ccdffb9a
FR		 494 RTL_FEATURE_WOL = (1 << 0),
495 RTL_FEATURE_MSI = (1 << 1),
496 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 497};
498
355423d0
IV		 499struct rtl8169_counters {
500 __le64 tx_packets;
501 __le64 rx_packets;
502 __le64 tx_errors;
503 __le32 rx_errors;
504 __le16 rx_missed;
505 __le16 align_errors;
506 __le32 tx_one_collision;
507 __le32 tx_multi_collision;
508 __le64 rx_unicast;
509 __le64 rx_broadcast;
510 __le32 rx_multicast;
511 __le16 tx_aborted;
512 __le16 tx_underun;
513};
514
1da177e4
LT		 515struct rtl8169_private {
516 void __iomem *mmio_addr; /* memory map physical address */
517 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 518 struct net_device *dev;
bea3348e 519 struct napi_struct napi;
1da177e4 520 spinlock_t lock; /* spin lock flag */
b57b7e5a 521 u32 msg_enable;
1da177e4
LT		 522 int chipset;
523 int mac_version;
1da177e4
LT		 524 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
525 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
526 u32 dirty_rx;
527 u32 dirty_tx;
528 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
529 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
530 dma_addr_t TxPhyAddr;
531 dma_addr_t RxPhyAddr;
6f0333b8 532 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 533 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 534 struct timer_list timer;
535 u16 cp_cmd;
0e485150
FR		 536 u16 intr_event;
537 u16 napi_event;
1da177e4 538 u16 intr_mask;
1da177e4
LT		 539 int phy_1000_ctrl_reg;
540#ifdef CONFIG_R8169_VLAN
541 struct vlan_group *vlgrp;
542#endif
c0e45c1c 543
544 struct mdio_ops {
545 void (*write)(void __iomem *, int, int);
546 int (*read)(void __iomem *, int);
547 } mdio_ops;
548
065c27c1 549 struct pll_power_ops {
550 void (*down)(struct rtl8169_private *);
551 void (*up)(struct rtl8169_private *);
552 } pll_power_ops;
553
54405cde 554 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 555 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 556 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 557 void (*hw_start)(struct net_device *);
4da19633 558 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 559 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 560 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
9c14ceaf 561 int pcie_cap;
c4028958 562 struct delayed_work task;
f23e7fda 563 unsigned features;
ccdffb9a
FR		 564
565 struct mii_if_info mii;
355423d0 566 struct rtl8169_counters counters;
e1759441 567 u32 saved_wolopts;
f1e02ed1 568
569 const struct firmware *fw;
1da177e4
LT		 570};
571
979b6c13 572MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 573MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 574module_param(use_dac, int, 0);
4300e8c7 575MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 576module_param_named(debug, debug.msg_enable, int, 0);
577MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 578MODULE_LICENSE("GPL");
579MODULE_VERSION(RTL8169_VERSION);
bca03d5f 580MODULE_FIRMWARE(FIRMWARE_8168D_1);
581MODULE_FIRMWARE(FIRMWARE_8168D_2);
5a5e4443 582MODULE_FIRMWARE(FIRMWARE_8105E_1);
1da177e4
LT		 583
584static int rtl8169_open(struct net_device *dev);
61357325
SH		 585static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
586 struct net_device *dev);
7d12e780 587static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 588static int rtl8169_init_ring(struct net_device *dev);
07ce4064 589static void rtl_hw_start(struct net_device *dev);
1da177e4 590static int rtl8169_close(struct net_device *dev);
07ce4064 591static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 592static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 593static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 594static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 595 void __iomem *, u32 budget);
4dcb7d33 596static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 597static void rtl8169_down(struct net_device *dev);
99f252b0 598static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 599static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 600
1da177e4 601static const unsigned int rtl8169_rx_config =
5b0384f4 602 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 603
b646d900 604static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
605{
606 void __iomem *ioaddr = tp->mmio_addr;
607 int i;
608
609 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
610 for (i = 0; i < 20; i++) {
611 udelay(100);
612 if (RTL_R32(OCPAR) & OCPAR_FLAG)
613 break;
614 }
615 return RTL_R32(OCPDR);
616}
617
618static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
619{
620 void __iomem *ioaddr = tp->mmio_addr;
621 int i;
622
623 RTL_W32(OCPDR, data);
624 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
625 for (i = 0; i < 20; i++) {
626 udelay(100);
627 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
628 break;
629 }
630}
631
632static void rtl8168_oob_notify(void __iomem *ioaddr, u8 cmd)
633{
634 int i;
635
636 RTL_W8(ERIDR, cmd);
637 RTL_W32(ERIAR, 0x800010e8);
638 msleep(2);
639 for (i = 0; i < 5; i++) {
640 udelay(100);
641 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
642 break;
643 }
644
645 ocp_write(ioaddr, 0x1, 0x30, 0x00000001);
646}
647
648#define OOB_CMD_RESET 0x00
649#define OOB_CMD_DRIVER_START 0x05
650#define OOB_CMD_DRIVER_STOP 0x06
651
652static void rtl8168_driver_start(struct rtl8169_private *tp)
653{
654 int i;
655
656 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
657
658 for (i = 0; i < 10; i++) {
659 msleep(10);
660 if (ocp_read(tp, 0x0f, 0x0010) & 0x00000800)
661 break;
662 }
663}
664
665static void rtl8168_driver_stop(struct rtl8169_private *tp)
666{
667 int i;
668
669 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
670
671 for (i = 0; i < 10; i++) {
672 msleep(10);
673 if ((ocp_read(tp, 0x0f, 0x0010) & 0x00000800) == 0)
674 break;
675 }
676}
677
678
4da19633 679static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 680{
681 int i;
682
a6baf3af 683 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 684
2371408c 685 for (i = 20; i > 0; i--) {
07d3f51f
FR		 686 /*
687 * Check if the RTL8169 has completed writing to the specified
688 * MII register.
689 */
5b0384f4 690 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 691 break;
2371408c 692 udelay(25);
1da177e4 693 }
024a07ba 694 /*
81a95f04
TT		 695 * According to hardware specs a 20us delay is required after write
696 * complete indication, but before sending next command.
024a07ba 697 */
81a95f04 698 udelay(20);
1da177e4
LT		 699}
700
4da19633 701static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 702{
703 int i, value = -1;
704
a6baf3af 705 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 706
2371408c 707 for (i = 20; i > 0; i--) {
07d3f51f
FR		 708 /*
709 * Check if the RTL8169 has completed retrieving data from
710 * the specified MII register.
711 */
1da177e4 712 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 713 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 714 break;
715 }
2371408c 716 udelay(25);
1da177e4 717 }
81a95f04
TT		 718 /*
719 * According to hardware specs a 20us delay is required after read
720 * complete indication, but before sending next command.
721 */
722 udelay(20);
723
1da177e4
LT		 724 return value;
725}
726
c0e45c1c 727static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
728{
729 int i;
730
731 RTL_W32(OCPDR, data |
732 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
733 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
734 RTL_W32(EPHY_RXER_NUM, 0);
735
736 for (i = 0; i < 100; i++) {
737 mdelay(1);
738 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
739 break;
740 }
741}
742
743static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
744{
745 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
746 (value & OCPDR_DATA_MASK));
747}
748
749static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
750{
751 int i;
752
753 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
754
755 mdelay(1);
756 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
757 RTL_W32(EPHY_RXER_NUM, 0);
758
759 for (i = 0; i < 100; i++) {
760 mdelay(1);
761 if (RTL_R32(OCPAR) & OCPAR_FLAG)
762 break;
763 }
764
765 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
766}
767
e6de30d6 768#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
769
770static void r8168dp_2_mdio_start(void __iomem *ioaddr)
771{
772 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
773}
774
775static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
776{
777 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
778}
779
780static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
781{
782 r8168dp_2_mdio_start(ioaddr);
783
784 r8169_mdio_write(ioaddr, reg_addr, value);
785
786 r8168dp_2_mdio_stop(ioaddr);
787}
788
789static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
790{
791 int value;
792
793 r8168dp_2_mdio_start(ioaddr);
794
795 value = r8169_mdio_read(ioaddr, reg_addr);
796
797 r8168dp_2_mdio_stop(ioaddr);
798
799 return value;
800}
801
4da19633 802static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 803{
c0e45c1c 804 tp->mdio_ops.write(tp->mmio_addr, location, val);
dacf8154
FR		 805}
806
4da19633 807static int rtl_readphy(struct rtl8169_private *tp, int location)
808{
c0e45c1c 809 return tp->mdio_ops.read(tp->mmio_addr, location);
4da19633 810}
811
812static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
813{
814 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
815}
816
817static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 818{
819 int val;
820
4da19633 821 val = rtl_readphy(tp, reg_addr);
822 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 823}
824
ccdffb9a
FR		 825static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
826 int val)
827{
828 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 829
4da19633 830 rtl_writephy(tp, location, val);
ccdffb9a
FR		 831}
832
833static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
834{
835 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 836
4da19633 837 return rtl_readphy(tp, location);
ccdffb9a
FR		 838}
839
dacf8154
FR		 840static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
841{
842 unsigned int i;
843
844 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
845 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
846
847 for (i = 0; i < 100; i++) {
848 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
849 break;
850 udelay(10);
851 }
852}
853
854static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
855{
856 u16 value = 0xffff;
857 unsigned int i;
858
859 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
860
861 for (i = 0; i < 100; i++) {
862 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
863 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
864 break;
865 }
866 udelay(10);
867 }
868
869 return value;
870}
871
872static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
873{
874 unsigned int i;
875
876 RTL_W32(CSIDR, value);
877 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
878 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
879
880 for (i = 0; i < 100; i++) {
881 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
882 break;
883 udelay(10);
884 }
885}
886
887static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
888{
889 u32 value = ~0x00;
890 unsigned int i;
891
892 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
893 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
894
895 for (i = 0; i < 100; i++) {
896 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
897 value = RTL_R32(CSIDR);
898 break;
899 }
900 udelay(10);
901 }
902
903 return value;
904}
905
daf9df6d 906static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
907{
908 u8 value = 0xff;
909 unsigned int i;
910
911 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
912
913 for (i = 0; i < 300; i++) {
914 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
915 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
916 break;
917 }
918 udelay(100);
919 }
920
921 return value;
922}
923
1da177e4
LT		 924static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
925{
926 RTL_W16(IntrMask, 0x0000);
927
928 RTL_W16(IntrStatus, 0xffff);
929}
930
931static void rtl8169_asic_down(void __iomem *ioaddr)
932{
933 RTL_W8(ChipCmd, 0x00);
934 rtl8169_irq_mask_and_ack(ioaddr);
935 RTL_R16(CPlusCmd);
936}
937
4da19633 938static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 939{
4da19633 940 void __iomem *ioaddr = tp->mmio_addr;
941
1da177e4
LT		 942 return RTL_R32(TBICSR) & TBIReset;
943}
944
4da19633 945static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 946{
4da19633 947 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 948}
949
950static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
951{
952 return RTL_R32(TBICSR) & TBILinkOk;
953}
954
955static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
956{
957 return RTL_R8(PHYstatus) & LinkStatus;
958}
959
4da19633 960static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 961{
4da19633 962 void __iomem *ioaddr = tp->mmio_addr;
963
1da177e4
LT		 964 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
965}
966
4da19633 967static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 968{
969 unsigned int val;
970
4da19633 971 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
972 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 973}
974
e4fbce74 975static void __rtl8169_check_link_status(struct net_device *dev,
07d3f51f 976 struct rtl8169_private *tp,
e4fbce74
RW		 977 void __iomem *ioaddr,
978 bool pm)
1da177e4
LT		 979{
980 unsigned long flags;
981
982 spin_lock_irqsave(&tp->lock, flags);
983 if (tp->link_ok(ioaddr)) {
e1759441 984 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 985 if (pm)
986 pm_request_resume(&tp->pci_dev->dev);
1da177e4 987 netif_carrier_on(dev);
1519e57f
FR		 988 if (net_ratelimit())
989 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 990 } else {
1da177e4 991 netif_carrier_off(dev);
bf82c189 992 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74
RW		 993 if (pm)
994 pm_schedule_suspend(&tp->pci_dev->dev, 100);
b57b7e5a 995 }
1da177e4
LT		 996 spin_unlock_irqrestore(&tp->lock, flags);
997}
998
e4fbce74
RW		 999static void rtl8169_check_link_status(struct net_device *dev,
1000 struct rtl8169_private *tp,
1001 void __iomem *ioaddr)
1002{
1003 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1004}
1005
e1759441
RW		 1006#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1007
1008static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1009{
61a4dcc2
FR		 1010 void __iomem *ioaddr = tp->mmio_addr;
1011 u8 options;
e1759441 1012 u32 wolopts = 0;
61a4dcc2
FR		 1013
1014 options = RTL_R8(Config1);
1015 if (!(options & PMEnable))
e1759441 1016 return 0;
61a4dcc2
FR		 1017
1018 options = RTL_R8(Config3);
1019 if (options & LinkUp)
e1759441 1020 wolopts |= WAKE_PHY;
61a4dcc2 1021 if (options & MagicPacket)
e1759441 1022 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1023
1024 options = RTL_R8(Config5);
1025 if (options & UWF)
e1759441 1026 wolopts |= WAKE_UCAST;
61a4dcc2 1027 if (options & BWF)
e1759441 1028 wolopts |= WAKE_BCAST;
61a4dcc2 1029 if (options & MWF)
e1759441 1030 wolopts |= WAKE_MCAST;
61a4dcc2 1031
e1759441 1032 return wolopts;
61a4dcc2
FR		 1033}
1034
e1759441 1035static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1036{
1037 struct rtl8169_private *tp = netdev_priv(dev);
e1759441
RW		 1038
1039 spin_lock_irq(&tp->lock);
1040
1041 wol->supported = WAKE_ANY;
1042 wol->wolopts = __rtl8169_get_wol(tp);
1043
1044 spin_unlock_irq(&tp->lock);
1045}
1046
1047static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1048{
61a4dcc2 1049 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1050 unsigned int i;
350f7596 1051 static const struct {
61a4dcc2
FR		 1052 u32 opt;
1053 u16 reg;
1054 u8 mask;
1055 } cfg[] = {
1056 { WAKE_ANY, Config1, PMEnable },
1057 { WAKE_PHY, Config3, LinkUp },
1058 { WAKE_MAGIC, Config3, MagicPacket },
1059 { WAKE_UCAST, Config5, UWF },
1060 { WAKE_BCAST, Config5, BWF },
1061 { WAKE_MCAST, Config5, MWF },
1062 { WAKE_ANY, Config5, LanWake }
1063 };
1064
61a4dcc2
FR		 1065 RTL_W8(Cfg9346, Cfg9346_Unlock);
1066
1067 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1068 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1069 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1070 options |= cfg[i].mask;
1071 RTL_W8(cfg[i].reg, options);
1072 }
1073
1074 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1075}
1076
1077static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1078{
1079 struct rtl8169_private *tp = netdev_priv(dev);
1080
1081 spin_lock_irq(&tp->lock);
61a4dcc2 1082
f23e7fda
FR		 1083 if (wol->wolopts)
1084 tp->features |= RTL_FEATURE_WOL;
1085 else
1086 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1087 __rtl8169_set_wol(tp, wol->wolopts);
61a4dcc2
FR		 1088 spin_unlock_irq(&tp->lock);
1089
ea80907f 1090 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1091
61a4dcc2
FR		 1092 return 0;
1093}
1094
1da177e4
LT		 1095static void rtl8169_get_drvinfo(struct net_device *dev,
1096 struct ethtool_drvinfo *info)
1097{
1098 struct rtl8169_private *tp = netdev_priv(dev);
1099
1100 strcpy(info->driver, MODULENAME);
1101 strcpy(info->version, RTL8169_VERSION);
1102 strcpy(info->bus_info, pci_name(tp->pci_dev));
1103}
1104
1105static int rtl8169_get_regs_len(struct net_device *dev)
1106{
1107 return R8169_REGS_SIZE;
1108}
1109
1110static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1111 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1112{
1113 struct rtl8169_private *tp = netdev_priv(dev);
1114 void __iomem *ioaddr = tp->mmio_addr;
1115 int ret = 0;
1116 u32 reg;
1117
1118 reg = RTL_R32(TBICSR);
1119 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1120 (duplex == DUPLEX_FULL)) {
1121 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1122 } else if (autoneg == AUTONEG_ENABLE)
1123 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1124 else {
bf82c189
JP		 1125 netif_warn(tp, link, dev,
1126 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1127 ret = -EOPNOTSUPP;
1128 }
1129
1130 return ret;
1131}
1132
1133static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1134 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1135{
1136 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1137 int giga_ctrl, bmcr;
54405cde 1138 int rc = -EINVAL;
1da177e4 1139
716b50a3
HW		 1140 rtl_writephy(tp, 0x1f, 0x0000);
1141
1da177e4 1142 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1143 int auto_nego;
1144
4da19633 1145 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1146 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1147 ADVERTISE_100HALF | ADVERTISE_100FULL);
1148
1149 if (adv & ADVERTISED_10baseT_Half)
1150 auto_nego |= ADVERTISE_10HALF;
1151 if (adv & ADVERTISED_10baseT_Full)
1152 auto_nego |= ADVERTISE_10FULL;
1153 if (adv & ADVERTISED_100baseT_Half)
1154 auto_nego |= ADVERTISE_100HALF;
1155 if (adv & ADVERTISED_100baseT_Full)
1156 auto_nego |= ADVERTISE_100FULL;
1157
3577aa1b 1158 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1159
4da19633 1160 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1161 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1162
3577aa1b 1163 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1164 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
1165 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
1166 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
1167 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
1168 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
1169 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
1170 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
5a5e4443
HW		 1171 (tp->mac_version != RTL_GIGA_MAC_VER_16) &&
1172 (tp->mac_version != RTL_GIGA_MAC_VER_29) &&
1173 (tp->mac_version != RTL_GIGA_MAC_VER_30)) {
54405cde
ON		 1174 if (adv & ADVERTISED_1000baseT_Half)
1175 giga_ctrl |= ADVERTISE_1000HALF;
1176 if (adv & ADVERTISED_1000baseT_Full)
1177 giga_ctrl |= ADVERTISE_1000FULL;
1178 } else if (adv & (ADVERTISED_1000baseT_Half |
1179 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1180 netif_info(tp, link, dev,
1181 "PHY does not support 1000Mbps\n");
54405cde 1182 goto out;
bcf0bf90 1183 }
1da177e4 1184
3577aa1b 1185 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1186
4da19633 1187 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1188 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1189 } else {
1190 giga_ctrl = 0;
1191
1192 if (speed == SPEED_10)
1193 bmcr = 0;
1194 else if (speed == SPEED_100)
1195 bmcr = BMCR_SPEED100;
1196 else
54405cde 1197 goto out;
3577aa1b 1198
1199 if (duplex == DUPLEX_FULL)
1200 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1201 }
1202
1da177e4
LT		 1203 tp->phy_1000_ctrl_reg = giga_ctrl;
1204
4da19633 1205 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1206
1207 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1208 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1209 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1210 rtl_writephy(tp, 0x17, 0x2138);
1211 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1212 } else {
4da19633 1213 rtl_writephy(tp, 0x17, 0x2108);
1214 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1215 }
1216 }
1217
54405cde
ON		 1218 rc = 0;
1219out:
1220 return rc;
1da177e4
LT		 1221}
1222
1223static int rtl8169_set_speed(struct net_device *dev,
54405cde 1224 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1225{
1226 struct rtl8169_private *tp = netdev_priv(dev);
1227 int ret;
1228
54405cde 1229 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1da177e4 1230
64e4bfb4 1231 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1232 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1233
1234 return ret;
1235}
1236
1237static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1238{
1239 struct rtl8169_private *tp = netdev_priv(dev);
1240 unsigned long flags;
1241 int ret;
1242
1243 spin_lock_irqsave(&tp->lock, flags);
54405cde
ON		 1244 ret = rtl8169_set_speed(dev,
1245 cmd->autoneg, cmd->speed, cmd->duplex, cmd->advertising);
1da177e4 1246 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 1247
1da177e4
LT		 1248 return ret;
1249}
1250
1251static u32 rtl8169_get_rx_csum(struct net_device *dev)
1252{
1253 struct rtl8169_private *tp = netdev_priv(dev);
1254
1255 return tp->cp_cmd & RxChkSum;
1256}
1257
1258static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1259{
1260 struct rtl8169_private *tp = netdev_priv(dev);
1261 void __iomem *ioaddr = tp->mmio_addr;
1262 unsigned long flags;
1263
1264 spin_lock_irqsave(&tp->lock, flags);
1265
1266 if (data)
1267 tp->cp_cmd |= RxChkSum;
1268 else
1269 tp->cp_cmd &= ~RxChkSum;
1270
1271 RTL_W16(CPlusCmd, tp->cp_cmd);
1272 RTL_R16(CPlusCmd);
1273
1274 spin_unlock_irqrestore(&tp->lock, flags);
1275
1276 return 0;
1277}
1278
1279#ifdef CONFIG_R8169_VLAN
1280
1281static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1282 struct sk_buff *skb)
1283{
eab6d18d 1284 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1285 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1286}
1287
1288static void rtl8169_vlan_rx_register(struct net_device *dev,
1289 struct vlan_group *grp)
1290{
1291 struct rtl8169_private *tp = netdev_priv(dev);
1292 void __iomem *ioaddr = tp->mmio_addr;
1293 unsigned long flags;
1294
1295 spin_lock_irqsave(&tp->lock, flags);
1296 tp->vlgrp = grp;
05af2142
SW		 1297 /*
1298 * Do not disable RxVlan on 8110SCd.
1299 */
1300 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1da177e4
LT		 1301 tp->cp_cmd |= RxVlan;
1302 else
1303 tp->cp_cmd &= ~RxVlan;
1304 RTL_W16(CPlusCmd, tp->cp_cmd);
1305 RTL_R16(CPlusCmd);
1306 spin_unlock_irqrestore(&tp->lock, flags);
1307}
1308
1da177e4 1309static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
630b943c 1310 struct sk_buff *skb, int polling)
1da177e4
LT		 1311{
1312 u32 opts2 = le32_to_cpu(desc->opts2);
865c652d 1313 struct vlan_group *vlgrp = tp->vlgrp;
1da177e4
LT		 1314 int ret;
1315
865c652d 1316 if (vlgrp && (opts2 & RxVlanTag)) {
2edae08e
ED		 1317 u16 vtag = swab16(opts2 & 0xffff);
1318
1319 if (likely(polling))
1320 vlan_gro_receive(&tp->napi, vlgrp, vtag, skb);
1321 else
1322 __vlan_hwaccel_rx(skb, vlgrp, vtag, polling);
1da177e4
LT		 1323 ret = 0;
1324 } else
1325 ret = -1;
1326 desc->opts2 = 0;
1327 return ret;
1328}
1329
1330#else /* !CONFIG_R8169_VLAN */
1331
1332static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1333 struct sk_buff *skb)
1334{
1335 return 0;
1336}
1337
1338static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
630b943c 1339 struct sk_buff *skb, int polling)
1da177e4
LT		 1340{
1341 return -1;
1342}
1343
1344#endif
1345
ccdffb9a 1346static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1347{
1348 struct rtl8169_private *tp = netdev_priv(dev);
1349 void __iomem *ioaddr = tp->mmio_addr;
1350 u32 status;
1351
1352 cmd->supported =
1353 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1354 cmd->port = PORT_FIBRE;
1355 cmd->transceiver = XCVR_INTERNAL;
1356
1357 status = RTL_R32(TBICSR);
1358 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1359 cmd->autoneg = !!(status & TBINwEnable);
1360
1361 cmd->speed = SPEED_1000;
1362 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1363
1364 return 0;
1da177e4
LT		 1365}
1366
ccdffb9a 1367static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1368{
1369 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1370
1371 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1372}
1373
1374static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1375{
1376 struct rtl8169_private *tp = netdev_priv(dev);
1377 unsigned long flags;
ccdffb9a 1378 int rc;
1da177e4
LT		 1379
1380 spin_lock_irqsave(&tp->lock, flags);
1381
ccdffb9a 1382 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1383
1384 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1385 return rc;
1da177e4
LT		 1386}
1387
1388static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1389 void *p)
1390{
5b0384f4
FR		 1391 struct rtl8169_private *tp = netdev_priv(dev);
1392 unsigned long flags;
1da177e4 1393
5b0384f4
FR		 1394 if (regs->len > R8169_REGS_SIZE)
1395 regs->len = R8169_REGS_SIZE;
1da177e4 1396
5b0384f4
FR		 1397 spin_lock_irqsave(&tp->lock, flags);
1398 memcpy_fromio(p, tp->mmio_addr, regs->len);
1399 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1400}
1401
b57b7e5a
SH		 1402static u32 rtl8169_get_msglevel(struct net_device *dev)
1403{
1404 struct rtl8169_private *tp = netdev_priv(dev);
1405
1406 return tp->msg_enable;
1407}
1408
1409static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1410{
1411 struct rtl8169_private *tp = netdev_priv(dev);
1412
1413 tp->msg_enable = value;
1414}
1415
d4a3a0fc
SH		 1416static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1417 "tx_packets",
1418 "rx_packets",
1419 "tx_errors",
1420 "rx_errors",
1421 "rx_missed",
1422 "align_errors",
1423 "tx_single_collisions",
1424 "tx_multi_collisions",
1425 "unicast",
1426 "broadcast",
1427 "multicast",
1428 "tx_aborted",
1429 "tx_underrun",
1430};
1431
b9f2c044 1432static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1433{
b9f2c044
JG		 1434 switch (sset) {
1435 case ETH_SS_STATS:
1436 return ARRAY_SIZE(rtl8169_gstrings);
1437 default:
1438 return -EOPNOTSUPP;
1439 }
d4a3a0fc
SH		 1440}
1441
355423d0 1442static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1443{
1444 struct rtl8169_private *tp = netdev_priv(dev);
1445 void __iomem *ioaddr = tp->mmio_addr;
1446 struct rtl8169_counters *counters;
1447 dma_addr_t paddr;
1448 u32 cmd;
355423d0 1449 int wait = 1000;
48addcc9 1450 struct device *d = &tp->pci_dev->dev;
d4a3a0fc 1451
355423d0
IV		 1452 /*
1453 * Some chips are unable to dump tally counters when the receiver
1454 * is disabled.
1455 */
1456 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1457 return;
d4a3a0fc 1458
48addcc9 1459 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1460 if (!counters)
1461 return;
1462
1463 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1464 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1465 RTL_W32(CounterAddrLow, cmd);
1466 RTL_W32(CounterAddrLow, cmd | CounterDump);
1467
355423d0
IV		 1468 while (wait--) {
1469 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1470 /* copy updated counters */
1471 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1472 break;
355423d0
IV		 1473 }
1474 udelay(10);
d4a3a0fc
SH		 1475 }
1476
1477 RTL_W32(CounterAddrLow, 0);
1478 RTL_W32(CounterAddrHigh, 0);
1479
48addcc9 1480 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1481}
1482
355423d0
IV		 1483static void rtl8169_get_ethtool_stats(struct net_device *dev,
1484 struct ethtool_stats *stats, u64 *data)
1485{
1486 struct rtl8169_private *tp = netdev_priv(dev);
1487
1488 ASSERT_RTNL();
1489
1490 rtl8169_update_counters(dev);
1491
1492 data[0] = le64_to_cpu(tp->counters.tx_packets);
1493 data[1] = le64_to_cpu(tp->counters.rx_packets);
1494 data[2] = le64_to_cpu(tp->counters.tx_errors);
1495 data[3] = le32_to_cpu(tp->counters.rx_errors);
1496 data[4] = le16_to_cpu(tp->counters.rx_missed);
1497 data[5] = le16_to_cpu(tp->counters.align_errors);
1498 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1499 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1500 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1501 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1502 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1503 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1504 data[12] = le16_to_cpu(tp->counters.tx_underun);
1505}
1506
d4a3a0fc
SH		 1507static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1508{
1509 switch(stringset) {
1510 case ETH_SS_STATS:
1511 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1512 break;
1513 }
1514}
1515
7282d491 1516static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1517 .get_drvinfo = rtl8169_get_drvinfo,
1518 .get_regs_len = rtl8169_get_regs_len,
1519 .get_link = ethtool_op_get_link,
1520 .get_settings = rtl8169_get_settings,
1521 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1522 .get_msglevel = rtl8169_get_msglevel,
1523 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1524 .get_rx_csum = rtl8169_get_rx_csum,
1525 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1526 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1527 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1528 .set_tso = ethtool_op_set_tso,
1529 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1530 .get_wol = rtl8169_get_wol,
1531 .set_wol = rtl8169_set_wol,
d4a3a0fc 1532 .get_strings = rtl8169_get_strings,
b9f2c044 1533 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1534 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1535};
1536
07d3f51f
FR		 1537static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1538 void __iomem *ioaddr)
1da177e4 1539{
0e485150
FR		 1540 /*
1541 * The driver currently handles the 8168Bf and the 8168Be identically
1542 * but they can be identified more specifically through the test below
1543 * if needed:
1544 *
1545 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1546 *
1547 * Same thing for the 8101Eb and the 8101Ec:
1548 *
1549 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1550 */
350f7596 1551 static const struct {
1da177e4 1552 u32 mask;
e3cf0cc0 1553 u32 val;
1da177e4
LT		 1554 int mac_version;
1555 } mac_info[] = {
5b538df9 1556 /* 8168D family. */
daf9df6d 1557 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1558 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 1559 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1560
e6de30d6 1561 /* 8168DP family. */
1562 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1563 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
1564
ef808d50 1565 /* 8168C family. */
17c99297 1566 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1567 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1568 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1569 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1570 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1571 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1572 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1573 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1574 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1575
1576 /* 8168B family. */
1577 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1578 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1579 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1580 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1581
1582 /* 8101 family. */
5a5e4443
HW		 1583 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1584 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1585 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 1586 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1587 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1588 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1589 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1590 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1591 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1592 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1593 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1594 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1595 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1596 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1597 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1598 /* FIXME: where did these entries come from ? -- FR */
1599 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1600 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1601
1602 /* 8110 family. */
1603 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1604 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1605 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1606 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1607 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1608 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1609
f21b75e9
JD		 1610 /* Catch-all */
1611 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1da177e4
LT		 1612 }, *p = mac_info;
1613 u32 reg;
1614
e3cf0cc0
FR		 1615 reg = RTL_R32(TxConfig);
1616 while ((reg & p->mask) != p->val)
1da177e4
LT		 1617 p++;
1618 tp->mac_version = p->mac_version;
1619}
1620
1621static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1622{
bcf0bf90 1623 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1624}
1625
867763c1
FR		 1626struct phy_reg {
1627 u16 reg;
1628 u16 val;
1629};
1630
4da19633 1631static void rtl_writephy_batch(struct rtl8169_private *tp,
1632 const struct phy_reg *regs, int len)
867763c1
FR		 1633{
1634 while (len-- > 0) {
4da19633 1635 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 1636 regs++;
1637 }
1638}
1639
bca03d5f 1640#define PHY_READ 0x00000000
1641#define PHY_DATA_OR 0x10000000
1642#define PHY_DATA_AND 0x20000000
1643#define PHY_BJMPN 0x30000000
1644#define PHY_READ_EFUSE 0x40000000
1645#define PHY_READ_MAC_BYTE 0x50000000
1646#define PHY_WRITE_MAC_BYTE 0x60000000
1647#define PHY_CLEAR_READCOUNT 0x70000000
1648#define PHY_WRITE 0x80000000
1649#define PHY_READCOUNT_EQ_SKIP 0x90000000
1650#define PHY_COMP_EQ_SKIPN 0xa0000000
1651#define PHY_COMP_NEQ_SKIPN 0xb0000000
1652#define PHY_WRITE_PREVIOUS 0xc0000000
1653#define PHY_SKIPN 0xd0000000
1654#define PHY_DELAY_MS 0xe0000000
1655#define PHY_WRITE_ERI_WORD 0xf0000000
1656
1657static void
1658rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1659{
bca03d5f 1660 __le32 *phytable = (__le32 *)fw->data;
1661 struct net_device *dev = tp->dev;
42b82dc1 1662 size_t index, fw_size = fw->size / sizeof(*phytable);
1663 u32 predata, count;
bca03d5f 1664
1665 if (fw->size % sizeof(*phytable)) {
1666 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1667 return;
1668 }
1669
42b82dc1 1670 for (index = 0; index < fw_size; index++) {
1671 u32 action = le32_to_cpu(phytable[index]);
1672 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 1673
42b82dc1 1674 switch(action & 0xf0000000) {
1675 case PHY_READ:
1676 case PHY_DATA_OR:
1677 case PHY_DATA_AND:
1678 case PHY_READ_EFUSE:
1679 case PHY_CLEAR_READCOUNT:
1680 case PHY_WRITE:
1681 case PHY_WRITE_PREVIOUS:
1682 case PHY_DELAY_MS:
1683 break;
1684
1685 case PHY_BJMPN:
1686 if (regno > index) {
1687 netif_err(tp, probe, tp->dev,
1688 "Out of range of firmware\n");
1689 return;
1690 }
1691 break;
1692 case PHY_READCOUNT_EQ_SKIP:
1693 if (index + 2 >= fw_size) {
1694 netif_err(tp, probe, tp->dev,
1695 "Out of range of firmware\n");
1696 return;
1697 }
1698 break;
1699 case PHY_COMP_EQ_SKIPN:
1700 case PHY_COMP_NEQ_SKIPN:
1701 case PHY_SKIPN:
1702 if (index + 1 + regno >= fw_size) {
1703 netif_err(tp, probe, tp->dev,
1704 "Out of range of firmware\n");
1705 return;
1706 }
bca03d5f 1707 break;
1708
42b82dc1 1709 case PHY_READ_MAC_BYTE:
1710 case PHY_WRITE_MAC_BYTE:
1711 case PHY_WRITE_ERI_WORD:
1712 default:
1713 netif_err(tp, probe, tp->dev,
1714 "Invalid action 0x%08x\n", action);
bca03d5f 1715 return;
1716 }
1717 }
1718
42b82dc1 1719 predata = 0;
1720 count = 0;
1721
1722 for (index = 0; index < fw_size; ) {
1723 u32 action = le32_to_cpu(phytable[index]);
bca03d5f 1724 u32 data = action & 0x0000ffff;
42b82dc1 1725 u32 regno = (action & 0x0fff0000) >> 16;
1726
1727 if (!action)
1728 break;
bca03d5f 1729
1730 switch(action & 0xf0000000) {
42b82dc1 1731 case PHY_READ:
1732 predata = rtl_readphy(tp, regno);
1733 count++;
1734 index++;
1735 break;
1736 case PHY_DATA_OR:
1737 predata |= data;
1738 index++;
1739 break;
1740 case PHY_DATA_AND:
1741 predata &= data;
1742 index++;
1743 break;
1744 case PHY_BJMPN:
1745 index -= regno;
1746 break;
1747 case PHY_READ_EFUSE:
1748 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1749 index++;
1750 break;
1751 case PHY_CLEAR_READCOUNT:
1752 count = 0;
1753 index++;
1754 break;
bca03d5f 1755 case PHY_WRITE:
42b82dc1 1756 rtl_writephy(tp, regno, data);
1757 index++;
1758 break;
1759 case PHY_READCOUNT_EQ_SKIP:
1760 if (count == data)
1761 index += 2;
1762 else
1763 index += 1;
bca03d5f 1764 break;
42b82dc1 1765 case PHY_COMP_EQ_SKIPN:
1766 if (predata == data)
1767 index += regno;
1768 index++;
1769 break;
1770 case PHY_COMP_NEQ_SKIPN:
1771 if (predata != data)
1772 index += regno;
1773 index++;
1774 break;
1775 case PHY_WRITE_PREVIOUS:
1776 rtl_writephy(tp, regno, predata);
1777 index++;
1778 break;
1779 case PHY_SKIPN:
1780 index += regno + 1;
1781 break;
1782 case PHY_DELAY_MS:
1783 mdelay(data);
1784 index++;
1785 break;
1786
1787 case PHY_READ_MAC_BYTE:
1788 case PHY_WRITE_MAC_BYTE:
1789 case PHY_WRITE_ERI_WORD:
bca03d5f 1790 default:
1791 BUG();
1792 }
1793 }
1794}
1795
f1e02ed1 1796static void rtl_release_firmware(struct rtl8169_private *tp)
1797{
1798 release_firmware(tp->fw);
1799 tp->fw = NULL;
1800}
1801
1802static int rtl_apply_firmware(struct rtl8169_private *tp, const char *fw_name)
1803{
1804 const struct firmware **fw = &tp->fw;
1805 int rc = !*fw;
1806
1807 if (rc) {
1808 rc = request_firmware(fw, fw_name, &tp->pci_dev->dev);
1809 if (rc < 0)
1810 goto out;
1811 }
1812
1813 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1814 rtl_phy_write_fw(tp, *fw);
1815out:
1816 return rc;
1817}
1818
4da19633 1819static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 1820{
350f7596 1821 static const struct phy_reg phy_reg_init[] = {
0b9b571d 1822 { 0x1f, 0x0001 },
1823 { 0x06, 0x006e },
1824 { 0x08, 0x0708 },
1825 { 0x15, 0x4000 },
1826 { 0x18, 0x65c7 },
1da177e4 1827
0b9b571d 1828 { 0x1f, 0x0001 },
1829 { 0x03, 0x00a1 },
1830 { 0x02, 0x0008 },
1831 { 0x01, 0x0120 },
1832 { 0x00, 0x1000 },
1833 { 0x04, 0x0800 },
1834 { 0x04, 0x0000 },
1da177e4 1835
0b9b571d 1836 { 0x03, 0xff41 },
1837 { 0x02, 0xdf60 },
1838 { 0x01, 0x0140 },
1839 { 0x00, 0x0077 },
1840 { 0x04, 0x7800 },
1841 { 0x04, 0x7000 },
1842
1843 { 0x03, 0x802f },
1844 { 0x02, 0x4f02 },
1845 { 0x01, 0x0409 },
1846 { 0x00, 0xf0f9 },
1847 { 0x04, 0x9800 },
1848 { 0x04, 0x9000 },
1849
1850 { 0x03, 0xdf01 },
1851 { 0x02, 0xdf20 },
1852 { 0x01, 0xff95 },
1853 { 0x00, 0xba00 },
1854 { 0x04, 0xa800 },
1855 { 0x04, 0xa000 },
1856
1857 { 0x03, 0xff41 },
1858 { 0x02, 0xdf20 },
1859 { 0x01, 0x0140 },
1860 { 0x00, 0x00bb },
1861 { 0x04, 0xb800 },
1862 { 0x04, 0xb000 },
1863
1864 { 0x03, 0xdf41 },
1865 { 0x02, 0xdc60 },
1866 { 0x01, 0x6340 },
1867 { 0x00, 0x007d },
1868 { 0x04, 0xd800 },
1869 { 0x04, 0xd000 },
1870
1871 { 0x03, 0xdf01 },
1872 { 0x02, 0xdf20 },
1873 { 0x01, 0x100a },
1874 { 0x00, 0xa0ff },
1875 { 0x04, 0xf800 },
1876 { 0x04, 0xf000 },
1877
1878 { 0x1f, 0x0000 },
1879 { 0x0b, 0x0000 },
1880 { 0x00, 0x9200 }
1881 };
1da177e4 1882
4da19633 1883 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 1884}
1885
4da19633 1886static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 1887{
350f7596 1888 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 1889 { 0x1f, 0x0002 },
1890 { 0x01, 0x90d0 },
1891 { 0x1f, 0x0000 }
1892 };
1893
4da19633 1894 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1895}
1896
4da19633 1897static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 1898{
1899 struct pci_dev *pdev = tp->pci_dev;
1900 u16 vendor_id, device_id;
1901
1902 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1903 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1904
1905 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1906 return;
1907
4da19633 1908 rtl_writephy(tp, 0x1f, 0x0001);
1909 rtl_writephy(tp, 0x10, 0xf01b);
1910 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 1911}
1912
4da19633 1913static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 1914{
350f7596 1915 static const struct phy_reg phy_reg_init[] = {
2e955856 1916 { 0x1f, 0x0001 },
1917 { 0x04, 0x0000 },
1918 { 0x03, 0x00a1 },
1919 { 0x02, 0x0008 },
1920 { 0x01, 0x0120 },
1921 { 0x00, 0x1000 },
1922 { 0x04, 0x0800 },
1923 { 0x04, 0x9000 },
1924 { 0x03, 0x802f },
1925 { 0x02, 0x4f02 },
1926 { 0x01, 0x0409 },
1927 { 0x00, 0xf099 },
1928 { 0x04, 0x9800 },
1929 { 0x04, 0xa000 },
1930 { 0x03, 0xdf01 },
1931 { 0x02, 0xdf20 },
1932 { 0x01, 0xff95 },
1933 { 0x00, 0xba00 },
1934 { 0x04, 0xa800 },
1935 { 0x04, 0xf000 },
1936 { 0x03, 0xdf01 },
1937 { 0x02, 0xdf20 },
1938 { 0x01, 0x101a },
1939 { 0x00, 0xa0ff },
1940 { 0x04, 0xf800 },
1941 { 0x04, 0x0000 },
1942 { 0x1f, 0x0000 },
1943
1944 { 0x1f, 0x0001 },
1945 { 0x10, 0xf41b },
1946 { 0x14, 0xfb54 },
1947 { 0x18, 0xf5c7 },
1948 { 0x1f, 0x0000 },
1949
1950 { 0x1f, 0x0001 },
1951 { 0x17, 0x0cc0 },
1952 { 0x1f, 0x0000 }
1953 };
1954
4da19633 1955 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 1956
4da19633 1957 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 1958}
1959
4da19633 1960static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 1961{
350f7596 1962 static const struct phy_reg phy_reg_init[] = {
8c7006aa 1963 { 0x1f, 0x0001 },
1964 { 0x04, 0x0000 },
1965 { 0x03, 0x00a1 },
1966 { 0x02, 0x0008 },
1967 { 0x01, 0x0120 },
1968 { 0x00, 0x1000 },
1969 { 0x04, 0x0800 },
1970 { 0x04, 0x9000 },
1971 { 0x03, 0x802f },
1972 { 0x02, 0x4f02 },
1973 { 0x01, 0x0409 },
1974 { 0x00, 0xf099 },
1975 { 0x04, 0x9800 },
1976 { 0x04, 0xa000 },
1977 { 0x03, 0xdf01 },
1978 { 0x02, 0xdf20 },
1979 { 0x01, 0xff95 },
1980 { 0x00, 0xba00 },
1981 { 0x04, 0xa800 },
1982 { 0x04, 0xf000 },
1983 { 0x03, 0xdf01 },
1984 { 0x02, 0xdf20 },
1985 { 0x01, 0x101a },
1986 { 0x00, 0xa0ff },
1987 { 0x04, 0xf800 },
1988 { 0x04, 0x0000 },
1989 { 0x1f, 0x0000 },
1990
1991 { 0x1f, 0x0001 },
1992 { 0x0b, 0x8480 },
1993 { 0x1f, 0x0000 },
1994
1995 { 0x1f, 0x0001 },
1996 { 0x18, 0x67c7 },
1997 { 0x04, 0x2000 },
1998 { 0x03, 0x002f },
1999 { 0x02, 0x4360 },
2000 { 0x01, 0x0109 },
2001 { 0x00, 0x3022 },
2002 { 0x04, 0x2800 },
2003 { 0x1f, 0x0000 },
2004
2005 { 0x1f, 0x0001 },
2006 { 0x17, 0x0cc0 },
2007 { 0x1f, 0x0000 }
2008 };
2009
4da19633 2010 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2011}
2012
4da19633 2013static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2014{
350f7596 2015 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2016 { 0x10, 0xf41b },
2017 { 0x1f, 0x0000 }
2018 };
2019
4da19633 2020 rtl_writephy(tp, 0x1f, 0x0001);
2021 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2022
4da19633 2023 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2024}
2025
4da19633 2026static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2027{
350f7596 2028 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2029 { 0x1f, 0x0001 },
2030 { 0x10, 0xf41b },
2031 { 0x1f, 0x0000 }
2032 };
2033
4da19633 2034 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2035}
2036
4da19633 2037static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2038{
350f7596 2039 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2040 { 0x1f, 0x0000 },
2041 { 0x1d, 0x0f00 },
2042 { 0x1f, 0x0002 },
2043 { 0x0c, 0x1ec8 },
2044 { 0x1f, 0x0000 }
2045 };
2046
4da19633 2047 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2048}
2049
4da19633 2050static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2051{
350f7596 2052 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2053 { 0x1f, 0x0001 },
2054 { 0x1d, 0x3d98 },
2055 { 0x1f, 0x0000 }
2056 };
2057
4da19633 2058 rtl_writephy(tp, 0x1f, 0x0000);
2059 rtl_patchphy(tp, 0x14, 1 << 5);
2060 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2061
4da19633 2062 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2063}
2064
4da19633 2065static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2066{
350f7596 2067 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2068 { 0x1f, 0x0001 },
2069 { 0x12, 0x2300 },
867763c1
FR		 2070 { 0x1f, 0x0002 },
2071 { 0x00, 0x88d4 },
2072 { 0x01, 0x82b1 },
2073 { 0x03, 0x7002 },
2074 { 0x08, 0x9e30 },
2075 { 0x09, 0x01f0 },
2076 { 0x0a, 0x5500 },
2077 { 0x0c, 0x00c8 },
2078 { 0x1f, 0x0003 },
2079 { 0x12, 0xc096 },
2080 { 0x16, 0x000a },
f50d4275
FR		 2081 { 0x1f, 0x0000 },
2082 { 0x1f, 0x0000 },
2083 { 0x09, 0x2000 },
2084 { 0x09, 0x0000 }
867763c1
FR		 2085 };
2086
4da19633 2087 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2088
4da19633 2089 rtl_patchphy(tp, 0x14, 1 << 5);
2090 rtl_patchphy(tp, 0x0d, 1 << 5);
2091 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2092}
2093
4da19633 2094static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2095{
350f7596 2096 static const struct phy_reg phy_reg_init[] = {
f50d4275 2097 { 0x1f, 0x0001 },
7da97ec9 2098 { 0x12, 0x2300 },
f50d4275
FR		 2099 { 0x03, 0x802f },
2100 { 0x02, 0x4f02 },
2101 { 0x01, 0x0409 },
2102 { 0x00, 0xf099 },
2103 { 0x04, 0x9800 },
2104 { 0x04, 0x9000 },
2105 { 0x1d, 0x3d98 },
7da97ec9
FR		 2106 { 0x1f, 0x0002 },
2107 { 0x0c, 0x7eb8 },
f50d4275
FR		 2108 { 0x06, 0x0761 },
2109 { 0x1f, 0x0003 },
2110 { 0x16, 0x0f0a },
7da97ec9
FR		 2111 { 0x1f, 0x0000 }
2112 };
2113
4da19633 2114 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2115
4da19633 2116 rtl_patchphy(tp, 0x16, 1 << 0);
2117 rtl_patchphy(tp, 0x14, 1 << 5);
2118 rtl_patchphy(tp, 0x0d, 1 << 5);
2119 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2120}
2121
4da19633 2122static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2123{
350f7596 2124 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2125 { 0x1f, 0x0001 },
2126 { 0x12, 0x2300 },
2127 { 0x1d, 0x3d98 },
2128 { 0x1f, 0x0002 },
2129 { 0x0c, 0x7eb8 },
2130 { 0x06, 0x5461 },
2131 { 0x1f, 0x0003 },
2132 { 0x16, 0x0f0a },
2133 { 0x1f, 0x0000 }
2134 };
2135
4da19633 2136 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2137
4da19633 2138 rtl_patchphy(tp, 0x16, 1 << 0);
2139 rtl_patchphy(tp, 0x14, 1 << 5);
2140 rtl_patchphy(tp, 0x0d, 1 << 5);
2141 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2142}
2143
4da19633 2144static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2145{
4da19633 2146 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2147}
2148
bca03d5f 2149static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2150{
350f7596 2151 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2152 /* Channel Estimation */
5b538df9 2153 { 0x1f, 0x0001 },
daf9df6d 2154 { 0x06, 0x4064 },
2155 { 0x07, 0x2863 },
2156 { 0x08, 0x059c },
2157 { 0x09, 0x26b4 },
2158 { 0x0a, 0x6a19 },
2159 { 0x0b, 0xdcc8 },
2160 { 0x10, 0xf06d },
2161 { 0x14, 0x7f68 },
2162 { 0x18, 0x7fd9 },
2163 { 0x1c, 0xf0ff },
2164 { 0x1d, 0x3d9c },
5b538df9 2165 { 0x1f, 0x0003 },
daf9df6d 2166 { 0x12, 0xf49f },
2167 { 0x13, 0x070b },
2168 { 0x1a, 0x05ad },
bca03d5f 2169 { 0x14, 0x94c0 },
2170
2171 /*
2172 * Tx Error Issue
2173 * enhance line driver power
2174 */
5b538df9 2175 { 0x1f, 0x0002 },
daf9df6d 2176 { 0x06, 0x5561 },
2177 { 0x1f, 0x0005 },
2178 { 0x05, 0x8332 },
bca03d5f 2179 { 0x06, 0x5561 },
2180
2181 /*
2182 * Can not link to 1Gbps with bad cable
2183 * Decrease SNR threshold form 21.07dB to 19.04dB
2184 */
2185 { 0x1f, 0x0001 },
2186 { 0x17, 0x0cc0 },
daf9df6d 2187
5b538df9 2188 { 0x1f, 0x0000 },
bca03d5f 2189 { 0x0d, 0xf880 }
daf9df6d 2190 };
bca03d5f 2191 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 2192
4da19633 2193 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2194
bca03d5f 2195 /*
2196 * Rx Error Issue
2197 * Fine Tune Switching regulator parameter
2198 */
4da19633 2199 rtl_writephy(tp, 0x1f, 0x0002);
2200 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2201 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2202
daf9df6d 2203 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2204 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2205 { 0x1f, 0x0002 },
2206 { 0x05, 0x669a },
2207 { 0x1f, 0x0005 },
2208 { 0x05, 0x8330 },
2209 { 0x06, 0x669a },
2210 { 0x1f, 0x0002 }
2211 };
2212 int val;
2213
4da19633 2214 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2215
4da19633 2216 val = rtl_readphy(tp, 0x0d);
daf9df6d 2217
2218 if ((val & 0x00ff) != 0x006c) {
350f7596 2219 static const u32 set[] = {
daf9df6d 2220 0x0065, 0x0066, 0x0067, 0x0068,
2221 0x0069, 0x006a, 0x006b, 0x006c
2222 };
2223 int i;
2224
4da19633 2225 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2226
2227 val &= 0xff00;
2228 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2229 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2230 }
2231 } else {
350f7596 2232 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2233 { 0x1f, 0x0002 },
2234 { 0x05, 0x6662 },
2235 { 0x1f, 0x0005 },
2236 { 0x05, 0x8330 },
2237 { 0x06, 0x6662 }
2238 };
2239
4da19633 2240 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2241 }
2242
bca03d5f 2243 /* RSET couple improve */
4da19633 2244 rtl_writephy(tp, 0x1f, 0x0002);
2245 rtl_patchphy(tp, 0x0d, 0x0300);
2246 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2247
bca03d5f 2248 /* Fine tune PLL performance */
4da19633 2249 rtl_writephy(tp, 0x1f, 0x0002);
2250 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2251 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2252
4da19633 2253 rtl_writephy(tp, 0x1f, 0x0005);
2254 rtl_writephy(tp, 0x05, 0x001b);
f1e02ed1 2255 if ((rtl_readphy(tp, 0x06) != 0xbf00) ||
2256 (rtl_apply_firmware(tp, FIRMWARE_8168D_1) < 0)) {
bca03d5f 2257 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2258 }
2259
4da19633 2260 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2261}
2262
bca03d5f 2263static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2264{
350f7596 2265 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2266 /* Channel Estimation */
daf9df6d 2267 { 0x1f, 0x0001 },
2268 { 0x06, 0x4064 },
2269 { 0x07, 0x2863 },
2270 { 0x08, 0x059c },
2271 { 0x09, 0x26b4 },
2272 { 0x0a, 0x6a19 },
2273 { 0x0b, 0xdcc8 },
2274 { 0x10, 0xf06d },
2275 { 0x14, 0x7f68 },
2276 { 0x18, 0x7fd9 },
2277 { 0x1c, 0xf0ff },
2278 { 0x1d, 0x3d9c },
2279 { 0x1f, 0x0003 },
2280 { 0x12, 0xf49f },
2281 { 0x13, 0x070b },
2282 { 0x1a, 0x05ad },
2283 { 0x14, 0x94c0 },
2284
bca03d5f 2285 /*
2286 * Tx Error Issue
2287 * enhance line driver power
2288 */
daf9df6d 2289 { 0x1f, 0x0002 },
2290 { 0x06, 0x5561 },
2291 { 0x1f, 0x0005 },
2292 { 0x05, 0x8332 },
bca03d5f 2293 { 0x06, 0x5561 },
2294
2295 /*
2296 * Can not link to 1Gbps with bad cable
2297 * Decrease SNR threshold form 21.07dB to 19.04dB
2298 */
2299 { 0x1f, 0x0001 },
2300 { 0x17, 0x0cc0 },
daf9df6d 2301
2302 { 0x1f, 0x0000 },
bca03d5f 2303 { 0x0d, 0xf880 }
5b538df9 2304 };
bca03d5f 2305 void __iomem *ioaddr = tp->mmio_addr;
5b538df9 2306
4da19633 2307 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2308
daf9df6d 2309 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2310 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2311 { 0x1f, 0x0002 },
2312 { 0x05, 0x669a },
5b538df9 2313 { 0x1f, 0x0005 },
daf9df6d 2314 { 0x05, 0x8330 },
2315 { 0x06, 0x669a },
2316
2317 { 0x1f, 0x0002 }
2318 };
2319 int val;
2320
4da19633 2321 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2322
4da19633 2323 val = rtl_readphy(tp, 0x0d);
daf9df6d 2324 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2325 static const u32 set[] = {
daf9df6d 2326 0x0065, 0x0066, 0x0067, 0x0068,
2327 0x0069, 0x006a, 0x006b, 0x006c
2328 };
2329 int i;
2330
4da19633 2331 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2332
2333 val &= 0xff00;
2334 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2335 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2336 }
2337 } else {
350f7596 2338 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2339 { 0x1f, 0x0002 },
2340 { 0x05, 0x2642 },
5b538df9 2341 { 0x1f, 0x0005 },
daf9df6d 2342 { 0x05, 0x8330 },
2343 { 0x06, 0x2642 }
5b538df9
FR		 2344 };
2345
4da19633 2346 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2347 }
2348
bca03d5f 2349 /* Fine tune PLL performance */
4da19633 2350 rtl_writephy(tp, 0x1f, 0x0002);
2351 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2352 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2353
bca03d5f 2354 /* Switching regulator Slew rate */
4da19633 2355 rtl_writephy(tp, 0x1f, 0x0002);
2356 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2357
4da19633 2358 rtl_writephy(tp, 0x1f, 0x0005);
2359 rtl_writephy(tp, 0x05, 0x001b);
f1e02ed1 2360 if ((rtl_readphy(tp, 0x06) != 0xb300) ||
2361 (rtl_apply_firmware(tp, FIRMWARE_8168D_2) < 0)) {
bca03d5f 2362 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2363 }
2364
4da19633 2365 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2366}
2367
4da19633 2368static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2369{
350f7596 2370 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2371 { 0x1f, 0x0002 },
2372 { 0x10, 0x0008 },
2373 { 0x0d, 0x006c },
2374
2375 { 0x1f, 0x0000 },
2376 { 0x0d, 0xf880 },
2377
2378 { 0x1f, 0x0001 },
2379 { 0x17, 0x0cc0 },
2380
2381 { 0x1f, 0x0001 },
2382 { 0x0b, 0xa4d8 },
2383 { 0x09, 0x281c },
2384 { 0x07, 0x2883 },
2385 { 0x0a, 0x6b35 },
2386 { 0x1d, 0x3da4 },
2387 { 0x1c, 0xeffd },
2388 { 0x14, 0x7f52 },
2389 { 0x18, 0x7fc6 },
2390 { 0x08, 0x0601 },
2391 { 0x06, 0x4063 },
2392 { 0x10, 0xf074 },
2393 { 0x1f, 0x0003 },
2394 { 0x13, 0x0789 },
2395 { 0x12, 0xf4bd },
2396 { 0x1a, 0x04fd },
2397 { 0x14, 0x84b0 },
2398 { 0x1f, 0x0000 },
2399 { 0x00, 0x9200 },
2400
2401 { 0x1f, 0x0005 },
2402 { 0x01, 0x0340 },
2403 { 0x1f, 0x0001 },
2404 { 0x04, 0x4000 },
2405 { 0x03, 0x1d21 },
2406 { 0x02, 0x0c32 },
2407 { 0x01, 0x0200 },
2408 { 0x00, 0x5554 },
2409 { 0x04, 0x4800 },
2410 { 0x04, 0x4000 },
2411 { 0x04, 0xf000 },
2412 { 0x03, 0xdf01 },
2413 { 0x02, 0xdf20 },
2414 { 0x01, 0x101a },
2415 { 0x00, 0xa0ff },
2416 { 0x04, 0xf800 },
2417 { 0x04, 0xf000 },
2418 { 0x1f, 0x0000 },
2419
2420 { 0x1f, 0x0007 },
2421 { 0x1e, 0x0023 },
2422 { 0x16, 0x0000 },
2423 { 0x1f, 0x0000 }
2424 };
2425
4da19633 2426 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2427}
2428
e6de30d6 2429static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2430{
2431 static const struct phy_reg phy_reg_init[] = {
2432 { 0x1f, 0x0001 },
2433 { 0x17, 0x0cc0 },
2434
2435 { 0x1f, 0x0007 },
2436 { 0x1e, 0x002d },
2437 { 0x18, 0x0040 },
2438 { 0x1f, 0x0000 }
2439 };
2440
2441 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2442 rtl_patchphy(tp, 0x0d, 1 << 5);
2443}
2444
4da19633 2445static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 2446{
350f7596 2447 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 2448 { 0x1f, 0x0003 },
2449 { 0x08, 0x441d },
2450 { 0x01, 0x9100 },
2451 { 0x1f, 0x0000 }
2452 };
2453
4da19633 2454 rtl_writephy(tp, 0x1f, 0x0000);
2455 rtl_patchphy(tp, 0x11, 1 << 12);
2456 rtl_patchphy(tp, 0x19, 1 << 13);
2457 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 2458
4da19633 2459 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 2460}
2461
5a5e4443
HW		 2462static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2463{
2464 static const struct phy_reg phy_reg_init[] = {
2465 { 0x1f, 0x0005 },
2466 { 0x1a, 0x0000 },
2467 { 0x1f, 0x0000 },
2468
2469 { 0x1f, 0x0004 },
2470 { 0x1c, 0x0000 },
2471 { 0x1f, 0x0000 },
2472
2473 { 0x1f, 0x0001 },
2474 { 0x15, 0x7701 },
2475 { 0x1f, 0x0000 }
2476 };
2477
2478 /* Disable ALDPS before ram code */
2479 rtl_writephy(tp, 0x1f, 0x0000);
2480 rtl_writephy(tp, 0x18, 0x0310);
2481 msleep(100);
2482
2483 if (rtl_apply_firmware(tp, FIRMWARE_8105E_1) < 0)
2484 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2485
2486 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2487}
2488
5615d9f1
FR		 2489static void rtl_hw_phy_config(struct net_device *dev)
2490{
2491 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 2492
2493 rtl8169_print_mac_version(tp);
2494
2495 switch (tp->mac_version) {
2496 case RTL_GIGA_MAC_VER_01:
2497 break;
2498 case RTL_GIGA_MAC_VER_02:
2499 case RTL_GIGA_MAC_VER_03:
4da19633 2500 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 2501 break;
2502 case RTL_GIGA_MAC_VER_04:
4da19633 2503 rtl8169sb_hw_phy_config(tp);
5615d9f1 2504 break;
2e955856 2505 case RTL_GIGA_MAC_VER_05:
4da19633 2506 rtl8169scd_hw_phy_config(tp);
2e955856 2507 break;
8c7006aa 2508 case RTL_GIGA_MAC_VER_06:
4da19633 2509 rtl8169sce_hw_phy_config(tp);
8c7006aa 2510 break;
2857ffb7
FR		 2511 case RTL_GIGA_MAC_VER_07:
2512 case RTL_GIGA_MAC_VER_08:
2513 case RTL_GIGA_MAC_VER_09:
4da19633 2514 rtl8102e_hw_phy_config(tp);
2857ffb7 2515 break;
236b8082 2516 case RTL_GIGA_MAC_VER_11:
4da19633 2517 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 2518 break;
2519 case RTL_GIGA_MAC_VER_12:
4da19633 2520 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 2521 break;
2522 case RTL_GIGA_MAC_VER_17:
4da19633 2523 rtl8168bef_hw_phy_config(tp);
236b8082 2524 break;
867763c1 2525 case RTL_GIGA_MAC_VER_18:
4da19633 2526 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 2527 break;
2528 case RTL_GIGA_MAC_VER_19:
4da19633 2529 rtl8168c_1_hw_phy_config(tp);
867763c1 2530 break;
7da97ec9 2531 case RTL_GIGA_MAC_VER_20:
4da19633 2532 rtl8168c_2_hw_phy_config(tp);
7da97ec9 2533 break;
197ff761 2534 case RTL_GIGA_MAC_VER_21:
4da19633 2535 rtl8168c_3_hw_phy_config(tp);
197ff761 2536 break;
6fb07058 2537 case RTL_GIGA_MAC_VER_22:
4da19633 2538 rtl8168c_4_hw_phy_config(tp);
6fb07058 2539 break;
ef3386f0 2540 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 2541 case RTL_GIGA_MAC_VER_24:
4da19633 2542 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 2543 break;
5b538df9 2544 case RTL_GIGA_MAC_VER_25:
bca03d5f 2545 rtl8168d_1_hw_phy_config(tp);
daf9df6d 2546 break;
2547 case RTL_GIGA_MAC_VER_26:
bca03d5f 2548 rtl8168d_2_hw_phy_config(tp);
daf9df6d 2549 break;
2550 case RTL_GIGA_MAC_VER_27:
4da19633 2551 rtl8168d_3_hw_phy_config(tp);
5b538df9 2552 break;
e6de30d6 2553 case RTL_GIGA_MAC_VER_28:
2554 rtl8168d_4_hw_phy_config(tp);
2555 break;
5a5e4443
HW		 2556 case RTL_GIGA_MAC_VER_29:
2557 case RTL_GIGA_MAC_VER_30:
2558 rtl8105e_hw_phy_config(tp);
2559 break;
ef3386f0 2560
5615d9f1
FR		 2561 default:
2562 break;
2563 }
2564}
2565
1da177e4
LT		 2566static void rtl8169_phy_timer(unsigned long __opaque)
2567{
2568 struct net_device *dev = (struct net_device *)__opaque;
2569 struct rtl8169_private *tp = netdev_priv(dev);
2570 struct timer_list *timer = &tp->timer;
2571 void __iomem *ioaddr = tp->mmio_addr;
2572 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2573
bcf0bf90 2574 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 2575
64e4bfb4 2576 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 2577 return;
2578
2579 spin_lock_irq(&tp->lock);
2580
4da19633 2581 if (tp->phy_reset_pending(tp)) {
5b0384f4 2582 /*
1da177e4
LT		 2583 * A busy loop could burn quite a few cycles on nowadays CPU.
2584 * Let's delay the execution of the timer for a few ticks.
2585 */
2586 timeout = HZ/10;
2587 goto out_mod_timer;
2588 }
2589
2590 if (tp->link_ok(ioaddr))
2591 goto out_unlock;
2592
bf82c189 2593 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4 2594
4da19633 2595 tp->phy_reset_enable(tp);
1da177e4
LT		 2596
2597out_mod_timer:
2598 mod_timer(timer, jiffies + timeout);
2599out_unlock:
2600 spin_unlock_irq(&tp->lock);
2601}
2602
2603static inline void rtl8169_delete_timer(struct net_device *dev)
2604{
2605 struct rtl8169_private *tp = netdev_priv(dev);
2606 struct timer_list *timer = &tp->timer;
2607
e179bb7b 2608 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2609 return;
2610
2611 del_timer_sync(timer);
2612}
2613
2614static inline void rtl8169_request_timer(struct net_device *dev)
2615{
2616 struct rtl8169_private *tp = netdev_priv(dev);
2617 struct timer_list *timer = &tp->timer;
2618
e179bb7b 2619 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2620 return;
2621
2efa53f3 2622 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 2623}
2624
2625#ifdef CONFIG_NET_POLL_CONTROLLER
2626/*
2627 * Polling 'interrupt' - used by things like netconsole to send skbs
2628 * without having to re-enable interrupts. It's not called while
2629 * the interrupt routine is executing.
2630 */
2631static void rtl8169_netpoll(struct net_device *dev)
2632{
2633 struct rtl8169_private *tp = netdev_priv(dev);
2634 struct pci_dev *pdev = tp->pci_dev;
2635
2636 disable_irq(pdev->irq);
7d12e780 2637 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 2638 enable_irq(pdev->irq);
2639}
2640#endif
2641
2642static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2643 void __iomem *ioaddr)
2644{
2645 iounmap(ioaddr);
2646 pci_release_regions(pdev);
87aeec76 2647 pci_clear_mwi(pdev);
1da177e4
LT		 2648 pci_disable_device(pdev);
2649 free_netdev(dev);
2650}
2651
bf793295
FR		 2652static void rtl8169_phy_reset(struct net_device *dev,
2653 struct rtl8169_private *tp)
2654{
07d3f51f 2655 unsigned int i;
bf793295 2656
4da19633 2657 tp->phy_reset_enable(tp);
bf793295 2658 for (i = 0; i < 100; i++) {
4da19633 2659 if (!tp->phy_reset_pending(tp))
bf793295
FR		 2660 return;
2661 msleep(1);
2662 }
bf82c189 2663 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 2664}
2665
4ff96fa6
FR		 2666static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2667{
2668 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 2669
5615d9f1 2670 rtl_hw_phy_config(dev);
4ff96fa6 2671
77332894
MS		 2672 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2673 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2674 RTL_W8(0x82, 0x01);
2675 }
4ff96fa6 2676
6dccd16b
FR		 2677 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2678
2679 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2680 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 2681
bcf0bf90 2682 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 2683 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2684 RTL_W8(0x82, 0x01);
2685 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 2686 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 2687 }
2688
bf793295
FR		 2689 rtl8169_phy_reset(dev, tp);
2690
54405cde
ON		 2691 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
2692 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2693 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2694 tp->mii.supports_gmii ?
2695 ADVERTISED_1000baseT_Half |
2696 ADVERTISED_1000baseT_Full : 0);
4ff96fa6 2697
bf82c189
JP		 2698 if (RTL_R8(PHYstatus) & TBI_Enable)
2699 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 2700}
2701
773d2021
FR		 2702static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2703{
2704 void __iomem *ioaddr = tp->mmio_addr;
2705 u32 high;
2706 u32 low;
2707
2708 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2709 high = addr[4] | (addr[5] << 8);
2710
2711 spin_lock_irq(&tp->lock);
2712
2713 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 2714
773d2021 2715 RTL_W32(MAC4, high);
908ba2bf 2716 RTL_R32(MAC4);
2717
78f1cd02 2718 RTL_W32(MAC0, low);
908ba2bf 2719 RTL_R32(MAC0);
2720
773d2021
FR		 2721 RTL_W8(Cfg9346, Cfg9346_Lock);
2722
2723 spin_unlock_irq(&tp->lock);
2724}
2725
2726static int rtl_set_mac_address(struct net_device *dev, void *p)
2727{
2728 struct rtl8169_private *tp = netdev_priv(dev);
2729 struct sockaddr *addr = p;
2730
2731 if (!is_valid_ether_addr(addr->sa_data))
2732 return -EADDRNOTAVAIL;
2733
2734 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2735
2736 rtl_rar_set(tp, dev->dev_addr);
2737
2738 return 0;
2739}
2740
5f787a1a
FR		 2741static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2742{
2743 struct rtl8169_private *tp = netdev_priv(dev);
2744 struct mii_ioctl_data *data = if_mii(ifr);
2745
8b4ab28d
FR		 2746 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2747}
5f787a1a 2748
8b4ab28d
FR		 2749static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2750{
5f787a1a
FR		 2751 switch (cmd) {
2752 case SIOCGMIIPHY:
2753 data->phy_id = 32; /* Internal PHY */
2754 return 0;
2755
2756 case SIOCGMIIREG:
4da19633 2757 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 2758 return 0;
2759
2760 case SIOCSMIIREG:
4da19633 2761 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 2762 return 0;
2763 }
2764 return -EOPNOTSUPP;
2765}
2766
8b4ab28d
FR		 2767static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2768{
2769 return -EOPNOTSUPP;
2770}
2771
0e485150
FR		 2772static const struct rtl_cfg_info {
2773 void (*hw_start)(struct net_device *);
2774 unsigned int region;
2775 unsigned int align;
2776 u16 intr_event;
2777 u16 napi_event;
ccdffb9a 2778 unsigned features;
f21b75e9 2779 u8 default_ver;
0e485150
FR		 2780} rtl_cfg_infos [] = {
2781 [RTL_CFG_0] = {
2782 .hw_start = rtl_hw_start_8169,
2783 .region = 1,
e9f63f30 2784 .align = 0,
0e485150
FR		 2785 .intr_event = SYSErr | LinkChg | RxOverflow |
2786 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2787 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2788 .features = RTL_FEATURE_GMII,
2789 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 2790 },
2791 [RTL_CFG_1] = {
2792 .hw_start = rtl_hw_start_8168,
2793 .region = 2,
2794 .align = 8,
53f57357 2795 .intr_event = SYSErr | LinkChg | RxOverflow |
0e485150 2796 TxErr | TxOK | RxOK | RxErr,
fbac58fc 2797 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2798 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2799 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 2800 },
2801 [RTL_CFG_2] = {
2802 .hw_start = rtl_hw_start_8101,
2803 .region = 2,
2804 .align = 8,
2805 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2806 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2807 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2808 .features = RTL_FEATURE_MSI,
2809 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 2810 }
2811};
2812
fbac58fc
FR		 2813/* Cfg9346_Unlock assumed. */
2814static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2815 const struct rtl_cfg_info *cfg)
2816{
2817 unsigned msi = 0;
2818 u8 cfg2;
2819
2820 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 2821 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 2822 if (pci_enable_msi(pdev)) {
2823 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2824 } else {
2825 cfg2 |= MSIEnable;
2826 msi = RTL_FEATURE_MSI;
2827 }
2828 }
2829 RTL_W8(Config2, cfg2);
2830 return msi;
2831}
2832
2833static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2834{
2835 if (tp->features & RTL_FEATURE_MSI) {
2836 pci_disable_msi(pdev);
2837 tp->features &= ~RTL_FEATURE_MSI;
2838 }
2839}
2840
8b4ab28d
FR		 2841static const struct net_device_ops rtl8169_netdev_ops = {
2842 .ndo_open = rtl8169_open,
2843 .ndo_stop = rtl8169_close,
2844 .ndo_get_stats = rtl8169_get_stats,
00829823 2845 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 2846 .ndo_tx_timeout = rtl8169_tx_timeout,
2847 .ndo_validate_addr = eth_validate_addr,
2848 .ndo_change_mtu = rtl8169_change_mtu,
2849 .ndo_set_mac_address = rtl_set_mac_address,
2850 .ndo_do_ioctl = rtl8169_ioctl,
2851 .ndo_set_multicast_list = rtl_set_rx_mode,
2852#ifdef CONFIG_R8169_VLAN
2853 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2854#endif
2855#ifdef CONFIG_NET_POLL_CONTROLLER
2856 .ndo_poll_controller = rtl8169_netpoll,
2857#endif
2858
2859};
2860
c0e45c1c 2861static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2862{
2863 struct mdio_ops *ops = &tp->mdio_ops;
2864
2865 switch (tp->mac_version) {
2866 case RTL_GIGA_MAC_VER_27:
2867 ops->write = r8168dp_1_mdio_write;
2868 ops->read = r8168dp_1_mdio_read;
2869 break;
e6de30d6 2870 case RTL_GIGA_MAC_VER_28:
2871 ops->write = r8168dp_2_mdio_write;
2872 ops->read = r8168dp_2_mdio_read;
2873 break;
c0e45c1c 2874 default:
2875 ops->write = r8169_mdio_write;
2876 ops->read = r8169_mdio_read;
2877 break;
2878 }
2879}
2880
065c27c1 2881static void r810x_phy_power_down(struct rtl8169_private *tp)
2882{
2883 rtl_writephy(tp, 0x1f, 0x0000);
2884 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2885}
2886
2887static void r810x_phy_power_up(struct rtl8169_private *tp)
2888{
2889 rtl_writephy(tp, 0x1f, 0x0000);
2890 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2891}
2892
2893static void r810x_pll_power_down(struct rtl8169_private *tp)
2894{
2895 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2896 rtl_writephy(tp, 0x1f, 0x0000);
2897 rtl_writephy(tp, MII_BMCR, 0x0000);
2898 return;
2899 }
2900
2901 r810x_phy_power_down(tp);
2902}
2903
2904static void r810x_pll_power_up(struct rtl8169_private *tp)
2905{
2906 r810x_phy_power_up(tp);
2907}
2908
2909static void r8168_phy_power_up(struct rtl8169_private *tp)
2910{
2911 rtl_writephy(tp, 0x1f, 0x0000);
2912 rtl_writephy(tp, 0x0e, 0x0000);
2913 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2914}
2915
2916static void r8168_phy_power_down(struct rtl8169_private *tp)
2917{
2918 rtl_writephy(tp, 0x1f, 0x0000);
2919 rtl_writephy(tp, 0x0e, 0x0200);
2920 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2921}
2922
2923static void r8168_pll_power_down(struct rtl8169_private *tp)
2924{
2925 void __iomem *ioaddr = tp->mmio_addr;
2926
2927 if (tp->mac_version == RTL_GIGA_MAC_VER_27)
2928 return;
2929
2930 if (((tp->mac_version == RTL_GIGA_MAC_VER_23) ||
2931 (tp->mac_version == RTL_GIGA_MAC_VER_24)) &&
2932 (RTL_R16(CPlusCmd) & ASF)) {
2933 return;
2934 }
2935
2936 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2937 rtl_writephy(tp, 0x1f, 0x0000);
2938 rtl_writephy(tp, MII_BMCR, 0x0000);
2939
2940 RTL_W32(RxConfig, RTL_R32(RxConfig) |
2941 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2942 return;
2943 }
2944
2945 r8168_phy_power_down(tp);
2946
2947 switch (tp->mac_version) {
2948 case RTL_GIGA_MAC_VER_25:
2949 case RTL_GIGA_MAC_VER_26:
2950 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
2951 break;
2952 }
2953}
2954
2955static void r8168_pll_power_up(struct rtl8169_private *tp)
2956{
2957 void __iomem *ioaddr = tp->mmio_addr;
2958
2959 if (tp->mac_version == RTL_GIGA_MAC_VER_27)
2960 return;
2961
2962 switch (tp->mac_version) {
2963 case RTL_GIGA_MAC_VER_25:
2964 case RTL_GIGA_MAC_VER_26:
2965 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
2966 break;
2967 }
2968
2969 r8168_phy_power_up(tp);
2970}
2971
2972static void rtl_pll_power_op(struct rtl8169_private *tp,
2973 void (*op)(struct rtl8169_private *))
2974{
2975 if (op)
2976 op(tp);
2977}
2978
2979static void rtl_pll_power_down(struct rtl8169_private *tp)
2980{
2981 rtl_pll_power_op(tp, tp->pll_power_ops.down);
2982}
2983
2984static void rtl_pll_power_up(struct rtl8169_private *tp)
2985{
2986 rtl_pll_power_op(tp, tp->pll_power_ops.up);
2987}
2988
2989static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
2990{
2991 struct pll_power_ops *ops = &tp->pll_power_ops;
2992
2993 switch (tp->mac_version) {
2994 case RTL_GIGA_MAC_VER_07:
2995 case RTL_GIGA_MAC_VER_08:
2996 case RTL_GIGA_MAC_VER_09:
2997 case RTL_GIGA_MAC_VER_10:
2998 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 2999 case RTL_GIGA_MAC_VER_29:
3000 case RTL_GIGA_MAC_VER_30:
065c27c1 3001 ops->down = r810x_pll_power_down;
3002 ops->up = r810x_pll_power_up;
3003 break;
3004
3005 case RTL_GIGA_MAC_VER_11:
3006 case RTL_GIGA_MAC_VER_12:
3007 case RTL_GIGA_MAC_VER_17:
3008 case RTL_GIGA_MAC_VER_18:
3009 case RTL_GIGA_MAC_VER_19:
3010 case RTL_GIGA_MAC_VER_20:
3011 case RTL_GIGA_MAC_VER_21:
3012 case RTL_GIGA_MAC_VER_22:
3013 case RTL_GIGA_MAC_VER_23:
3014 case RTL_GIGA_MAC_VER_24:
3015 case RTL_GIGA_MAC_VER_25:
3016 case RTL_GIGA_MAC_VER_26:
3017 case RTL_GIGA_MAC_VER_27:
e6de30d6 3018 case RTL_GIGA_MAC_VER_28:
065c27c1 3019 ops->down = r8168_pll_power_down;
3020 ops->up = r8168_pll_power_up;
3021 break;
3022
3023 default:
3024 ops->down = NULL;
3025 ops->up = NULL;
3026 break;
3027 }
3028}
3029
1da177e4 3030static int __devinit
4ff96fa6 3031rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 3032{
0e485150
FR		 3033 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3034 const unsigned int region = cfg->region;
1da177e4 3035 struct rtl8169_private *tp;
ccdffb9a 3036 struct mii_if_info *mii;
4ff96fa6
FR		 3037 struct net_device *dev;
3038 void __iomem *ioaddr;
07d3f51f
FR		 3039 unsigned int i;
3040 int rc;
1da177e4 3041
4ff96fa6
FR		 3042 if (netif_msg_drv(&debug)) {
3043 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3044 MODULENAME, RTL8169_VERSION);
3045 }
1da177e4 3046
1da177e4 3047 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 3048 if (!dev) {
b57b7e5a 3049 if (netif_msg_drv(&debug))
9b91cf9d 3050 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 3051 rc = -ENOMEM;
3052 goto out;
1da177e4
LT		 3053 }
3054
1da177e4 3055 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 3056 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 3057 tp = netdev_priv(dev);
c4028958 3058 tp->dev = dev;
21e197f2 3059 tp->pci_dev = pdev;
b57b7e5a 3060 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 3061
ccdffb9a
FR		 3062 mii = &tp->mii;
3063 mii->dev = dev;
3064 mii->mdio_read = rtl_mdio_read;
3065 mii->mdio_write = rtl_mdio_write;
3066 mii->phy_id_mask = 0x1f;
3067 mii->reg_num_mask = 0x1f;
3068 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3069
1da177e4
LT		 3070 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3071 rc = pci_enable_device(pdev);
b57b7e5a 3072 if (rc < 0) {
bf82c189 3073 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 3074 goto err_out_free_dev_1;
1da177e4
LT		 3075 }
3076
87aeec76 3077 if (pci_set_mwi(pdev) < 0)
3078 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 3079
1da177e4 3080 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 3081 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 3082 netif_err(tp, probe, dev,
3083 "region #%d not an MMIO resource, aborting\n",
3084 region);
1da177e4 3085 rc = -ENODEV;
87aeec76 3086 goto err_out_mwi_2;
1da177e4 3087 }
4ff96fa6 3088
1da177e4 3089 /* check for weird/broken PCI region reporting */
bcf0bf90 3090 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 3091 netif_err(tp, probe, dev,
3092 "Invalid PCI region size(s), aborting\n");
1da177e4 3093 rc = -ENODEV;
87aeec76 3094 goto err_out_mwi_2;
1da177e4
LT		 3095 }
3096
3097 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 3098 if (rc < 0) {
bf82c189 3099 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 3100 goto err_out_mwi_2;
1da177e4
LT		 3101 }
3102
3103 tp->cp_cmd = PCIMulRW | RxChkSum;
3104
3105 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 3106 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 3107 tp->cp_cmd |= PCIDAC;
3108 dev->features |= NETIF_F_HIGHDMA;
3109 } else {
284901a9 3110 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 3111 if (rc < 0) {
bf82c189 3112 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 3113 goto err_out_free_res_3;
1da177e4
LT		 3114 }
3115 }
3116
1da177e4 3117 /* ioremap MMIO region */
bcf0bf90 3118 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 3119 if (!ioaddr) {
bf82c189 3120 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 3121 rc = -EIO;
87aeec76 3122 goto err_out_free_res_3;
1da177e4
LT		 3123 }
3124
4300e8c7
DM		 3125 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3126 if (!tp->pcie_cap)
3127 netif_info(tp, probe, dev, "no PCI Express capability\n");
3128
d78ad8cb 3129 RTL_W16(IntrMask, 0x0000);
1da177e4
LT		 3130
3131 /* Soft reset the chip. */
3132 RTL_W8(ChipCmd, CmdReset);
3133
3134 /* Check that the chip has finished the reset. */
07d3f51f 3135 for (i = 0; i < 100; i++) {
1da177e4
LT		 3136 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3137 break;
b518fa8e 3138 msleep_interruptible(1);
1da177e4
LT		 3139 }
3140
d78ad8cb
KW		 3141 RTL_W16(IntrStatus, 0xffff);
3142
ca52efd5 3143 pci_set_master(pdev);
3144
1da177e4
LT		 3145 /* Identify chip attached to board */
3146 rtl8169_get_mac_version(tp, ioaddr);
1da177e4 3147
c0e45c1c 3148 rtl_init_mdio_ops(tp);
065c27c1 3149 rtl_init_pll_power_ops(tp);
c0e45c1c 3150
f21b75e9
JD		 3151 /* Use appropriate default if unknown */
3152 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
bf82c189
JP		 3153 netif_notice(tp, probe, dev,
3154 "unknown MAC, using family default\n");
f21b75e9
JD		 3155 tp->mac_version = cfg->default_ver;
3156 }
3157
1da177e4 3158 rtl8169_print_mac_version(tp);
1da177e4 3159
cee60c37 3160 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 3161 if (tp->mac_version == rtl_chip_info[i].mac_version)
3162 break;
3163 }
cee60c37 3164 if (i == ARRAY_SIZE(rtl_chip_info)) {
f21b75e9
JD		 3165 dev_err(&pdev->dev,
3166 "driver bug, MAC version not found in rtl_chip_info\n");
87aeec76 3167 goto err_out_msi_4;
1da177e4
LT		 3168 }
3169 tp->chipset = i;
3170
5d06a99f
FR		 3171 RTL_W8(Cfg9346, Cfg9346_Unlock);
3172 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3173 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 3174 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3175 tp->features |= RTL_FEATURE_WOL;
3176 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3177 tp->features |= RTL_FEATURE_WOL;
fbac58fc 3178 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 3179 RTL_W8(Cfg9346, Cfg9346_Lock);
3180
66ec5d4f
FR		 3181 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3182 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 3183 tp->set_speed = rtl8169_set_speed_tbi;
3184 tp->get_settings = rtl8169_gset_tbi;
3185 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3186 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3187 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 3188 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4 3189
64e4bfb4 3190 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 3191 } else {
3192 tp->set_speed = rtl8169_set_speed_xmii;
3193 tp->get_settings = rtl8169_gset_xmii;
3194 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3195 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3196 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 3197 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 3198 }
3199
df58ef51
FR		 3200 spin_lock_init(&tp->lock);
3201
738e1e69
PV		 3202 tp->mmio_addr = ioaddr;
3203
7bf6bf48 3204 /* Get MAC address */
1da177e4
LT		 3205 for (i = 0; i < MAC_ADDR_LEN; i++)
3206 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 3207 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 3208
1da177e4 3209 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 3210 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3211 dev->irq = pdev->irq;
3212 dev->base_addr = (unsigned long) ioaddr;
1da177e4 3213
bea3348e 3214 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 3215
3216#ifdef CONFIG_R8169_VLAN
3217 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4 3218#endif
2edae08e 3219 dev->features |= NETIF_F_GRO;
1da177e4
LT		 3220
3221 tp->intr_mask = 0xffff;
0e485150
FR		 3222 tp->hw_start = cfg->hw_start;
3223 tp->intr_event = cfg->intr_event;
3224 tp->napi_event = cfg->napi_event;
1da177e4 3225
2efa53f3
FR		 3226 init_timer(&tp->timer);
3227 tp->timer.data = (unsigned long) dev;
3228 tp->timer.function = rtl8169_phy_timer;
3229
1da177e4 3230 rc = register_netdev(dev);
4ff96fa6 3231 if (rc < 0)
87aeec76 3232 goto err_out_msi_4;
1da177e4
LT		 3233
3234 pci_set_drvdata(pdev, dev);
3235
bf82c189
JP		 3236 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3237 rtl_chip_info[tp->chipset].name,
3238 dev->base_addr, dev->dev_addr,
3239 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
1da177e4 3240
e6de30d6 3241 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3242 (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
b646d900 3243 rtl8168_driver_start(tp);
e6de30d6 3244 }
b646d900 3245
8b76ab39 3246 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 3247
f3ec4f87
AS		 3248 if (pci_dev_run_wake(pdev))
3249 pm_runtime_put_noidle(&pdev->dev);
e1759441 3250
0d672e9f
IV		 3251 netif_carrier_off(dev);
3252
4ff96fa6
FR		 3253out:
3254 return rc;
1da177e4 3255
87aeec76 3256err_out_msi_4:
fbac58fc 3257 rtl_disable_msi(pdev, tp);
4ff96fa6 3258 iounmap(ioaddr);
87aeec76 3259err_out_free_res_3:
4ff96fa6 3260 pci_release_regions(pdev);
87aeec76 3261err_out_mwi_2:
4ff96fa6 3262 pci_clear_mwi(pdev);
4ff96fa6
FR		 3263 pci_disable_device(pdev);
3264err_out_free_dev_1:
3265 free_netdev(dev);
3266 goto out;
1da177e4
LT		 3267}
3268
07d3f51f 3269static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3270{
3271 struct net_device *dev = pci_get_drvdata(pdev);
3272 struct rtl8169_private *tp = netdev_priv(dev);
3273
e6de30d6 3274 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3275 (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
b646d900 3276 rtl8168_driver_stop(tp);
e6de30d6 3277 }
b646d900 3278
23f333a2 3279 cancel_delayed_work_sync(&tp->task);
eb2a021c 3280
f1e02ed1 3281 rtl_release_firmware(tp);
3282
1da177e4 3283 unregister_netdev(dev);
cc098dc7 3284
f3ec4f87
AS		 3285 if (pci_dev_run_wake(pdev))
3286 pm_runtime_get_noresume(&pdev->dev);
e1759441 3287
cc098dc7
IV		 3288 /* restore original MAC address */
3289 rtl_rar_set(tp, dev->perm_addr);
3290
fbac58fc 3291 rtl_disable_msi(pdev, tp);
1da177e4
LT		 3292 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3293 pci_set_drvdata(pdev, NULL);
3294}
3295
1da177e4
LT		 3296static int rtl8169_open(struct net_device *dev)
3297{
3298 struct rtl8169_private *tp = netdev_priv(dev);
eee3a96c 3299 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 3300 struct pci_dev *pdev = tp->pci_dev;
99f252b0 3301 int retval = -ENOMEM;
1da177e4 3302
e1759441 3303 pm_runtime_get_sync(&pdev->dev);
1da177e4 3304
1da177e4
LT		 3305 /*
3306 * Rx and Tx desscriptors needs 256 bytes alignment.
82553bb6 3307 * dma_alloc_coherent provides more.
1da177e4 3308 */
82553bb6
SG		 3309 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3310 &tp->TxPhyAddr, GFP_KERNEL);
1da177e4 3311 if (!tp->TxDescArray)
e1759441 3312 goto err_pm_runtime_put;
1da177e4 3313
82553bb6
SG		 3314 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3315 &tp->RxPhyAddr, GFP_KERNEL);
1da177e4 3316 if (!tp->RxDescArray)
99f252b0 3317 goto err_free_tx_0;
1da177e4
LT		 3318
3319 retval = rtl8169_init_ring(dev);
3320 if (retval < 0)
99f252b0 3321 goto err_free_rx_1;
1da177e4 3322
c4028958 3323 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 3324
99f252b0
FR		 3325 smp_mb();
3326
fbac58fc
FR		 3327 retval = request_irq(dev->irq, rtl8169_interrupt,
3328 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 3329 dev->name, dev);
3330 if (retval < 0)
3331 goto err_release_ring_2;
3332
bea3348e 3333 napi_enable(&tp->napi);
bea3348e 3334
eee3a96c 3335 rtl8169_init_phy(dev, tp);
3336
3337 /*
3338 * Pretend we are using VLANs; This bypasses a nasty bug where
3339 * Interrupts stop flowing on high load on 8110SCd controllers.
3340 */
3341 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3342 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3343
065c27c1 3344 rtl_pll_power_up(tp);
3345
07ce4064 3346 rtl_hw_start(dev);
1da177e4
LT		 3347
3348 rtl8169_request_timer(dev);
3349
e1759441
RW		 3350 tp->saved_wolopts = 0;
3351 pm_runtime_put_noidle(&pdev->dev);
3352
eee3a96c 3353 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4
LT		 3354out:
3355 return retval;
3356
99f252b0
FR		 3357err_release_ring_2:
3358 rtl8169_rx_clear(tp);
3359err_free_rx_1:
82553bb6
SG		 3360 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3361 tp->RxPhyAddr);
e1759441 3362 tp->RxDescArray = NULL;
99f252b0 3363err_free_tx_0:
82553bb6
SG		 3364 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3365 tp->TxPhyAddr);
e1759441
RW		 3366 tp->TxDescArray = NULL;
3367err_pm_runtime_put:
3368 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 3369 goto out;
3370}
3371
e6de30d6 3372static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 3373{
e6de30d6 3374 void __iomem *ioaddr = tp->mmio_addr;
3375
1da177e4
LT		 3376 /* Disable interrupts */
3377 rtl8169_irq_mask_and_ack(ioaddr);
3378
e6de30d6 3379 if (tp->mac_version == RTL_GIGA_MAC_VER_28) {
3380 while (RTL_R8(TxPoll) & NPQ)
3381 udelay(20);
3382
3383 }
3384
1da177e4
LT		 3385 /* Reset the chipset */
3386 RTL_W8(ChipCmd, CmdReset);
3387
3388 /* PCI commit */
3389 RTL_R8(ChipCmd);
3390}
3391
7f796d83 3392static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 3393{
3394 void __iomem *ioaddr = tp->mmio_addr;
3395 u32 cfg = rtl8169_rx_config;
3396
3397 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3398 RTL_W32(RxConfig, cfg);
3399
3400 /* Set DMA burst size and Interframe Gap Time */
3401 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3402 (InterFrameGap << TxInterFrameGapShift));
3403}
3404
07ce4064 3405static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 3406{
3407 struct rtl8169_private *tp = netdev_priv(dev);
3408 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 3409 unsigned int i;
1da177e4
LT		 3410
3411 /* Soft reset the chip. */
3412 RTL_W8(ChipCmd, CmdReset);
3413
3414 /* Check that the chip has finished the reset. */
07d3f51f 3415 for (i = 0; i < 100; i++) {
1da177e4
LT		 3416 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3417 break;
b518fa8e 3418 msleep_interruptible(1);
1da177e4
LT		 3419 }
3420
07ce4064
FR		 3421 tp->hw_start(dev);
3422
07ce4064
FR		 3423 netif_start_queue(dev);
3424}
3425
3426
7f796d83
FR		 3427static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3428 void __iomem *ioaddr)
3429{
3430 /*
3431 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3432 * register to be written before TxDescAddrLow to work.
3433 * Switching from MMIO to I/O access fixes the issue as well.
3434 */
3435 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 3436 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 3437 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 3438 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 3439}
3440
3441static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3442{
3443 u16 cmd;
3444
3445 cmd = RTL_R16(CPlusCmd);
3446 RTL_W16(CPlusCmd, cmd);
3447 return cmd;
3448}
3449
fdd7b4c3 3450static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 3451{
3452 /* Low hurts. Let's disable the filtering. */
207d6e87 3453 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 3454}
3455
6dccd16b
FR		 3456static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3457{
350f7596 3458 static const struct {
6dccd16b
FR		 3459 u32 mac_version;
3460 u32 clk;
3461 u32 val;
3462 } cfg2_info [] = {
3463 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3464 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3465 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3466 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3467 }, *p = cfg2_info;
3468 unsigned int i;
3469 u32 clk;
3470
3471 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 3472 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 3473 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3474 RTL_W32(0x7c, p->val);
3475 break;
3476 }
3477 }
3478}
3479
07ce4064
FR		 3480static void rtl_hw_start_8169(struct net_device *dev)
3481{
3482 struct rtl8169_private *tp = netdev_priv(dev);
3483 void __iomem *ioaddr = tp->mmio_addr;
3484 struct pci_dev *pdev = tp->pci_dev;
07ce4064 3485
9cb427b6
FR		 3486 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3487 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3488 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3489 }
3490
1da177e4 3491 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 3492 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3493 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3494 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3495 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3496 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3497
f0298f81 3498 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 3499
6f0333b8 3500 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 3501
c946b304
FR		 3502 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3503 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3504 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3505 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3506 rtl_set_rx_tx_config_registers(tp);
1da177e4 3507
7f796d83 3508 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 3509
bcf0bf90
FR		 3510 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3511 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 3512 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 3513 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 3514 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 3515 }
3516
bcf0bf90
FR		 3517 RTL_W16(CPlusCmd, tp->cp_cmd);
3518
6dccd16b
FR		 3519 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3520
1da177e4
LT		 3521 /*
3522 * Undocumented corner. Supposedly:
3523 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3524 */
3525 RTL_W16(IntrMitigate, 0x0000);
3526
7f796d83 3527 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 3528
c946b304
FR		 3529 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3530 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3531 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3532 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3533 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3534 rtl_set_rx_tx_config_registers(tp);
3535 }
3536
1da177e4 3537 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 3538
3539 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3540 RTL_R8(IntrMask);
1da177e4
LT		 3541
3542 RTL_W32(RxMissed, 0);
3543
07ce4064 3544 rtl_set_rx_mode(dev);
1da177e4
LT		 3545
3546 /* no early-rx interrupts */
3547 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 3548
3549 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 3550 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3551}
1da177e4 3552
9c14ceaf 3553static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 3554{
9c14ceaf
FR		 3555 struct net_device *dev = pci_get_drvdata(pdev);
3556 struct rtl8169_private *tp = netdev_priv(dev);
3557 int cap = tp->pcie_cap;
3558
3559 if (cap) {
3560 u16 ctl;
458a9f61 3561
9c14ceaf
FR		 3562 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3563 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3564 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3565 }
458a9f61
FR		 3566}
3567
650e8d5d 3568static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
dacf8154
FR		 3569{
3570 u32 csi;
3571
3572 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
650e8d5d 3573 rtl_csi_write(ioaddr, 0x070c, csi | bits);
3574}
3575
e6de30d6 3576static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3577{
3578 rtl_csi_access_enable(ioaddr, 0x17000000);
3579}
3580
650e8d5d 3581static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3582{
3583 rtl_csi_access_enable(ioaddr, 0x27000000);
dacf8154
FR		 3584}
3585
3586struct ephy_info {
3587 unsigned int offset;
3588 u16 mask;
3589 u16 bits;
3590};
3591
350f7596 3592static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 3593{
3594 u16 w;
3595
3596 while (len-- > 0) {
3597 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3598 rtl_ephy_write(ioaddr, e->offset, w);
3599 e++;
3600 }
3601}
3602
b726e493
FR		 3603static void rtl_disable_clock_request(struct pci_dev *pdev)
3604{
3605 struct net_device *dev = pci_get_drvdata(pdev);
3606 struct rtl8169_private *tp = netdev_priv(dev);
3607 int cap = tp->pcie_cap;
3608
3609 if (cap) {
3610 u16 ctl;
3611
3612 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3613 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3614 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3615 }
3616}
3617
e6de30d6 3618static void rtl_enable_clock_request(struct pci_dev *pdev)
3619{
3620 struct net_device *dev = pci_get_drvdata(pdev);
3621 struct rtl8169_private *tp = netdev_priv(dev);
3622 int cap = tp->pcie_cap;
3623
3624 if (cap) {
3625 u16 ctl;
3626
3627 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3628 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3629 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3630 }
3631}
3632
b726e493
FR		 3633#define R8168_CPCMD_QUIRK_MASK (\
3634 EnableBist | \
3635 Mac_dbgo_oe | \
3636 Force_half_dup | \
3637 Force_rxflow_en | \
3638 Force_txflow_en | \
3639 Cxpl_dbg_sel | \
3640 ASF | \
3641 PktCntrDisable | \
3642 Mac_dbgo_sel)
3643
219a1e9d
FR		 3644static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3645{
b726e493
FR		 3646 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3647
3648 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3649
2e68ae44
FR		 3650 rtl_tx_performance_tweak(pdev,
3651 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 3652}
3653
3654static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3655{
3656 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493 3657
f0298f81 3658 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 3659
3660 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 3661}
3662
3663static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3664{
b726e493
FR		 3665 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3666
3667 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3668
219a1e9d 3669 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 3670
3671 rtl_disable_clock_request(pdev);
3672
3673 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 3674}
3675
ef3386f0 3676static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 3677{
350f7596 3678 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 3679 { 0x01, 0, 0x0001 },
3680 { 0x02, 0x0800, 0x1000 },
3681 { 0x03, 0, 0x0042 },
3682 { 0x06, 0x0080, 0x0000 },
3683 { 0x07, 0, 0x2000 }
3684 };
3685
650e8d5d 3686 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3687
3688 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3689
219a1e9d
FR		 3690 __rtl_hw_start_8168cp(ioaddr, pdev);
3691}
3692
ef3386f0
FR		 3693static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3694{
650e8d5d 3695 rtl_csi_access_enable_2(ioaddr);
ef3386f0
FR		 3696
3697 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3698
3699 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3700
3701 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3702}
3703
7f3e3d3a
FR		 3704static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3705{
650e8d5d 3706 rtl_csi_access_enable_2(ioaddr);
7f3e3d3a
FR		 3707
3708 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3709
3710 /* Magic. */
3711 RTL_W8(DBG_REG, 0x20);
3712
f0298f81 3713 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 3714
3715 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3716
3717 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3718}
3719
219a1e9d
FR		 3720static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3721{
350f7596 3722 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 3723 { 0x02, 0x0800, 0x1000 },
3724 { 0x03, 0, 0x0002 },
3725 { 0x06, 0x0080, 0x0000 }
3726 };
3727
650e8d5d 3728 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3729
3730 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3731
3732 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3733
219a1e9d
FR		 3734 __rtl_hw_start_8168cp(ioaddr, pdev);
3735}
3736
3737static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3738{
350f7596 3739 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 3740 { 0x01, 0, 0x0001 },
3741 { 0x03, 0x0400, 0x0220 }
3742 };
3743
650e8d5d 3744 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3745
3746 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3747
219a1e9d
FR		 3748 __rtl_hw_start_8168cp(ioaddr, pdev);
3749}
3750
197ff761
FR		 3751static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3752{
3753 rtl_hw_start_8168c_2(ioaddr, pdev);
3754}
3755
6fb07058
FR		 3756static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3757{
650e8d5d 3758 rtl_csi_access_enable_2(ioaddr);
6fb07058
FR		 3759
3760 __rtl_hw_start_8168cp(ioaddr, pdev);
3761}
3762
5b538df9
FR		 3763static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3764{
650e8d5d 3765 rtl_csi_access_enable_2(ioaddr);
5b538df9
FR		 3766
3767 rtl_disable_clock_request(pdev);
3768
f0298f81 3769 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 3770
3771 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3772
3773 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3774}
3775
e6de30d6 3776static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
3777{
3778 static const struct ephy_info e_info_8168d_4[] = {
3779 { 0x0b, ~0, 0x48 },
3780 { 0x19, 0x20, 0x50 },
3781 { 0x0c, ~0, 0x20 }
3782 };
3783 int i;
3784
3785 rtl_csi_access_enable_1(ioaddr);
3786
3787 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3788
3789 RTL_W8(MaxTxPacketSize, TxPacketMax);
3790
3791 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
3792 const struct ephy_info *e = e_info_8168d_4 + i;
3793 u16 w;
3794
3795 w = rtl_ephy_read(ioaddr, e->offset);
3796 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
3797 }
3798
3799 rtl_enable_clock_request(pdev);
3800}
3801
07ce4064
FR		 3802static void rtl_hw_start_8168(struct net_device *dev)
3803{
2dd99530
FR		 3804 struct rtl8169_private *tp = netdev_priv(dev);
3805 void __iomem *ioaddr = tp->mmio_addr;
0e485150 3806 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 3807
3808 RTL_W8(Cfg9346, Cfg9346_Unlock);
3809
f0298f81 3810 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 3811
6f0333b8 3812 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 3813
0e485150 3814 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 3815
3816 RTL_W16(CPlusCmd, tp->cp_cmd);
3817
0e485150 3818 RTL_W16(IntrMitigate, 0x5151);
2dd99530 3819
0e485150 3820 /* Work around for RxFIFO overflow. */
b5ba6d12
IV		 3821 if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
3822 tp->mac_version == RTL_GIGA_MAC_VER_22) {
0e485150
FR		 3823 tp->intr_event |= RxFIFOOver | PCSTimeout;
3824 tp->intr_event &= ~RxOverflow;
3825 }
3826
3827 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 3828
b8363901
FR		 3829 rtl_set_rx_mode(dev);
3830
3831 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3832 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 3833
3834 RTL_R8(IntrMask);
3835
219a1e9d
FR		 3836 switch (tp->mac_version) {
3837 case RTL_GIGA_MAC_VER_11:
3838 rtl_hw_start_8168bb(ioaddr, pdev);
3839 break;
3840
3841 case RTL_GIGA_MAC_VER_12:
3842 case RTL_GIGA_MAC_VER_17:
3843 rtl_hw_start_8168bef(ioaddr, pdev);
3844 break;
3845
3846 case RTL_GIGA_MAC_VER_18:
ef3386f0 3847 rtl_hw_start_8168cp_1(ioaddr, pdev);
219a1e9d
FR		 3848 break;
3849
3850 case RTL_GIGA_MAC_VER_19:
3851 rtl_hw_start_8168c_1(ioaddr, pdev);
3852 break;
3853
3854 case RTL_GIGA_MAC_VER_20:
3855 rtl_hw_start_8168c_2(ioaddr, pdev);
3856 break;
3857
197ff761
FR		 3858 case RTL_GIGA_MAC_VER_21:
3859 rtl_hw_start_8168c_3(ioaddr, pdev);
3860 break;
3861
6fb07058
FR		 3862 case RTL_GIGA_MAC_VER_22:
3863 rtl_hw_start_8168c_4(ioaddr, pdev);
3864 break;
3865
ef3386f0
FR		 3866 case RTL_GIGA_MAC_VER_23:
3867 rtl_hw_start_8168cp_2(ioaddr, pdev);
3868 break;
3869
7f3e3d3a
FR		 3870 case RTL_GIGA_MAC_VER_24:
3871 rtl_hw_start_8168cp_3(ioaddr, pdev);
3872 break;
3873
5b538df9 3874 case RTL_GIGA_MAC_VER_25:
daf9df6d 3875 case RTL_GIGA_MAC_VER_26:
3876 case RTL_GIGA_MAC_VER_27:
5b538df9
FR		 3877 rtl_hw_start_8168d(ioaddr, pdev);
3878 break;
3879
e6de30d6 3880 case RTL_GIGA_MAC_VER_28:
3881 rtl_hw_start_8168d_4(ioaddr, pdev);
3882 break;
3883
219a1e9d
FR		 3884 default:
3885 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3886 dev->name, tp->mac_version);
3887 break;
3888 }
2dd99530 3889
0e485150
FR		 3890 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3891
b8363901
FR		 3892 RTL_W8(Cfg9346, Cfg9346_Lock);
3893
2dd99530 3894 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 3895
0e485150 3896 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3897}
1da177e4 3898
2857ffb7
FR		 3899#define R810X_CPCMD_QUIRK_MASK (\
3900 EnableBist | \
3901 Mac_dbgo_oe | \
3902 Force_half_dup | \
5edcc537 3903 Force_rxflow_en | \
2857ffb7
FR		 3904 Force_txflow_en | \
3905 Cxpl_dbg_sel | \
3906 ASF | \
3907 PktCntrDisable | \
3908 PCIDAC | \
3909 PCIMulRW)
3910
3911static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3912{
350f7596 3913 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 3914 { 0x01, 0, 0x6e65 },
3915 { 0x02, 0, 0x091f },
3916 { 0x03, 0, 0xc2f9 },
3917 { 0x06, 0, 0xafb5 },
3918 { 0x07, 0, 0x0e00 },
3919 { 0x19, 0, 0xec80 },
3920 { 0x01, 0, 0x2e65 },
3921 { 0x01, 0, 0x6e65 }
3922 };
3923 u8 cfg1;
3924
650e8d5d 3925 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 3926
3927 RTL_W8(DBG_REG, FIX_NAK_1);
3928
3929 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3930
3931 RTL_W8(Config1,
3932 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3933 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3934
3935 cfg1 = RTL_R8(Config1);
3936 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3937 RTL_W8(Config1, cfg1 & ~LEDS0);
3938
3939 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3940
3941 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3942}
3943
3944static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3945{
650e8d5d 3946 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 3947
3948 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3949
3950 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3951 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3952
3953 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3954}
3955
3956static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3957{
3958 rtl_hw_start_8102e_2(ioaddr, pdev);
3959
3960 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3961}
3962
5a5e4443
HW		 3963static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3964{
3965 static const struct ephy_info e_info_8105e_1[] = {
3966 { 0x07, 0, 0x4000 },
3967 { 0x19, 0, 0x0200 },
3968 { 0x19, 0, 0x0020 },
3969 { 0x1e, 0, 0x2000 },
3970 { 0x03, 0, 0x0001 },
3971 { 0x19, 0, 0x0100 },
3972 { 0x19, 0, 0x0004 },
3973 { 0x0a, 0, 0x0020 }
3974 };
3975
3976 /* Force LAN exit from ASPM if Rx/Tx are not idel */
3977 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
3978
3979 /* disable Early Tally Counter */
3980 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
3981
3982 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
3983 RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
3984
3985 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
3986}
3987
3988static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3989{
3990 rtl_hw_start_8105e_1(ioaddr, pdev);
3991 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
3992}
3993
07ce4064
FR		 3994static void rtl_hw_start_8101(struct net_device *dev)
3995{
cdf1a608
FR		 3996 struct rtl8169_private *tp = netdev_priv(dev);
3997 void __iomem *ioaddr = tp->mmio_addr;
3998 struct pci_dev *pdev = tp->pci_dev;
3999
e3cf0cc0
FR		 4000 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
4001 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 4002 int cap = tp->pcie_cap;
4003
4004 if (cap) {
4005 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4006 PCI_EXP_DEVCTL_NOSNOOP_EN);
4007 }
cdf1a608
FR		 4008 }
4009
2857ffb7
FR		 4010 switch (tp->mac_version) {
4011 case RTL_GIGA_MAC_VER_07:
4012 rtl_hw_start_8102e_1(ioaddr, pdev);
4013 break;
4014
4015 case RTL_GIGA_MAC_VER_08:
4016 rtl_hw_start_8102e_3(ioaddr, pdev);
4017 break;
4018
4019 case RTL_GIGA_MAC_VER_09:
4020 rtl_hw_start_8102e_2(ioaddr, pdev);
4021 break;
5a5e4443
HW		 4022
4023 case RTL_GIGA_MAC_VER_29:
4024 rtl_hw_start_8105e_1(ioaddr, pdev);
4025 break;
4026 case RTL_GIGA_MAC_VER_30:
4027 rtl_hw_start_8105e_2(ioaddr, pdev);
4028 break;
cdf1a608
FR		 4029 }
4030
4031 RTL_W8(Cfg9346, Cfg9346_Unlock);
4032
f0298f81 4033 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 4034
6f0333b8 4035 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608
FR		 4036
4037 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4038
4039 RTL_W16(CPlusCmd, tp->cp_cmd);
4040
4041 RTL_W16(IntrMitigate, 0x0000);
4042
4043 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4044
4045 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4046 rtl_set_rx_tx_config_registers(tp);
4047
4048 RTL_W8(Cfg9346, Cfg9346_Lock);
4049
4050 RTL_R8(IntrMask);
4051
cdf1a608
FR		 4052 rtl_set_rx_mode(dev);
4053
0e485150
FR		 4054 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4055
cdf1a608 4056 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 4057
0e485150 4058 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4059}
4060
4061static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4062{
1da177e4
LT		 4063 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4064 return -EINVAL;
4065
4066 dev->mtu = new_mtu;
323bb685 4067 return 0;
1da177e4
LT		 4068}
4069
4070static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4071{
95e0918d 4072 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 4073 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4074}
4075
6f0333b8
ED		 4076static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4077 void **data_buff, struct RxDesc *desc)
1da177e4 4078{
48addcc9 4079 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 4080 DMA_FROM_DEVICE);
48addcc9 4081
6f0333b8
ED		 4082 kfree(*data_buff);
4083 *data_buff = NULL;
1da177e4
LT		 4084 rtl8169_make_unusable_by_asic(desc);
4085}
4086
4087static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4088{
4089 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4090
4091 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4092}
4093
4094static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4095 u32 rx_buf_sz)
4096{
4097 desc->addr = cpu_to_le64(mapping);
4098 wmb();
4099 rtl8169_mark_to_asic(desc, rx_buf_sz);
4100}
4101
6f0333b8
ED		 4102static inline void *rtl8169_align(void *data)
4103{
4104 return (void *)ALIGN((long)data, 16);
4105}
4106
0ecbe1ca
SG		 4107static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4108 struct RxDesc *desc)
1da177e4 4109{
6f0333b8 4110 void *data;
1da177e4 4111 dma_addr_t mapping;
48addcc9 4112 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 4113 struct net_device *dev = tp->dev;
6f0333b8 4114 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 4115
6f0333b8
ED		 4116 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4117 if (!data)
4118 return NULL;
e9f63f30 4119
6f0333b8
ED		 4120 if (rtl8169_align(data) != data) {
4121 kfree(data);
4122 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4123 if (!data)
4124 return NULL;
4125 }
3eafe507 4126
48addcc9 4127 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 4128 DMA_FROM_DEVICE);
d827d86b
SG		 4129 if (unlikely(dma_mapping_error(d, mapping))) {
4130 if (net_ratelimit())
4131 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 4132 goto err_out;
d827d86b 4133 }
1da177e4
LT		 4134
4135 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 4136 return data;
3eafe507
SG		 4137
4138err_out:
4139 kfree(data);
4140 return NULL;
1da177e4
LT		 4141}
4142
4143static void rtl8169_rx_clear(struct rtl8169_private *tp)
4144{
07d3f51f 4145 unsigned int i;
1da177e4
LT		 4146
4147 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 4148 if (tp->Rx_databuff[i]) {
4149 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 4150 tp->RxDescArray + i);
4151 }
4152 }
4153}
4154
0ecbe1ca 4155static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 4156{
0ecbe1ca
SG		 4157 desc->opts1 |= cpu_to_le32(RingEnd);
4158}
5b0384f4 4159
0ecbe1ca
SG		 4160static int rtl8169_rx_fill(struct rtl8169_private *tp)
4161{
4162 unsigned int i;
1da177e4 4163
0ecbe1ca
SG		 4164 for (i = 0; i < NUM_RX_DESC; i++) {
4165 void *data;
4ae47c2d 4166
6f0333b8 4167 if (tp->Rx_databuff[i])
1da177e4 4168 continue;
bcf0bf90 4169
0ecbe1ca 4170 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 4171 if (!data) {
4172 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 4173 goto err_out;
6f0333b8
ED		 4174 }
4175 tp->Rx_databuff[i] = data;
1da177e4 4176 }
1da177e4 4177
0ecbe1ca
SG		 4178 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4179 return 0;
4180
4181err_out:
4182 rtl8169_rx_clear(tp);
4183 return -ENOMEM;
1da177e4
LT		 4184}
4185
4186static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4187{
4188 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4189}
4190
4191static int rtl8169_init_ring(struct net_device *dev)
4192{
4193 struct rtl8169_private *tp = netdev_priv(dev);
4194
4195 rtl8169_init_ring_indexes(tp);
4196
4197 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 4198 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 4199
0ecbe1ca 4200 return rtl8169_rx_fill(tp);
1da177e4
LT		 4201}
4202
48addcc9 4203static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 4204 struct TxDesc *desc)
4205{
4206 unsigned int len = tx_skb->len;
4207
48addcc9
SG		 4208 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4209
1da177e4
LT		 4210 desc->opts1 = 0x00;
4211 desc->opts2 = 0x00;
4212 desc->addr = 0x00;
4213 tx_skb->len = 0;
4214}
4215
3eafe507
SG		 4216static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4217 unsigned int n)
1da177e4
LT		 4218{
4219 unsigned int i;
4220
3eafe507
SG		 4221 for (i = 0; i < n; i++) {
4222 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 4223 struct ring_info *tx_skb = tp->tx_skb + entry;
4224 unsigned int len = tx_skb->len;
4225
4226 if (len) {
4227 struct sk_buff *skb = tx_skb->skb;
4228
48addcc9 4229 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 4230 tp->TxDescArray + entry);
4231 if (skb) {
cac4b22f 4232 tp->dev->stats.tx_dropped++;
1da177e4
LT		 4233 dev_kfree_skb(skb);
4234 tx_skb->skb = NULL;
4235 }
1da177e4
LT		 4236 }
4237 }
3eafe507
SG		 4238}
4239
4240static void rtl8169_tx_clear(struct rtl8169_private *tp)
4241{
4242 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 4243 tp->cur_tx = tp->dirty_tx = 0;
4244}
4245
c4028958 4246static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 4247{
4248 struct rtl8169_private *tp = netdev_priv(dev);
4249
c4028958 4250 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 4251 schedule_delayed_work(&tp->task, 4);
4252}
4253
4254static void rtl8169_wait_for_quiescence(struct net_device *dev)
4255{
4256 struct rtl8169_private *tp = netdev_priv(dev);
4257 void __iomem *ioaddr = tp->mmio_addr;
4258
4259 synchronize_irq(dev->irq);
4260
4261 /* Wait for any pending NAPI task to complete */
bea3348e 4262 napi_disable(&tp->napi);
1da177e4
LT		 4263
4264 rtl8169_irq_mask_and_ack(ioaddr);
4265
d1d08d12
DM		 4266 tp->intr_mask = 0xffff;
4267 RTL_W16(IntrMask, tp->intr_event);
bea3348e 4268 napi_enable(&tp->napi);
1da177e4
LT		 4269}
4270
c4028958 4271static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 4272{
c4028958
DH		 4273 struct rtl8169_private *tp =
4274 container_of(work, struct rtl8169_private, task.work);
4275 struct net_device *dev = tp->dev;
1da177e4
LT		 4276 int ret;
4277
eb2a021c
FR		 4278 rtnl_lock();
4279
4280 if (!netif_running(dev))
4281 goto out_unlock;
4282
4283 rtl8169_wait_for_quiescence(dev);
4284 rtl8169_close(dev);
1da177e4
LT		 4285
4286 ret = rtl8169_open(dev);
4287 if (unlikely(ret < 0)) {
bf82c189
JP		 4288 if (net_ratelimit())
4289 netif_err(tp, drv, dev,
4290 "reinit failure (status = %d). Rescheduling\n",
4291 ret);
1da177e4
LT		 4292 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4293 }
eb2a021c
FR		 4294
4295out_unlock:
4296 rtnl_unlock();
1da177e4
LT		 4297}
4298
c4028958 4299static void rtl8169_reset_task(struct work_struct *work)
1da177e4 4300{
c4028958
DH		 4301 struct rtl8169_private *tp =
4302 container_of(work, struct rtl8169_private, task.work);
4303 struct net_device *dev = tp->dev;
1da177e4 4304
eb2a021c
FR		 4305 rtnl_lock();
4306
1da177e4 4307 if (!netif_running(dev))
eb2a021c 4308 goto out_unlock;
1da177e4
LT		 4309
4310 rtl8169_wait_for_quiescence(dev);
4311
bea3348e 4312 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 4313 rtl8169_tx_clear(tp);
4314
4315 if (tp->dirty_rx == tp->cur_rx) {
4316 rtl8169_init_ring_indexes(tp);
07ce4064 4317 rtl_hw_start(dev);
1da177e4 4318 netif_wake_queue(dev);
cebf8cc7 4319 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 4320 } else {
bf82c189
JP		 4321 if (net_ratelimit())
4322 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
1da177e4
LT		 4323 rtl8169_schedule_work(dev, rtl8169_reset_task);
4324 }
eb2a021c
FR		 4325
4326out_unlock:
4327 rtnl_unlock();
1da177e4
LT		 4328}
4329
4330static void rtl8169_tx_timeout(struct net_device *dev)
4331{
4332 struct rtl8169_private *tp = netdev_priv(dev);
4333
e6de30d6 4334 rtl8169_hw_reset(tp);
1da177e4
LT		 4335
4336 /* Let's wait a bit while any (async) irq lands on */
4337 rtl8169_schedule_work(dev, rtl8169_reset_task);
4338}
4339
4340static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4341 u32 opts1)
4342{
4343 struct skb_shared_info *info = skb_shinfo(skb);
4344 unsigned int cur_frag, entry;
a6343afb 4345 struct TxDesc * uninitialized_var(txd);
48addcc9 4346 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4347
4348 entry = tp->cur_tx;
4349 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4350 skb_frag_t *frag = info->frags + cur_frag;
4351 dma_addr_t mapping;
4352 u32 status, len;
4353 void *addr;
4354
4355 entry = (entry + 1) % NUM_TX_DESC;
4356
4357 txd = tp->TxDescArray + entry;
4358 len = frag->size;
4359 addr = ((void *) page_address(frag->page)) + frag->page_offset;
48addcc9 4360 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 4361 if (unlikely(dma_mapping_error(d, mapping))) {
4362 if (net_ratelimit())
4363 netif_err(tp, drv, tp->dev,
4364 "Failed to map TX fragments DMA!\n");
3eafe507 4365 goto err_out;
d827d86b 4366 }
1da177e4
LT		 4367
4368 /* anti gcc 2.95.3 bugware (sic) */
4369 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4370
4371 txd->opts1 = cpu_to_le32(status);
4372 txd->addr = cpu_to_le64(mapping);
4373
4374 tp->tx_skb[entry].len = len;
4375 }
4376
4377 if (cur_frag) {
4378 tp->tx_skb[entry].skb = skb;
4379 txd->opts1 |= cpu_to_le32(LastFrag);
4380 }
4381
4382 return cur_frag;
3eafe507
SG		 4383
4384err_out:
4385 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4386 return -EIO;
1da177e4
LT		 4387}
4388
4389static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4390{
4391 if (dev->features & NETIF_F_TSO) {
7967168c 4392 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 4393
4394 if (mss)
4395 return LargeSend | ((mss & MSSMask) << MSSShift);
4396 }
84fa7933 4397 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 4398 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 4399
4400 if (ip->protocol == IPPROTO_TCP)
4401 return IPCS | TCPCS;
4402 else if (ip->protocol == IPPROTO_UDP)
4403 return IPCS | UDPCS;
4404 WARN_ON(1); /* we need a WARN() */
4405 }
4406 return 0;
4407}
4408
61357325
SH		 4409static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4410 struct net_device *dev)
1da177e4
LT		 4411{
4412 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 4413 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 4414 struct TxDesc *txd = tp->TxDescArray + entry;
4415 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 4416 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4417 dma_addr_t mapping;
4418 u32 status, len;
4419 u32 opts1;
3eafe507 4420 int frags;
5b0384f4 4421
1da177e4 4422 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 4423 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 4424 goto err_stop_0;
1da177e4
LT		 4425 }
4426
4427 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 4428 goto err_stop_0;
4429
4430 len = skb_headlen(skb);
48addcc9 4431 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 4432 if (unlikely(dma_mapping_error(d, mapping))) {
4433 if (net_ratelimit())
4434 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 4435 goto err_dma_0;
d827d86b 4436 }
3eafe507
SG		 4437
4438 tp->tx_skb[entry].len = len;
4439 txd->addr = cpu_to_le64(mapping);
4440 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
1da177e4
LT		 4441
4442 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4443
4444 frags = rtl8169_xmit_frags(tp, skb, opts1);
3eafe507
SG		 4445 if (frags < 0)
4446 goto err_dma_1;
4447 else if (frags)
1da177e4 4448 opts1 |= FirstFrag;
3eafe507 4449 else {
1da177e4
LT		 4450 opts1 |= FirstFrag | LastFrag;
4451 tp->tx_skb[entry].skb = skb;
4452 }
4453
1da177e4
LT		 4454 wmb();
4455
4456 /* anti gcc 2.95.3 bugware (sic) */
4457 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4458 txd->opts1 = cpu_to_le32(status);
4459
1da177e4
LT		 4460 tp->cur_tx += frags + 1;
4461
4c020a96 4462 wmb();
1da177e4 4463
275391a4 4464 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 4465
4466 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4467 netif_stop_queue(dev);
4468 smp_rmb();
4469 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4470 netif_wake_queue(dev);
4471 }
4472
61357325 4473 return NETDEV_TX_OK;
1da177e4 4474
3eafe507 4475err_dma_1:
48addcc9 4476 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 4477err_dma_0:
4478 dev_kfree_skb(skb);
4479 dev->stats.tx_dropped++;
4480 return NETDEV_TX_OK;
4481
4482err_stop_0:
1da177e4 4483 netif_stop_queue(dev);
cebf8cc7 4484 dev->stats.tx_dropped++;
61357325 4485 return NETDEV_TX_BUSY;
1da177e4
LT		 4486}
4487
4488static void rtl8169_pcierr_interrupt(struct net_device *dev)
4489{
4490 struct rtl8169_private *tp = netdev_priv(dev);
4491 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 4492 u16 pci_status, pci_cmd;
4493
4494 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4495 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4496
bf82c189
JP		 4497 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4498 pci_cmd, pci_status);
1da177e4
LT		 4499
4500 /*
4501 * The recovery sequence below admits a very elaborated explanation:
4502 * - it seems to work;
d03902b8
FR		 4503 * - I did not see what else could be done;
4504 * - it makes iop3xx happy.
1da177e4
LT		 4505 *
4506 * Feel free to adjust to your needs.
4507 */
a27993f3 4508 if (pdev->broken_parity_status)
d03902b8
FR		 4509 pci_cmd &= ~PCI_COMMAND_PARITY;
4510 else
4511 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4512
4513 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 4514
4515 pci_write_config_word(pdev, PCI_STATUS,
4516 pci_status & (PCI_STATUS_DETECTED_PARITY |
4517 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4518 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4519
4520 /* The infamous DAC f*ckup only happens at boot time */
4521 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 4522 void __iomem *ioaddr = tp->mmio_addr;
4523
bf82c189 4524 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 4525 tp->cp_cmd &= ~PCIDAC;
4526 RTL_W16(CPlusCmd, tp->cp_cmd);
4527 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 4528 }
4529
e6de30d6 4530 rtl8169_hw_reset(tp);
d03902b8
FR		 4531
4532 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 4533}
4534
07d3f51f
FR		 4535static void rtl8169_tx_interrupt(struct net_device *dev,
4536 struct rtl8169_private *tp,
4537 void __iomem *ioaddr)
1da177e4
LT		 4538{
4539 unsigned int dirty_tx, tx_left;
4540
1da177e4
LT		 4541 dirty_tx = tp->dirty_tx;
4542 smp_rmb();
4543 tx_left = tp->cur_tx - dirty_tx;
4544
4545 while (tx_left > 0) {
4546 unsigned int entry = dirty_tx % NUM_TX_DESC;
4547 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 4548 u32 status;
4549
4550 rmb();
4551 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4552 if (status & DescOwn)
4553 break;
4554
48addcc9
SG		 4555 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4556 tp->TxDescArray + entry);
1da177e4 4557 if (status & LastFrag) {
cac4b22f
SG		 4558 dev->stats.tx_packets++;
4559 dev->stats.tx_bytes += tx_skb->skb->len;
87433bfc 4560 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 4561 tx_skb->skb = NULL;
4562 }
4563 dirty_tx++;
4564 tx_left--;
4565 }
4566
4567 if (tp->dirty_tx != dirty_tx) {
4568 tp->dirty_tx = dirty_tx;
4569 smp_wmb();
4570 if (netif_queue_stopped(dev) &&
4571 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4572 netif_wake_queue(dev);
4573 }
d78ae2dc
FR		 4574 /*
4575 * 8168 hack: TxPoll requests are lost when the Tx packets are
4576 * too close. Let's kick an extra TxPoll request when a burst
4577 * of start_xmit activity is detected (if it is not detected,
4578 * it is slow enough). -- FR
4579 */
4580 smp_rmb();
4581 if (tp->cur_tx != dirty_tx)
4582 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 4583 }
4584}
4585
126fa4b9
FR		 4586static inline int rtl8169_fragmented_frame(u32 status)
4587{
4588 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4589}
4590
adea1ac7 4591static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 4592{
1da177e4
LT		 4593 u32 status = opts1 & RxProtoMask;
4594
4595 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 4596 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 4597 skb->ip_summed = CHECKSUM_UNNECESSARY;
4598 else
bc8acf2c 4599 skb_checksum_none_assert(skb);
1da177e4
LT		 4600}
4601
6f0333b8
ED		 4602static struct sk_buff *rtl8169_try_rx_copy(void *data,
4603 struct rtl8169_private *tp,
4604 int pkt_size,
4605 dma_addr_t addr)
1da177e4 4606{
b449655f 4607 struct sk_buff *skb;
48addcc9 4608 struct device *d = &tp->pci_dev->dev;
b449655f 4609
6f0333b8 4610 data = rtl8169_align(data);
48addcc9 4611 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 4612 prefetch(data);
4613 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4614 if (skb)
4615 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 4616 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4617
6f0333b8 4618 return skb;
1da177e4
LT		 4619}
4620
630b943c
ED		 4621/*
4622 * Warning : rtl8169_rx_interrupt() might be called :
4623 * 1) from NAPI (softirq) context
4624 * (polling = 1 : we should call netif_receive_skb())
4625 * 2) from process context (rtl8169_reset_task())
4626 * (polling = 0 : we must call netif_rx() instead)
4627 */
07d3f51f
FR		 4628static int rtl8169_rx_interrupt(struct net_device *dev,
4629 struct rtl8169_private *tp,
bea3348e 4630 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 4631{
4632 unsigned int cur_rx, rx_left;
6f0333b8 4633 unsigned int count;
630b943c 4634 int polling = (budget != ~(u32)0) ? 1 : 0;
1da177e4 4635
1da177e4
LT		 4636 cur_rx = tp->cur_rx;
4637 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 4638 rx_left = min(rx_left, budget);
1da177e4 4639
4dcb7d33 4640 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 4641 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 4642 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 4643 u32 status;
4644
4645 rmb();
126fa4b9 4646 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 4647
4648 if (status & DescOwn)
4649 break;
4dcb7d33 4650 if (unlikely(status & RxRES)) {
bf82c189
JP		 4651 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4652 status);
cebf8cc7 4653 dev->stats.rx_errors++;
1da177e4 4654 if (status & (RxRWT | RxRUNT))
cebf8cc7 4655 dev->stats.rx_length_errors++;
1da177e4 4656 if (status & RxCRC)
cebf8cc7 4657 dev->stats.rx_crc_errors++;
9dccf611
FR		 4658 if (status & RxFOVF) {
4659 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 4660 dev->stats.rx_fifo_errors++;
9dccf611 4661 }
6f0333b8 4662 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 4663 } else {
6f0333b8 4664 struct sk_buff *skb;
b449655f 4665 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 4666 int pkt_size = (status & 0x00001FFF) - 4;
1da177e4 4667
126fa4b9
FR		 4668 /*
4669 * The driver does not support incoming fragmented
4670 * frames. They are seen as a symptom of over-mtu
4671 * sized frames.
4672 */
4673 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 4674 dev->stats.rx_dropped++;
4675 dev->stats.rx_length_errors++;
6f0333b8 4676 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 4677 continue;
126fa4b9
FR		 4678 }
4679
6f0333b8
ED		 4680 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4681 tp, pkt_size, addr);
4682 rtl8169_mark_to_asic(desc, rx_buf_sz);
4683 if (!skb) {
4684 dev->stats.rx_dropped++;
4685 continue;
1da177e4
LT		 4686 }
4687
adea1ac7 4688 rtl8169_rx_csum(skb, status);
1da177e4
LT		 4689 skb_put(skb, pkt_size);
4690 skb->protocol = eth_type_trans(skb, dev);
4691
630b943c
ED		 4692 if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) {
4693 if (likely(polling))
2edae08e 4694 napi_gro_receive(&tp->napi, skb);
630b943c
ED		 4695 else
4696 netif_rx(skb);
4697 }
1da177e4 4698
cebf8cc7
FR		 4699 dev->stats.rx_bytes += pkt_size;
4700 dev->stats.rx_packets++;
1da177e4 4701 }
6dccd16b
FR		 4702
4703 /* Work around for AMD plateform. */
95e0918d 4704 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 4705 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4706 desc->opts2 = 0;
4707 cur_rx++;
4708 }
1da177e4
LT		 4709 }
4710
4711 count = cur_rx - tp->cur_rx;
4712 tp->cur_rx = cur_rx;
4713
6f0333b8 4714 tp->dirty_rx += count;
1da177e4
LT		 4715
4716 return count;
4717}
4718
07d3f51f 4719static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 4720{
07d3f51f 4721 struct net_device *dev = dev_instance;
1da177e4 4722 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4723 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 4724 int handled = 0;
865c652d 4725 int status;
1da177e4 4726
f11a377b
DD		 4727 /* loop handling interrupts until we have no new ones or
4728 * we hit a invalid/hotplug case.
4729 */
865c652d 4730 status = RTL_R16(IntrStatus);
f11a377b
DD		 4731 while (status && status != 0xffff) {
4732 handled = 1;
1da177e4 4733
f11a377b
DD		 4734 /* Handle all of the error cases first. These will reset
4735 * the chip, so just exit the loop.
4736 */
4737 if (unlikely(!netif_running(dev))) {
4738 rtl8169_asic_down(ioaddr);
4739 break;
4740 }
1da177e4 4741
1519e57f
FR		 4742 if (unlikely(status & RxFIFOOver)) {
4743 switch (tp->mac_version) {
4744 /* Work around for rx fifo overflow */
4745 case RTL_GIGA_MAC_VER_11:
4746 case RTL_GIGA_MAC_VER_22:
4747 case RTL_GIGA_MAC_VER_26:
4748 netif_stop_queue(dev);
4749 rtl8169_tx_timeout(dev);
4750 goto done;
f60ac8e7
FR		 4751 /* Testers needed. */
4752 case RTL_GIGA_MAC_VER_17:
4753 case RTL_GIGA_MAC_VER_19:
4754 case RTL_GIGA_MAC_VER_20:
4755 case RTL_GIGA_MAC_VER_21:
4756 case RTL_GIGA_MAC_VER_23:
4757 case RTL_GIGA_MAC_VER_24:
4758 case RTL_GIGA_MAC_VER_27:
4759 case RTL_GIGA_MAC_VER_28:
1519e57f
FR		 4760 /* Experimental science. Pktgen proof. */
4761 case RTL_GIGA_MAC_VER_12:
4762 case RTL_GIGA_MAC_VER_25:
4763 if (status == RxFIFOOver)
4764 goto done;
4765 break;
4766 default:
4767 break;
4768 }
f11a377b 4769 }
1da177e4 4770
f11a377b
DD		 4771 if (unlikely(status & SYSErr)) {
4772 rtl8169_pcierr_interrupt(dev);
4773 break;
4774 }
1da177e4 4775
f11a377b 4776 if (status & LinkChg)
e4fbce74 4777 __rtl8169_check_link_status(dev, tp, ioaddr, true);
0e485150 4778
f11a377b
DD		 4779 /* We need to see the lastest version of tp->intr_mask to
4780 * avoid ignoring an MSI interrupt and having to wait for
4781 * another event which may never come.
4782 */
4783 smp_rmb();
4784 if (status & tp->intr_mask & tp->napi_event) {
4785 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4786 tp->intr_mask = ~tp->napi_event;
4787
4788 if (likely(napi_schedule_prep(&tp->napi)))
4789 __napi_schedule(&tp->napi);
bf82c189
JP		 4790 else
4791 netif_info(tp, intr, dev,
4792 "interrupt %04x in poll\n", status);
f11a377b 4793 }
1da177e4 4794
f11a377b
DD		 4795 /* We only get a new MSI interrupt when all active irq
4796 * sources on the chip have been acknowledged. So, ack
4797 * everything we've seen and check if new sources have become
4798 * active to avoid blocking all interrupts from the chip.
4799 */
4800 RTL_W16(IntrStatus,
4801 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4802 status = RTL_R16(IntrStatus);
865c652d 4803 }
1519e57f 4804done:
1da177e4
LT		 4805 return IRQ_RETVAL(handled);
4806}
4807
bea3348e 4808static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 4809{
bea3348e
SH		 4810 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4811 struct net_device *dev = tp->dev;
1da177e4 4812 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 4813 int work_done;
1da177e4 4814
bea3348e 4815 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 4816 rtl8169_tx_interrupt(dev, tp, ioaddr);
4817
bea3348e 4818 if (work_done < budget) {
288379f0 4819 napi_complete(napi);
f11a377b
DD		 4820
4821 /* We need for force the visibility of tp->intr_mask
4822 * for other CPUs, as we can loose an MSI interrupt
4823 * and potentially wait for a retransmit timeout if we don't.
4824 * The posted write to IntrMask is safe, as it will
4825 * eventually make it to the chip and we won't loose anything
4826 * until it does.
1da177e4 4827 */
f11a377b 4828 tp->intr_mask = 0xffff;
4c020a96 4829 wmb();
0e485150 4830 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4831 }
4832
bea3348e 4833 return work_done;
1da177e4 4834}
1da177e4 4835
523a6094
FR		 4836static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4837{
4838 struct rtl8169_private *tp = netdev_priv(dev);
4839
4840 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4841 return;
4842
4843 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4844 RTL_W32(RxMissed, 0);
4845}
4846
1da177e4
LT		 4847static void rtl8169_down(struct net_device *dev)
4848{
4849 struct rtl8169_private *tp = netdev_priv(dev);
4850 void __iomem *ioaddr = tp->mmio_addr;
1da177e4
LT		 4851
4852 rtl8169_delete_timer(dev);
4853
4854 netif_stop_queue(dev);
4855
93dd79e8 4856 napi_disable(&tp->napi);
93dd79e8 4857
1da177e4
LT		 4858 spin_lock_irq(&tp->lock);
4859
4860 rtl8169_asic_down(ioaddr);
323bb685
SG		 4861 /*
4862 * At this point device interrupts can not be enabled in any function,
4863 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
4864 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
4865 */
523a6094 4866 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4867
4868 spin_unlock_irq(&tp->lock);
4869
4870 synchronize_irq(dev->irq);
4871
1da177e4 4872 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 4873 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4 4874
1da177e4
LT		 4875 rtl8169_tx_clear(tp);
4876
4877 rtl8169_rx_clear(tp);
065c27c1 4878
4879 rtl_pll_power_down(tp);
1da177e4
LT		 4880}
4881
4882static int rtl8169_close(struct net_device *dev)
4883{
4884 struct rtl8169_private *tp = netdev_priv(dev);
4885 struct pci_dev *pdev = tp->pci_dev;
4886
e1759441
RW		 4887 pm_runtime_get_sync(&pdev->dev);
4888
355423d0
IV		 4889 /* update counters before going down */
4890 rtl8169_update_counters(dev);
4891
1da177e4
LT		 4892 rtl8169_down(dev);
4893
4894 free_irq(dev->irq, dev);
4895
82553bb6
SG		 4896 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4897 tp->RxPhyAddr);
4898 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4899 tp->TxPhyAddr);
1da177e4
LT		 4900 tp->TxDescArray = NULL;
4901 tp->RxDescArray = NULL;
4902
e1759441
RW		 4903 pm_runtime_put_sync(&pdev->dev);
4904
1da177e4
LT		 4905 return 0;
4906}
4907
07ce4064 4908static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 4909{
4910 struct rtl8169_private *tp = netdev_priv(dev);
4911 void __iomem *ioaddr = tp->mmio_addr;
4912 unsigned long flags;
4913 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 4914 int rx_mode;
1da177e4
LT		 4915 u32 tmp = 0;
4916
4917 if (dev->flags & IFF_PROMISC) {
4918 /* Unconditionally log net taps. */
bf82c189 4919 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 4920 rx_mode =
4921 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4922 AcceptAllPhys;
4923 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 4924 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 4925 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 4926 /* Too many to filter perfectly -- accept all multicasts. */
4927 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4928 mc_filter[1] = mc_filter[0] = 0xffffffff;
4929 } else {
22bedad3 4930 struct netdev_hw_addr *ha;
07d3f51f 4931
1da177e4
LT		 4932 rx_mode = AcceptBroadcast | AcceptMyPhys;
4933 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 4934 netdev_for_each_mc_addr(ha, dev) {
4935 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 4936 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4937 rx_mode |= AcceptMulticast;
4938 }
4939 }
4940
4941 spin_lock_irqsave(&tp->lock, flags);
4942
4943 tmp = rtl8169_rx_config | rx_mode |
4944 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4945
f887cce8 4946 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 4947 u32 data = mc_filter[0];
4948
4949 mc_filter[0] = swab32(mc_filter[1]);
4950 mc_filter[1] = swab32(data);
bcf0bf90
FR		 4951 }
4952
1da177e4 4953 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 4954 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 4955
57a9f236
FR		 4956 RTL_W32(RxConfig, tmp);
4957
1da177e4
LT		 4958 spin_unlock_irqrestore(&tp->lock, flags);
4959}
4960
4961/**
4962 * rtl8169_get_stats - Get rtl8169 read/write statistics
4963 * @dev: The Ethernet Device to get statistics for
4964 *
4965 * Get TX/RX statistics for rtl8169
4966 */
4967static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4968{
4969 struct rtl8169_private *tp = netdev_priv(dev);
4970 void __iomem *ioaddr = tp->mmio_addr;
4971 unsigned long flags;
4972
4973 if (netif_running(dev)) {
4974 spin_lock_irqsave(&tp->lock, flags);
523a6094 4975 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4976 spin_unlock_irqrestore(&tp->lock, flags);
4977 }
5b0384f4 4978
cebf8cc7 4979 return &dev->stats;
1da177e4
LT		 4980}
4981
861ab440 4982static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 4983{
065c27c1 4984 struct rtl8169_private *tp = netdev_priv(dev);
4985
5d06a99f 4986 if (!netif_running(dev))
861ab440 4987 return;
5d06a99f 4988
065c27c1 4989 rtl_pll_power_down(tp);
4990
5d06a99f
FR		 4991 netif_device_detach(dev);
4992 netif_stop_queue(dev);
861ab440
RW		 4993}
4994
4995#ifdef CONFIG_PM
4996
4997static int rtl8169_suspend(struct device *device)
4998{
4999 struct pci_dev *pdev = to_pci_dev(device);
5000 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 5001
861ab440 5002 rtl8169_net_suspend(dev);
1371fa6d 5003
5d06a99f
FR		 5004 return 0;
5005}
5006
e1759441
RW		 5007static void __rtl8169_resume(struct net_device *dev)
5008{
065c27c1 5009 struct rtl8169_private *tp = netdev_priv(dev);
5010
e1759441 5011 netif_device_attach(dev);
065c27c1 5012
5013 rtl_pll_power_up(tp);
5014
e1759441
RW		 5015 rtl8169_schedule_work(dev, rtl8169_reset_task);
5016}
5017
861ab440 5018static int rtl8169_resume(struct device *device)
5d06a99f 5019{
861ab440 5020 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 5021 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 5022 struct rtl8169_private *tp = netdev_priv(dev);
5023
5024 rtl8169_init_phy(dev, tp);
5d06a99f 5025
e1759441
RW		 5026 if (netif_running(dev))
5027 __rtl8169_resume(dev);
5d06a99f 5028
e1759441
RW		 5029 return 0;
5030}
5031
5032static int rtl8169_runtime_suspend(struct device *device)
5033{
5034 struct pci_dev *pdev = to_pci_dev(device);
5035 struct net_device *dev = pci_get_drvdata(pdev);
5036 struct rtl8169_private *tp = netdev_priv(dev);
5037
5038 if (!tp->TxDescArray)
5039 return 0;
5040
5041 spin_lock_irq(&tp->lock);
5042 tp->saved_wolopts = __rtl8169_get_wol(tp);
5043 __rtl8169_set_wol(tp, WAKE_ANY);
5044 spin_unlock_irq(&tp->lock);
5045
5046 rtl8169_net_suspend(dev);
5047
5048 return 0;
5049}
5050
5051static int rtl8169_runtime_resume(struct device *device)
5052{
5053 struct pci_dev *pdev = to_pci_dev(device);
5054 struct net_device *dev = pci_get_drvdata(pdev);
5055 struct rtl8169_private *tp = netdev_priv(dev);
5056
5057 if (!tp->TxDescArray)
5058 return 0;
5059
5060 spin_lock_irq(&tp->lock);
5061 __rtl8169_set_wol(tp, tp->saved_wolopts);
5062 tp->saved_wolopts = 0;
5063 spin_unlock_irq(&tp->lock);
5064
fccec10b
SG		 5065 rtl8169_init_phy(dev, tp);
5066
e1759441 5067 __rtl8169_resume(dev);
5d06a99f 5068
5d06a99f
FR		 5069 return 0;
5070}
5071
e1759441
RW		 5072static int rtl8169_runtime_idle(struct device *device)
5073{
5074 struct pci_dev *pdev = to_pci_dev(device);
5075 struct net_device *dev = pci_get_drvdata(pdev);
5076 struct rtl8169_private *tp = netdev_priv(dev);
5077
e4fbce74 5078 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 5079}
5080
47145210 5081static const struct dev_pm_ops rtl8169_pm_ops = {
861ab440
RW		 5082 .suspend = rtl8169_suspend,
5083 .resume = rtl8169_resume,
5084 .freeze = rtl8169_suspend,
5085 .thaw = rtl8169_resume,
5086 .poweroff = rtl8169_suspend,
5087 .restore = rtl8169_resume,
e1759441
RW		 5088 .runtime_suspend = rtl8169_runtime_suspend,
5089 .runtime_resume = rtl8169_runtime_resume,
5090 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 5091};
5092
5093#define RTL8169_PM_OPS (&rtl8169_pm_ops)
5094
5095#else /* !CONFIG_PM */
5096
5097#define RTL8169_PM_OPS NULL
5098
5099#endif /* !CONFIG_PM */
5100
1765f95d
FR		 5101static void rtl_shutdown(struct pci_dev *pdev)
5102{
861ab440 5103 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 5104 struct rtl8169_private *tp = netdev_priv(dev);
5105 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 5106
5107 rtl8169_net_suspend(dev);
1765f95d 5108
cc098dc7
IV		 5109 /* restore original MAC address */
5110 rtl_rar_set(tp, dev->perm_addr);
5111
4bb3f522 5112 spin_lock_irq(&tp->lock);
5113
5114 rtl8169_asic_down(ioaddr);
5115
5116 spin_unlock_irq(&tp->lock);
5117
861ab440 5118 if (system_state == SYSTEM_POWER_OFF) {
ca52efd5 5119 /* WoL fails with some 8168 when the receiver is disabled. */
5120 if (tp->features & RTL_FEATURE_WOL) {
5121 pci_clear_master(pdev);
5122
5123 RTL_W8(ChipCmd, CmdRxEnb);
5124 /* PCI commit */
5125 RTL_R8(ChipCmd);
5126 }
5127
861ab440
RW		 5128 pci_wake_from_d3(pdev, true);
5129 pci_set_power_state(pdev, PCI_D3hot);
5130 }
5131}
5d06a99f 5132
1da177e4
LT		 5133static struct pci_driver rtl8169_pci_driver = {
5134 .name = MODULENAME,
5135 .id_table = rtl8169_pci_tbl,
5136 .probe = rtl8169_init_one,
5137 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 5138 .shutdown = rtl_shutdown,
861ab440 5139 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 5140};
5141
07d3f51f 5142static int __init rtl8169_init_module(void)
1da177e4 5143{
29917620 5144 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 5145}
5146
07d3f51f 5147static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 5148{
5149 pci_unregister_driver(&rtl8169_pci_driver);
5150}
5151
5152module_init(rtl8169_init_module);
5153module_exit(rtl8169_cleanup_module);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git