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[thirdparty/kernel/stable.git] / drivers / net / r8169.c
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1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
a6b7a407 25#include <linux/interrupt.h>
1da177e4 26#include <linux/dma-mapping.h>
e1759441 27#include <linux/pm_runtime.h>
bca03d5f 28#include <linux/firmware.h>
ba04c7c9 29#include <linux/pci-aspm.h>
70c71606 30#include <linux/prefetch.h>
1da177e4 31
99f252b0 32#include <asm/system.h>
1da177e4
LT		 33#include <asm/io.h>
34#include <asm/irq.h>
35
865c652d 36#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 37#define MODULENAME "r8169"
38#define PFX MODULENAME ": "
39
bca03d5f 40#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 42#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 44#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
5a5e4443 45#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
bca03d5f 46
1da177e4
LT		 47#ifdef RTL8169_DEBUG
48#define assert(expr) \
5b0384f4
FR		 49 if (!(expr)) { \
50 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 51 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 52 }
06fa7358
JP		 53#define dprintk(fmt, args...) \
54 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 55#else
56#define assert(expr) do {} while (0)
57#define dprintk(fmt, args...) do {} while (0)
58#endif /* RTL8169_DEBUG */
59
b57b7e5a 60#define R8169_MSG_DEFAULT \
f0e837d9 61 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 62
1da177e4
LT		 63#define TX_BUFFS_AVAIL(tp) \
64 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
65
1da177e4
LT		 66/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
67 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 68static const int multicast_filter_limit = 32;
1da177e4
LT		 69
70/* MAC address length */
71#define MAC_ADDR_LEN 6
72
9c14ceaf 73#define MAX_READ_REQUEST_SHIFT 12
1da177e4 74#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
1da177e4
LT		 75#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
76#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
77
78#define R8169_REGS_SIZE 256
79#define R8169_NAPI_WEIGHT 64
80#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
81#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
82#define RX_BUF_SIZE 1536 /* Rx Buffer size */
83#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
84#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
85
86#define RTL8169_TX_TIMEOUT (6*HZ)
87#define RTL8169_PHY_TIMEOUT (10*HZ)
88
ea8dbdd1 89#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
90#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 91#define RTL_EEPROM_SIG_ADDR 0x0000
92
1da177e4
LT		 93/* write/read MMIO register */
94#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
95#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
96#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
97#define RTL_R8(reg) readb (ioaddr + (reg))
98#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 99#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 100
101enum mac_version {
85bffe6c
FR		 102 RTL_GIGA_MAC_VER_01 = 0,
103 RTL_GIGA_MAC_VER_02,
104 RTL_GIGA_MAC_VER_03,
105 RTL_GIGA_MAC_VER_04,
106 RTL_GIGA_MAC_VER_05,
107 RTL_GIGA_MAC_VER_06,
108 RTL_GIGA_MAC_VER_07,
109 RTL_GIGA_MAC_VER_08,
110 RTL_GIGA_MAC_VER_09,
111 RTL_GIGA_MAC_VER_10,
112 RTL_GIGA_MAC_VER_11,
113 RTL_GIGA_MAC_VER_12,
114 RTL_GIGA_MAC_VER_13,
115 RTL_GIGA_MAC_VER_14,
116 RTL_GIGA_MAC_VER_15,
117 RTL_GIGA_MAC_VER_16,
118 RTL_GIGA_MAC_VER_17,
119 RTL_GIGA_MAC_VER_18,
120 RTL_GIGA_MAC_VER_19,
121 RTL_GIGA_MAC_VER_20,
122 RTL_GIGA_MAC_VER_21,
123 RTL_GIGA_MAC_VER_22,
124 RTL_GIGA_MAC_VER_23,
125 RTL_GIGA_MAC_VER_24,
126 RTL_GIGA_MAC_VER_25,
127 RTL_GIGA_MAC_VER_26,
128 RTL_GIGA_MAC_VER_27,
129 RTL_GIGA_MAC_VER_28,
130 RTL_GIGA_MAC_VER_29,
131 RTL_GIGA_MAC_VER_30,
132 RTL_GIGA_MAC_VER_31,
133 RTL_GIGA_MAC_VER_32,
134 RTL_GIGA_MAC_VER_33,
70090424 135 RTL_GIGA_MAC_VER_34,
85bffe6c 136 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 137};
138
2b7b4318
FR		 139enum rtl_tx_desc_version {
140 RTL_TD_0 = 0,
141 RTL_TD_1 = 1,
142};
143
85bffe6c
FR		 144#define _R(NAME,TD,FW) \
145 { .name = NAME, .txd_version = TD, .fw_name = FW }
1da177e4 146
3c6bee1d 147static const struct {
1da177e4 148 const char *name;
2b7b4318 149 enum rtl_tx_desc_version txd_version;
953a12cc 150 const char *fw_name;
85bffe6c
FR		 151} rtl_chip_infos[] = {
152 /* PCI devices. */
153 [RTL_GIGA_MAC_VER_01] =
154 _R("RTL8169", RTL_TD_0, NULL),
155 [RTL_GIGA_MAC_VER_02] =
156 _R("RTL8169s", RTL_TD_0, NULL),
157 [RTL_GIGA_MAC_VER_03] =
158 _R("RTL8110s", RTL_TD_0, NULL),
159 [RTL_GIGA_MAC_VER_04] =
160 _R("RTL8169sb/8110sb", RTL_TD_0, NULL),
161 [RTL_GIGA_MAC_VER_05] =
162 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
163 [RTL_GIGA_MAC_VER_06] =
164 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
165 /* PCI-E devices. */
166 [RTL_GIGA_MAC_VER_07] =
167 _R("RTL8102e", RTL_TD_1, NULL),
168 [RTL_GIGA_MAC_VER_08] =
169 _R("RTL8102e", RTL_TD_1, NULL),
170 [RTL_GIGA_MAC_VER_09] =
171 _R("RTL8102e", RTL_TD_1, NULL),
172 [RTL_GIGA_MAC_VER_10] =
173 _R("RTL8101e", RTL_TD_0, NULL),
174 [RTL_GIGA_MAC_VER_11] =
175 _R("RTL8168b/8111b", RTL_TD_0, NULL),
176 [RTL_GIGA_MAC_VER_12] =
177 _R("RTL8168b/8111b", RTL_TD_0, NULL),
178 [RTL_GIGA_MAC_VER_13] =
179 _R("RTL8101e", RTL_TD_0, NULL),
180 [RTL_GIGA_MAC_VER_14] =
181 _R("RTL8100e", RTL_TD_0, NULL),
182 [RTL_GIGA_MAC_VER_15] =
183 _R("RTL8100e", RTL_TD_0, NULL),
184 [RTL_GIGA_MAC_VER_16] =
185 _R("RTL8101e", RTL_TD_0, NULL),
186 [RTL_GIGA_MAC_VER_17] =
187 _R("RTL8168b/8111b", RTL_TD_0, NULL),
188 [RTL_GIGA_MAC_VER_18] =
189 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
190 [RTL_GIGA_MAC_VER_19] =
191 _R("RTL8168c/8111c", RTL_TD_1, NULL),
192 [RTL_GIGA_MAC_VER_20] =
193 _R("RTL8168c/8111c", RTL_TD_1, NULL),
194 [RTL_GIGA_MAC_VER_21] =
195 _R("RTL8168c/8111c", RTL_TD_1, NULL),
196 [RTL_GIGA_MAC_VER_22] =
197 _R("RTL8168c/8111c", RTL_TD_1, NULL),
198 [RTL_GIGA_MAC_VER_23] =
199 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
200 [RTL_GIGA_MAC_VER_24] =
201 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
202 [RTL_GIGA_MAC_VER_25] =
203 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1),
204 [RTL_GIGA_MAC_VER_26] =
205 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2),
206 [RTL_GIGA_MAC_VER_27] =
207 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
208 [RTL_GIGA_MAC_VER_28] =
209 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
210 [RTL_GIGA_MAC_VER_29] =
211 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
212 [RTL_GIGA_MAC_VER_30] =
213 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
214 [RTL_GIGA_MAC_VER_31] =
215 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
216 [RTL_GIGA_MAC_VER_32] =
217 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1),
218 [RTL_GIGA_MAC_VER_33] =
70090424
HW		 219 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2),
220 [RTL_GIGA_MAC_VER_34] =
221 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3)
953a12cc 222};
85bffe6c 223#undef _R
953a12cc 224
bcf0bf90
FR		 225enum cfg_version {
226 RTL_CFG_0 = 0x00,
227 RTL_CFG_1,
228 RTL_CFG_2
229};
230
07ce4064
FR		 231static void rtl_hw_start_8169(struct net_device *);
232static void rtl_hw_start_8168(struct net_device *);
233static void rtl_hw_start_8101(struct net_device *);
234
a3aa1884 235static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 236 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 237 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 238 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 239 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 240 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
241 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 242 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 243 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
244 { PCI_VENDOR_ID_LINKSYS, 0x1032,
245 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 246 { 0x0001, 0x8168,
247 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 248 {0,},
249};
250
251MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
252
6f0333b8 253static int rx_buf_sz = 16383;
4300e8c7 254static int use_dac;
b57b7e5a
SH		 255static struct {
256 u32 msg_enable;
257} debug = { -1 };
1da177e4 258
07d3f51f
FR		 259enum rtl_registers {
260 MAC0 = 0, /* Ethernet hardware address. */
773d2021 261 MAC4 = 4,
07d3f51f
FR		 262 MAR0 = 8, /* Multicast filter. */
263 CounterAddrLow = 0x10,
264 CounterAddrHigh = 0x14,
265 TxDescStartAddrLow = 0x20,
266 TxDescStartAddrHigh = 0x24,
267 TxHDescStartAddrLow = 0x28,
268 TxHDescStartAddrHigh = 0x2c,
269 FLASH = 0x30,
270 ERSR = 0x36,
271 ChipCmd = 0x37,
272 TxPoll = 0x38,
273 IntrMask = 0x3c,
274 IntrStatus = 0x3e,
4f6b00e5 275
07d3f51f 276 TxConfig = 0x40,
4f6b00e5
HW		 277#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
278#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 279
4f6b00e5
HW		 280 RxConfig = 0x44,
281#define RX128_INT_EN (1 << 15) /* 8111c and later */
282#define RX_MULTI_EN (1 << 14) /* 8111c only */
283#define RXCFG_FIFO_SHIFT 13
284 /* No threshold before first PCI xfer */
285#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
286#define RXCFG_DMA_SHIFT 8
287 /* Unlimited maximum PCI burst. */
288#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 289
07d3f51f
FR		 290 RxMissed = 0x4c,
291 Cfg9346 = 0x50,
292 Config0 = 0x51,
293 Config1 = 0x52,
294 Config2 = 0x53,
295 Config3 = 0x54,
296 Config4 = 0x55,
297 Config5 = 0x56,
298 MultiIntr = 0x5c,
299 PHYAR = 0x60,
07d3f51f
FR		 300 PHYstatus = 0x6c,
301 RxMaxSize = 0xda,
302 CPlusCmd = 0xe0,
303 IntrMitigate = 0xe2,
304 RxDescAddrLow = 0xe4,
305 RxDescAddrHigh = 0xe8,
f0298f81 306 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
307
308#define NoEarlyTx 0x3f /* Max value : no early transmit. */
309
310 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
311
312#define TxPacketMax (8064 >> 7)
313
07d3f51f
FR		 314 FuncEvent = 0xf0,
315 FuncEventMask = 0xf4,
316 FuncPresetState = 0xf8,
317 FuncForceEvent = 0xfc,
1da177e4
LT		 318};
319
f162a5d1
FR		 320enum rtl8110_registers {
321 TBICSR = 0x64,
322 TBI_ANAR = 0x68,
323 TBI_LPAR = 0x6a,
324};
325
326enum rtl8168_8101_registers {
327 CSIDR = 0x64,
328 CSIAR = 0x68,
329#define CSIAR_FLAG 0x80000000
330#define CSIAR_WRITE_CMD 0x80000000
331#define CSIAR_BYTE_ENABLE 0x0f
332#define CSIAR_BYTE_ENABLE_SHIFT 12
333#define CSIAR_ADDR_MASK 0x0fff
065c27c1 334 PMCH = 0x6f,
f162a5d1
FR		 335 EPHYAR = 0x80,
336#define EPHYAR_FLAG 0x80000000
337#define EPHYAR_WRITE_CMD 0x80000000
338#define EPHYAR_REG_MASK 0x1f
339#define EPHYAR_REG_SHIFT 16
340#define EPHYAR_DATA_MASK 0xffff
5a5e4443 341 DLLPR = 0xd0,
4f6b00e5 342#define PFM_EN (1 << 6)
f162a5d1
FR		 343 DBG_REG = 0xd1,
344#define FIX_NAK_1 (1 << 4)
345#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 346 TWSI = 0xd2,
347 MCU = 0xd3,
4f6b00e5 348#define NOW_IS_OOB (1 << 7)
5a5e4443
HW		 349#define EN_NDP (1 << 3)
350#define EN_OOB_RESET (1 << 2)
daf9df6d 351 EFUSEAR = 0xdc,
352#define EFUSEAR_FLAG 0x80000000
353#define EFUSEAR_WRITE_CMD 0x80000000
354#define EFUSEAR_READ_CMD 0x00000000
355#define EFUSEAR_REG_MASK 0x03ff
356#define EFUSEAR_REG_SHIFT 8
357#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 358};
359
c0e45c1c 360enum rtl8168_registers {
4f6b00e5
HW		 361 LED_FREQ = 0x1a,
362 EEE_LED = 0x1b,
b646d900 363 ERIDR = 0x70,
364 ERIAR = 0x74,
365#define ERIAR_FLAG 0x80000000
366#define ERIAR_WRITE_CMD 0x80000000
367#define ERIAR_READ_CMD 0x00000000
368#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 369#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 370#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
371#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
372#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
373#define ERIAR_MASK_SHIFT 12
374#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
375#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
376#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 377 EPHY_RXER_NUM = 0x7c,
378 OCPDR = 0xb0, /* OCP GPHY access */
379#define OCPDR_WRITE_CMD 0x80000000
380#define OCPDR_READ_CMD 0x00000000
381#define OCPDR_REG_MASK 0x7f
382#define OCPDR_GPHY_REG_SHIFT 16
383#define OCPDR_DATA_MASK 0xffff
384 OCPAR = 0xb4,
385#define OCPAR_FLAG 0x80000000
386#define OCPAR_GPHY_WRITE_CMD 0x8000f060
387#define OCPAR_GPHY_READ_CMD 0x0000f060
01dc7fec 388 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
389 MISC = 0xf0, /* 8168e only. */
cecb5fd7 390#define TXPLA_RST (1 << 29)
4f6b00e5 391#define PWM_EN (1 << 22)
c0e45c1c 392};
393
07d3f51f 394enum rtl_register_content {
1da177e4 395 /* InterruptStatusBits */
07d3f51f
FR		 396 SYSErr = 0x8000,
397 PCSTimeout = 0x4000,
398 SWInt = 0x0100,
399 TxDescUnavail = 0x0080,
400 RxFIFOOver = 0x0040,
401 LinkChg = 0x0020,
402 RxOverflow = 0x0010,
403 TxErr = 0x0008,
404 TxOK = 0x0004,
405 RxErr = 0x0002,
406 RxOK = 0x0001,
1da177e4
LT		 407
408 /* RxStatusDesc */
9dccf611
FR		 409 RxFOVF = (1 << 23),
410 RxRWT = (1 << 22),
411 RxRES = (1 << 21),
412 RxRUNT = (1 << 20),
413 RxCRC = (1 << 19),
1da177e4
LT		 414
415 /* ChipCmdBits */
4f6b00e5 416 StopReq = 0x80,
07d3f51f
FR		 417 CmdReset = 0x10,
418 CmdRxEnb = 0x08,
419 CmdTxEnb = 0x04,
420 RxBufEmpty = 0x01,
1da177e4 421
275391a4
FR		 422 /* TXPoll register p.5 */
423 HPQ = 0x80, /* Poll cmd on the high prio queue */
424 NPQ = 0x40, /* Poll cmd on the low prio queue */
425 FSWInt = 0x01, /* Forced software interrupt */
426
1da177e4 427 /* Cfg9346Bits */
07d3f51f
FR		 428 Cfg9346_Lock = 0x00,
429 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 430
431 /* rx_mode_bits */
07d3f51f
FR		 432 AcceptErr = 0x20,
433 AcceptRunt = 0x10,
434 AcceptBroadcast = 0x08,
435 AcceptMulticast = 0x04,
436 AcceptMyPhys = 0x02,
437 AcceptAllPhys = 0x01,
1da177e4 438
1da177e4
LT		 439 /* TxConfigBits */
440 TxInterFrameGapShift = 24,
441 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
442
5d06a99f 443 /* Config1 register p.24 */
f162a5d1
FR		 444 LEDS1 = (1 << 7),
445 LEDS0 = (1 << 6),
fbac58fc 446 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 447 Speed_down = (1 << 4),
448 MEMMAP = (1 << 3),
449 IOMAP = (1 << 2),
450 VPD = (1 << 1),
5d06a99f
FR		 451 PMEnable = (1 << 0), /* Power Management Enable */
452
6dccd16b
FR		 453 /* Config2 register p. 25 */
454 PCI_Clock_66MHz = 0x01,
455 PCI_Clock_33MHz = 0x00,
456
61a4dcc2
FR		 457 /* Config3 register p.25 */
458 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
459 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 460 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 461
5d06a99f 462 /* Config5 register p.27 */
61a4dcc2
FR		 463 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
464 MWF = (1 << 5), /* Accept Multicast wakeup frame */
465 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 466 Spi_en = (1 << 3),
61a4dcc2 467 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 468 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
469
1da177e4
LT		 470 /* TBICSR p.28 */
471 TBIReset = 0x80000000,
472 TBILoopback = 0x40000000,
473 TBINwEnable = 0x20000000,
474 TBINwRestart = 0x10000000,
475 TBILinkOk = 0x02000000,
476 TBINwComplete = 0x01000000,
477
478 /* CPlusCmd p.31 */
f162a5d1
FR		 479 EnableBist = (1 << 15), // 8168 8101
480 Mac_dbgo_oe = (1 << 14), // 8168 8101
481 Normal_mode = (1 << 13), // unused
482 Force_half_dup = (1 << 12), // 8168 8101
483 Force_rxflow_en = (1 << 11), // 8168 8101
484 Force_txflow_en = (1 << 10), // 8168 8101
485 Cxpl_dbg_sel = (1 << 9), // 8168 8101
486 ASF = (1 << 8), // 8168 8101
487 PktCntrDisable = (1 << 7), // 8168 8101
488 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 489 RxVlan = (1 << 6),
490 RxChkSum = (1 << 5),
491 PCIDAC = (1 << 4),
492 PCIMulRW = (1 << 3),
0e485150
FR		 493 INTT_0 = 0x0000, // 8168
494 INTT_1 = 0x0001, // 8168
495 INTT_2 = 0x0002, // 8168
496 INTT_3 = 0x0003, // 8168
1da177e4
LT		 497
498 /* rtl8169_PHYstatus */
07d3f51f
FR		 499 TBI_Enable = 0x80,
500 TxFlowCtrl = 0x40,
501 RxFlowCtrl = 0x20,
502 _1000bpsF = 0x10,
503 _100bps = 0x08,
504 _10bps = 0x04,
505 LinkStatus = 0x02,
506 FullDup = 0x01,
1da177e4 507
1da177e4 508 /* _TBICSRBit */
07d3f51f 509 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 510
511 /* DumpCounterCommand */
07d3f51f 512 CounterDump = 0x8,
1da177e4
LT		 513};
514
2b7b4318
FR		 515enum rtl_desc_bit {
516 /* First doubleword. */
1da177e4
LT		 517 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
518 RingEnd = (1 << 30), /* End of descriptor ring */
519 FirstFrag = (1 << 29), /* First segment of a packet */
520 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 521};
522
523/* Generic case. */
524enum rtl_tx_desc_bit {
525 /* First doubleword. */
526 TD_LSO = (1 << 27), /* Large Send Offload */
527#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 528
2b7b4318
FR		 529 /* Second doubleword. */
530 TxVlanTag = (1 << 17), /* Add VLAN tag */
531};
532
533/* 8169, 8168b and 810x except 8102e. */
534enum rtl_tx_desc_bit_0 {
535 /* First doubleword. */
536#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
537 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
538 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
539 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
540};
541
542/* 8102e, 8168c and beyond. */
543enum rtl_tx_desc_bit_1 {
544 /* Second doubleword. */
545#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
546 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
547 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
548 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
549};
1da177e4 550
2b7b4318
FR		 551static const struct rtl_tx_desc_info {
552 struct {
553 u32 udp;
554 u32 tcp;
555 } checksum;
556 u16 mss_shift;
557 u16 opts_offset;
558} tx_desc_info [] = {
559 [RTL_TD_0] = {
560 .checksum = {
561 .udp = TD0_IP_CS | TD0_UDP_CS,
562 .tcp = TD0_IP_CS | TD0_TCP_CS
563 },
564 .mss_shift = TD0_MSS_SHIFT,
565 .opts_offset = 0
566 },
567 [RTL_TD_1] = {
568 .checksum = {
569 .udp = TD1_IP_CS | TD1_UDP_CS,
570 .tcp = TD1_IP_CS | TD1_TCP_CS
571 },
572 .mss_shift = TD1_MSS_SHIFT,
573 .opts_offset = 1
574 }
575};
576
577enum rtl_rx_desc_bit {
1da177e4
LT		 578 /* Rx private */
579 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
580 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
581
582#define RxProtoUDP (PID1)
583#define RxProtoTCP (PID0)
584#define RxProtoIP (PID1 | PID0)
585#define RxProtoMask RxProtoIP
586
587 IPFail = (1 << 16), /* IP checksum failed */
588 UDPFail = (1 << 15), /* UDP/IP checksum failed */
589 TCPFail = (1 << 14), /* TCP/IP checksum failed */
590 RxVlanTag = (1 << 16), /* VLAN tag available */
591};
592
593#define RsvdMask 0x3fffc000
594
595struct TxDesc {
6cccd6e7
REB		 596 __le32 opts1;
597 __le32 opts2;
598 __le64 addr;
1da177e4
LT		 599};
600
601struct RxDesc {
6cccd6e7
REB		 602 __le32 opts1;
603 __le32 opts2;
604 __le64 addr;
1da177e4
LT		 605};
606
607struct ring_info {
608 struct sk_buff *skb;
609 u32 len;
610 u8 __pad[sizeof(void *) - sizeof(u32)];
611};
612
f23e7fda 613enum features {
ccdffb9a
FR		 614 RTL_FEATURE_WOL = (1 << 0),
615 RTL_FEATURE_MSI = (1 << 1),
616 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 617};
618
355423d0
IV		 619struct rtl8169_counters {
620 __le64 tx_packets;
621 __le64 rx_packets;
622 __le64 tx_errors;
623 __le32 rx_errors;
624 __le16 rx_missed;
625 __le16 align_errors;
626 __le32 tx_one_collision;
627 __le32 tx_multi_collision;
628 __le64 rx_unicast;
629 __le64 rx_broadcast;
630 __le32 rx_multicast;
631 __le16 tx_aborted;
632 __le16 tx_underun;
633};
634
1da177e4
LT		 635struct rtl8169_private {
636 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 637 struct pci_dev *pci_dev;
c4028958 638 struct net_device *dev;
bea3348e 639 struct napi_struct napi;
cecb5fd7 640 spinlock_t lock;
b57b7e5a 641 u32 msg_enable;
2b7b4318
FR		 642 u16 txd_version;
643 u16 mac_version;
1da177e4
LT		 644 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
645 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
646 u32 dirty_rx;
647 u32 dirty_tx;
648 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
649 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
650 dma_addr_t TxPhyAddr;
651 dma_addr_t RxPhyAddr;
6f0333b8 652 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 653 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 654 struct timer_list timer;
655 u16 cp_cmd;
0e485150
FR		 656 u16 intr_event;
657 u16 napi_event;
1da177e4 658 u16 intr_mask;
c0e45c1c 659
660 struct mdio_ops {
661 void (*write)(void __iomem *, int, int);
662 int (*read)(void __iomem *, int);
663 } mdio_ops;
664
065c27c1 665 struct pll_power_ops {
666 void (*down)(struct rtl8169_private *);
667 void (*up)(struct rtl8169_private *);
668 } pll_power_ops;
669
54405cde 670 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 671 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 672 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 673 void (*hw_start)(struct net_device *);
4da19633 674 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 675 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 676 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
c4028958 677 struct delayed_work task;
f23e7fda 678 unsigned features;
ccdffb9a
FR		 679
680 struct mii_if_info mii;
355423d0 681 struct rtl8169_counters counters;
e1759441 682 u32 saved_wolopts;
f1e02ed1 683
b6ffd97f
FR		 684 struct rtl_fw {
685 const struct firmware *fw;
1c361efb
FR		 686
687#define RTL_VER_SIZE 32
688
689 char version[RTL_VER_SIZE];
690
691 struct rtl_fw_phy_action {
692 __le32 *code;
693 size_t size;
694 } phy_action;
b6ffd97f 695 } *rtl_fw;
953a12cc 696#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN);
1da177e4
LT		 697};
698
979b6c13 699MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 700MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 701module_param(use_dac, int, 0);
4300e8c7 702MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 703module_param_named(debug, debug.msg_enable, int, 0);
704MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 705MODULE_LICENSE("GPL");
706MODULE_VERSION(RTL8169_VERSION);
bca03d5f 707MODULE_FIRMWARE(FIRMWARE_8168D_1);
708MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 709MODULE_FIRMWARE(FIRMWARE_8168E_1);
710MODULE_FIRMWARE(FIRMWARE_8168E_2);
5a5e4443 711MODULE_FIRMWARE(FIRMWARE_8105E_1);
1da177e4
LT		 712
713static int rtl8169_open(struct net_device *dev);
61357325
SH		 714static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
715 struct net_device *dev);
7d12e780 716static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 717static int rtl8169_init_ring(struct net_device *dev);
07ce4064 718static void rtl_hw_start(struct net_device *dev);
1da177e4 719static int rtl8169_close(struct net_device *dev);
07ce4064 720static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 721static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 722static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 723static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 724 void __iomem *, u32 budget);
4dcb7d33 725static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 726static void rtl8169_down(struct net_device *dev);
99f252b0 727static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 728static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 729
b646d900 730static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
731{
732 void __iomem *ioaddr = tp->mmio_addr;
733 int i;
734
735 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
736 for (i = 0; i < 20; i++) {
737 udelay(100);
738 if (RTL_R32(OCPAR) & OCPAR_FLAG)
739 break;
740 }
741 return RTL_R32(OCPDR);
742}
743
744static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
745{
746 void __iomem *ioaddr = tp->mmio_addr;
747 int i;
748
749 RTL_W32(OCPDR, data);
750 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
751 for (i = 0; i < 20; i++) {
752 udelay(100);
753 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
754 break;
755 }
756}
757
fac5b3ca 758static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 759{
fac5b3ca 760 void __iomem *ioaddr = tp->mmio_addr;
b646d900 761 int i;
762
763 RTL_W8(ERIDR, cmd);
764 RTL_W32(ERIAR, 0x800010e8);
765 msleep(2);
766 for (i = 0; i < 5; i++) {
767 udelay(100);
1e4e82ba 768 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
b646d900 769 break;
770 }
771
fac5b3ca 772 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 773}
774
775#define OOB_CMD_RESET 0x00
776#define OOB_CMD_DRIVER_START 0x05
777#define OOB_CMD_DRIVER_STOP 0x06
778
cecb5fd7
FR		 779static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
780{
781 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
782}
783
b646d900 784static void rtl8168_driver_start(struct rtl8169_private *tp)
785{
cecb5fd7 786 u16 reg;
b646d900 787 int i;
788
789 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
790
cecb5fd7 791 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 792
b646d900 793 for (i = 0; i < 10; i++) {
794 msleep(10);
4804b3b3 795 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
b646d900 796 break;
797 }
798}
799
800static void rtl8168_driver_stop(struct rtl8169_private *tp)
801{
cecb5fd7 802 u16 reg;
b646d900 803 int i;
804
805 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
806
cecb5fd7 807 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 808
b646d900 809 for (i = 0; i < 10; i++) {
810 msleep(10);
4804b3b3 811 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
b646d900 812 break;
813 }
814}
815
4804b3b3 816static int r8168dp_check_dash(struct rtl8169_private *tp)
817{
cecb5fd7 818 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 819
cecb5fd7 820 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 821}
b646d900 822
4da19633 823static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 824{
825 int i;
826
a6baf3af 827 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 828
2371408c 829 for (i = 20; i > 0; i--) {
07d3f51f
FR		 830 /*
831 * Check if the RTL8169 has completed writing to the specified
832 * MII register.
833 */
5b0384f4 834 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 835 break;
2371408c 836 udelay(25);
1da177e4 837 }
024a07ba 838 /*
81a95f04
TT		 839 * According to hardware specs a 20us delay is required after write
840 * complete indication, but before sending next command.
024a07ba 841 */
81a95f04 842 udelay(20);
1da177e4
LT		 843}
844
4da19633 845static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 846{
847 int i, value = -1;
848
a6baf3af 849 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 850
2371408c 851 for (i = 20; i > 0; i--) {
07d3f51f
FR		 852 /*
853 * Check if the RTL8169 has completed retrieving data from
854 * the specified MII register.
855 */
1da177e4 856 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 857 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 858 break;
859 }
2371408c 860 udelay(25);
1da177e4 861 }
81a95f04
TT		 862 /*
863 * According to hardware specs a 20us delay is required after read
864 * complete indication, but before sending next command.
865 */
866 udelay(20);
867
1da177e4
LT		 868 return value;
869}
870
c0e45c1c 871static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
872{
873 int i;
874
875 RTL_W32(OCPDR, data |
876 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
877 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
878 RTL_W32(EPHY_RXER_NUM, 0);
879
880 for (i = 0; i < 100; i++) {
881 mdelay(1);
882 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
883 break;
884 }
885}
886
887static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
888{
889 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
890 (value & OCPDR_DATA_MASK));
891}
892
893static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
894{
895 int i;
896
897 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
898
899 mdelay(1);
900 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
901 RTL_W32(EPHY_RXER_NUM, 0);
902
903 for (i = 0; i < 100; i++) {
904 mdelay(1);
905 if (RTL_R32(OCPAR) & OCPAR_FLAG)
906 break;
907 }
908
909 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
910}
911
e6de30d6 912#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
913
914static void r8168dp_2_mdio_start(void __iomem *ioaddr)
915{
916 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
917}
918
919static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
920{
921 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
922}
923
924static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
925{
926 r8168dp_2_mdio_start(ioaddr);
927
928 r8169_mdio_write(ioaddr, reg_addr, value);
929
930 r8168dp_2_mdio_stop(ioaddr);
931}
932
933static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
934{
935 int value;
936
937 r8168dp_2_mdio_start(ioaddr);
938
939 value = r8169_mdio_read(ioaddr, reg_addr);
940
941 r8168dp_2_mdio_stop(ioaddr);
942
943 return value;
944}
945
4da19633 946static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 947{
c0e45c1c 948 tp->mdio_ops.write(tp->mmio_addr, location, val);
dacf8154
FR		 949}
950
4da19633 951static int rtl_readphy(struct rtl8169_private *tp, int location)
952{
c0e45c1c 953 return tp->mdio_ops.read(tp->mmio_addr, location);
4da19633 954}
955
956static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
957{
958 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
959}
960
961static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 962{
963 int val;
964
4da19633 965 val = rtl_readphy(tp, reg_addr);
966 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 967}
968
ccdffb9a
FR		 969static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
970 int val)
971{
972 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 973
4da19633 974 rtl_writephy(tp, location, val);
ccdffb9a
FR		 975}
976
977static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
978{
979 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 980
4da19633 981 return rtl_readphy(tp, location);
ccdffb9a
FR		 982}
983
dacf8154
FR		 984static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
985{
986 unsigned int i;
987
988 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
989 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
990
991 for (i = 0; i < 100; i++) {
992 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
993 break;
994 udelay(10);
995 }
996}
997
998static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
999{
1000 u16 value = 0xffff;
1001 unsigned int i;
1002
1003 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1004
1005 for (i = 0; i < 100; i++) {
1006 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1007 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1008 break;
1009 }
1010 udelay(10);
1011 }
1012
1013 return value;
1014}
1015
1016static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1017{
1018 unsigned int i;
1019
1020 RTL_W32(CSIDR, value);
1021 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1022 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1023
1024 for (i = 0; i < 100; i++) {
1025 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1026 break;
1027 udelay(10);
1028 }
1029}
1030
1031static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1032{
1033 u32 value = ~0x00;
1034 unsigned int i;
1035
1036 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1037 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1038
1039 for (i = 0; i < 100; i++) {
1040 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1041 value = RTL_R32(CSIDR);
1042 break;
1043 }
1044 udelay(10);
1045 }
1046
1047 return value;
1048}
1049
133ac40a
HW		 1050static
1051void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1052{
1053 unsigned int i;
1054
1055 BUG_ON((addr & 3) || (mask == 0));
1056 RTL_W32(ERIDR, val);
1057 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1058
1059 for (i = 0; i < 100; i++) {
1060 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1061 break;
1062 udelay(100);
1063 }
1064}
1065
1066static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1067{
1068 u32 value = ~0x00;
1069 unsigned int i;
1070
1071 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1072
1073 for (i = 0; i < 100; i++) {
1074 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1075 value = RTL_R32(ERIDR);
1076 break;
1077 }
1078 udelay(100);
1079 }
1080
1081 return value;
1082}
1083
1084static void
1085rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1086{
1087 u32 val;
1088
1089 val = rtl_eri_read(ioaddr, addr, type);
1090 rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1091}
1092
daf9df6d 1093static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1094{
1095 u8 value = 0xff;
1096 unsigned int i;
1097
1098 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1099
1100 for (i = 0; i < 300; i++) {
1101 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1102 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1103 break;
1104 }
1105 udelay(100);
1106 }
1107
1108 return value;
1109}
1110
1da177e4
LT		 1111static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1112{
1113 RTL_W16(IntrMask, 0x0000);
1114
1115 RTL_W16(IntrStatus, 0xffff);
1116}
1117
4da19633 1118static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1119{
4da19633 1120 void __iomem *ioaddr = tp->mmio_addr;
1121
1da177e4
LT		 1122 return RTL_R32(TBICSR) & TBIReset;
1123}
1124
4da19633 1125static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1126{
4da19633 1127 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1128}
1129
1130static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1131{
1132 return RTL_R32(TBICSR) & TBILinkOk;
1133}
1134
1135static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1136{
1137 return RTL_R8(PHYstatus) & LinkStatus;
1138}
1139
4da19633 1140static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1141{
4da19633 1142 void __iomem *ioaddr = tp->mmio_addr;
1143
1da177e4
LT		 1144 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1145}
1146
4da19633 1147static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1148{
1149 unsigned int val;
1150
4da19633 1151 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1152 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1153}
1154
70090424
HW		 1155static void rtl_link_chg_patch(struct rtl8169_private *tp)
1156{
1157 void __iomem *ioaddr = tp->mmio_addr;
1158 struct net_device *dev = tp->dev;
1159
1160 if (!netif_running(dev))
1161 return;
1162
1163 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1164 if (RTL_R8(PHYstatus) & _1000bpsF) {
1165 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1166 0x00000011, ERIAR_EXGMAC);
1167 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1168 0x00000005, ERIAR_EXGMAC);
1169 } else if (RTL_R8(PHYstatus) & _100bps) {
1170 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1171 0x0000001f, ERIAR_EXGMAC);
1172 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1173 0x00000005, ERIAR_EXGMAC);
1174 } else {
1175 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1176 0x0000001f, ERIAR_EXGMAC);
1177 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1178 0x0000003f, ERIAR_EXGMAC);
1179 }
1180 /* Reset packet filter */
1181 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1182 ERIAR_EXGMAC);
1183 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1184 ERIAR_EXGMAC);
1185 }
1186}
1187
e4fbce74 1188static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1189 struct rtl8169_private *tp,
1190 void __iomem *ioaddr, bool pm)
1da177e4
LT		 1191{
1192 unsigned long flags;
1193
1194 spin_lock_irqsave(&tp->lock, flags);
1195 if (tp->link_ok(ioaddr)) {
70090424 1196 rtl_link_chg_patch(tp);
e1759441 1197 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1198 if (pm)
1199 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1200 netif_carrier_on(dev);
1519e57f
FR		 1201 if (net_ratelimit())
1202 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1203 } else {
1da177e4 1204 netif_carrier_off(dev);
bf82c189 1205 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74
RW		 1206 if (pm)
1207 pm_schedule_suspend(&tp->pci_dev->dev, 100);
b57b7e5a 1208 }
1da177e4
LT		 1209 spin_unlock_irqrestore(&tp->lock, flags);
1210}
1211
e4fbce74
RW		 1212static void rtl8169_check_link_status(struct net_device *dev,
1213 struct rtl8169_private *tp,
1214 void __iomem *ioaddr)
1215{
1216 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1217}
1218
e1759441
RW		 1219#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1220
1221static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1222{
61a4dcc2
FR		 1223 void __iomem *ioaddr = tp->mmio_addr;
1224 u8 options;
e1759441 1225 u32 wolopts = 0;
61a4dcc2
FR		 1226
1227 options = RTL_R8(Config1);
1228 if (!(options & PMEnable))
e1759441 1229 return 0;
61a4dcc2
FR		 1230
1231 options = RTL_R8(Config3);
1232 if (options & LinkUp)
e1759441 1233 wolopts |= WAKE_PHY;
61a4dcc2 1234 if (options & MagicPacket)
e1759441 1235 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1236
1237 options = RTL_R8(Config5);
1238 if (options & UWF)
e1759441 1239 wolopts |= WAKE_UCAST;
61a4dcc2 1240 if (options & BWF)
e1759441 1241 wolopts |= WAKE_BCAST;
61a4dcc2 1242 if (options & MWF)
e1759441 1243 wolopts |= WAKE_MCAST;
61a4dcc2 1244
e1759441 1245 return wolopts;
61a4dcc2
FR		 1246}
1247
e1759441 1248static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1249{
1250 struct rtl8169_private *tp = netdev_priv(dev);
e1759441
RW		 1251
1252 spin_lock_irq(&tp->lock);
1253
1254 wol->supported = WAKE_ANY;
1255 wol->wolopts = __rtl8169_get_wol(tp);
1256
1257 spin_unlock_irq(&tp->lock);
1258}
1259
1260static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1261{
61a4dcc2 1262 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1263 unsigned int i;
350f7596 1264 static const struct {
61a4dcc2
FR		 1265 u32 opt;
1266 u16 reg;
1267 u8 mask;
1268 } cfg[] = {
1269 { WAKE_ANY, Config1, PMEnable },
1270 { WAKE_PHY, Config3, LinkUp },
1271 { WAKE_MAGIC, Config3, MagicPacket },
1272 { WAKE_UCAST, Config5, UWF },
1273 { WAKE_BCAST, Config5, BWF },
1274 { WAKE_MCAST, Config5, MWF },
1275 { WAKE_ANY, Config5, LanWake }
1276 };
1277
61a4dcc2
FR		 1278 RTL_W8(Cfg9346, Cfg9346_Unlock);
1279
1280 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1281 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1282 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1283 options |= cfg[i].mask;
1284 RTL_W8(cfg[i].reg, options);
1285 }
1286
1287 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1288}
1289
1290static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1291{
1292 struct rtl8169_private *tp = netdev_priv(dev);
1293
1294 spin_lock_irq(&tp->lock);
61a4dcc2 1295
f23e7fda
FR		 1296 if (wol->wolopts)
1297 tp->features |= RTL_FEATURE_WOL;
1298 else
1299 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1300 __rtl8169_set_wol(tp, wol->wolopts);
61a4dcc2
FR		 1301 spin_unlock_irq(&tp->lock);
1302
ea80907f 1303 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1304
61a4dcc2
FR		 1305 return 0;
1306}
1307
31bd204f
FR		 1308static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1309{
85bffe6c 1310 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1311}
1312
1da177e4
LT		 1313static void rtl8169_get_drvinfo(struct net_device *dev,
1314 struct ethtool_drvinfo *info)
1315{
1316 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1317 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4
LT		 1318
1319 strcpy(info->driver, MODULENAME);
1320 strcpy(info->version, RTL8169_VERSION);
1321 strcpy(info->bus_info, pci_name(tp->pci_dev));
1c361efb
FR		 1322 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1323 strcpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" :
1324 rtl_fw->version);
1da177e4
LT		 1325}
1326
1327static int rtl8169_get_regs_len(struct net_device *dev)
1328{
1329 return R8169_REGS_SIZE;
1330}
1331
1332static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1333 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1334{
1335 struct rtl8169_private *tp = netdev_priv(dev);
1336 void __iomem *ioaddr = tp->mmio_addr;
1337 int ret = 0;
1338 u32 reg;
1339
1340 reg = RTL_R32(TBICSR);
1341 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1342 (duplex == DUPLEX_FULL)) {
1343 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1344 } else if (autoneg == AUTONEG_ENABLE)
1345 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1346 else {
bf82c189
JP		 1347 netif_warn(tp, link, dev,
1348 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1349 ret = -EOPNOTSUPP;
1350 }
1351
1352 return ret;
1353}
1354
1355static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1356 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1357{
1358 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1359 int giga_ctrl, bmcr;
54405cde 1360 int rc = -EINVAL;
1da177e4 1361
716b50a3 1362 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1363
1364 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1365 int auto_nego;
1366
4da19633 1367 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1368 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1369 ADVERTISE_100HALF | ADVERTISE_100FULL);
1370
1371 if (adv & ADVERTISED_10baseT_Half)
1372 auto_nego |= ADVERTISE_10HALF;
1373 if (adv & ADVERTISED_10baseT_Full)
1374 auto_nego |= ADVERTISE_10FULL;
1375 if (adv & ADVERTISED_100baseT_Half)
1376 auto_nego |= ADVERTISE_100HALF;
1377 if (adv & ADVERTISED_100baseT_Full)
1378 auto_nego |= ADVERTISE_100FULL;
1379
3577aa1b 1380 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1381
4da19633 1382 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1383 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1384
3577aa1b 1385 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1386 if (tp->mii.supports_gmii) {
54405cde
ON		 1387 if (adv & ADVERTISED_1000baseT_Half)
1388 giga_ctrl |= ADVERTISE_1000HALF;
1389 if (adv & ADVERTISED_1000baseT_Full)
1390 giga_ctrl |= ADVERTISE_1000FULL;
1391 } else if (adv & (ADVERTISED_1000baseT_Half |
1392 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1393 netif_info(tp, link, dev,
1394 "PHY does not support 1000Mbps\n");
54405cde 1395 goto out;
bcf0bf90 1396 }
1da177e4 1397
3577aa1b 1398 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1399
4da19633 1400 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1401 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1402 } else {
1403 giga_ctrl = 0;
1404
1405 if (speed == SPEED_10)
1406 bmcr = 0;
1407 else if (speed == SPEED_100)
1408 bmcr = BMCR_SPEED100;
1409 else
54405cde 1410 goto out;
3577aa1b 1411
1412 if (duplex == DUPLEX_FULL)
1413 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1414 }
1415
4da19633 1416 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1417
cecb5fd7
FR		 1418 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1419 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1420 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1421 rtl_writephy(tp, 0x17, 0x2138);
1422 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1423 } else {
4da19633 1424 rtl_writephy(tp, 0x17, 0x2108);
1425 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1426 }
1427 }
1428
54405cde
ON		 1429 rc = 0;
1430out:
1431 return rc;
1da177e4
LT		 1432}
1433
1434static int rtl8169_set_speed(struct net_device *dev,
54405cde 1435 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1436{
1437 struct rtl8169_private *tp = netdev_priv(dev);
1438 int ret;
1439
54405cde 1440 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1441 if (ret < 0)
1442 goto out;
1da177e4 1443
4876cc1e
FR		 1444 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1445 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1446 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1447 }
1448out:
1da177e4
LT		 1449 return ret;
1450}
1451
1452static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1453{
1454 struct rtl8169_private *tp = netdev_priv(dev);
1455 unsigned long flags;
1456 int ret;
1457
4876cc1e
FR		 1458 del_timer_sync(&tp->timer);
1459
1da177e4 1460 spin_lock_irqsave(&tp->lock, flags);
cecb5fd7 1461 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1462 cmd->duplex, cmd->advertising);
1da177e4 1463 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 1464
1da177e4
LT		 1465 return ret;
1466}
1467
350fb32a 1468static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1da177e4 1469{
2b7b4318 1470 if (dev->mtu > TD_MSS_MAX)
350fb32a 1471 features &= ~NETIF_F_ALL_TSO;
1da177e4 1472
350fb32a 1473 return features;
1da177e4
LT		 1474}
1475
350fb32a 1476static int rtl8169_set_features(struct net_device *dev, u32 features)
1da177e4
LT		 1477{
1478 struct rtl8169_private *tp = netdev_priv(dev);
1479 void __iomem *ioaddr = tp->mmio_addr;
1480 unsigned long flags;
1481
1482 spin_lock_irqsave(&tp->lock, flags);
1483
350fb32a 1484 if (features & NETIF_F_RXCSUM)
1da177e4
LT		 1485 tp->cp_cmd |= RxChkSum;
1486 else
1487 tp->cp_cmd &= ~RxChkSum;
1488
350fb32a
MM		 1489 if (dev->features & NETIF_F_HW_VLAN_RX)
1490 tp->cp_cmd |= RxVlan;
1491 else
1492 tp->cp_cmd &= ~RxVlan;
1493
1da177e4
LT		 1494 RTL_W16(CPlusCmd, tp->cp_cmd);
1495 RTL_R16(CPlusCmd);
1496
1497 spin_unlock_irqrestore(&tp->lock, flags);
1498
1499 return 0;
1500}
1501
1da177e4
LT		 1502static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1503 struct sk_buff *skb)
1504{
eab6d18d 1505 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1506 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1507}
1508
7a8fc77b 1509static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1510{
1511 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1512
7a8fc77b
FR		 1513 if (opts2 & RxVlanTag)
1514 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
2edae08e 1515
1da177e4 1516 desc->opts2 = 0;
1da177e4
LT		 1517}
1518
ccdffb9a 1519static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1520{
1521 struct rtl8169_private *tp = netdev_priv(dev);
1522 void __iomem *ioaddr = tp->mmio_addr;
1523 u32 status;
1524
1525 cmd->supported =
1526 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1527 cmd->port = PORT_FIBRE;
1528 cmd->transceiver = XCVR_INTERNAL;
1529
1530 status = RTL_R32(TBICSR);
1531 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1532 cmd->autoneg = !!(status & TBINwEnable);
1533
70739497 1534 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1535 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1536
1537 return 0;
1da177e4
LT		 1538}
1539
ccdffb9a 1540static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1541{
1542 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1543
1544 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1545}
1546
1547static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1548{
1549 struct rtl8169_private *tp = netdev_priv(dev);
1550 unsigned long flags;
ccdffb9a 1551 int rc;
1da177e4
LT		 1552
1553 spin_lock_irqsave(&tp->lock, flags);
1554
ccdffb9a 1555 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1556
1557 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1558 return rc;
1da177e4
LT		 1559}
1560
1561static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1562 void *p)
1563{
5b0384f4
FR		 1564 struct rtl8169_private *tp = netdev_priv(dev);
1565 unsigned long flags;
1da177e4 1566
5b0384f4
FR		 1567 if (regs->len > R8169_REGS_SIZE)
1568 regs->len = R8169_REGS_SIZE;
1da177e4 1569
5b0384f4
FR		 1570 spin_lock_irqsave(&tp->lock, flags);
1571 memcpy_fromio(p, tp->mmio_addr, regs->len);
1572 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1573}
1574
b57b7e5a
SH		 1575static u32 rtl8169_get_msglevel(struct net_device *dev)
1576{
1577 struct rtl8169_private *tp = netdev_priv(dev);
1578
1579 return tp->msg_enable;
1580}
1581
1582static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1583{
1584 struct rtl8169_private *tp = netdev_priv(dev);
1585
1586 tp->msg_enable = value;
1587}
1588
d4a3a0fc
SH		 1589static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1590 "tx_packets",
1591 "rx_packets",
1592 "tx_errors",
1593 "rx_errors",
1594 "rx_missed",
1595 "align_errors",
1596 "tx_single_collisions",
1597 "tx_multi_collisions",
1598 "unicast",
1599 "broadcast",
1600 "multicast",
1601 "tx_aborted",
1602 "tx_underrun",
1603};
1604
b9f2c044 1605static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1606{
b9f2c044
JG		 1607 switch (sset) {
1608 case ETH_SS_STATS:
1609 return ARRAY_SIZE(rtl8169_gstrings);
1610 default:
1611 return -EOPNOTSUPP;
1612 }
d4a3a0fc
SH		 1613}
1614
355423d0 1615static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1616{
1617 struct rtl8169_private *tp = netdev_priv(dev);
1618 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 1619 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 1620 struct rtl8169_counters *counters;
1621 dma_addr_t paddr;
1622 u32 cmd;
355423d0 1623 int wait = 1000;
d4a3a0fc 1624
355423d0
IV		 1625 /*
1626 * Some chips are unable to dump tally counters when the receiver
1627 * is disabled.
1628 */
1629 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1630 return;
d4a3a0fc 1631
48addcc9 1632 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1633 if (!counters)
1634 return;
1635
1636 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1637 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1638 RTL_W32(CounterAddrLow, cmd);
1639 RTL_W32(CounterAddrLow, cmd | CounterDump);
1640
355423d0
IV		 1641 while (wait--) {
1642 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
355423d0 1643 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1644 break;
355423d0
IV		 1645 }
1646 udelay(10);
d4a3a0fc
SH		 1647 }
1648
1649 RTL_W32(CounterAddrLow, 0);
1650 RTL_W32(CounterAddrHigh, 0);
1651
48addcc9 1652 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1653}
1654
355423d0
IV		 1655static void rtl8169_get_ethtool_stats(struct net_device *dev,
1656 struct ethtool_stats *stats, u64 *data)
1657{
1658 struct rtl8169_private *tp = netdev_priv(dev);
1659
1660 ASSERT_RTNL();
1661
1662 rtl8169_update_counters(dev);
1663
1664 data[0] = le64_to_cpu(tp->counters.tx_packets);
1665 data[1] = le64_to_cpu(tp->counters.rx_packets);
1666 data[2] = le64_to_cpu(tp->counters.tx_errors);
1667 data[3] = le32_to_cpu(tp->counters.rx_errors);
1668 data[4] = le16_to_cpu(tp->counters.rx_missed);
1669 data[5] = le16_to_cpu(tp->counters.align_errors);
1670 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1671 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1672 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1673 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1674 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1675 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1676 data[12] = le16_to_cpu(tp->counters.tx_underun);
1677}
1678
d4a3a0fc
SH		 1679static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1680{
1681 switch(stringset) {
1682 case ETH_SS_STATS:
1683 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1684 break;
1685 }
1686}
1687
7282d491 1688static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1689 .get_drvinfo = rtl8169_get_drvinfo,
1690 .get_regs_len = rtl8169_get_regs_len,
1691 .get_link = ethtool_op_get_link,
1692 .get_settings = rtl8169_get_settings,
1693 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1694 .get_msglevel = rtl8169_get_msglevel,
1695 .set_msglevel = rtl8169_set_msglevel,
1da177e4 1696 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1697 .get_wol = rtl8169_get_wol,
1698 .set_wol = rtl8169_set_wol,
d4a3a0fc 1699 .get_strings = rtl8169_get_strings,
b9f2c044 1700 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1701 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1702};
1703
07d3f51f 1704static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 1705 struct net_device *dev, u8 default_version)
1da177e4 1706{
5d320a20 1707 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 1708 /*
1709 * The driver currently handles the 8168Bf and the 8168Be identically
1710 * but they can be identified more specifically through the test below
1711 * if needed:
1712 *
1713 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1714 *
1715 * Same thing for the 8101Eb and the 8101Ec:
1716 *
1717 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1718 */
3744100e 1719 static const struct rtl_mac_info {
1da177e4 1720 u32 mask;
e3cf0cc0 1721 u32 val;
1da177e4
LT		 1722 int mac_version;
1723 } mac_info[] = {
01dc7fec 1724 /* 8168E family. */
70090424 1725 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 1726 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1727 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1728 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1729
5b538df9 1730 /* 8168D family. */
daf9df6d 1731 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1732 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 1733 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1734
e6de30d6 1735 /* 8168DP family. */
1736 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1737 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 1738 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 1739
ef808d50 1740 /* 8168C family. */
17c99297 1741 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1742 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1743 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1744 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1745 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1746 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1747 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1748 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1749 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1750
1751 /* 8168B family. */
1752 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1753 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1754 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1755 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1756
1757 /* 8101 family. */
36a0e6c2 1758 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 1759 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1760 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1761 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 1762 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1763 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1764 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1765 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1766 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1767 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1768 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1769 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1770 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1771 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1772 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1773 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1774 /* FIXME: where did these entries come from ? -- FR */
1775 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1776 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1777
1778 /* 8110 family. */
1779 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1780 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1781 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1782 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1783 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1784 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1785
f21b75e9
JD		 1786 /* Catch-all */
1787 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 1788 };
1789 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 1790 u32 reg;
1791
e3cf0cc0
FR		 1792 reg = RTL_R32(TxConfig);
1793 while ((reg & p->mask) != p->val)
1da177e4
LT		 1794 p++;
1795 tp->mac_version = p->mac_version;
5d320a20
FR		 1796
1797 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1798 netif_notice(tp, probe, dev,
1799 "unknown MAC, using family default\n");
1800 tp->mac_version = default_version;
1801 }
1da177e4
LT		 1802}
1803
1804static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1805{
bcf0bf90 1806 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1807}
1808
867763c1
FR		 1809struct phy_reg {
1810 u16 reg;
1811 u16 val;
1812};
1813
4da19633 1814static void rtl_writephy_batch(struct rtl8169_private *tp,
1815 const struct phy_reg *regs, int len)
867763c1
FR		 1816{
1817 while (len-- > 0) {
4da19633 1818 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 1819 regs++;
1820 }
1821}
1822
bca03d5f 1823#define PHY_READ 0x00000000
1824#define PHY_DATA_OR 0x10000000
1825#define PHY_DATA_AND 0x20000000
1826#define PHY_BJMPN 0x30000000
1827#define PHY_READ_EFUSE 0x40000000
1828#define PHY_READ_MAC_BYTE 0x50000000
1829#define PHY_WRITE_MAC_BYTE 0x60000000
1830#define PHY_CLEAR_READCOUNT 0x70000000
1831#define PHY_WRITE 0x80000000
1832#define PHY_READCOUNT_EQ_SKIP 0x90000000
1833#define PHY_COMP_EQ_SKIPN 0xa0000000
1834#define PHY_COMP_NEQ_SKIPN 0xb0000000
1835#define PHY_WRITE_PREVIOUS 0xc0000000
1836#define PHY_SKIPN 0xd0000000
1837#define PHY_DELAY_MS 0xe0000000
1838#define PHY_WRITE_ERI_WORD 0xf0000000
1839
960aee6c
HW		 1840struct fw_info {
1841 u32 magic;
1842 char version[RTL_VER_SIZE];
1843 __le32 fw_start;
1844 __le32 fw_len;
1845 u8 chksum;
1846} __packed;
1847
1c361efb
FR		 1848#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1849
1850static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 1851{
b6ffd97f 1852 const struct firmware *fw = rtl_fw->fw;
960aee6c 1853 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 1854 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1855 char *version = rtl_fw->version;
1856 bool rc = false;
1857
1858 if (fw->size < FW_OPCODE_SIZE)
1859 goto out;
960aee6c
HW		 1860
1861 if (!fw_info->magic) {
1862 size_t i, size, start;
1863 u8 checksum = 0;
1864
1865 if (fw->size < sizeof(*fw_info))
1866 goto out;
1867
1868 for (i = 0; i < fw->size; i++)
1869 checksum += fw->data[i];
1870 if (checksum != 0)
1871 goto out;
1872
1873 start = le32_to_cpu(fw_info->fw_start);
1874 if (start > fw->size)
1875 goto out;
1876
1877 size = le32_to_cpu(fw_info->fw_len);
1878 if (size > (fw->size - start) / FW_OPCODE_SIZE)
1879 goto out;
1880
1881 memcpy(version, fw_info->version, RTL_VER_SIZE);
1882
1883 pa->code = (__le32 *)(fw->data + start);
1884 pa->size = size;
1885 } else {
1c361efb
FR		 1886 if (fw->size % FW_OPCODE_SIZE)
1887 goto out;
1888
1889 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
1890
1891 pa->code = (__le32 *)fw->data;
1892 pa->size = fw->size / FW_OPCODE_SIZE;
1893 }
1894 version[RTL_VER_SIZE - 1] = 0;
1895
1896 rc = true;
1897out:
1898 return rc;
1899}
1900
fd112f2e
FR		 1901static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
1902 struct rtl_fw_phy_action *pa)
1c361efb 1903{
fd112f2e 1904 bool rc = false;
1c361efb 1905 size_t index;
bca03d5f 1906
1c361efb
FR		 1907 for (index = 0; index < pa->size; index++) {
1908 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 1909 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 1910
42b82dc1 1911 switch(action & 0xf0000000) {
1912 case PHY_READ:
1913 case PHY_DATA_OR:
1914 case PHY_DATA_AND:
1915 case PHY_READ_EFUSE:
1916 case PHY_CLEAR_READCOUNT:
1917 case PHY_WRITE:
1918 case PHY_WRITE_PREVIOUS:
1919 case PHY_DELAY_MS:
1920 break;
1921
1922 case PHY_BJMPN:
1923 if (regno > index) {
fd112f2e 1924 netif_err(tp, ifup, tp->dev,
cecb5fd7 1925 "Out of range of firmware\n");
fd112f2e 1926 goto out;
42b82dc1 1927 }
1928 break;
1929 case PHY_READCOUNT_EQ_SKIP:
1c361efb 1930 if (index + 2 >= pa->size) {
fd112f2e 1931 netif_err(tp, ifup, tp->dev,
cecb5fd7 1932 "Out of range of firmware\n");
fd112f2e 1933 goto out;
42b82dc1 1934 }
1935 break;
1936 case PHY_COMP_EQ_SKIPN:
1937 case PHY_COMP_NEQ_SKIPN:
1938 case PHY_SKIPN:
1c361efb 1939 if (index + 1 + regno >= pa->size) {
fd112f2e 1940 netif_err(tp, ifup, tp->dev,
cecb5fd7 1941 "Out of range of firmware\n");
fd112f2e 1942 goto out;
42b82dc1 1943 }
bca03d5f 1944 break;
1945
42b82dc1 1946 case PHY_READ_MAC_BYTE:
1947 case PHY_WRITE_MAC_BYTE:
1948 case PHY_WRITE_ERI_WORD:
1949 default:
fd112f2e 1950 netif_err(tp, ifup, tp->dev,
42b82dc1 1951 "Invalid action 0x%08x\n", action);
fd112f2e 1952 goto out;
bca03d5f 1953 }
1954 }
fd112f2e
FR		 1955 rc = true;
1956out:
1957 return rc;
1958}
bca03d5f 1959
fd112f2e
FR		 1960static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1961{
1962 struct net_device *dev = tp->dev;
1963 int rc = -EINVAL;
1964
1965 if (!rtl_fw_format_ok(tp, rtl_fw)) {
1966 netif_err(tp, ifup, dev, "invalid firwmare\n");
1967 goto out;
1968 }
1969
1970 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
1971 rc = 0;
1972out:
1973 return rc;
1974}
1975
1976static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1977{
1978 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1979 u32 predata, count;
1980 size_t index;
1981
1982 predata = count = 0;
42b82dc1 1983
1c361efb
FR		 1984 for (index = 0; index < pa->size; ) {
1985 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 1986 u32 data = action & 0x0000ffff;
42b82dc1 1987 u32 regno = (action & 0x0fff0000) >> 16;
1988
1989 if (!action)
1990 break;
bca03d5f 1991
1992 switch(action & 0xf0000000) {
42b82dc1 1993 case PHY_READ:
1994 predata = rtl_readphy(tp, regno);
1995 count++;
1996 index++;
1997 break;
1998 case PHY_DATA_OR:
1999 predata |= data;
2000 index++;
2001 break;
2002 case PHY_DATA_AND:
2003 predata &= data;
2004 index++;
2005 break;
2006 case PHY_BJMPN:
2007 index -= regno;
2008 break;
2009 case PHY_READ_EFUSE:
2010 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2011 index++;
2012 break;
2013 case PHY_CLEAR_READCOUNT:
2014 count = 0;
2015 index++;
2016 break;
bca03d5f 2017 case PHY_WRITE:
42b82dc1 2018 rtl_writephy(tp, regno, data);
2019 index++;
2020 break;
2021 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2022 index += (count == data) ? 2 : 1;
bca03d5f 2023 break;
42b82dc1 2024 case PHY_COMP_EQ_SKIPN:
2025 if (predata == data)
2026 index += regno;
2027 index++;
2028 break;
2029 case PHY_COMP_NEQ_SKIPN:
2030 if (predata != data)
2031 index += regno;
2032 index++;
2033 break;
2034 case PHY_WRITE_PREVIOUS:
2035 rtl_writephy(tp, regno, predata);
2036 index++;
2037 break;
2038 case PHY_SKIPN:
2039 index += regno + 1;
2040 break;
2041 case PHY_DELAY_MS:
2042 mdelay(data);
2043 index++;
2044 break;
2045
2046 case PHY_READ_MAC_BYTE:
2047 case PHY_WRITE_MAC_BYTE:
2048 case PHY_WRITE_ERI_WORD:
bca03d5f 2049 default:
2050 BUG();
2051 }
2052 }
2053}
2054
f1e02ed1 2055static void rtl_release_firmware(struct rtl8169_private *tp)
2056{
b6ffd97f
FR		 2057 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2058 release_firmware(tp->rtl_fw->fw);
2059 kfree(tp->rtl_fw);
2060 }
2061 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2062}
2063
953a12cc 2064static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2065{
b6ffd97f 2066 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2067
2068 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
b6ffd97f
FR		 2069 if (!IS_ERR_OR_NULL(rtl_fw))
2070 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2071}
2072
2073static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2074{
2075 if (rtl_readphy(tp, reg) != val)
2076 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2077 else
2078 rtl_apply_firmware(tp);
f1e02ed1 2079}
2080
4da19633 2081static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2082{
350f7596 2083 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2084 { 0x1f, 0x0001 },
2085 { 0x06, 0x006e },
2086 { 0x08, 0x0708 },
2087 { 0x15, 0x4000 },
2088 { 0x18, 0x65c7 },
1da177e4 2089
0b9b571d 2090 { 0x1f, 0x0001 },
2091 { 0x03, 0x00a1 },
2092 { 0x02, 0x0008 },
2093 { 0x01, 0x0120 },
2094 { 0x00, 0x1000 },
2095 { 0x04, 0x0800 },
2096 { 0x04, 0x0000 },
1da177e4 2097
0b9b571d 2098 { 0x03, 0xff41 },
2099 { 0x02, 0xdf60 },
2100 { 0x01, 0x0140 },
2101 { 0x00, 0x0077 },
2102 { 0x04, 0x7800 },
2103 { 0x04, 0x7000 },
2104
2105 { 0x03, 0x802f },
2106 { 0x02, 0x4f02 },
2107 { 0x01, 0x0409 },
2108 { 0x00, 0xf0f9 },
2109 { 0x04, 0x9800 },
2110 { 0x04, 0x9000 },
2111
2112 { 0x03, 0xdf01 },
2113 { 0x02, 0xdf20 },
2114 { 0x01, 0xff95 },
2115 { 0x00, 0xba00 },
2116 { 0x04, 0xa800 },
2117 { 0x04, 0xa000 },
2118
2119 { 0x03, 0xff41 },
2120 { 0x02, 0xdf20 },
2121 { 0x01, 0x0140 },
2122 { 0x00, 0x00bb },
2123 { 0x04, 0xb800 },
2124 { 0x04, 0xb000 },
2125
2126 { 0x03, 0xdf41 },
2127 { 0x02, 0xdc60 },
2128 { 0x01, 0x6340 },
2129 { 0x00, 0x007d },
2130 { 0x04, 0xd800 },
2131 { 0x04, 0xd000 },
2132
2133 { 0x03, 0xdf01 },
2134 { 0x02, 0xdf20 },
2135 { 0x01, 0x100a },
2136 { 0x00, 0xa0ff },
2137 { 0x04, 0xf800 },
2138 { 0x04, 0xf000 },
2139
2140 { 0x1f, 0x0000 },
2141 { 0x0b, 0x0000 },
2142 { 0x00, 0x9200 }
2143 };
1da177e4 2144
4da19633 2145 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2146}
2147
4da19633 2148static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2149{
350f7596 2150 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2151 { 0x1f, 0x0002 },
2152 { 0x01, 0x90d0 },
2153 { 0x1f, 0x0000 }
2154 };
2155
4da19633 2156 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2157}
2158
4da19633 2159static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2160{
2161 struct pci_dev *pdev = tp->pci_dev;
2162 u16 vendor_id, device_id;
2163
2164 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
2165 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
2166
2167 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
2168 return;
2169
4da19633 2170 rtl_writephy(tp, 0x1f, 0x0001);
2171 rtl_writephy(tp, 0x10, 0xf01b);
2172 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2173}
2174
4da19633 2175static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2176{
350f7596 2177 static const struct phy_reg phy_reg_init[] = {
2e955856 2178 { 0x1f, 0x0001 },
2179 { 0x04, 0x0000 },
2180 { 0x03, 0x00a1 },
2181 { 0x02, 0x0008 },
2182 { 0x01, 0x0120 },
2183 { 0x00, 0x1000 },
2184 { 0x04, 0x0800 },
2185 { 0x04, 0x9000 },
2186 { 0x03, 0x802f },
2187 { 0x02, 0x4f02 },
2188 { 0x01, 0x0409 },
2189 { 0x00, 0xf099 },
2190 { 0x04, 0x9800 },
2191 { 0x04, 0xa000 },
2192 { 0x03, 0xdf01 },
2193 { 0x02, 0xdf20 },
2194 { 0x01, 0xff95 },
2195 { 0x00, 0xba00 },
2196 { 0x04, 0xa800 },
2197 { 0x04, 0xf000 },
2198 { 0x03, 0xdf01 },
2199 { 0x02, 0xdf20 },
2200 { 0x01, 0x101a },
2201 { 0x00, 0xa0ff },
2202 { 0x04, 0xf800 },
2203 { 0x04, 0x0000 },
2204 { 0x1f, 0x0000 },
2205
2206 { 0x1f, 0x0001 },
2207 { 0x10, 0xf41b },
2208 { 0x14, 0xfb54 },
2209 { 0x18, 0xf5c7 },
2210 { 0x1f, 0x0000 },
2211
2212 { 0x1f, 0x0001 },
2213 { 0x17, 0x0cc0 },
2214 { 0x1f, 0x0000 }
2215 };
2216
4da19633 2217 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2218
4da19633 2219 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2220}
2221
4da19633 2222static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2223{
350f7596 2224 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2225 { 0x1f, 0x0001 },
2226 { 0x04, 0x0000 },
2227 { 0x03, 0x00a1 },
2228 { 0x02, 0x0008 },
2229 { 0x01, 0x0120 },
2230 { 0x00, 0x1000 },
2231 { 0x04, 0x0800 },
2232 { 0x04, 0x9000 },
2233 { 0x03, 0x802f },
2234 { 0x02, 0x4f02 },
2235 { 0x01, 0x0409 },
2236 { 0x00, 0xf099 },
2237 { 0x04, 0x9800 },
2238 { 0x04, 0xa000 },
2239 { 0x03, 0xdf01 },
2240 { 0x02, 0xdf20 },
2241 { 0x01, 0xff95 },
2242 { 0x00, 0xba00 },
2243 { 0x04, 0xa800 },
2244 { 0x04, 0xf000 },
2245 { 0x03, 0xdf01 },
2246 { 0x02, 0xdf20 },
2247 { 0x01, 0x101a },
2248 { 0x00, 0xa0ff },
2249 { 0x04, 0xf800 },
2250 { 0x04, 0x0000 },
2251 { 0x1f, 0x0000 },
2252
2253 { 0x1f, 0x0001 },
2254 { 0x0b, 0x8480 },
2255 { 0x1f, 0x0000 },
2256
2257 { 0x1f, 0x0001 },
2258 { 0x18, 0x67c7 },
2259 { 0x04, 0x2000 },
2260 { 0x03, 0x002f },
2261 { 0x02, 0x4360 },
2262 { 0x01, 0x0109 },
2263 { 0x00, 0x3022 },
2264 { 0x04, 0x2800 },
2265 { 0x1f, 0x0000 },
2266
2267 { 0x1f, 0x0001 },
2268 { 0x17, 0x0cc0 },
2269 { 0x1f, 0x0000 }
2270 };
2271
4da19633 2272 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2273}
2274
4da19633 2275static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2276{
350f7596 2277 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2278 { 0x10, 0xf41b },
2279 { 0x1f, 0x0000 }
2280 };
2281
4da19633 2282 rtl_writephy(tp, 0x1f, 0x0001);
2283 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2284
4da19633 2285 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2286}
2287
4da19633 2288static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2289{
350f7596 2290 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2291 { 0x1f, 0x0001 },
2292 { 0x10, 0xf41b },
2293 { 0x1f, 0x0000 }
2294 };
2295
4da19633 2296 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2297}
2298
4da19633 2299static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2300{
350f7596 2301 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2302 { 0x1f, 0x0000 },
2303 { 0x1d, 0x0f00 },
2304 { 0x1f, 0x0002 },
2305 { 0x0c, 0x1ec8 },
2306 { 0x1f, 0x0000 }
2307 };
2308
4da19633 2309 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2310}
2311
4da19633 2312static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2313{
350f7596 2314 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2315 { 0x1f, 0x0001 },
2316 { 0x1d, 0x3d98 },
2317 { 0x1f, 0x0000 }
2318 };
2319
4da19633 2320 rtl_writephy(tp, 0x1f, 0x0000);
2321 rtl_patchphy(tp, 0x14, 1 << 5);
2322 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2323
4da19633 2324 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2325}
2326
4da19633 2327static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2328{
350f7596 2329 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2330 { 0x1f, 0x0001 },
2331 { 0x12, 0x2300 },
867763c1
FR		 2332 { 0x1f, 0x0002 },
2333 { 0x00, 0x88d4 },
2334 { 0x01, 0x82b1 },
2335 { 0x03, 0x7002 },
2336 { 0x08, 0x9e30 },
2337 { 0x09, 0x01f0 },
2338 { 0x0a, 0x5500 },
2339 { 0x0c, 0x00c8 },
2340 { 0x1f, 0x0003 },
2341 { 0x12, 0xc096 },
2342 { 0x16, 0x000a },
f50d4275
FR		 2343 { 0x1f, 0x0000 },
2344 { 0x1f, 0x0000 },
2345 { 0x09, 0x2000 },
2346 { 0x09, 0x0000 }
867763c1
FR		 2347 };
2348
4da19633 2349 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2350
4da19633 2351 rtl_patchphy(tp, 0x14, 1 << 5);
2352 rtl_patchphy(tp, 0x0d, 1 << 5);
2353 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2354}
2355
4da19633 2356static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2357{
350f7596 2358 static const struct phy_reg phy_reg_init[] = {
f50d4275 2359 { 0x1f, 0x0001 },
7da97ec9 2360 { 0x12, 0x2300 },
f50d4275
FR		 2361 { 0x03, 0x802f },
2362 { 0x02, 0x4f02 },
2363 { 0x01, 0x0409 },
2364 { 0x00, 0xf099 },
2365 { 0x04, 0x9800 },
2366 { 0x04, 0x9000 },
2367 { 0x1d, 0x3d98 },
7da97ec9
FR		 2368 { 0x1f, 0x0002 },
2369 { 0x0c, 0x7eb8 },
f50d4275
FR		 2370 { 0x06, 0x0761 },
2371 { 0x1f, 0x0003 },
2372 { 0x16, 0x0f0a },
7da97ec9
FR		 2373 { 0x1f, 0x0000 }
2374 };
2375
4da19633 2376 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2377
4da19633 2378 rtl_patchphy(tp, 0x16, 1 << 0);
2379 rtl_patchphy(tp, 0x14, 1 << 5);
2380 rtl_patchphy(tp, 0x0d, 1 << 5);
2381 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2382}
2383
4da19633 2384static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2385{
350f7596 2386 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2387 { 0x1f, 0x0001 },
2388 { 0x12, 0x2300 },
2389 { 0x1d, 0x3d98 },
2390 { 0x1f, 0x0002 },
2391 { 0x0c, 0x7eb8 },
2392 { 0x06, 0x5461 },
2393 { 0x1f, 0x0003 },
2394 { 0x16, 0x0f0a },
2395 { 0x1f, 0x0000 }
2396 };
2397
4da19633 2398 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2399
4da19633 2400 rtl_patchphy(tp, 0x16, 1 << 0);
2401 rtl_patchphy(tp, 0x14, 1 << 5);
2402 rtl_patchphy(tp, 0x0d, 1 << 5);
2403 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2404}
2405
4da19633 2406static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2407{
4da19633 2408 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2409}
2410
bca03d5f 2411static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2412{
350f7596 2413 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2414 /* Channel Estimation */
5b538df9 2415 { 0x1f, 0x0001 },
daf9df6d 2416 { 0x06, 0x4064 },
2417 { 0x07, 0x2863 },
2418 { 0x08, 0x059c },
2419 { 0x09, 0x26b4 },
2420 { 0x0a, 0x6a19 },
2421 { 0x0b, 0xdcc8 },
2422 { 0x10, 0xf06d },
2423 { 0x14, 0x7f68 },
2424 { 0x18, 0x7fd9 },
2425 { 0x1c, 0xf0ff },
2426 { 0x1d, 0x3d9c },
5b538df9 2427 { 0x1f, 0x0003 },
daf9df6d 2428 { 0x12, 0xf49f },
2429 { 0x13, 0x070b },
2430 { 0x1a, 0x05ad },
bca03d5f 2431 { 0x14, 0x94c0 },
2432
2433 /*
2434 * Tx Error Issue
cecb5fd7 2435 * Enhance line driver power
bca03d5f 2436 */
5b538df9 2437 { 0x1f, 0x0002 },
daf9df6d 2438 { 0x06, 0x5561 },
2439 { 0x1f, 0x0005 },
2440 { 0x05, 0x8332 },
bca03d5f 2441 { 0x06, 0x5561 },
2442
2443 /*
2444 * Can not link to 1Gbps with bad cable
2445 * Decrease SNR threshold form 21.07dB to 19.04dB
2446 */
2447 { 0x1f, 0x0001 },
2448 { 0x17, 0x0cc0 },
daf9df6d 2449
5b538df9 2450 { 0x1f, 0x0000 },
bca03d5f 2451 { 0x0d, 0xf880 }
daf9df6d 2452 };
bca03d5f 2453 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 2454
4da19633 2455 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2456
bca03d5f 2457 /*
2458 * Rx Error Issue
2459 * Fine Tune Switching regulator parameter
2460 */
4da19633 2461 rtl_writephy(tp, 0x1f, 0x0002);
2462 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2463 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2464
daf9df6d 2465 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2466 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2467 { 0x1f, 0x0002 },
2468 { 0x05, 0x669a },
2469 { 0x1f, 0x0005 },
2470 { 0x05, 0x8330 },
2471 { 0x06, 0x669a },
2472 { 0x1f, 0x0002 }
2473 };
2474 int val;
2475
4da19633 2476 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2477
4da19633 2478 val = rtl_readphy(tp, 0x0d);
daf9df6d 2479
2480 if ((val & 0x00ff) != 0x006c) {
350f7596 2481 static const u32 set[] = {
daf9df6d 2482 0x0065, 0x0066, 0x0067, 0x0068,
2483 0x0069, 0x006a, 0x006b, 0x006c
2484 };
2485 int i;
2486
4da19633 2487 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2488
2489 val &= 0xff00;
2490 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2491 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2492 }
2493 } else {
350f7596 2494 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2495 { 0x1f, 0x0002 },
2496 { 0x05, 0x6662 },
2497 { 0x1f, 0x0005 },
2498 { 0x05, 0x8330 },
2499 { 0x06, 0x6662 }
2500 };
2501
4da19633 2502 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2503 }
2504
bca03d5f 2505 /* RSET couple improve */
4da19633 2506 rtl_writephy(tp, 0x1f, 0x0002);
2507 rtl_patchphy(tp, 0x0d, 0x0300);
2508 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2509
bca03d5f 2510 /* Fine tune PLL performance */
4da19633 2511 rtl_writephy(tp, 0x1f, 0x0002);
2512 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2513 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2514
4da19633 2515 rtl_writephy(tp, 0x1f, 0x0005);
2516 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2517
2518 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2519
4da19633 2520 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2521}
2522
bca03d5f 2523static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2524{
350f7596 2525 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2526 /* Channel Estimation */
daf9df6d 2527 { 0x1f, 0x0001 },
2528 { 0x06, 0x4064 },
2529 { 0x07, 0x2863 },
2530 { 0x08, 0x059c },
2531 { 0x09, 0x26b4 },
2532 { 0x0a, 0x6a19 },
2533 { 0x0b, 0xdcc8 },
2534 { 0x10, 0xf06d },
2535 { 0x14, 0x7f68 },
2536 { 0x18, 0x7fd9 },
2537 { 0x1c, 0xf0ff },
2538 { 0x1d, 0x3d9c },
2539 { 0x1f, 0x0003 },
2540 { 0x12, 0xf49f },
2541 { 0x13, 0x070b },
2542 { 0x1a, 0x05ad },
2543 { 0x14, 0x94c0 },
2544
bca03d5f 2545 /*
2546 * Tx Error Issue
cecb5fd7 2547 * Enhance line driver power
bca03d5f 2548 */
daf9df6d 2549 { 0x1f, 0x0002 },
2550 { 0x06, 0x5561 },
2551 { 0x1f, 0x0005 },
2552 { 0x05, 0x8332 },
bca03d5f 2553 { 0x06, 0x5561 },
2554
2555 /*
2556 * Can not link to 1Gbps with bad cable
2557 * Decrease SNR threshold form 21.07dB to 19.04dB
2558 */
2559 { 0x1f, 0x0001 },
2560 { 0x17, 0x0cc0 },
daf9df6d 2561
2562 { 0x1f, 0x0000 },
bca03d5f 2563 { 0x0d, 0xf880 }
5b538df9 2564 };
bca03d5f 2565 void __iomem *ioaddr = tp->mmio_addr;
5b538df9 2566
4da19633 2567 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2568
daf9df6d 2569 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2570 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2571 { 0x1f, 0x0002 },
2572 { 0x05, 0x669a },
5b538df9 2573 { 0x1f, 0x0005 },
daf9df6d 2574 { 0x05, 0x8330 },
2575 { 0x06, 0x669a },
2576
2577 { 0x1f, 0x0002 }
2578 };
2579 int val;
2580
4da19633 2581 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2582
4da19633 2583 val = rtl_readphy(tp, 0x0d);
daf9df6d 2584 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2585 static const u32 set[] = {
daf9df6d 2586 0x0065, 0x0066, 0x0067, 0x0068,
2587 0x0069, 0x006a, 0x006b, 0x006c
2588 };
2589 int i;
2590
4da19633 2591 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2592
2593 val &= 0xff00;
2594 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2595 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2596 }
2597 } else {
350f7596 2598 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2599 { 0x1f, 0x0002 },
2600 { 0x05, 0x2642 },
5b538df9 2601 { 0x1f, 0x0005 },
daf9df6d 2602 { 0x05, 0x8330 },
2603 { 0x06, 0x2642 }
5b538df9
FR		 2604 };
2605
4da19633 2606 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2607 }
2608
bca03d5f 2609 /* Fine tune PLL performance */
4da19633 2610 rtl_writephy(tp, 0x1f, 0x0002);
2611 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2612 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2613
bca03d5f 2614 /* Switching regulator Slew rate */
4da19633 2615 rtl_writephy(tp, 0x1f, 0x0002);
2616 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2617
4da19633 2618 rtl_writephy(tp, 0x1f, 0x0005);
2619 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2620
2621 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2622
4da19633 2623 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2624}
2625
4da19633 2626static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2627{
350f7596 2628 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2629 { 0x1f, 0x0002 },
2630 { 0x10, 0x0008 },
2631 { 0x0d, 0x006c },
2632
2633 { 0x1f, 0x0000 },
2634 { 0x0d, 0xf880 },
2635
2636 { 0x1f, 0x0001 },
2637 { 0x17, 0x0cc0 },
2638
2639 { 0x1f, 0x0001 },
2640 { 0x0b, 0xa4d8 },
2641 { 0x09, 0x281c },
2642 { 0x07, 0x2883 },
2643 { 0x0a, 0x6b35 },
2644 { 0x1d, 0x3da4 },
2645 { 0x1c, 0xeffd },
2646 { 0x14, 0x7f52 },
2647 { 0x18, 0x7fc6 },
2648 { 0x08, 0x0601 },
2649 { 0x06, 0x4063 },
2650 { 0x10, 0xf074 },
2651 { 0x1f, 0x0003 },
2652 { 0x13, 0x0789 },
2653 { 0x12, 0xf4bd },
2654 { 0x1a, 0x04fd },
2655 { 0x14, 0x84b0 },
2656 { 0x1f, 0x0000 },
2657 { 0x00, 0x9200 },
2658
2659 { 0x1f, 0x0005 },
2660 { 0x01, 0x0340 },
2661 { 0x1f, 0x0001 },
2662 { 0x04, 0x4000 },
2663 { 0x03, 0x1d21 },
2664 { 0x02, 0x0c32 },
2665 { 0x01, 0x0200 },
2666 { 0x00, 0x5554 },
2667 { 0x04, 0x4800 },
2668 { 0x04, 0x4000 },
2669 { 0x04, 0xf000 },
2670 { 0x03, 0xdf01 },
2671 { 0x02, 0xdf20 },
2672 { 0x01, 0x101a },
2673 { 0x00, 0xa0ff },
2674 { 0x04, 0xf800 },
2675 { 0x04, 0xf000 },
2676 { 0x1f, 0x0000 },
2677
2678 { 0x1f, 0x0007 },
2679 { 0x1e, 0x0023 },
2680 { 0x16, 0x0000 },
2681 { 0x1f, 0x0000 }
2682 };
2683
4da19633 2684 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2685}
2686
e6de30d6 2687static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2688{
2689 static const struct phy_reg phy_reg_init[] = {
2690 { 0x1f, 0x0001 },
2691 { 0x17, 0x0cc0 },
2692
2693 { 0x1f, 0x0007 },
2694 { 0x1e, 0x002d },
2695 { 0x18, 0x0040 },
2696 { 0x1f, 0x0000 }
2697 };
2698
2699 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2700 rtl_patchphy(tp, 0x0d, 1 << 5);
2701}
2702
70090424 2703static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 2704{
2705 static const struct phy_reg phy_reg_init[] = {
2706 /* Enable Delay cap */
2707 { 0x1f, 0x0005 },
2708 { 0x05, 0x8b80 },
2709 { 0x06, 0xc896 },
2710 { 0x1f, 0x0000 },
2711
2712 /* Channel estimation fine tune */
2713 { 0x1f, 0x0001 },
2714 { 0x0b, 0x6c20 },
2715 { 0x07, 0x2872 },
2716 { 0x1c, 0xefff },
2717 { 0x1f, 0x0003 },
2718 { 0x14, 0x6420 },
2719 { 0x1f, 0x0000 },
2720
2721 /* Update PFM & 10M TX idle timer */
2722 { 0x1f, 0x0007 },
2723 { 0x1e, 0x002f },
2724 { 0x15, 0x1919 },
2725 { 0x1f, 0x0000 },
2726
2727 { 0x1f, 0x0007 },
2728 { 0x1e, 0x00ac },
2729 { 0x18, 0x0006 },
2730 { 0x1f, 0x0000 }
2731 };
2732
15ecd039
FR		 2733 rtl_apply_firmware(tp);
2734
01dc7fec 2735 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2736
2737 /* DCO enable for 10M IDLE Power */
2738 rtl_writephy(tp, 0x1f, 0x0007);
2739 rtl_writephy(tp, 0x1e, 0x0023);
2740 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2741 rtl_writephy(tp, 0x1f, 0x0000);
2742
2743 /* For impedance matching */
2744 rtl_writephy(tp, 0x1f, 0x0002);
2745 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 2746 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 2747
2748 /* PHY auto speed down */
2749 rtl_writephy(tp, 0x1f, 0x0007);
2750 rtl_writephy(tp, 0x1e, 0x002d);
2751 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2752 rtl_writephy(tp, 0x1f, 0x0000);
2753 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2754
2755 rtl_writephy(tp, 0x1f, 0x0005);
2756 rtl_writephy(tp, 0x05, 0x8b86);
2757 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2758 rtl_writephy(tp, 0x1f, 0x0000);
2759
2760 rtl_writephy(tp, 0x1f, 0x0005);
2761 rtl_writephy(tp, 0x05, 0x8b85);
2762 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2763 rtl_writephy(tp, 0x1f, 0x0007);
2764 rtl_writephy(tp, 0x1e, 0x0020);
2765 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2766 rtl_writephy(tp, 0x1f, 0x0006);
2767 rtl_writephy(tp, 0x00, 0x5a00);
2768 rtl_writephy(tp, 0x1f, 0x0000);
2769 rtl_writephy(tp, 0x0d, 0x0007);
2770 rtl_writephy(tp, 0x0e, 0x003c);
2771 rtl_writephy(tp, 0x0d, 0x4007);
2772 rtl_writephy(tp, 0x0e, 0x0000);
2773 rtl_writephy(tp, 0x0d, 0x0000);
2774}
2775
70090424
HW		 2776static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2777{
2778 static const struct phy_reg phy_reg_init[] = {
2779 /* Enable Delay cap */
2780 { 0x1f, 0x0004 },
2781 { 0x1f, 0x0007 },
2782 { 0x1e, 0x00ac },
2783 { 0x18, 0x0006 },
2784 { 0x1f, 0x0002 },
2785 { 0x1f, 0x0000 },
2786 { 0x1f, 0x0000 },
2787
2788 /* Channel estimation fine tune */
2789 { 0x1f, 0x0003 },
2790 { 0x09, 0xa20f },
2791 { 0x1f, 0x0000 },
2792 { 0x1f, 0x0000 },
2793
2794 /* Green Setting */
2795 { 0x1f, 0x0005 },
2796 { 0x05, 0x8b5b },
2797 { 0x06, 0x9222 },
2798 { 0x05, 0x8b6d },
2799 { 0x06, 0x8000 },
2800 { 0x05, 0x8b76 },
2801 { 0x06, 0x8000 },
2802 { 0x1f, 0x0000 }
2803 };
2804
2805 rtl_apply_firmware(tp);
2806
2807 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2808
2809 /* For 4-corner performance improve */
2810 rtl_writephy(tp, 0x1f, 0x0005);
2811 rtl_writephy(tp, 0x05, 0x8b80);
2812 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2813 rtl_writephy(tp, 0x1f, 0x0000);
2814
2815 /* PHY auto speed down */
2816 rtl_writephy(tp, 0x1f, 0x0004);
2817 rtl_writephy(tp, 0x1f, 0x0007);
2818 rtl_writephy(tp, 0x1e, 0x002d);
2819 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2820 rtl_writephy(tp, 0x1f, 0x0002);
2821 rtl_writephy(tp, 0x1f, 0x0000);
2822 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2823
2824 /* improve 10M EEE waveform */
2825 rtl_writephy(tp, 0x1f, 0x0005);
2826 rtl_writephy(tp, 0x05, 0x8b86);
2827 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2828 rtl_writephy(tp, 0x1f, 0x0000);
2829
2830 /* Improve 2-pair detection performance */
2831 rtl_writephy(tp, 0x1f, 0x0005);
2832 rtl_writephy(tp, 0x05, 0x8b85);
2833 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2834 rtl_writephy(tp, 0x1f, 0x0000);
2835
2836 /* EEE setting */
2837 rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
2838 ERIAR_EXGMAC);
2839 rtl_writephy(tp, 0x1f, 0x0005);
2840 rtl_writephy(tp, 0x05, 0x8b85);
2841 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2842 rtl_writephy(tp, 0x1f, 0x0004);
2843 rtl_writephy(tp, 0x1f, 0x0007);
2844 rtl_writephy(tp, 0x1e, 0x0020);
2845 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
2846 rtl_writephy(tp, 0x1f, 0x0002);
2847 rtl_writephy(tp, 0x1f, 0x0000);
2848 rtl_writephy(tp, 0x0d, 0x0007);
2849 rtl_writephy(tp, 0x0e, 0x003c);
2850 rtl_writephy(tp, 0x0d, 0x4007);
2851 rtl_writephy(tp, 0x0e, 0x0000);
2852 rtl_writephy(tp, 0x0d, 0x0000);
2853
2854 /* Green feature */
2855 rtl_writephy(tp, 0x1f, 0x0003);
2856 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
2857 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
2858 rtl_writephy(tp, 0x1f, 0x0000);
2859}
2860
4da19633 2861static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 2862{
350f7596 2863 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 2864 { 0x1f, 0x0003 },
2865 { 0x08, 0x441d },
2866 { 0x01, 0x9100 },
2867 { 0x1f, 0x0000 }
2868 };
2869
4da19633 2870 rtl_writephy(tp, 0x1f, 0x0000);
2871 rtl_patchphy(tp, 0x11, 1 << 12);
2872 rtl_patchphy(tp, 0x19, 1 << 13);
2873 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 2874
4da19633 2875 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 2876}
2877
5a5e4443
HW		 2878static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2879{
2880 static const struct phy_reg phy_reg_init[] = {
2881 { 0x1f, 0x0005 },
2882 { 0x1a, 0x0000 },
2883 { 0x1f, 0x0000 },
2884
2885 { 0x1f, 0x0004 },
2886 { 0x1c, 0x0000 },
2887 { 0x1f, 0x0000 },
2888
2889 { 0x1f, 0x0001 },
2890 { 0x15, 0x7701 },
2891 { 0x1f, 0x0000 }
2892 };
2893
2894 /* Disable ALDPS before ram code */
2895 rtl_writephy(tp, 0x1f, 0x0000);
2896 rtl_writephy(tp, 0x18, 0x0310);
2897 msleep(100);
2898
953a12cc 2899 rtl_apply_firmware(tp);
5a5e4443
HW		 2900
2901 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2902}
2903
5615d9f1
FR		 2904static void rtl_hw_phy_config(struct net_device *dev)
2905{
2906 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 2907
2908 rtl8169_print_mac_version(tp);
2909
2910 switch (tp->mac_version) {
2911 case RTL_GIGA_MAC_VER_01:
2912 break;
2913 case RTL_GIGA_MAC_VER_02:
2914 case RTL_GIGA_MAC_VER_03:
4da19633 2915 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 2916 break;
2917 case RTL_GIGA_MAC_VER_04:
4da19633 2918 rtl8169sb_hw_phy_config(tp);
5615d9f1 2919 break;
2e955856 2920 case RTL_GIGA_MAC_VER_05:
4da19633 2921 rtl8169scd_hw_phy_config(tp);
2e955856 2922 break;
8c7006aa 2923 case RTL_GIGA_MAC_VER_06:
4da19633 2924 rtl8169sce_hw_phy_config(tp);
8c7006aa 2925 break;
2857ffb7
FR		 2926 case RTL_GIGA_MAC_VER_07:
2927 case RTL_GIGA_MAC_VER_08:
2928 case RTL_GIGA_MAC_VER_09:
4da19633 2929 rtl8102e_hw_phy_config(tp);
2857ffb7 2930 break;
236b8082 2931 case RTL_GIGA_MAC_VER_11:
4da19633 2932 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 2933 break;
2934 case RTL_GIGA_MAC_VER_12:
4da19633 2935 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 2936 break;
2937 case RTL_GIGA_MAC_VER_17:
4da19633 2938 rtl8168bef_hw_phy_config(tp);
236b8082 2939 break;
867763c1 2940 case RTL_GIGA_MAC_VER_18:
4da19633 2941 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 2942 break;
2943 case RTL_GIGA_MAC_VER_19:
4da19633 2944 rtl8168c_1_hw_phy_config(tp);
867763c1 2945 break;
7da97ec9 2946 case RTL_GIGA_MAC_VER_20:
4da19633 2947 rtl8168c_2_hw_phy_config(tp);
7da97ec9 2948 break;
197ff761 2949 case RTL_GIGA_MAC_VER_21:
4da19633 2950 rtl8168c_3_hw_phy_config(tp);
197ff761 2951 break;
6fb07058 2952 case RTL_GIGA_MAC_VER_22:
4da19633 2953 rtl8168c_4_hw_phy_config(tp);
6fb07058 2954 break;
ef3386f0 2955 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 2956 case RTL_GIGA_MAC_VER_24:
4da19633 2957 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 2958 break;
5b538df9 2959 case RTL_GIGA_MAC_VER_25:
bca03d5f 2960 rtl8168d_1_hw_phy_config(tp);
daf9df6d 2961 break;
2962 case RTL_GIGA_MAC_VER_26:
bca03d5f 2963 rtl8168d_2_hw_phy_config(tp);
daf9df6d 2964 break;
2965 case RTL_GIGA_MAC_VER_27:
4da19633 2966 rtl8168d_3_hw_phy_config(tp);
5b538df9 2967 break;
e6de30d6 2968 case RTL_GIGA_MAC_VER_28:
2969 rtl8168d_4_hw_phy_config(tp);
2970 break;
5a5e4443
HW		 2971 case RTL_GIGA_MAC_VER_29:
2972 case RTL_GIGA_MAC_VER_30:
2973 rtl8105e_hw_phy_config(tp);
2974 break;
cecb5fd7
FR		 2975 case RTL_GIGA_MAC_VER_31:
2976 /* None. */
2977 break;
01dc7fec 2978 case RTL_GIGA_MAC_VER_32:
01dc7fec 2979 case RTL_GIGA_MAC_VER_33:
70090424
HW		 2980 rtl8168e_1_hw_phy_config(tp);
2981 break;
2982 case RTL_GIGA_MAC_VER_34:
2983 rtl8168e_2_hw_phy_config(tp);
01dc7fec 2984 break;
ef3386f0 2985
5615d9f1
FR		 2986 default:
2987 break;
2988 }
2989}
2990
1da177e4
LT		 2991static void rtl8169_phy_timer(unsigned long __opaque)
2992{
2993 struct net_device *dev = (struct net_device *)__opaque;
2994 struct rtl8169_private *tp = netdev_priv(dev);
2995 struct timer_list *timer = &tp->timer;
2996 void __iomem *ioaddr = tp->mmio_addr;
2997 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2998
bcf0bf90 2999 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 3000
1da177e4
LT		 3001 spin_lock_irq(&tp->lock);
3002
4da19633 3003 if (tp->phy_reset_pending(tp)) {
5b0384f4 3004 /*
1da177e4
LT		 3005 * A busy loop could burn quite a few cycles on nowadays CPU.
3006 * Let's delay the execution of the timer for a few ticks.
3007 */
3008 timeout = HZ/10;
3009 goto out_mod_timer;
3010 }
3011
3012 if (tp->link_ok(ioaddr))
3013 goto out_unlock;
3014
bf82c189 3015 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4 3016
4da19633 3017 tp->phy_reset_enable(tp);
1da177e4
LT		 3018
3019out_mod_timer:
3020 mod_timer(timer, jiffies + timeout);
3021out_unlock:
3022 spin_unlock_irq(&tp->lock);
3023}
3024
1da177e4
LT		 3025#ifdef CONFIG_NET_POLL_CONTROLLER
3026/*
3027 * Polling 'interrupt' - used by things like netconsole to send skbs
3028 * without having to re-enable interrupts. It's not called while
3029 * the interrupt routine is executing.
3030 */
3031static void rtl8169_netpoll(struct net_device *dev)
3032{
3033 struct rtl8169_private *tp = netdev_priv(dev);
3034 struct pci_dev *pdev = tp->pci_dev;
3035
3036 disable_irq(pdev->irq);
7d12e780 3037 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 3038 enable_irq(pdev->irq);
3039}
3040#endif
3041
3042static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3043 void __iomem *ioaddr)
3044{
3045 iounmap(ioaddr);
3046 pci_release_regions(pdev);
87aeec76 3047 pci_clear_mwi(pdev);
1da177e4
LT		 3048 pci_disable_device(pdev);
3049 free_netdev(dev);
3050}
3051
bf793295
FR		 3052static void rtl8169_phy_reset(struct net_device *dev,
3053 struct rtl8169_private *tp)
3054{
07d3f51f 3055 unsigned int i;
bf793295 3056
4da19633 3057 tp->phy_reset_enable(tp);
bf793295 3058 for (i = 0; i < 100; i++) {
4da19633 3059 if (!tp->phy_reset_pending(tp))
bf793295
FR		 3060 return;
3061 msleep(1);
3062 }
bf82c189 3063 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 3064}
3065
4ff96fa6
FR		 3066static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3067{
3068 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 3069
5615d9f1 3070 rtl_hw_phy_config(dev);
4ff96fa6 3071
77332894
MS		 3072 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3073 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3074 RTL_W8(0x82, 0x01);
3075 }
4ff96fa6 3076
6dccd16b
FR		 3077 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3078
3079 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3080 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 3081
bcf0bf90 3082 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 3083 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3084 RTL_W8(0x82, 0x01);
3085 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 3086 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 3087 }
3088
bf793295
FR		 3089 rtl8169_phy_reset(dev, tp);
3090
54405cde 3091 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 3092 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3093 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3094 (tp->mii.supports_gmii ?
3095 ADVERTISED_1000baseT_Half |
3096 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 3097
bf82c189
JP		 3098 if (RTL_R8(PHYstatus) & TBI_Enable)
3099 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 3100}
3101
773d2021
FR		 3102static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3103{
3104 void __iomem *ioaddr = tp->mmio_addr;
3105 u32 high;
3106 u32 low;
3107
3108 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3109 high = addr[4] | (addr[5] << 8);
3110
3111 spin_lock_irq(&tp->lock);
3112
3113 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 3114
773d2021 3115 RTL_W32(MAC4, high);
908ba2bf 3116 RTL_R32(MAC4);
3117
78f1cd02 3118 RTL_W32(MAC0, low);
908ba2bf 3119 RTL_R32(MAC0);
3120
773d2021
FR		 3121 RTL_W8(Cfg9346, Cfg9346_Lock);
3122
3123 spin_unlock_irq(&tp->lock);
3124}
3125
3126static int rtl_set_mac_address(struct net_device *dev, void *p)
3127{
3128 struct rtl8169_private *tp = netdev_priv(dev);
3129 struct sockaddr *addr = p;
3130
3131 if (!is_valid_ether_addr(addr->sa_data))
3132 return -EADDRNOTAVAIL;
3133
3134 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3135
3136 rtl_rar_set(tp, dev->dev_addr);
3137
3138 return 0;
3139}
3140
5f787a1a
FR		 3141static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3142{
3143 struct rtl8169_private *tp = netdev_priv(dev);
3144 struct mii_ioctl_data *data = if_mii(ifr);
3145
8b4ab28d
FR		 3146 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3147}
5f787a1a 3148
cecb5fd7
FR		 3149static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3150 struct mii_ioctl_data *data, int cmd)
8b4ab28d 3151{
5f787a1a
FR		 3152 switch (cmd) {
3153 case SIOCGMIIPHY:
3154 data->phy_id = 32; /* Internal PHY */
3155 return 0;
3156
3157 case SIOCGMIIREG:
4da19633 3158 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 3159 return 0;
3160
3161 case SIOCSMIIREG:
4da19633 3162 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 3163 return 0;
3164 }
3165 return -EOPNOTSUPP;
3166}
3167
8b4ab28d
FR		 3168static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3169{
3170 return -EOPNOTSUPP;
3171}
3172
0e485150
FR		 3173static const struct rtl_cfg_info {
3174 void (*hw_start)(struct net_device *);
3175 unsigned int region;
3176 unsigned int align;
3177 u16 intr_event;
3178 u16 napi_event;
ccdffb9a 3179 unsigned features;
f21b75e9 3180 u8 default_ver;
0e485150
FR		 3181} rtl_cfg_infos [] = {
3182 [RTL_CFG_0] = {
3183 .hw_start = rtl_hw_start_8169,
3184 .region = 1,
e9f63f30 3185 .align = 0,
0e485150
FR		 3186 .intr_event = SYSErr | LinkChg | RxOverflow |
3187 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 3188 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 3189 .features = RTL_FEATURE_GMII,
3190 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 3191 },
3192 [RTL_CFG_1] = {
3193 .hw_start = rtl_hw_start_8168,
3194 .region = 2,
3195 .align = 8,
53f57357 3196 .intr_event = SYSErr | LinkChg | RxOverflow |
0e485150 3197 TxErr | TxOK | RxOK | RxErr,
fbac58fc 3198 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 3199 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3200 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 3201 },
3202 [RTL_CFG_2] = {
3203 .hw_start = rtl_hw_start_8101,
3204 .region = 2,
3205 .align = 8,
3206 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
3207 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 3208 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 3209 .features = RTL_FEATURE_MSI,
3210 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 3211 }
3212};
3213
fbac58fc
FR		 3214/* Cfg9346_Unlock assumed. */
3215static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
3216 const struct rtl_cfg_info *cfg)
3217{
3218 unsigned msi = 0;
3219 u8 cfg2;
3220
3221 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 3222 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 3223 if (pci_enable_msi(pdev)) {
3224 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
3225 } else {
3226 cfg2 |= MSIEnable;
3227 msi = RTL_FEATURE_MSI;
3228 }
3229 }
3230 RTL_W8(Config2, cfg2);
3231 return msi;
3232}
3233
3234static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3235{
3236 if (tp->features & RTL_FEATURE_MSI) {
3237 pci_disable_msi(pdev);
3238 tp->features &= ~RTL_FEATURE_MSI;
3239 }
3240}
3241
8b4ab28d
FR		 3242static const struct net_device_ops rtl8169_netdev_ops = {
3243 .ndo_open = rtl8169_open,
3244 .ndo_stop = rtl8169_close,
3245 .ndo_get_stats = rtl8169_get_stats,
00829823 3246 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 3247 .ndo_tx_timeout = rtl8169_tx_timeout,
3248 .ndo_validate_addr = eth_validate_addr,
3249 .ndo_change_mtu = rtl8169_change_mtu,
350fb32a
MM		 3250 .ndo_fix_features = rtl8169_fix_features,
3251 .ndo_set_features = rtl8169_set_features,
8b4ab28d
FR		 3252 .ndo_set_mac_address = rtl_set_mac_address,
3253 .ndo_do_ioctl = rtl8169_ioctl,
3254 .ndo_set_multicast_list = rtl_set_rx_mode,
8b4ab28d
FR		 3255#ifdef CONFIG_NET_POLL_CONTROLLER
3256 .ndo_poll_controller = rtl8169_netpoll,
3257#endif
3258
3259};
3260
c0e45c1c 3261static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3262{
3263 struct mdio_ops *ops = &tp->mdio_ops;
3264
3265 switch (tp->mac_version) {
3266 case RTL_GIGA_MAC_VER_27:
3267 ops->write = r8168dp_1_mdio_write;
3268 ops->read = r8168dp_1_mdio_read;
3269 break;
e6de30d6 3270 case RTL_GIGA_MAC_VER_28:
4804b3b3 3271 case RTL_GIGA_MAC_VER_31:
e6de30d6 3272 ops->write = r8168dp_2_mdio_write;
3273 ops->read = r8168dp_2_mdio_read;
3274 break;
c0e45c1c 3275 default:
3276 ops->write = r8169_mdio_write;
3277 ops->read = r8169_mdio_read;
3278 break;
3279 }
3280}
3281
065c27c1 3282static void r810x_phy_power_down(struct rtl8169_private *tp)
3283{
3284 rtl_writephy(tp, 0x1f, 0x0000);
3285 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3286}
3287
3288static void r810x_phy_power_up(struct rtl8169_private *tp)
3289{
3290 rtl_writephy(tp, 0x1f, 0x0000);
3291 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3292}
3293
3294static void r810x_pll_power_down(struct rtl8169_private *tp)
3295{
3296 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3297 rtl_writephy(tp, 0x1f, 0x0000);
3298 rtl_writephy(tp, MII_BMCR, 0x0000);
3299 return;
3300 }
3301
3302 r810x_phy_power_down(tp);
3303}
3304
3305static void r810x_pll_power_up(struct rtl8169_private *tp)
3306{
3307 r810x_phy_power_up(tp);
3308}
3309
3310static void r8168_phy_power_up(struct rtl8169_private *tp)
3311{
3312 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3313 switch (tp->mac_version) {
3314 case RTL_GIGA_MAC_VER_11:
3315 case RTL_GIGA_MAC_VER_12:
3316 case RTL_GIGA_MAC_VER_17:
3317 case RTL_GIGA_MAC_VER_18:
3318 case RTL_GIGA_MAC_VER_19:
3319 case RTL_GIGA_MAC_VER_20:
3320 case RTL_GIGA_MAC_VER_21:
3321 case RTL_GIGA_MAC_VER_22:
3322 case RTL_GIGA_MAC_VER_23:
3323 case RTL_GIGA_MAC_VER_24:
3324 case RTL_GIGA_MAC_VER_25:
3325 case RTL_GIGA_MAC_VER_26:
3326 case RTL_GIGA_MAC_VER_27:
3327 case RTL_GIGA_MAC_VER_28:
3328 case RTL_GIGA_MAC_VER_31:
3329 rtl_writephy(tp, 0x0e, 0x0000);
3330 break;
3331 default:
3332 break;
3333 }
065c27c1 3334 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3335}
3336
3337static void r8168_phy_power_down(struct rtl8169_private *tp)
3338{
3339 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3340 switch (tp->mac_version) {
3341 case RTL_GIGA_MAC_VER_32:
3342 case RTL_GIGA_MAC_VER_33:
3343 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3344 break;
3345
3346 case RTL_GIGA_MAC_VER_11:
3347 case RTL_GIGA_MAC_VER_12:
3348 case RTL_GIGA_MAC_VER_17:
3349 case RTL_GIGA_MAC_VER_18:
3350 case RTL_GIGA_MAC_VER_19:
3351 case RTL_GIGA_MAC_VER_20:
3352 case RTL_GIGA_MAC_VER_21:
3353 case RTL_GIGA_MAC_VER_22:
3354 case RTL_GIGA_MAC_VER_23:
3355 case RTL_GIGA_MAC_VER_24:
3356 case RTL_GIGA_MAC_VER_25:
3357 case RTL_GIGA_MAC_VER_26:
3358 case RTL_GIGA_MAC_VER_27:
3359 case RTL_GIGA_MAC_VER_28:
3360 case RTL_GIGA_MAC_VER_31:
3361 rtl_writephy(tp, 0x0e, 0x0200);
3362 default:
3363 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3364 break;
3365 }
065c27c1 3366}
3367
3368static void r8168_pll_power_down(struct rtl8169_private *tp)
3369{
3370 void __iomem *ioaddr = tp->mmio_addr;
3371
cecb5fd7
FR		 3372 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3373 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3374 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3375 r8168dp_check_dash(tp)) {
065c27c1 3376 return;
5d2e1957 3377 }
065c27c1 3378
cecb5fd7
FR		 3379 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3380 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 3381 (RTL_R16(CPlusCmd) & ASF)) {
3382 return;
3383 }
3384
01dc7fec 3385 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3386 tp->mac_version == RTL_GIGA_MAC_VER_33)
3387 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3388
065c27c1 3389 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3390 rtl_writephy(tp, 0x1f, 0x0000);
3391 rtl_writephy(tp, MII_BMCR, 0x0000);
3392
d4ed95d7
HW		 3393 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3394 tp->mac_version == RTL_GIGA_MAC_VER_33)
3395 RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast |
3396 AcceptMulticast | AcceptMyPhys);
065c27c1 3397 return;
3398 }
3399
3400 r8168_phy_power_down(tp);
3401
3402 switch (tp->mac_version) {
3403 case RTL_GIGA_MAC_VER_25:
3404 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3405 case RTL_GIGA_MAC_VER_27:
3406 case RTL_GIGA_MAC_VER_28:
4804b3b3 3407 case RTL_GIGA_MAC_VER_31:
01dc7fec 3408 case RTL_GIGA_MAC_VER_32:
3409 case RTL_GIGA_MAC_VER_33:
065c27c1 3410 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3411 break;
3412 }
3413}
3414
3415static void r8168_pll_power_up(struct rtl8169_private *tp)
3416{
3417 void __iomem *ioaddr = tp->mmio_addr;
3418
cecb5fd7
FR		 3419 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3420 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3421 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3422 r8168dp_check_dash(tp)) {
065c27c1 3423 return;
5d2e1957 3424 }
065c27c1 3425
3426 switch (tp->mac_version) {
3427 case RTL_GIGA_MAC_VER_25:
3428 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3429 case RTL_GIGA_MAC_VER_27:
3430 case RTL_GIGA_MAC_VER_28:
4804b3b3 3431 case RTL_GIGA_MAC_VER_31:
01dc7fec 3432 case RTL_GIGA_MAC_VER_32:
3433 case RTL_GIGA_MAC_VER_33:
065c27c1 3434 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3435 break;
3436 }
3437
3438 r8168_phy_power_up(tp);
3439}
3440
3441static void rtl_pll_power_op(struct rtl8169_private *tp,
3442 void (*op)(struct rtl8169_private *))
3443{
3444 if (op)
3445 op(tp);
3446}
3447
3448static void rtl_pll_power_down(struct rtl8169_private *tp)
3449{
3450 rtl_pll_power_op(tp, tp->pll_power_ops.down);
3451}
3452
3453static void rtl_pll_power_up(struct rtl8169_private *tp)
3454{
3455 rtl_pll_power_op(tp, tp->pll_power_ops.up);
3456}
3457
3458static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3459{
3460 struct pll_power_ops *ops = &tp->pll_power_ops;
3461
3462 switch (tp->mac_version) {
3463 case RTL_GIGA_MAC_VER_07:
3464 case RTL_GIGA_MAC_VER_08:
3465 case RTL_GIGA_MAC_VER_09:
3466 case RTL_GIGA_MAC_VER_10:
3467 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 3468 case RTL_GIGA_MAC_VER_29:
3469 case RTL_GIGA_MAC_VER_30:
065c27c1 3470 ops->down = r810x_pll_power_down;
3471 ops->up = r810x_pll_power_up;
3472 break;
3473
3474 case RTL_GIGA_MAC_VER_11:
3475 case RTL_GIGA_MAC_VER_12:
3476 case RTL_GIGA_MAC_VER_17:
3477 case RTL_GIGA_MAC_VER_18:
3478 case RTL_GIGA_MAC_VER_19:
3479 case RTL_GIGA_MAC_VER_20:
3480 case RTL_GIGA_MAC_VER_21:
3481 case RTL_GIGA_MAC_VER_22:
3482 case RTL_GIGA_MAC_VER_23:
3483 case RTL_GIGA_MAC_VER_24:
3484 case RTL_GIGA_MAC_VER_25:
3485 case RTL_GIGA_MAC_VER_26:
3486 case RTL_GIGA_MAC_VER_27:
e6de30d6 3487 case RTL_GIGA_MAC_VER_28:
4804b3b3 3488 case RTL_GIGA_MAC_VER_31:
01dc7fec 3489 case RTL_GIGA_MAC_VER_32:
3490 case RTL_GIGA_MAC_VER_33:
70090424 3491 case RTL_GIGA_MAC_VER_34:
065c27c1 3492 ops->down = r8168_pll_power_down;
3493 ops->up = r8168_pll_power_up;
3494 break;
3495
3496 default:
3497 ops->down = NULL;
3498 ops->up = NULL;
3499 break;
3500 }
3501}
3502
e542a226
HW		 3503static void rtl_init_rxcfg(struct rtl8169_private *tp)
3504{
3505 void __iomem *ioaddr = tp->mmio_addr;
3506
3507 switch (tp->mac_version) {
3508 case RTL_GIGA_MAC_VER_01:
3509 case RTL_GIGA_MAC_VER_02:
3510 case RTL_GIGA_MAC_VER_03:
3511 case RTL_GIGA_MAC_VER_04:
3512 case RTL_GIGA_MAC_VER_05:
3513 case RTL_GIGA_MAC_VER_06:
3514 case RTL_GIGA_MAC_VER_10:
3515 case RTL_GIGA_MAC_VER_11:
3516 case RTL_GIGA_MAC_VER_12:
3517 case RTL_GIGA_MAC_VER_13:
3518 case RTL_GIGA_MAC_VER_14:
3519 case RTL_GIGA_MAC_VER_15:
3520 case RTL_GIGA_MAC_VER_16:
3521 case RTL_GIGA_MAC_VER_17:
3522 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3523 break;
3524 case RTL_GIGA_MAC_VER_18:
3525 case RTL_GIGA_MAC_VER_19:
3526 case RTL_GIGA_MAC_VER_20:
3527 case RTL_GIGA_MAC_VER_21:
3528 case RTL_GIGA_MAC_VER_22:
3529 case RTL_GIGA_MAC_VER_23:
3530 case RTL_GIGA_MAC_VER_24:
3531 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3532 break;
3533 default:
3534 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3535 break;
3536 }
3537}
3538
92fc43b4
HW		 3539static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3540{
3541 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3542}
3543
6f43adc8
FR		 3544static void rtl_hw_reset(struct rtl8169_private *tp)
3545{
3546 void __iomem *ioaddr = tp->mmio_addr;
3547 int i;
3548
3549 /* Soft reset the chip. */
3550 RTL_W8(ChipCmd, CmdReset);
3551
3552 /* Check that the chip has finished the reset. */
3553 for (i = 0; i < 100; i++) {
3554 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3555 break;
92fc43b4 3556 udelay(100);
6f43adc8 3557 }
92fc43b4
HW		 3558
3559 rtl8169_init_ring_indexes(tp);
6f43adc8
FR		 3560}
3561
1da177e4 3562static int __devinit
4ff96fa6 3563rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 3564{
0e485150
FR		 3565 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3566 const unsigned int region = cfg->region;
1da177e4 3567 struct rtl8169_private *tp;
ccdffb9a 3568 struct mii_if_info *mii;
4ff96fa6
FR		 3569 struct net_device *dev;
3570 void __iomem *ioaddr;
2b7b4318 3571 int chipset, i;
07d3f51f 3572 int rc;
1da177e4 3573
4ff96fa6
FR		 3574 if (netif_msg_drv(&debug)) {
3575 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3576 MODULENAME, RTL8169_VERSION);
3577 }
1da177e4 3578
1da177e4 3579 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 3580 if (!dev) {
b57b7e5a 3581 if (netif_msg_drv(&debug))
9b91cf9d 3582 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 3583 rc = -ENOMEM;
3584 goto out;
1da177e4
LT		 3585 }
3586
1da177e4 3587 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 3588 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 3589 tp = netdev_priv(dev);
c4028958 3590 tp->dev = dev;
21e197f2 3591 tp->pci_dev = pdev;
b57b7e5a 3592 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 3593
ccdffb9a
FR		 3594 mii = &tp->mii;
3595 mii->dev = dev;
3596 mii->mdio_read = rtl_mdio_read;
3597 mii->mdio_write = rtl_mdio_write;
3598 mii->phy_id_mask = 0x1f;
3599 mii->reg_num_mask = 0x1f;
3600 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3601
ba04c7c9
SG		 3602 /* disable ASPM completely as that cause random device stop working
3603 * problems as well as full system hangs for some PCIe devices users */
3604 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3605 PCIE_LINK_STATE_CLKPM);
3606
1da177e4
LT		 3607 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3608 rc = pci_enable_device(pdev);
b57b7e5a 3609 if (rc < 0) {
bf82c189 3610 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 3611 goto err_out_free_dev_1;
1da177e4
LT		 3612 }
3613
87aeec76 3614 if (pci_set_mwi(pdev) < 0)
3615 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 3616
1da177e4 3617 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 3618 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 3619 netif_err(tp, probe, dev,
3620 "region #%d not an MMIO resource, aborting\n",
3621 region);
1da177e4 3622 rc = -ENODEV;
87aeec76 3623 goto err_out_mwi_2;
1da177e4 3624 }
4ff96fa6 3625
1da177e4 3626 /* check for weird/broken PCI region reporting */
bcf0bf90 3627 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 3628 netif_err(tp, probe, dev,
3629 "Invalid PCI region size(s), aborting\n");
1da177e4 3630 rc = -ENODEV;
87aeec76 3631 goto err_out_mwi_2;
1da177e4
LT		 3632 }
3633
3634 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 3635 if (rc < 0) {
bf82c189 3636 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 3637 goto err_out_mwi_2;
1da177e4
LT		 3638 }
3639
d24e9aaf 3640 tp->cp_cmd = RxChkSum;
1da177e4
LT		 3641
3642 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 3643 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 3644 tp->cp_cmd |= PCIDAC;
3645 dev->features |= NETIF_F_HIGHDMA;
3646 } else {
284901a9 3647 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 3648 if (rc < 0) {
bf82c189 3649 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 3650 goto err_out_free_res_3;
1da177e4
LT		 3651 }
3652 }
3653
1da177e4 3654 /* ioremap MMIO region */
bcf0bf90 3655 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 3656 if (!ioaddr) {
bf82c189 3657 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 3658 rc = -EIO;
87aeec76 3659 goto err_out_free_res_3;
1da177e4 3660 }
6f43adc8 3661 tp->mmio_addr = ioaddr;
1da177e4 3662
e44daade
JM		 3663 if (!pci_is_pcie(pdev))
3664 netif_info(tp, probe, dev, "not PCI Express\n");
4300e8c7 3665
e542a226
HW		 3666 /* Identify chip attached to board */
3667 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
3668
3669 rtl_init_rxcfg(tp);
3670
d78ad8cb 3671 RTL_W16(IntrMask, 0x0000);
1da177e4 3672
6f43adc8 3673 rtl_hw_reset(tp);
1da177e4 3674
d78ad8cb
KW		 3675 RTL_W16(IntrStatus, 0xffff);
3676
ca52efd5 3677 pci_set_master(pdev);
3678
7a8fc77b
FR		 3679 /*
3680 * Pretend we are using VLANs; This bypasses a nasty bug where
3681 * Interrupts stop flowing on high load on 8110SCd controllers.
3682 */
3683 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3684 tp->cp_cmd |= RxVlan;
3685
c0e45c1c 3686 rtl_init_mdio_ops(tp);
065c27c1 3687 rtl_init_pll_power_ops(tp);
c0e45c1c 3688
1da177e4 3689 rtl8169_print_mac_version(tp);
1da177e4 3690
85bffe6c
FR		 3691 chipset = tp->mac_version;
3692 tp->txd_version = rtl_chip_infos[chipset].txd_version;
1da177e4 3693
5d06a99f
FR		 3694 RTL_W8(Cfg9346, Cfg9346_Unlock);
3695 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3696 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 3697 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3698 tp->features |= RTL_FEATURE_WOL;
3699 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3700 tp->features |= RTL_FEATURE_WOL;
fbac58fc 3701 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 3702 RTL_W8(Cfg9346, Cfg9346_Lock);
3703
66ec5d4f
FR		 3704 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3705 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 3706 tp->set_speed = rtl8169_set_speed_tbi;
3707 tp->get_settings = rtl8169_gset_tbi;
3708 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3709 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3710 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 3711 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4
LT		 3712 } else {
3713 tp->set_speed = rtl8169_set_speed_xmii;
3714 tp->get_settings = rtl8169_gset_xmii;
3715 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3716 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3717 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 3718 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 3719 }
3720
df58ef51
FR		 3721 spin_lock_init(&tp->lock);
3722
7bf6bf48 3723 /* Get MAC address */
1da177e4
LT		 3724 for (i = 0; i < MAC_ADDR_LEN; i++)
3725 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 3726 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 3727
1da177e4 3728 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 3729 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3730 dev->irq = pdev->irq;
3731 dev->base_addr = (unsigned long) ioaddr;
1da177e4 3732
bea3348e 3733 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4 3734
350fb32a
MM		 3735 /* don't enable SG, IP_CSUM and TSO by default - it might not work
3736 * properly for all devices */
3737 dev->features |= NETIF_F_RXCSUM |
3738 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3739
3740 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3741 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3742 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3743 NETIF_F_HIGHDMA;
3744
3745 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3746 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3747 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
1da177e4
LT		 3748
3749 tp->intr_mask = 0xffff;
0e485150
FR		 3750 tp->hw_start = cfg->hw_start;
3751 tp->intr_event = cfg->intr_event;
3752 tp->napi_event = cfg->napi_event;
1da177e4 3753
2efa53f3
FR		 3754 init_timer(&tp->timer);
3755 tp->timer.data = (unsigned long) dev;
3756 tp->timer.function = rtl8169_phy_timer;
3757
b6ffd97f 3758 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
953a12cc 3759
1da177e4 3760 rc = register_netdev(dev);
4ff96fa6 3761 if (rc < 0)
87aeec76 3762 goto err_out_msi_4;
1da177e4
LT		 3763
3764 pci_set_drvdata(pdev, dev);
3765
bf82c189 3766 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
85bffe6c 3767 rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
bf82c189 3768 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
1da177e4 3769
cecb5fd7
FR		 3770 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3771 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3772 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 3773 rtl8168_driver_start(tp);
e6de30d6 3774 }
b646d900 3775
8b76ab39 3776 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 3777
f3ec4f87
AS		 3778 if (pci_dev_run_wake(pdev))
3779 pm_runtime_put_noidle(&pdev->dev);
e1759441 3780
0d672e9f
IV		 3781 netif_carrier_off(dev);
3782
4ff96fa6
FR		 3783out:
3784 return rc;
1da177e4 3785
87aeec76 3786err_out_msi_4:
fbac58fc 3787 rtl_disable_msi(pdev, tp);
4ff96fa6 3788 iounmap(ioaddr);
87aeec76 3789err_out_free_res_3:
4ff96fa6 3790 pci_release_regions(pdev);
87aeec76 3791err_out_mwi_2:
4ff96fa6 3792 pci_clear_mwi(pdev);
4ff96fa6
FR		 3793 pci_disable_device(pdev);
3794err_out_free_dev_1:
3795 free_netdev(dev);
3796 goto out;
1da177e4
LT		 3797}
3798
07d3f51f 3799static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3800{
3801 struct net_device *dev = pci_get_drvdata(pdev);
3802 struct rtl8169_private *tp = netdev_priv(dev);
3803
cecb5fd7
FR		 3804 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3805 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3806 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 3807 rtl8168_driver_stop(tp);
e6de30d6 3808 }
b646d900 3809
23f333a2 3810 cancel_delayed_work_sync(&tp->task);
eb2a021c 3811
1da177e4 3812 unregister_netdev(dev);
cc098dc7 3813
953a12cc
FR		 3814 rtl_release_firmware(tp);
3815
f3ec4f87
AS		 3816 if (pci_dev_run_wake(pdev))
3817 pm_runtime_get_noresume(&pdev->dev);
e1759441 3818
cc098dc7
IV		 3819 /* restore original MAC address */
3820 rtl_rar_set(tp, dev->perm_addr);
3821
fbac58fc 3822 rtl_disable_msi(pdev, tp);
1da177e4
LT		 3823 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3824 pci_set_drvdata(pdev, NULL);
3825}
3826
b6ffd97f 3827static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 3828{
b6ffd97f
FR		 3829 struct rtl_fw *rtl_fw;
3830 const char *name;
3831 int rc = -ENOMEM;
953a12cc 3832
b6ffd97f
FR		 3833 name = rtl_lookup_firmware_name(tp);
3834 if (!name)
3835 goto out_no_firmware;
953a12cc 3836
b6ffd97f
FR		 3837 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3838 if (!rtl_fw)
3839 goto err_warn;
31bd204f 3840
b6ffd97f
FR		 3841 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3842 if (rc < 0)
3843 goto err_free;
3844
fd112f2e
FR		 3845 rc = rtl_check_firmware(tp, rtl_fw);
3846 if (rc < 0)
3847 goto err_release_firmware;
3848
b6ffd97f
FR		 3849 tp->rtl_fw = rtl_fw;
3850out:
3851 return;
3852
fd112f2e
FR		 3853err_release_firmware:
3854 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 3855err_free:
3856 kfree(rtl_fw);
3857err_warn:
3858 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3859 name, rc);
3860out_no_firmware:
3861 tp->rtl_fw = NULL;
3862 goto out;
3863}
3864
3865static void rtl_request_firmware(struct rtl8169_private *tp)
3866{
3867 if (IS_ERR(tp->rtl_fw))
3868 rtl_request_uncached_firmware(tp);
953a12cc
FR		 3869}
3870
1da177e4
LT		 3871static int rtl8169_open(struct net_device *dev)
3872{
3873 struct rtl8169_private *tp = netdev_priv(dev);
eee3a96c 3874 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 3875 struct pci_dev *pdev = tp->pci_dev;
99f252b0 3876 int retval = -ENOMEM;
1da177e4 3877
e1759441 3878 pm_runtime_get_sync(&pdev->dev);
1da177e4 3879
1da177e4
LT		 3880 /*
3881 * Rx and Tx desscriptors needs 256 bytes alignment.
82553bb6 3882 * dma_alloc_coherent provides more.
1da177e4 3883 */
82553bb6
SG		 3884 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3885 &tp->TxPhyAddr, GFP_KERNEL);
1da177e4 3886 if (!tp->TxDescArray)
e1759441 3887 goto err_pm_runtime_put;
1da177e4 3888
82553bb6
SG		 3889 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3890 &tp->RxPhyAddr, GFP_KERNEL);
1da177e4 3891 if (!tp->RxDescArray)
99f252b0 3892 goto err_free_tx_0;
1da177e4
LT		 3893
3894 retval = rtl8169_init_ring(dev);
3895 if (retval < 0)
99f252b0 3896 goto err_free_rx_1;
1da177e4 3897
c4028958 3898 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 3899
99f252b0
FR		 3900 smp_mb();
3901
953a12cc
FR		 3902 rtl_request_firmware(tp);
3903
fbac58fc
FR		 3904 retval = request_irq(dev->irq, rtl8169_interrupt,
3905 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 3906 dev->name, dev);
3907 if (retval < 0)
953a12cc 3908 goto err_release_fw_2;
99f252b0 3909
bea3348e 3910 napi_enable(&tp->napi);
bea3348e 3911
eee3a96c 3912 rtl8169_init_phy(dev, tp);
3913
350fb32a 3914 rtl8169_set_features(dev, dev->features);
eee3a96c 3915
065c27c1 3916 rtl_pll_power_up(tp);
3917
07ce4064 3918 rtl_hw_start(dev);
1da177e4 3919
e1759441
RW		 3920 tp->saved_wolopts = 0;
3921 pm_runtime_put_noidle(&pdev->dev);
3922
eee3a96c 3923 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4
LT		 3924out:
3925 return retval;
3926
953a12cc
FR		 3927err_release_fw_2:
3928 rtl_release_firmware(tp);
99f252b0
FR		 3929 rtl8169_rx_clear(tp);
3930err_free_rx_1:
82553bb6
SG		 3931 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3932 tp->RxPhyAddr);
e1759441 3933 tp->RxDescArray = NULL;
99f252b0 3934err_free_tx_0:
82553bb6
SG		 3935 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3936 tp->TxPhyAddr);
e1759441
RW		 3937 tp->TxDescArray = NULL;
3938err_pm_runtime_put:
3939 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 3940 goto out;
3941}
3942
92fc43b4
HW		 3943static void rtl_rx_close(struct rtl8169_private *tp)
3944{
3945 void __iomem *ioaddr = tp->mmio_addr;
3946 u32 rxcfg = RTL_R32(RxConfig);
3947
3948 rxcfg &= ~(AcceptErr | AcceptRunt | AcceptBroadcast | AcceptMulticast |
3949 AcceptMyPhys | AcceptAllPhys);
3950 RTL_W32(RxConfig, rxcfg);
3951}
3952
e6de30d6 3953static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 3954{
e6de30d6 3955 void __iomem *ioaddr = tp->mmio_addr;
3956
1da177e4
LT		 3957 /* Disable interrupts */
3958 rtl8169_irq_mask_and_ack(ioaddr);
3959
92fc43b4
HW		 3960 rtl_rx_close(tp);
3961
5d2e1957 3962 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 3963 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3964 tp->mac_version == RTL_GIGA_MAC_VER_31) {
e6de30d6 3965 while (RTL_R8(TxPoll) & NPQ)
3966 udelay(20);
70090424
HW		 3967 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3968 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
3969 udelay(100);
92fc43b4
HW		 3970 } else {
3971 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
3972 udelay(100);
e6de30d6 3973 }
3974
92fc43b4 3975 rtl_hw_reset(tp);
1da177e4
LT		 3976}
3977
7f796d83 3978static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 3979{
3980 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 3981
3982 /* Set DMA burst size and Interframe Gap Time */
3983 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3984 (InterFrameGap << TxInterFrameGapShift));
3985}
3986
07ce4064 3987static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 3988{
3989 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 3990
07ce4064
FR		 3991 tp->hw_start(dev);
3992
07ce4064
FR		 3993 netif_start_queue(dev);
3994}
3995
7f796d83
FR		 3996static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3997 void __iomem *ioaddr)
3998{
3999 /*
4000 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4001 * register to be written before TxDescAddrLow to work.
4002 * Switching from MMIO to I/O access fixes the issue as well.
4003 */
4004 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 4005 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 4006 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 4007 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4008}
4009
4010static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4011{
4012 u16 cmd;
4013
4014 cmd = RTL_R16(CPlusCmd);
4015 RTL_W16(CPlusCmd, cmd);
4016 return cmd;
4017}
4018
fdd7b4c3 4019static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 4020{
4021 /* Low hurts. Let's disable the filtering. */
207d6e87 4022 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 4023}
4024
6dccd16b
FR		 4025static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4026{
3744100e 4027 static const struct rtl_cfg2_info {
6dccd16b
FR		 4028 u32 mac_version;
4029 u32 clk;
4030 u32 val;
4031 } cfg2_info [] = {
4032 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4033 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4034 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4035 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4036 };
4037 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4038 unsigned int i;
4039 u32 clk;
4040
4041 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 4042 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 4043 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4044 RTL_W32(0x7c, p->val);
4045 break;
4046 }
4047 }
4048}
4049
07ce4064
FR		 4050static void rtl_hw_start_8169(struct net_device *dev)
4051{
4052 struct rtl8169_private *tp = netdev_priv(dev);
4053 void __iomem *ioaddr = tp->mmio_addr;
4054 struct pci_dev *pdev = tp->pci_dev;
07ce4064 4055
9cb427b6
FR		 4056 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4057 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4058 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4059 }
4060
1da177e4 4061 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 4062 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4063 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4064 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4065 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 4066 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4067
e542a226
HW		 4068 rtl_init_rxcfg(tp);
4069
f0298f81 4070 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 4071
6f0333b8 4072 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 4073
cecb5fd7
FR		 4074 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4075 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4076 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4077 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 4078 rtl_set_rx_tx_config_registers(tp);
1da177e4 4079
7f796d83 4080 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 4081
cecb5fd7
FR		 4082 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4083 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 4084 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 4085 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 4086 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4087 }
4088
bcf0bf90
FR		 4089 RTL_W16(CPlusCmd, tp->cp_cmd);
4090
6dccd16b
FR		 4091 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4092
1da177e4
LT		 4093 /*
4094 * Undocumented corner. Supposedly:
4095 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4096 */
4097 RTL_W16(IntrMitigate, 0x0000);
4098
7f796d83 4099 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 4100
cecb5fd7
FR		 4101 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4102 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4103 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4104 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 4105 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4106 rtl_set_rx_tx_config_registers(tp);
4107 }
4108
1da177e4 4109 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 4110
4111 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4112 RTL_R8(IntrMask);
1da177e4
LT		 4113
4114 RTL_W32(RxMissed, 0);
4115
07ce4064 4116 rtl_set_rx_mode(dev);
1da177e4
LT		 4117
4118 /* no early-rx interrupts */
4119 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 4120
4121 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 4122 RTL_W16(IntrMask, tp->intr_event);
07ce4064 4123}
1da177e4 4124
9c14ceaf 4125static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 4126{
e44daade 4127 int cap = pci_pcie_cap(pdev);
9c14ceaf
FR		 4128
4129 if (cap) {
4130 u16 ctl;
458a9f61 4131
9c14ceaf
FR		 4132 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
4133 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
4134 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
4135 }
458a9f61
FR		 4136}
4137
650e8d5d 4138static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
dacf8154
FR		 4139{
4140 u32 csi;
4141
4142 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
650e8d5d 4143 rtl_csi_write(ioaddr, 0x070c, csi | bits);
4144}
4145
e6de30d6 4146static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4147{
4148 rtl_csi_access_enable(ioaddr, 0x17000000);
4149}
4150
650e8d5d 4151static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4152{
4153 rtl_csi_access_enable(ioaddr, 0x27000000);
dacf8154
FR		 4154}
4155
4156struct ephy_info {
4157 unsigned int offset;
4158 u16 mask;
4159 u16 bits;
4160};
4161
350f7596 4162static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 4163{
4164 u16 w;
4165
4166 while (len-- > 0) {
4167 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4168 rtl_ephy_write(ioaddr, e->offset, w);
4169 e++;
4170 }
4171}
4172
b726e493
FR		 4173static void rtl_disable_clock_request(struct pci_dev *pdev)
4174{
e44daade 4175 int cap = pci_pcie_cap(pdev);
b726e493
FR		 4176
4177 if (cap) {
4178 u16 ctl;
4179
4180 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4181 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4182 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4183 }
4184}
4185
e6de30d6 4186static void rtl_enable_clock_request(struct pci_dev *pdev)
4187{
e44daade 4188 int cap = pci_pcie_cap(pdev);
e6de30d6 4189
4190 if (cap) {
4191 u16 ctl;
4192
4193 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4194 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4195 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4196 }
4197}
4198
b726e493
FR		 4199#define R8168_CPCMD_QUIRK_MASK (\
4200 EnableBist | \
4201 Mac_dbgo_oe | \
4202 Force_half_dup | \
4203 Force_rxflow_en | \
4204 Force_txflow_en | \
4205 Cxpl_dbg_sel | \
4206 ASF | \
4207 PktCntrDisable | \
4208 Mac_dbgo_sel)
4209
219a1e9d
FR		 4210static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4211{
b726e493
FR		 4212 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4213
4214 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4215
2e68ae44
FR		 4216 rtl_tx_performance_tweak(pdev,
4217 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 4218}
4219
4220static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4221{
4222 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493 4223
f0298f81 4224 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 4225
4226 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 4227}
4228
4229static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4230{
b726e493
FR		 4231 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4232
4233 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4234
219a1e9d 4235 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 4236
4237 rtl_disable_clock_request(pdev);
4238
4239 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 4240}
4241
ef3386f0 4242static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 4243{
350f7596 4244 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4245 { 0x01, 0, 0x0001 },
4246 { 0x02, 0x0800, 0x1000 },
4247 { 0x03, 0, 0x0042 },
4248 { 0x06, 0x0080, 0x0000 },
4249 { 0x07, 0, 0x2000 }
4250 };
4251
650e8d5d 4252 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4253
4254 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4255
219a1e9d
FR		 4256 __rtl_hw_start_8168cp(ioaddr, pdev);
4257}
4258
ef3386f0
FR		 4259static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4260{
650e8d5d 4261 rtl_csi_access_enable_2(ioaddr);
ef3386f0
FR		 4262
4263 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4264
4265 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4266
4267 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4268}
4269
7f3e3d3a
FR		 4270static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4271{
650e8d5d 4272 rtl_csi_access_enable_2(ioaddr);
7f3e3d3a
FR		 4273
4274 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4275
4276 /* Magic. */
4277 RTL_W8(DBG_REG, 0x20);
4278
f0298f81 4279 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 4280
4281 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4282
4283 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4284}
4285
219a1e9d
FR		 4286static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4287{
350f7596 4288 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4289 { 0x02, 0x0800, 0x1000 },
4290 { 0x03, 0, 0x0002 },
4291 { 0x06, 0x0080, 0x0000 }
4292 };
4293
650e8d5d 4294 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4295
4296 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4297
4298 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4299
219a1e9d
FR		 4300 __rtl_hw_start_8168cp(ioaddr, pdev);
4301}
4302
4303static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4304{
350f7596 4305 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 4306 { 0x01, 0, 0x0001 },
4307 { 0x03, 0x0400, 0x0220 }
4308 };
4309
650e8d5d 4310 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4311
4312 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4313
219a1e9d
FR		 4314 __rtl_hw_start_8168cp(ioaddr, pdev);
4315}
4316
197ff761
FR		 4317static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4318{
4319 rtl_hw_start_8168c_2(ioaddr, pdev);
4320}
4321
6fb07058
FR		 4322static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4323{
650e8d5d 4324 rtl_csi_access_enable_2(ioaddr);
6fb07058
FR		 4325
4326 __rtl_hw_start_8168cp(ioaddr, pdev);
4327}
4328
5b538df9
FR		 4329static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4330{
650e8d5d 4331 rtl_csi_access_enable_2(ioaddr);
5b538df9
FR		 4332
4333 rtl_disable_clock_request(pdev);
4334
f0298f81 4335 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 4336
4337 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4338
4339 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4340}
4341
4804b3b3 4342static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4343{
4344 rtl_csi_access_enable_1(ioaddr);
4345
4346 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4347
4348 RTL_W8(MaxTxPacketSize, TxPacketMax);
4349
4350 rtl_disable_clock_request(pdev);
4351}
4352
e6de30d6 4353static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4354{
4355 static const struct ephy_info e_info_8168d_4[] = {
4356 { 0x0b, ~0, 0x48 },
4357 { 0x19, 0x20, 0x50 },
4358 { 0x0c, ~0, 0x20 }
4359 };
4360 int i;
4361
4362 rtl_csi_access_enable_1(ioaddr);
4363
4364 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4365
4366 RTL_W8(MaxTxPacketSize, TxPacketMax);
4367
4368 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4369 const struct ephy_info *e = e_info_8168d_4 + i;
4370 u16 w;
4371
4372 w = rtl_ephy_read(ioaddr, e->offset);
4373 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4374 }
4375
4376 rtl_enable_clock_request(pdev);
4377}
4378
70090424 4379static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
01dc7fec 4380{
70090424 4381 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 4382 { 0x00, 0x0200, 0x0100 },
4383 { 0x00, 0x0000, 0x0004 },
4384 { 0x06, 0x0002, 0x0001 },
4385 { 0x06, 0x0000, 0x0030 },
4386 { 0x07, 0x0000, 0x2000 },
4387 { 0x00, 0x0000, 0x0020 },
4388 { 0x03, 0x5800, 0x2000 },
4389 { 0x03, 0x0000, 0x0001 },
4390 { 0x01, 0x0800, 0x1000 },
4391 { 0x07, 0x0000, 0x4000 },
4392 { 0x1e, 0x0000, 0x2000 },
4393 { 0x19, 0xffff, 0xfe6c },
4394 { 0x0a, 0x0000, 0x0040 }
4395 };
4396
4397 rtl_csi_access_enable_2(ioaddr);
4398
70090424 4399 rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 4400
4401 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4402
4403 RTL_W8(MaxTxPacketSize, TxPacketMax);
4404
4405 rtl_disable_clock_request(pdev);
4406
4407 /* Reset tx FIFO pointer */
cecb5fd7
FR		 4408 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4409 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 4410
cecb5fd7 4411 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 4412}
4413
70090424
HW		 4414static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4415{
4416 static const struct ephy_info e_info_8168e_2[] = {
4417 { 0x09, 0x0000, 0x0080 },
4418 { 0x19, 0x0000, 0x0224 }
4419 };
4420
4421 rtl_csi_access_enable_1(ioaddr);
4422
4423 rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4424
4425 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4426
4427 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4428 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4429 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4430 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4431 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4432 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4433 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4434 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4435 ERIAR_EXGMAC);
4436
4437 RTL_W8(MaxTxPacketSize, 0x27);
4438
4439 rtl_disable_clock_request(pdev);
4440
4441 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4442 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4443
4444 /* Adjust EEE LED frequency */
4445 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4446
4447 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4448 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4449 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4450}
4451
07ce4064
FR		 4452static void rtl_hw_start_8168(struct net_device *dev)
4453{
2dd99530
FR		 4454 struct rtl8169_private *tp = netdev_priv(dev);
4455 void __iomem *ioaddr = tp->mmio_addr;
0e485150 4456 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 4457
4458 RTL_W8(Cfg9346, Cfg9346_Unlock);
4459
f0298f81 4460 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 4461
6f0333b8 4462 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 4463
0e485150 4464 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 4465
4466 RTL_W16(CPlusCmd, tp->cp_cmd);
4467
0e485150 4468 RTL_W16(IntrMitigate, 0x5151);
2dd99530 4469
0e485150 4470 /* Work around for RxFIFO overflow. */
b5ba6d12
IV		 4471 if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4472 tp->mac_version == RTL_GIGA_MAC_VER_22) {
0e485150
FR		 4473 tp->intr_event |= RxFIFOOver | PCSTimeout;
4474 tp->intr_event &= ~RxOverflow;
4475 }
4476
4477 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 4478
b8363901
FR		 4479 rtl_set_rx_mode(dev);
4480
4481 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4482 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 4483
4484 RTL_R8(IntrMask);
4485
219a1e9d
FR		 4486 switch (tp->mac_version) {
4487 case RTL_GIGA_MAC_VER_11:
4488 rtl_hw_start_8168bb(ioaddr, pdev);
4804b3b3 4489 break;
219a1e9d
FR		 4490
4491 case RTL_GIGA_MAC_VER_12:
4492 case RTL_GIGA_MAC_VER_17:
4493 rtl_hw_start_8168bef(ioaddr, pdev);
4804b3b3 4494 break;
219a1e9d
FR		 4495
4496 case RTL_GIGA_MAC_VER_18:
ef3386f0 4497 rtl_hw_start_8168cp_1(ioaddr, pdev);
4804b3b3 4498 break;
219a1e9d
FR		 4499
4500 case RTL_GIGA_MAC_VER_19:
4501 rtl_hw_start_8168c_1(ioaddr, pdev);
4804b3b3 4502 break;
219a1e9d
FR		 4503
4504 case RTL_GIGA_MAC_VER_20:
4505 rtl_hw_start_8168c_2(ioaddr, pdev);
4804b3b3 4506 break;
219a1e9d 4507
197ff761
FR		 4508 case RTL_GIGA_MAC_VER_21:
4509 rtl_hw_start_8168c_3(ioaddr, pdev);
4804b3b3 4510 break;
197ff761 4511
6fb07058
FR		 4512 case RTL_GIGA_MAC_VER_22:
4513 rtl_hw_start_8168c_4(ioaddr, pdev);
4804b3b3 4514 break;
6fb07058 4515
ef3386f0
FR		 4516 case RTL_GIGA_MAC_VER_23:
4517 rtl_hw_start_8168cp_2(ioaddr, pdev);
4804b3b3 4518 break;
ef3386f0 4519
7f3e3d3a
FR		 4520 case RTL_GIGA_MAC_VER_24:
4521 rtl_hw_start_8168cp_3(ioaddr, pdev);
4804b3b3 4522 break;
7f3e3d3a 4523
5b538df9 4524 case RTL_GIGA_MAC_VER_25:
daf9df6d 4525 case RTL_GIGA_MAC_VER_26:
4526 case RTL_GIGA_MAC_VER_27:
5b538df9 4527 rtl_hw_start_8168d(ioaddr, pdev);
4804b3b3 4528 break;
5b538df9 4529
e6de30d6 4530 case RTL_GIGA_MAC_VER_28:
4531 rtl_hw_start_8168d_4(ioaddr, pdev);
4804b3b3 4532 break;
cecb5fd7 4533
4804b3b3 4534 case RTL_GIGA_MAC_VER_31:
4535 rtl_hw_start_8168dp(ioaddr, pdev);
4536 break;
4537
01dc7fec 4538 case RTL_GIGA_MAC_VER_32:
4539 case RTL_GIGA_MAC_VER_33:
70090424
HW		 4540 rtl_hw_start_8168e_1(ioaddr, pdev);
4541 break;
4542 case RTL_GIGA_MAC_VER_34:
4543 rtl_hw_start_8168e_2(ioaddr, pdev);
01dc7fec 4544 break;
e6de30d6 4545
219a1e9d
FR		 4546 default:
4547 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4548 dev->name, tp->mac_version);
4804b3b3 4549 break;
219a1e9d 4550 }
2dd99530 4551
0e485150
FR		 4552 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4553
b8363901
FR		 4554 RTL_W8(Cfg9346, Cfg9346_Lock);
4555
2dd99530 4556 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 4557
0e485150 4558 RTL_W16(IntrMask, tp->intr_event);
07ce4064 4559}
1da177e4 4560
2857ffb7
FR		 4561#define R810X_CPCMD_QUIRK_MASK (\
4562 EnableBist | \
4563 Mac_dbgo_oe | \
4564 Force_half_dup | \
5edcc537 4565 Force_rxflow_en | \
2857ffb7
FR		 4566 Force_txflow_en | \
4567 Cxpl_dbg_sel | \
4568 ASF | \
4569 PktCntrDisable | \
d24e9aaf 4570 Mac_dbgo_sel)
2857ffb7
FR		 4571
4572static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4573{
350f7596 4574 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 4575 { 0x01, 0, 0x6e65 },
4576 { 0x02, 0, 0x091f },
4577 { 0x03, 0, 0xc2f9 },
4578 { 0x06, 0, 0xafb5 },
4579 { 0x07, 0, 0x0e00 },
4580 { 0x19, 0, 0xec80 },
4581 { 0x01, 0, 0x2e65 },
4582 { 0x01, 0, 0x6e65 }
4583 };
4584 u8 cfg1;
4585
650e8d5d 4586 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 4587
4588 RTL_W8(DBG_REG, FIX_NAK_1);
4589
4590 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4591
4592 RTL_W8(Config1,
4593 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4594 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4595
4596 cfg1 = RTL_R8(Config1);
4597 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4598 RTL_W8(Config1, cfg1 & ~LEDS0);
4599
2857ffb7
FR		 4600 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4601}
4602
4603static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4604{
650e8d5d 4605 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 4606
4607 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4608
4609 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4610 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 4611}
4612
4613static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4614{
4615 rtl_hw_start_8102e_2(ioaddr, pdev);
4616
4617 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4618}
4619
5a5e4443
HW		 4620static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4621{
4622 static const struct ephy_info e_info_8105e_1[] = {
4623 { 0x07, 0, 0x4000 },
4624 { 0x19, 0, 0x0200 },
4625 { 0x19, 0, 0x0020 },
4626 { 0x1e, 0, 0x2000 },
4627 { 0x03, 0, 0x0001 },
4628 { 0x19, 0, 0x0100 },
4629 { 0x19, 0, 0x0004 },
4630 { 0x0a, 0, 0x0020 }
4631 };
4632
cecb5fd7 4633 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 4634 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4635
cecb5fd7 4636 /* Disable Early Tally Counter */
5a5e4443
HW		 4637 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4638
4639 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 4640 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443
HW		 4641
4642 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4643}
4644
4645static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4646{
4647 rtl_hw_start_8105e_1(ioaddr, pdev);
4648 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4649}
4650
07ce4064
FR		 4651static void rtl_hw_start_8101(struct net_device *dev)
4652{
cdf1a608
FR		 4653 struct rtl8169_private *tp = netdev_priv(dev);
4654 void __iomem *ioaddr = tp->mmio_addr;
4655 struct pci_dev *pdev = tp->pci_dev;
4656
cecb5fd7
FR		 4657 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4658 tp->mac_version == RTL_GIGA_MAC_VER_16) {
e44daade 4659 int cap = pci_pcie_cap(pdev);
9c14ceaf
FR		 4660
4661 if (cap) {
4662 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4663 PCI_EXP_DEVCTL_NOSNOOP_EN);
4664 }
cdf1a608
FR		 4665 }
4666
d24e9aaf
HW		 4667 RTL_W8(Cfg9346, Cfg9346_Unlock);
4668
2857ffb7
FR		 4669 switch (tp->mac_version) {
4670 case RTL_GIGA_MAC_VER_07:
4671 rtl_hw_start_8102e_1(ioaddr, pdev);
4672 break;
4673
4674 case RTL_GIGA_MAC_VER_08:
4675 rtl_hw_start_8102e_3(ioaddr, pdev);
4676 break;
4677
4678 case RTL_GIGA_MAC_VER_09:
4679 rtl_hw_start_8102e_2(ioaddr, pdev);
4680 break;
5a5e4443
HW		 4681
4682 case RTL_GIGA_MAC_VER_29:
4683 rtl_hw_start_8105e_1(ioaddr, pdev);
4684 break;
4685 case RTL_GIGA_MAC_VER_30:
4686 rtl_hw_start_8105e_2(ioaddr, pdev);
4687 break;
cdf1a608
FR		 4688 }
4689
d24e9aaf 4690 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 4691
f0298f81 4692 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 4693
6f0333b8 4694 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 4695
d24e9aaf 4696 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 4697 RTL_W16(CPlusCmd, tp->cp_cmd);
4698
4699 RTL_W16(IntrMitigate, 0x0000);
4700
4701 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4702
4703 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4704 rtl_set_rx_tx_config_registers(tp);
4705
cdf1a608
FR		 4706 RTL_R8(IntrMask);
4707
cdf1a608
FR		 4708 rtl_set_rx_mode(dev);
4709
4710 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 4711
0e485150 4712 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4713}
4714
4715static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4716{
1da177e4
LT		 4717 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4718 return -EINVAL;
4719
4720 dev->mtu = new_mtu;
350fb32a
MM		 4721 netdev_update_features(dev);
4722
323bb685 4723 return 0;
1da177e4
LT		 4724}
4725
4726static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4727{
95e0918d 4728 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 4729 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4730}
4731
6f0333b8
ED		 4732static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4733 void **data_buff, struct RxDesc *desc)
1da177e4 4734{
48addcc9 4735 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 4736 DMA_FROM_DEVICE);
48addcc9 4737
6f0333b8
ED		 4738 kfree(*data_buff);
4739 *data_buff = NULL;
1da177e4
LT		 4740 rtl8169_make_unusable_by_asic(desc);
4741}
4742
4743static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4744{
4745 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4746
4747 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4748}
4749
4750static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4751 u32 rx_buf_sz)
4752{
4753 desc->addr = cpu_to_le64(mapping);
4754 wmb();
4755 rtl8169_mark_to_asic(desc, rx_buf_sz);
4756}
4757
6f0333b8
ED		 4758static inline void *rtl8169_align(void *data)
4759{
4760 return (void *)ALIGN((long)data, 16);
4761}
4762
0ecbe1ca
SG		 4763static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4764 struct RxDesc *desc)
1da177e4 4765{
6f0333b8 4766 void *data;
1da177e4 4767 dma_addr_t mapping;
48addcc9 4768 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 4769 struct net_device *dev = tp->dev;
6f0333b8 4770 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 4771
6f0333b8
ED		 4772 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4773 if (!data)
4774 return NULL;
e9f63f30 4775
6f0333b8
ED		 4776 if (rtl8169_align(data) != data) {
4777 kfree(data);
4778 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4779 if (!data)
4780 return NULL;
4781 }
3eafe507 4782
48addcc9 4783 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 4784 DMA_FROM_DEVICE);
d827d86b
SG		 4785 if (unlikely(dma_mapping_error(d, mapping))) {
4786 if (net_ratelimit())
4787 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 4788 goto err_out;
d827d86b 4789 }
1da177e4
LT		 4790
4791 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 4792 return data;
3eafe507
SG		 4793
4794err_out:
4795 kfree(data);
4796 return NULL;
1da177e4
LT		 4797}
4798
4799static void rtl8169_rx_clear(struct rtl8169_private *tp)
4800{
07d3f51f 4801 unsigned int i;
1da177e4
LT		 4802
4803 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 4804 if (tp->Rx_databuff[i]) {
4805 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 4806 tp->RxDescArray + i);
4807 }
4808 }
4809}
4810
0ecbe1ca 4811static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 4812{
0ecbe1ca
SG		 4813 desc->opts1 |= cpu_to_le32(RingEnd);
4814}
5b0384f4 4815
0ecbe1ca
SG		 4816static int rtl8169_rx_fill(struct rtl8169_private *tp)
4817{
4818 unsigned int i;
1da177e4 4819
0ecbe1ca
SG		 4820 for (i = 0; i < NUM_RX_DESC; i++) {
4821 void *data;
4ae47c2d 4822
6f0333b8 4823 if (tp->Rx_databuff[i])
1da177e4 4824 continue;
bcf0bf90 4825
0ecbe1ca 4826 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 4827 if (!data) {
4828 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 4829 goto err_out;
6f0333b8
ED		 4830 }
4831 tp->Rx_databuff[i] = data;
1da177e4 4832 }
1da177e4 4833
0ecbe1ca
SG		 4834 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4835 return 0;
4836
4837err_out:
4838 rtl8169_rx_clear(tp);
4839 return -ENOMEM;
1da177e4
LT		 4840}
4841
1da177e4
LT		 4842static int rtl8169_init_ring(struct net_device *dev)
4843{
4844 struct rtl8169_private *tp = netdev_priv(dev);
4845
4846 rtl8169_init_ring_indexes(tp);
4847
4848 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 4849 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 4850
0ecbe1ca 4851 return rtl8169_rx_fill(tp);
1da177e4
LT		 4852}
4853
48addcc9 4854static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 4855 struct TxDesc *desc)
4856{
4857 unsigned int len = tx_skb->len;
4858
48addcc9
SG		 4859 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4860
1da177e4
LT		 4861 desc->opts1 = 0x00;
4862 desc->opts2 = 0x00;
4863 desc->addr = 0x00;
4864 tx_skb->len = 0;
4865}
4866
3eafe507
SG		 4867static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4868 unsigned int n)
1da177e4
LT		 4869{
4870 unsigned int i;
4871
3eafe507
SG		 4872 for (i = 0; i < n; i++) {
4873 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 4874 struct ring_info *tx_skb = tp->tx_skb + entry;
4875 unsigned int len = tx_skb->len;
4876
4877 if (len) {
4878 struct sk_buff *skb = tx_skb->skb;
4879
48addcc9 4880 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 4881 tp->TxDescArray + entry);
4882 if (skb) {
cac4b22f 4883 tp->dev->stats.tx_dropped++;
1da177e4
LT		 4884 dev_kfree_skb(skb);
4885 tx_skb->skb = NULL;
4886 }
1da177e4
LT		 4887 }
4888 }
3eafe507
SG		 4889}
4890
4891static void rtl8169_tx_clear(struct rtl8169_private *tp)
4892{
4893 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 4894 tp->cur_tx = tp->dirty_tx = 0;
4895}
4896
c4028958 4897static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 4898{
4899 struct rtl8169_private *tp = netdev_priv(dev);
4900
c4028958 4901 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 4902 schedule_delayed_work(&tp->task, 4);
4903}
4904
4905static void rtl8169_wait_for_quiescence(struct net_device *dev)
4906{
4907 struct rtl8169_private *tp = netdev_priv(dev);
4908 void __iomem *ioaddr = tp->mmio_addr;
4909
4910 synchronize_irq(dev->irq);
4911
4912 /* Wait for any pending NAPI task to complete */
bea3348e 4913 napi_disable(&tp->napi);
1da177e4
LT		 4914
4915 rtl8169_irq_mask_and_ack(ioaddr);
4916
d1d08d12
DM		 4917 tp->intr_mask = 0xffff;
4918 RTL_W16(IntrMask, tp->intr_event);
bea3348e 4919 napi_enable(&tp->napi);
1da177e4
LT		 4920}
4921
c4028958 4922static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 4923{
c4028958
DH		 4924 struct rtl8169_private *tp =
4925 container_of(work, struct rtl8169_private, task.work);
4926 struct net_device *dev = tp->dev;
1da177e4
LT		 4927 int ret;
4928
eb2a021c
FR		 4929 rtnl_lock();
4930
4931 if (!netif_running(dev))
4932 goto out_unlock;
4933
4934 rtl8169_wait_for_quiescence(dev);
4935 rtl8169_close(dev);
1da177e4
LT		 4936
4937 ret = rtl8169_open(dev);
4938 if (unlikely(ret < 0)) {
bf82c189
JP		 4939 if (net_ratelimit())
4940 netif_err(tp, drv, dev,
4941 "reinit failure (status = %d). Rescheduling\n",
4942 ret);
1da177e4
LT		 4943 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4944 }
eb2a021c
FR		 4945
4946out_unlock:
4947 rtnl_unlock();
1da177e4
LT		 4948}
4949
c4028958 4950static void rtl8169_reset_task(struct work_struct *work)
1da177e4 4951{
c4028958
DH		 4952 struct rtl8169_private *tp =
4953 container_of(work, struct rtl8169_private, task.work);
4954 struct net_device *dev = tp->dev;
56de414c 4955 int i;
1da177e4 4956
eb2a021c
FR		 4957 rtnl_lock();
4958
1da177e4 4959 if (!netif_running(dev))
eb2a021c 4960 goto out_unlock;
1da177e4
LT		 4961
4962 rtl8169_wait_for_quiescence(dev);
4963
56de414c
FR		 4964 for (i = 0; i < NUM_RX_DESC; i++)
4965 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4966
1da177e4
LT		 4967 rtl8169_tx_clear(tp);
4968
92fc43b4 4969 rtl8169_hw_reset(tp);
56de414c
FR		 4970 rtl_hw_start(dev);
4971 netif_wake_queue(dev);
4972 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
eb2a021c
FR		 4973
4974out_unlock:
4975 rtnl_unlock();
1da177e4
LT		 4976}
4977
4978static void rtl8169_tx_timeout(struct net_device *dev)
4979{
4980 struct rtl8169_private *tp = netdev_priv(dev);
4981
e6de30d6 4982 rtl8169_hw_reset(tp);
1da177e4
LT		 4983
4984 /* Let's wait a bit while any (async) irq lands on */
4985 rtl8169_schedule_work(dev, rtl8169_reset_task);
4986}
4987
4988static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 4989 u32 *opts)
1da177e4
LT		 4990{
4991 struct skb_shared_info *info = skb_shinfo(skb);
4992 unsigned int cur_frag, entry;
a6343afb 4993 struct TxDesc * uninitialized_var(txd);
48addcc9 4994 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4995
4996 entry = tp->cur_tx;
4997 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4998 skb_frag_t *frag = info->frags + cur_frag;
4999 dma_addr_t mapping;
5000 u32 status, len;
5001 void *addr;
5002
5003 entry = (entry + 1) % NUM_TX_DESC;
5004
5005 txd = tp->TxDescArray + entry;
5006 len = frag->size;
5007 addr = ((void *) page_address(frag->page)) + frag->page_offset;
48addcc9 5008 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5009 if (unlikely(dma_mapping_error(d, mapping))) {
5010 if (net_ratelimit())
5011 netif_err(tp, drv, tp->dev,
5012 "Failed to map TX fragments DMA!\n");
3eafe507 5013 goto err_out;
d827d86b 5014 }
1da177e4 5015
cecb5fd7 5016 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 5017 status = opts[0] | len |
5018 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5019
5020 txd->opts1 = cpu_to_le32(status);
2b7b4318 5021 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5022 txd->addr = cpu_to_le64(mapping);
5023
5024 tp->tx_skb[entry].len = len;
5025 }
5026
5027 if (cur_frag) {
5028 tp->tx_skb[entry].skb = skb;
5029 txd->opts1 |= cpu_to_le32(LastFrag);
5030 }
5031
5032 return cur_frag;
3eafe507
SG		 5033
5034err_out:
5035 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5036 return -EIO;
1da177e4
LT		 5037}
5038
2b7b4318
FR		 5039static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5040 struct sk_buff *skb, u32 *opts)
1da177e4 5041{
2b7b4318 5042 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 5043 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 5044 int offset = info->opts_offset;
350fb32a 5045
2b7b4318
FR		 5046 if (mss) {
5047 opts[0] |= TD_LSO;
5048 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5049 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 5050 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 5051
5052 if (ip->protocol == IPPROTO_TCP)
2b7b4318 5053 opts[offset] |= info->checksum.tcp;
1da177e4 5054 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 5055 opts[offset] |= info->checksum.udp;
5056 else
5057 WARN_ON_ONCE(1);
1da177e4 5058 }
1da177e4
LT		 5059}
5060
61357325
SH		 5061static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5062 struct net_device *dev)
1da177e4
LT		 5063{
5064 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 5065 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 5066 struct TxDesc *txd = tp->TxDescArray + entry;
5067 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 5068 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5069 dma_addr_t mapping;
5070 u32 status, len;
2b7b4318 5071 u32 opts[2];
3eafe507 5072 int frags;
5b0384f4 5073
1da177e4 5074 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 5075 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 5076 goto err_stop_0;
1da177e4
LT		 5077 }
5078
5079 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 5080 goto err_stop_0;
5081
5082 len = skb_headlen(skb);
48addcc9 5083 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 5084 if (unlikely(dma_mapping_error(d, mapping))) {
5085 if (net_ratelimit())
5086 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 5087 goto err_dma_0;
d827d86b 5088 }
3eafe507
SG		 5089
5090 tp->tx_skb[entry].len = len;
5091 txd->addr = cpu_to_le64(mapping);
1da177e4 5092
2b7b4318
FR		 5093 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5094 opts[0] = DescOwn;
1da177e4 5095
2b7b4318
FR		 5096 rtl8169_tso_csum(tp, skb, opts);
5097
5098 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 5099 if (frags < 0)
5100 goto err_dma_1;
5101 else if (frags)
2b7b4318 5102 opts[0] |= FirstFrag;
3eafe507 5103 else {
2b7b4318 5104 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 5105 tp->tx_skb[entry].skb = skb;
5106 }
5107
2b7b4318
FR		 5108 txd->opts2 = cpu_to_le32(opts[1]);
5109
1da177e4
LT		 5110 wmb();
5111
cecb5fd7 5112 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 5113 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5114 txd->opts1 = cpu_to_le32(status);
5115
1da177e4
LT		 5116 tp->cur_tx += frags + 1;
5117
4c020a96 5118 wmb();
1da177e4 5119
cecb5fd7 5120 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 5121
5122 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
5123 netif_stop_queue(dev);
5124 smp_rmb();
5125 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
5126 netif_wake_queue(dev);
5127 }
5128
61357325 5129 return NETDEV_TX_OK;
1da177e4 5130
3eafe507 5131err_dma_1:
48addcc9 5132 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 5133err_dma_0:
5134 dev_kfree_skb(skb);
5135 dev->stats.tx_dropped++;
5136 return NETDEV_TX_OK;
5137
5138err_stop_0:
1da177e4 5139 netif_stop_queue(dev);
cebf8cc7 5140 dev->stats.tx_dropped++;
61357325 5141 return NETDEV_TX_BUSY;
1da177e4
LT		 5142}
5143
5144static void rtl8169_pcierr_interrupt(struct net_device *dev)
5145{
5146 struct rtl8169_private *tp = netdev_priv(dev);
5147 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 5148 u16 pci_status, pci_cmd;
5149
5150 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5151 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5152
bf82c189
JP		 5153 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5154 pci_cmd, pci_status);
1da177e4
LT		 5155
5156 /*
5157 * The recovery sequence below admits a very elaborated explanation:
5158 * - it seems to work;
d03902b8
FR		 5159 * - I did not see what else could be done;
5160 * - it makes iop3xx happy.
1da177e4
LT		 5161 *
5162 * Feel free to adjust to your needs.
5163 */
a27993f3 5164 if (pdev->broken_parity_status)
d03902b8
FR		 5165 pci_cmd &= ~PCI_COMMAND_PARITY;
5166 else
5167 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5168
5169 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 5170
5171 pci_write_config_word(pdev, PCI_STATUS,
5172 pci_status & (PCI_STATUS_DETECTED_PARITY |
5173 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5174 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5175
5176 /* The infamous DAC f*ckup only happens at boot time */
5177 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 5178 void __iomem *ioaddr = tp->mmio_addr;
5179
bf82c189 5180 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 5181 tp->cp_cmd &= ~PCIDAC;
5182 RTL_W16(CPlusCmd, tp->cp_cmd);
5183 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 5184 }
5185
e6de30d6 5186 rtl8169_hw_reset(tp);
d03902b8
FR		 5187
5188 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 5189}
5190
07d3f51f
FR		 5191static void rtl8169_tx_interrupt(struct net_device *dev,
5192 struct rtl8169_private *tp,
5193 void __iomem *ioaddr)
1da177e4
LT		 5194{
5195 unsigned int dirty_tx, tx_left;
5196
1da177e4
LT		 5197 dirty_tx = tp->dirty_tx;
5198 smp_rmb();
5199 tx_left = tp->cur_tx - dirty_tx;
5200
5201 while (tx_left > 0) {
5202 unsigned int entry = dirty_tx % NUM_TX_DESC;
5203 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 5204 u32 status;
5205
5206 rmb();
5207 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5208 if (status & DescOwn)
5209 break;
5210
48addcc9
SG		 5211 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5212 tp->TxDescArray + entry);
1da177e4 5213 if (status & LastFrag) {
cac4b22f
SG		 5214 dev->stats.tx_packets++;
5215 dev->stats.tx_bytes += tx_skb->skb->len;
87433bfc 5216 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 5217 tx_skb->skb = NULL;
5218 }
5219 dirty_tx++;
5220 tx_left--;
5221 }
5222
5223 if (tp->dirty_tx != dirty_tx) {
5224 tp->dirty_tx = dirty_tx;
5225 smp_wmb();
5226 if (netif_queue_stopped(dev) &&
5227 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5228 netif_wake_queue(dev);
5229 }
d78ae2dc
FR		 5230 /*
5231 * 8168 hack: TxPoll requests are lost when the Tx packets are
5232 * too close. Let's kick an extra TxPoll request when a burst
5233 * of start_xmit activity is detected (if it is not detected,
5234 * it is slow enough). -- FR
5235 */
5236 smp_rmb();
5237 if (tp->cur_tx != dirty_tx)
5238 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 5239 }
5240}
5241
126fa4b9
FR		 5242static inline int rtl8169_fragmented_frame(u32 status)
5243{
5244 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5245}
5246
adea1ac7 5247static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 5248{
1da177e4
LT		 5249 u32 status = opts1 & RxProtoMask;
5250
5251 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 5252 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 5253 skb->ip_summed = CHECKSUM_UNNECESSARY;
5254 else
bc8acf2c 5255 skb_checksum_none_assert(skb);
1da177e4
LT		 5256}
5257
6f0333b8
ED		 5258static struct sk_buff *rtl8169_try_rx_copy(void *data,
5259 struct rtl8169_private *tp,
5260 int pkt_size,
5261 dma_addr_t addr)
1da177e4 5262{
b449655f 5263 struct sk_buff *skb;
48addcc9 5264 struct device *d = &tp->pci_dev->dev;
b449655f 5265
6f0333b8 5266 data = rtl8169_align(data);
48addcc9 5267 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 5268 prefetch(data);
5269 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5270 if (skb)
5271 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 5272 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5273
6f0333b8 5274 return skb;
1da177e4
LT		 5275}
5276
07d3f51f
FR		 5277static int rtl8169_rx_interrupt(struct net_device *dev,
5278 struct rtl8169_private *tp,
bea3348e 5279 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 5280{
5281 unsigned int cur_rx, rx_left;
6f0333b8 5282 unsigned int count;
1da177e4 5283
1da177e4
LT		 5284 cur_rx = tp->cur_rx;
5285 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 5286 rx_left = min(rx_left, budget);
1da177e4 5287
4dcb7d33 5288 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 5289 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 5290 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 5291 u32 status;
5292
5293 rmb();
126fa4b9 5294 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 5295
5296 if (status & DescOwn)
5297 break;
4dcb7d33 5298 if (unlikely(status & RxRES)) {
bf82c189
JP		 5299 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5300 status);
cebf8cc7 5301 dev->stats.rx_errors++;
1da177e4 5302 if (status & (RxRWT | RxRUNT))
cebf8cc7 5303 dev->stats.rx_length_errors++;
1da177e4 5304 if (status & RxCRC)
cebf8cc7 5305 dev->stats.rx_crc_errors++;
9dccf611
FR		 5306 if (status & RxFOVF) {
5307 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 5308 dev->stats.rx_fifo_errors++;
9dccf611 5309 }
6f0333b8 5310 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 5311 } else {
6f0333b8 5312 struct sk_buff *skb;
b449655f 5313 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 5314 int pkt_size = (status & 0x00001FFF) - 4;
1da177e4 5315
126fa4b9
FR		 5316 /*
5317 * The driver does not support incoming fragmented
5318 * frames. They are seen as a symptom of over-mtu
5319 * sized frames.
5320 */
5321 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 5322 dev->stats.rx_dropped++;
5323 dev->stats.rx_length_errors++;
6f0333b8 5324 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 5325 continue;
126fa4b9
FR		 5326 }
5327
6f0333b8
ED		 5328 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5329 tp, pkt_size, addr);
5330 rtl8169_mark_to_asic(desc, rx_buf_sz);
5331 if (!skb) {
5332 dev->stats.rx_dropped++;
5333 continue;
1da177e4
LT		 5334 }
5335
adea1ac7 5336 rtl8169_rx_csum(skb, status);
1da177e4
LT		 5337 skb_put(skb, pkt_size);
5338 skb->protocol = eth_type_trans(skb, dev);
5339
7a8fc77b
FR		 5340 rtl8169_rx_vlan_tag(desc, skb);
5341
56de414c 5342 napi_gro_receive(&tp->napi, skb);
1da177e4 5343
cebf8cc7
FR		 5344 dev->stats.rx_bytes += pkt_size;
5345 dev->stats.rx_packets++;
1da177e4 5346 }
6dccd16b
FR		 5347
5348 /* Work around for AMD plateform. */
95e0918d 5349 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 5350 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5351 desc->opts2 = 0;
5352 cur_rx++;
5353 }
1da177e4
LT		 5354 }
5355
5356 count = cur_rx - tp->cur_rx;
5357 tp->cur_rx = cur_rx;
5358
6f0333b8 5359 tp->dirty_rx += count;
1da177e4
LT		 5360
5361 return count;
5362}
5363
07d3f51f 5364static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 5365{
07d3f51f 5366 struct net_device *dev = dev_instance;
1da177e4 5367 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 5368 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 5369 int handled = 0;
865c652d 5370 int status;
1da177e4 5371
f11a377b
DD		 5372 /* loop handling interrupts until we have no new ones or
5373 * we hit a invalid/hotplug case.
5374 */
865c652d 5375 status = RTL_R16(IntrStatus);
f11a377b
DD		 5376 while (status && status != 0xffff) {
5377 handled = 1;
1da177e4 5378
f11a377b
DD		 5379 /* Handle all of the error cases first. These will reset
5380 * the chip, so just exit the loop.
5381 */
5382 if (unlikely(!netif_running(dev))) {
92fc43b4 5383 rtl8169_hw_reset(tp);
f11a377b
DD		 5384 break;
5385 }
1da177e4 5386
1519e57f
FR		 5387 if (unlikely(status & RxFIFOOver)) {
5388 switch (tp->mac_version) {
5389 /* Work around for rx fifo overflow */
5390 case RTL_GIGA_MAC_VER_11:
5391 case RTL_GIGA_MAC_VER_22:
5392 case RTL_GIGA_MAC_VER_26:
5393 netif_stop_queue(dev);
5394 rtl8169_tx_timeout(dev);
5395 goto done;
f60ac8e7
FR		 5396 /* Testers needed. */
5397 case RTL_GIGA_MAC_VER_17:
5398 case RTL_GIGA_MAC_VER_19:
5399 case RTL_GIGA_MAC_VER_20:
5400 case RTL_GIGA_MAC_VER_21:
5401 case RTL_GIGA_MAC_VER_23:
5402 case RTL_GIGA_MAC_VER_24:
5403 case RTL_GIGA_MAC_VER_27:
5404 case RTL_GIGA_MAC_VER_28:
4804b3b3 5405 case RTL_GIGA_MAC_VER_31:
1519e57f
FR		 5406 /* Experimental science. Pktgen proof. */
5407 case RTL_GIGA_MAC_VER_12:
5408 case RTL_GIGA_MAC_VER_25:
5409 if (status == RxFIFOOver)
5410 goto done;
5411 break;
5412 default:
5413 break;
5414 }
f11a377b 5415 }
1da177e4 5416
f11a377b
DD		 5417 if (unlikely(status & SYSErr)) {
5418 rtl8169_pcierr_interrupt(dev);
5419 break;
5420 }
1da177e4 5421
f11a377b 5422 if (status & LinkChg)
e4fbce74 5423 __rtl8169_check_link_status(dev, tp, ioaddr, true);
0e485150 5424
f11a377b
DD		 5425 /* We need to see the lastest version of tp->intr_mask to
5426 * avoid ignoring an MSI interrupt and having to wait for
5427 * another event which may never come.
5428 */
5429 smp_rmb();
5430 if (status & tp->intr_mask & tp->napi_event) {
5431 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5432 tp->intr_mask = ~tp->napi_event;
5433
5434 if (likely(napi_schedule_prep(&tp->napi)))
5435 __napi_schedule(&tp->napi);
bf82c189
JP		 5436 else
5437 netif_info(tp, intr, dev,
5438 "interrupt %04x in poll\n", status);
f11a377b 5439 }
1da177e4 5440
f11a377b
DD		 5441 /* We only get a new MSI interrupt when all active irq
5442 * sources on the chip have been acknowledged. So, ack
5443 * everything we've seen and check if new sources have become
5444 * active to avoid blocking all interrupts from the chip.
5445 */
5446 RTL_W16(IntrStatus,
5447 (status & RxFIFOOver) ? (status | RxOverflow) : status);
5448 status = RTL_R16(IntrStatus);
865c652d 5449 }
1519e57f 5450done:
1da177e4
LT		 5451 return IRQ_RETVAL(handled);
5452}
5453
bea3348e 5454static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 5455{
bea3348e
SH		 5456 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5457 struct net_device *dev = tp->dev;
1da177e4 5458 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 5459 int work_done;
1da177e4 5460
bea3348e 5461 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 5462 rtl8169_tx_interrupt(dev, tp, ioaddr);
5463
bea3348e 5464 if (work_done < budget) {
288379f0 5465 napi_complete(napi);
f11a377b
DD		 5466
5467 /* We need for force the visibility of tp->intr_mask
5468 * for other CPUs, as we can loose an MSI interrupt
5469 * and potentially wait for a retransmit timeout if we don't.
5470 * The posted write to IntrMask is safe, as it will
5471 * eventually make it to the chip and we won't loose anything
5472 * until it does.
1da177e4 5473 */
f11a377b 5474 tp->intr_mask = 0xffff;
4c020a96 5475 wmb();
0e485150 5476 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 5477 }
5478
bea3348e 5479 return work_done;
1da177e4 5480}
1da177e4 5481
523a6094
FR		 5482static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5483{
5484 struct rtl8169_private *tp = netdev_priv(dev);
5485
5486 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5487 return;
5488
5489 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5490 RTL_W32(RxMissed, 0);
5491}
5492
1da177e4
LT		 5493static void rtl8169_down(struct net_device *dev)
5494{
5495 struct rtl8169_private *tp = netdev_priv(dev);
5496 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 5497
4876cc1e 5498 del_timer_sync(&tp->timer);
1da177e4
LT		 5499
5500 netif_stop_queue(dev);
5501
93dd79e8 5502 napi_disable(&tp->napi);
93dd79e8 5503
1da177e4
LT		 5504 spin_lock_irq(&tp->lock);
5505
92fc43b4 5506 rtl8169_hw_reset(tp);
323bb685
SG		 5507 /*
5508 * At this point device interrupts can not be enabled in any function,
5509 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5510 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5511 */
523a6094 5512 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 5513
5514 spin_unlock_irq(&tp->lock);
5515
5516 synchronize_irq(dev->irq);
5517
1da177e4 5518 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 5519 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4 5520
1da177e4
LT		 5521 rtl8169_tx_clear(tp);
5522
5523 rtl8169_rx_clear(tp);
065c27c1 5524
5525 rtl_pll_power_down(tp);
1da177e4
LT		 5526}
5527
5528static int rtl8169_close(struct net_device *dev)
5529{
5530 struct rtl8169_private *tp = netdev_priv(dev);
5531 struct pci_dev *pdev = tp->pci_dev;
5532
e1759441
RW		 5533 pm_runtime_get_sync(&pdev->dev);
5534
cecb5fd7 5535 /* Update counters before going down */
355423d0
IV		 5536 rtl8169_update_counters(dev);
5537
1da177e4
LT		 5538 rtl8169_down(dev);
5539
5540 free_irq(dev->irq, dev);
5541
82553bb6
SG		 5542 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5543 tp->RxPhyAddr);
5544 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5545 tp->TxPhyAddr);
1da177e4
LT		 5546 tp->TxDescArray = NULL;
5547 tp->RxDescArray = NULL;
5548
e1759441
RW		 5549 pm_runtime_put_sync(&pdev->dev);
5550
1da177e4
LT		 5551 return 0;
5552}
5553
07ce4064 5554static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 5555{
5556 struct rtl8169_private *tp = netdev_priv(dev);
5557 void __iomem *ioaddr = tp->mmio_addr;
5558 unsigned long flags;
5559 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 5560 int rx_mode;
1da177e4
LT		 5561 u32 tmp = 0;
5562
5563 if (dev->flags & IFF_PROMISC) {
5564 /* Unconditionally log net taps. */
bf82c189 5565 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 5566 rx_mode =
5567 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5568 AcceptAllPhys;
5569 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 5570 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 5571 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 5572 /* Too many to filter perfectly -- accept all multicasts. */
5573 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5574 mc_filter[1] = mc_filter[0] = 0xffffffff;
5575 } else {
22bedad3 5576 struct netdev_hw_addr *ha;
07d3f51f 5577
1da177e4
LT		 5578 rx_mode = AcceptBroadcast | AcceptMyPhys;
5579 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 5580 netdev_for_each_mc_addr(ha, dev) {
5581 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 5582 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5583 rx_mode |= AcceptMulticast;
5584 }
5585 }
5586
5587 spin_lock_irqsave(&tp->lock, flags);
5588
e542a226 5589 tmp = RTL_R32(RxConfig) | rx_mode;
1da177e4 5590
f887cce8 5591 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 5592 u32 data = mc_filter[0];
5593
5594 mc_filter[0] = swab32(mc_filter[1]);
5595 mc_filter[1] = swab32(data);
bcf0bf90
FR		 5596 }
5597
1da177e4 5598 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 5599 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 5600
57a9f236
FR		 5601 RTL_W32(RxConfig, tmp);
5602
1da177e4
LT		 5603 spin_unlock_irqrestore(&tp->lock, flags);
5604}
5605
5606/**
5607 * rtl8169_get_stats - Get rtl8169 read/write statistics
5608 * @dev: The Ethernet Device to get statistics for
5609 *
5610 * Get TX/RX statistics for rtl8169
5611 */
5612static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5613{
5614 struct rtl8169_private *tp = netdev_priv(dev);
5615 void __iomem *ioaddr = tp->mmio_addr;
5616 unsigned long flags;
5617
5618 if (netif_running(dev)) {
5619 spin_lock_irqsave(&tp->lock, flags);
523a6094 5620 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 5621 spin_unlock_irqrestore(&tp->lock, flags);
5622 }
5b0384f4 5623
cebf8cc7 5624 return &dev->stats;
1da177e4
LT		 5625}
5626
861ab440 5627static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 5628{
065c27c1 5629 struct rtl8169_private *tp = netdev_priv(dev);
5630
5d06a99f 5631 if (!netif_running(dev))
861ab440 5632 return;
5d06a99f 5633
065c27c1 5634 rtl_pll_power_down(tp);
5635
5d06a99f
FR		 5636 netif_device_detach(dev);
5637 netif_stop_queue(dev);
861ab440
RW		 5638}
5639
5640#ifdef CONFIG_PM
5641
5642static int rtl8169_suspend(struct device *device)
5643{
5644 struct pci_dev *pdev = to_pci_dev(device);
5645 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 5646
861ab440 5647 rtl8169_net_suspend(dev);
1371fa6d 5648
5d06a99f
FR		 5649 return 0;
5650}
5651
e1759441
RW		 5652static void __rtl8169_resume(struct net_device *dev)
5653{
065c27c1 5654 struct rtl8169_private *tp = netdev_priv(dev);
5655
e1759441 5656 netif_device_attach(dev);
065c27c1 5657
5658 rtl_pll_power_up(tp);
5659
e1759441
RW		 5660 rtl8169_schedule_work(dev, rtl8169_reset_task);
5661}
5662
861ab440 5663static int rtl8169_resume(struct device *device)
5d06a99f 5664{
861ab440 5665 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 5666 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 5667 struct rtl8169_private *tp = netdev_priv(dev);
5668
5669 rtl8169_init_phy(dev, tp);
5d06a99f 5670
e1759441
RW		 5671 if (netif_running(dev))
5672 __rtl8169_resume(dev);
5d06a99f 5673
e1759441
RW		 5674 return 0;
5675}
5676
5677static int rtl8169_runtime_suspend(struct device *device)
5678{
5679 struct pci_dev *pdev = to_pci_dev(device);
5680 struct net_device *dev = pci_get_drvdata(pdev);
5681 struct rtl8169_private *tp = netdev_priv(dev);
5682
5683 if (!tp->TxDescArray)
5684 return 0;
5685
5686 spin_lock_irq(&tp->lock);
5687 tp->saved_wolopts = __rtl8169_get_wol(tp);
5688 __rtl8169_set_wol(tp, WAKE_ANY);
5689 spin_unlock_irq(&tp->lock);
5690
5691 rtl8169_net_suspend(dev);
5692
5693 return 0;
5694}
5695
5696static int rtl8169_runtime_resume(struct device *device)
5697{
5698 struct pci_dev *pdev = to_pci_dev(device);
5699 struct net_device *dev = pci_get_drvdata(pdev);
5700 struct rtl8169_private *tp = netdev_priv(dev);
5701
5702 if (!tp->TxDescArray)
5703 return 0;
5704
5705 spin_lock_irq(&tp->lock);
5706 __rtl8169_set_wol(tp, tp->saved_wolopts);
5707 tp->saved_wolopts = 0;
5708 spin_unlock_irq(&tp->lock);
5709
fccec10b
SG		 5710 rtl8169_init_phy(dev, tp);
5711
e1759441 5712 __rtl8169_resume(dev);
5d06a99f 5713
5d06a99f
FR		 5714 return 0;
5715}
5716
e1759441
RW		 5717static int rtl8169_runtime_idle(struct device *device)
5718{
5719 struct pci_dev *pdev = to_pci_dev(device);
5720 struct net_device *dev = pci_get_drvdata(pdev);
5721 struct rtl8169_private *tp = netdev_priv(dev);
5722
e4fbce74 5723 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 5724}
5725
47145210 5726static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 5727 .suspend = rtl8169_suspend,
5728 .resume = rtl8169_resume,
5729 .freeze = rtl8169_suspend,
5730 .thaw = rtl8169_resume,
5731 .poweroff = rtl8169_suspend,
5732 .restore = rtl8169_resume,
5733 .runtime_suspend = rtl8169_runtime_suspend,
5734 .runtime_resume = rtl8169_runtime_resume,
5735 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 5736};
5737
5738#define RTL8169_PM_OPS (&rtl8169_pm_ops)
5739
5740#else /* !CONFIG_PM */
5741
5742#define RTL8169_PM_OPS NULL
5743
5744#endif /* !CONFIG_PM */
5745
1765f95d
FR		 5746static void rtl_shutdown(struct pci_dev *pdev)
5747{
861ab440 5748 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 5749 struct rtl8169_private *tp = netdev_priv(dev);
5750 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 5751
5752 rtl8169_net_suspend(dev);
1765f95d 5753
cecb5fd7 5754 /* Restore original MAC address */
cc098dc7
IV		 5755 rtl_rar_set(tp, dev->perm_addr);
5756
4bb3f522 5757 spin_lock_irq(&tp->lock);
5758
92fc43b4 5759 rtl8169_hw_reset(tp);
4bb3f522 5760
5761 spin_unlock_irq(&tp->lock);
5762
861ab440 5763 if (system_state == SYSTEM_POWER_OFF) {
aaa89c08
HW		 5764 /* WoL fails with 8168b when the receiver is disabled. */
5765 if ((tp->mac_version == RTL_GIGA_MAC_VER_11 ||
5766 tp->mac_version == RTL_GIGA_MAC_VER_12 ||
5767 tp->mac_version == RTL_GIGA_MAC_VER_17) &&
5768 (tp->features & RTL_FEATURE_WOL)) {
ca52efd5 5769 pci_clear_master(pdev);
5770
5771 RTL_W8(ChipCmd, CmdRxEnb);
5772 /* PCI commit */
5773 RTL_R8(ChipCmd);
5774 }
5775
861ab440
RW		 5776 pci_wake_from_d3(pdev, true);
5777 pci_set_power_state(pdev, PCI_D3hot);
5778 }
5779}
5d06a99f 5780
1da177e4
LT		 5781static struct pci_driver rtl8169_pci_driver = {
5782 .name = MODULENAME,
5783 .id_table = rtl8169_pci_tbl,
5784 .probe = rtl8169_init_one,
5785 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 5786 .shutdown = rtl_shutdown,
861ab440 5787 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 5788};
5789
07d3f51f 5790static int __init rtl8169_init_module(void)
1da177e4 5791{
29917620 5792 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 5793}
5794
07d3f51f 5795static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 5796{
5797 pci_unregister_driver(&rtl8169_pci_driver);
5798}
5799
5800module_init(rtl8169_init_module);
5801module_exit(rtl8169_cleanup_module);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git