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r8169: phy init for the 8168
[thirdparty/kernel/stable.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
26
99f252b0 27#include <asm/system.h>
1da177e4
LT		 28#include <asm/io.h>
29#include <asm/irq.h>
30
f7ccf420
SH		 31#ifdef CONFIG_R8169_NAPI
32#define NAPI_SUFFIX "-NAPI"
33#else
34#define NAPI_SUFFIX ""
35#endif
36
37#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
1da177e4
LT		 38#define MODULENAME "r8169"
39#define PFX MODULENAME ": "
40
41#ifdef RTL8169_DEBUG
42#define assert(expr) \
5b0384f4
FR		 43 if (!(expr)) { \
44 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
45 #expr,__FILE__,__FUNCTION__,__LINE__); \
46 }
06fa7358
JP		 47#define dprintk(fmt, args...) \
48 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 49#else
50#define assert(expr) do {} while (0)
51#define dprintk(fmt, args...) do {} while (0)
52#endif /* RTL8169_DEBUG */
53
b57b7e5a 54#define R8169_MSG_DEFAULT \
f0e837d9 55 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 56
1da177e4
LT		 57#define TX_BUFFS_AVAIL(tp) \
58 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
59
60#ifdef CONFIG_R8169_NAPI
61#define rtl8169_rx_skb netif_receive_skb
0b50f81d 62#define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
1da177e4
LT		 63#define rtl8169_rx_quota(count, quota) min(count, quota)
64#else
65#define rtl8169_rx_skb netif_rx
0b50f81d 66#define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
1da177e4
LT		 67#define rtl8169_rx_quota(count, quota) count
68#endif
69
1da177e4 70/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309 71static const int max_interrupt_work = 20;
1da177e4
LT		 72
73/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
74 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 75static const int multicast_filter_limit = 32;
1da177e4
LT		 76
77/* MAC address length */
78#define MAC_ADDR_LEN 6
79
80#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
81#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
82#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 83#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 84#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
85#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
86#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
87
88#define R8169_REGS_SIZE 256
89#define R8169_NAPI_WEIGHT 64
90#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
91#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
92#define RX_BUF_SIZE 1536 /* Rx Buffer size */
93#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
94#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
95
96#define RTL8169_TX_TIMEOUT (6*HZ)
97#define RTL8169_PHY_TIMEOUT (10*HZ)
98
99/* write/read MMIO register */
100#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
101#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
102#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
103#define RTL_R8(reg) readb (ioaddr + (reg))
104#define RTL_R16(reg) readw (ioaddr + (reg))
105#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
106
107enum mac_version {
ba6eb6ee
FR		 108 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
109 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
110 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
111 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
112 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 113 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2dd99530 114 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 115 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
116 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
117 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
118 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
119 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
120 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
121 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
122 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
123 RTL_GIGA_MAC_VER_20 = 0x14 // 8168C
1da177e4
LT		 124};
125
1da177e4
LT		 126#define _R(NAME,MAC,MASK) \
127 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
128
3c6bee1d 129static const struct {
1da177e4
LT		 130 const char *name;
131 u8 mac_version;
132 u32 RxConfigMask; /* Clears the bits supported by this chip */
133} rtl_chip_info[] = {
ba6eb6ee
FR		 134 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
135 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
136 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
137 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
138 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 139 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
bcf0bf90
FR		 140 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
141 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
142 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
143 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 144 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
145 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
146 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
147 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
148 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
149 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880) // PCI-E
1da177e4
LT		 150};
151#undef _R
152
bcf0bf90
FR		 153enum cfg_version {
154 RTL_CFG_0 = 0x00,
155 RTL_CFG_1,
156 RTL_CFG_2
157};
158
07ce4064
FR		 159static void rtl_hw_start_8169(struct net_device *);
160static void rtl_hw_start_8168(struct net_device *);
161static void rtl_hw_start_8101(struct net_device *);
162
1da177e4 163static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 164 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 165 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 166 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 167 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 168 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
169 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 170 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 171 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
172 { PCI_VENDOR_ID_LINKSYS, 0x1032,
173 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
1da177e4
LT		 174 {0,},
175};
176
177MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
178
179static int rx_copybreak = 200;
180static int use_dac;
b57b7e5a
SH		 181static struct {
182 u32 msg_enable;
183} debug = { -1 };
1da177e4 184
07d3f51f
FR		 185enum rtl_registers {
186 MAC0 = 0, /* Ethernet hardware address. */
773d2021 187 MAC4 = 4,
07d3f51f
FR		 188 MAR0 = 8, /* Multicast filter. */
189 CounterAddrLow = 0x10,
190 CounterAddrHigh = 0x14,
191 TxDescStartAddrLow = 0x20,
192 TxDescStartAddrHigh = 0x24,
193 TxHDescStartAddrLow = 0x28,
194 TxHDescStartAddrHigh = 0x2c,
195 FLASH = 0x30,
196 ERSR = 0x36,
197 ChipCmd = 0x37,
198 TxPoll = 0x38,
199 IntrMask = 0x3c,
200 IntrStatus = 0x3e,
201 TxConfig = 0x40,
202 RxConfig = 0x44,
203 RxMissed = 0x4c,
204 Cfg9346 = 0x50,
205 Config0 = 0x51,
206 Config1 = 0x52,
207 Config2 = 0x53,
208 Config3 = 0x54,
209 Config4 = 0x55,
210 Config5 = 0x56,
211 MultiIntr = 0x5c,
212 PHYAR = 0x60,
213 TBICSR = 0x64,
214 TBI_ANAR = 0x68,
215 TBI_LPAR = 0x6a,
216 PHYstatus = 0x6c,
217 RxMaxSize = 0xda,
218 CPlusCmd = 0xe0,
219 IntrMitigate = 0xe2,
220 RxDescAddrLow = 0xe4,
221 RxDescAddrHigh = 0xe8,
222 EarlyTxThres = 0xec,
223 FuncEvent = 0xf0,
224 FuncEventMask = 0xf4,
225 FuncPresetState = 0xf8,
226 FuncForceEvent = 0xfc,
1da177e4
LT		 227};
228
07d3f51f 229enum rtl_register_content {
1da177e4 230 /* InterruptStatusBits */
07d3f51f
FR		 231 SYSErr = 0x8000,
232 PCSTimeout = 0x4000,
233 SWInt = 0x0100,
234 TxDescUnavail = 0x0080,
235 RxFIFOOver = 0x0040,
236 LinkChg = 0x0020,
237 RxOverflow = 0x0010,
238 TxErr = 0x0008,
239 TxOK = 0x0004,
240 RxErr = 0x0002,
241 RxOK = 0x0001,
1da177e4
LT		 242
243 /* RxStatusDesc */
9dccf611
FR		 244 RxFOVF = (1 << 23),
245 RxRWT = (1 << 22),
246 RxRES = (1 << 21),
247 RxRUNT = (1 << 20),
248 RxCRC = (1 << 19),
1da177e4
LT		 249
250 /* ChipCmdBits */
07d3f51f
FR		 251 CmdReset = 0x10,
252 CmdRxEnb = 0x08,
253 CmdTxEnb = 0x04,
254 RxBufEmpty = 0x01,
1da177e4 255
275391a4
FR		 256 /* TXPoll register p.5 */
257 HPQ = 0x80, /* Poll cmd on the high prio queue */
258 NPQ = 0x40, /* Poll cmd on the low prio queue */
259 FSWInt = 0x01, /* Forced software interrupt */
260
1da177e4 261 /* Cfg9346Bits */
07d3f51f
FR		 262 Cfg9346_Lock = 0x00,
263 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 264
265 /* rx_mode_bits */
07d3f51f
FR		 266 AcceptErr = 0x20,
267 AcceptRunt = 0x10,
268 AcceptBroadcast = 0x08,
269 AcceptMulticast = 0x04,
270 AcceptMyPhys = 0x02,
271 AcceptAllPhys = 0x01,
1da177e4
LT		 272
273 /* RxConfigBits */
07d3f51f
FR		 274 RxCfgFIFOShift = 13,
275 RxCfgDMAShift = 8,
1da177e4
LT		 276
277 /* TxConfigBits */
278 TxInterFrameGapShift = 24,
279 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
280
5d06a99f 281 /* Config1 register p.24 */
fbac58fc 282 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
5d06a99f
FR		 283 PMEnable = (1 << 0), /* Power Management Enable */
284
6dccd16b
FR		 285 /* Config2 register p. 25 */
286 PCI_Clock_66MHz = 0x01,
287 PCI_Clock_33MHz = 0x00,
288
61a4dcc2
FR		 289 /* Config3 register p.25 */
290 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
291 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
292
5d06a99f 293 /* Config5 register p.27 */
61a4dcc2
FR		 294 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
295 MWF = (1 << 5), /* Accept Multicast wakeup frame */
296 UWF = (1 << 4), /* Accept Unicast wakeup frame */
297 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 298 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
299
1da177e4
LT		 300 /* TBICSR p.28 */
301 TBIReset = 0x80000000,
302 TBILoopback = 0x40000000,
303 TBINwEnable = 0x20000000,
304 TBINwRestart = 0x10000000,
305 TBILinkOk = 0x02000000,
306 TBINwComplete = 0x01000000,
307
308 /* CPlusCmd p.31 */
0e485150 309 PktCntrDisable = (1 << 7), // 8168
1da177e4
LT		 310 RxVlan = (1 << 6),
311 RxChkSum = (1 << 5),
312 PCIDAC = (1 << 4),
313 PCIMulRW = (1 << 3),
0e485150
FR		 314 INTT_0 = 0x0000, // 8168
315 INTT_1 = 0x0001, // 8168
316 INTT_2 = 0x0002, // 8168
317 INTT_3 = 0x0003, // 8168
1da177e4
LT		 318
319 /* rtl8169_PHYstatus */
07d3f51f
FR		 320 TBI_Enable = 0x80,
321 TxFlowCtrl = 0x40,
322 RxFlowCtrl = 0x20,
323 _1000bpsF = 0x10,
324 _100bps = 0x08,
325 _10bps = 0x04,
326 LinkStatus = 0x02,
327 FullDup = 0x01,
1da177e4 328
1da177e4 329 /* _TBICSRBit */
07d3f51f 330 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 331
332 /* DumpCounterCommand */
07d3f51f 333 CounterDump = 0x8,
1da177e4
LT		 334};
335
07d3f51f 336enum desc_status_bit {
1da177e4
LT		 337 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
338 RingEnd = (1 << 30), /* End of descriptor ring */
339 FirstFrag = (1 << 29), /* First segment of a packet */
340 LastFrag = (1 << 28), /* Final segment of a packet */
341
342 /* Tx private */
343 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
344 MSSShift = 16, /* MSS value position */
345 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
346 IPCS = (1 << 18), /* Calculate IP checksum */
347 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
348 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
349 TxVlanTag = (1 << 17), /* Add VLAN tag */
350
351 /* Rx private */
352 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
353 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
354
355#define RxProtoUDP (PID1)
356#define RxProtoTCP (PID0)
357#define RxProtoIP (PID1 | PID0)
358#define RxProtoMask RxProtoIP
359
360 IPFail = (1 << 16), /* IP checksum failed */
361 UDPFail = (1 << 15), /* UDP/IP checksum failed */
362 TCPFail = (1 << 14), /* TCP/IP checksum failed */
363 RxVlanTag = (1 << 16), /* VLAN tag available */
364};
365
366#define RsvdMask 0x3fffc000
367
368struct TxDesc {
6cccd6e7
REB		 369 __le32 opts1;
370 __le32 opts2;
371 __le64 addr;
1da177e4
LT		 372};
373
374struct RxDesc {
6cccd6e7
REB		 375 __le32 opts1;
376 __le32 opts2;
377 __le64 addr;
1da177e4
LT		 378};
379
380struct ring_info {
381 struct sk_buff *skb;
382 u32 len;
383 u8 __pad[sizeof(void *) - sizeof(u32)];
384};
385
f23e7fda
FR		 386enum features {
387 RTL_FEATURE_WOL = (1 << 0),
fbac58fc 388 RTL_FEATURE_MSI = (1 << 1),
f23e7fda
FR		 389};
390
1da177e4
LT		 391struct rtl8169_private {
392 void __iomem *mmio_addr; /* memory map physical address */
393 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 394 struct net_device *dev;
bea3348e 395 struct napi_struct napi;
1da177e4 396 spinlock_t lock; /* spin lock flag */
b57b7e5a 397 u32 msg_enable;
1da177e4
LT		 398 int chipset;
399 int mac_version;
1da177e4
LT		 400 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
401 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
402 u32 dirty_rx;
403 u32 dirty_tx;
404 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
405 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
406 dma_addr_t TxPhyAddr;
407 dma_addr_t RxPhyAddr;
408 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
409 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 410 unsigned align;
1da177e4
LT		 411 unsigned rx_buf_sz;
412 struct timer_list timer;
413 u16 cp_cmd;
0e485150
FR		 414 u16 intr_event;
415 u16 napi_event;
1da177e4
LT		 416 u16 intr_mask;
417 int phy_auto_nego_reg;
418 int phy_1000_ctrl_reg;
419#ifdef CONFIG_R8169_VLAN
420 struct vlan_group *vlgrp;
421#endif
422 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
423 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
424 void (*phy_reset_enable)(void __iomem *);
07ce4064 425 void (*hw_start)(struct net_device *);
1da177e4
LT		 426 unsigned int (*phy_reset_pending)(void __iomem *);
427 unsigned int (*link_ok)(void __iomem *);
c4028958 428 struct delayed_work task;
f23e7fda 429 unsigned features;
1da177e4
LT		 430};
431
979b6c13 432MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 433MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 434module_param(rx_copybreak, int, 0);
1b7efd58 435MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 436module_param(use_dac, int, 0);
437MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 438module_param_named(debug, debug.msg_enable, int, 0);
439MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 440MODULE_LICENSE("GPL");
441MODULE_VERSION(RTL8169_VERSION);
442
443static int rtl8169_open(struct net_device *dev);
444static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 445static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 446static int rtl8169_init_ring(struct net_device *dev);
07ce4064 447static void rtl_hw_start(struct net_device *dev);
1da177e4 448static int rtl8169_close(struct net_device *dev);
07ce4064 449static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 450static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 451static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 452static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 453 void __iomem *, u32 budget);
4dcb7d33 454static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 455static void rtl8169_down(struct net_device *dev);
99f252b0 456static void rtl8169_rx_clear(struct rtl8169_private *tp);
1da177e4
LT		 457
458#ifdef CONFIG_R8169_NAPI
bea3348e 459static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4
LT		 460#endif
461
1da177e4 462static const unsigned int rtl8169_rx_config =
5b0384f4 463 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 464
07d3f51f 465static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 466{
467 int i;
468
07d3f51f 469 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0xFF) << 16 | value);
1da177e4 470
2371408c 471 for (i = 20; i > 0; i--) {
07d3f51f
FR		 472 /*
473 * Check if the RTL8169 has completed writing to the specified
474 * MII register.
475 */
5b0384f4 476 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 477 break;
2371408c 478 udelay(25);
1da177e4
LT		 479 }
480}
481
07d3f51f 482static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 483{
484 int i, value = -1;
485
07d3f51f 486 RTL_W32(PHYAR, 0x0 | (reg_addr & 0xFF) << 16);
1da177e4 487
2371408c 488 for (i = 20; i > 0; i--) {
07d3f51f
FR		 489 /*
490 * Check if the RTL8169 has completed retrieving data from
491 * the specified MII register.
492 */
1da177e4
LT		 493 if (RTL_R32(PHYAR) & 0x80000000) {
494 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
495 break;
496 }
2371408c 497 udelay(25);
1da177e4
LT		 498 }
499 return value;
500}
501
502static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
503{
504 RTL_W16(IntrMask, 0x0000);
505
506 RTL_W16(IntrStatus, 0xffff);
507}
508
509static void rtl8169_asic_down(void __iomem *ioaddr)
510{
511 RTL_W8(ChipCmd, 0x00);
512 rtl8169_irq_mask_and_ack(ioaddr);
513 RTL_R16(CPlusCmd);
514}
515
516static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
517{
518 return RTL_R32(TBICSR) & TBIReset;
519}
520
521static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
522{
64e4bfb4 523 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 524}
525
526static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
527{
528 return RTL_R32(TBICSR) & TBILinkOk;
529}
530
531static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
532{
533 return RTL_R8(PHYstatus) & LinkStatus;
534}
535
536static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
537{
538 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
539}
540
541static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
542{
543 unsigned int val;
544
9e0db8ef
FR		 545 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
546 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 547}
548
549static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 550 struct rtl8169_private *tp,
551 void __iomem *ioaddr)
1da177e4
LT		 552{
553 unsigned long flags;
554
555 spin_lock_irqsave(&tp->lock, flags);
556 if (tp->link_ok(ioaddr)) {
557 netif_carrier_on(dev);
b57b7e5a
SH		 558 if (netif_msg_ifup(tp))
559 printk(KERN_INFO PFX "%s: link up\n", dev->name);
560 } else {
561 if (netif_msg_ifdown(tp))
562 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 563 netif_carrier_off(dev);
b57b7e5a 564 }
1da177e4
LT		 565 spin_unlock_irqrestore(&tp->lock, flags);
566}
567
61a4dcc2
FR		 568static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
569{
570 struct rtl8169_private *tp = netdev_priv(dev);
571 void __iomem *ioaddr = tp->mmio_addr;
572 u8 options;
573
574 wol->wolopts = 0;
575
576#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
577 wol->supported = WAKE_ANY;
578
579 spin_lock_irq(&tp->lock);
580
581 options = RTL_R8(Config1);
582 if (!(options & PMEnable))
583 goto out_unlock;
584
585 options = RTL_R8(Config3);
586 if (options & LinkUp)
587 wol->wolopts |= WAKE_PHY;
588 if (options & MagicPacket)
589 wol->wolopts |= WAKE_MAGIC;
590
591 options = RTL_R8(Config5);
592 if (options & UWF)
593 wol->wolopts |= WAKE_UCAST;
594 if (options & BWF)
5b0384f4 595 wol->wolopts |= WAKE_BCAST;
61a4dcc2 596 if (options & MWF)
5b0384f4 597 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 598
599out_unlock:
600 spin_unlock_irq(&tp->lock);
601}
602
603static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
604{
605 struct rtl8169_private *tp = netdev_priv(dev);
606 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 607 unsigned int i;
61a4dcc2
FR		 608 static struct {
609 u32 opt;
610 u16 reg;
611 u8 mask;
612 } cfg[] = {
613 { WAKE_ANY, Config1, PMEnable },
614 { WAKE_PHY, Config3, LinkUp },
615 { WAKE_MAGIC, Config3, MagicPacket },
616 { WAKE_UCAST, Config5, UWF },
617 { WAKE_BCAST, Config5, BWF },
618 { WAKE_MCAST, Config5, MWF },
619 { WAKE_ANY, Config5, LanWake }
620 };
621
622 spin_lock_irq(&tp->lock);
623
624 RTL_W8(Cfg9346, Cfg9346_Unlock);
625
626 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
627 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
628 if (wol->wolopts & cfg[i].opt)
629 options |= cfg[i].mask;
630 RTL_W8(cfg[i].reg, options);
631 }
632
633 RTL_W8(Cfg9346, Cfg9346_Lock);
634
f23e7fda
FR		 635 if (wol->wolopts)
636 tp->features |= RTL_FEATURE_WOL;
637 else
638 tp->features &= ~RTL_FEATURE_WOL;
61a4dcc2
FR		 639
640 spin_unlock_irq(&tp->lock);
641
642 return 0;
643}
644
1da177e4
LT		 645static void rtl8169_get_drvinfo(struct net_device *dev,
646 struct ethtool_drvinfo *info)
647{
648 struct rtl8169_private *tp = netdev_priv(dev);
649
650 strcpy(info->driver, MODULENAME);
651 strcpy(info->version, RTL8169_VERSION);
652 strcpy(info->bus_info, pci_name(tp->pci_dev));
653}
654
655static int rtl8169_get_regs_len(struct net_device *dev)
656{
657 return R8169_REGS_SIZE;
658}
659
660static int rtl8169_set_speed_tbi(struct net_device *dev,
661 u8 autoneg, u16 speed, u8 duplex)
662{
663 struct rtl8169_private *tp = netdev_priv(dev);
664 void __iomem *ioaddr = tp->mmio_addr;
665 int ret = 0;
666 u32 reg;
667
668 reg = RTL_R32(TBICSR);
669 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
670 (duplex == DUPLEX_FULL)) {
671 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
672 } else if (autoneg == AUTONEG_ENABLE)
673 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
674 else {
b57b7e5a
SH		 675 if (netif_msg_link(tp)) {
676 printk(KERN_WARNING "%s: "
677 "incorrect speed setting refused in TBI mode\n",
678 dev->name);
679 }
1da177e4
LT		 680 ret = -EOPNOTSUPP;
681 }
682
683 return ret;
684}
685
686static int rtl8169_set_speed_xmii(struct net_device *dev,
687 u8 autoneg, u16 speed, u8 duplex)
688{
689 struct rtl8169_private *tp = netdev_priv(dev);
690 void __iomem *ioaddr = tp->mmio_addr;
691 int auto_nego, giga_ctrl;
692
64e4bfb4
FR		 693 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
694 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
695 ADVERTISE_100HALF | ADVERTISE_100FULL);
696 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
697 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 698
699 if (autoneg == AUTONEG_ENABLE) {
64e4bfb4
FR		 700 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
701 ADVERTISE_100HALF | ADVERTISE_100FULL);
702 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 703 } else {
704 if (speed == SPEED_10)
64e4bfb4 705 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1da177e4 706 else if (speed == SPEED_100)
64e4bfb4 707 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1da177e4 708 else if (speed == SPEED_1000)
64e4bfb4 709 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 710
711 if (duplex == DUPLEX_HALF)
64e4bfb4 712 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
726ecdcf
AG		 713
714 if (duplex == DUPLEX_FULL)
64e4bfb4 715 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
bcf0bf90
FR		 716
717 /* This tweak comes straight from Realtek's driver. */
718 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
e3cf0cc0
FR		 719 ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
720 (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
64e4bfb4 721 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
bcf0bf90
FR		 722 }
723 }
724
725 /* The 8100e/8101e do Fast Ethernet only. */
726 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
727 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
e3cf0cc0
FR		 728 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
729 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
64e4bfb4 730 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
bcf0bf90
FR		 731 netif_msg_link(tp)) {
732 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
733 dev->name);
734 }
64e4bfb4 735 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 736 }
737
623a1593
FR		 738 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
739
e3cf0cc0
FR		 740 if ((tp->mac_version == RTL_GIGA_MAC_VER_12) ||
741 (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
2584fbc3
RS		 742 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
743 mdio_write(ioaddr, 0x1f, 0x0000);
744 mdio_write(ioaddr, 0x0e, 0x0000);
745 }
746
1da177e4
LT		 747 tp->phy_auto_nego_reg = auto_nego;
748 tp->phy_1000_ctrl_reg = giga_ctrl;
749
64e4bfb4
FR		 750 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
751 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
752 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1da177e4
LT		 753 return 0;
754}
755
756static int rtl8169_set_speed(struct net_device *dev,
757 u8 autoneg, u16 speed, u8 duplex)
758{
759 struct rtl8169_private *tp = netdev_priv(dev);
760 int ret;
761
762 ret = tp->set_speed(dev, autoneg, speed, duplex);
763
64e4bfb4 764 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 765 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
766
767 return ret;
768}
769
770static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
771{
772 struct rtl8169_private *tp = netdev_priv(dev);
773 unsigned long flags;
774 int ret;
775
776 spin_lock_irqsave(&tp->lock, flags);
777 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
778 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 779
1da177e4
LT		 780 return ret;
781}
782
783static u32 rtl8169_get_rx_csum(struct net_device *dev)
784{
785 struct rtl8169_private *tp = netdev_priv(dev);
786
787 return tp->cp_cmd & RxChkSum;
788}
789
790static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
791{
792 struct rtl8169_private *tp = netdev_priv(dev);
793 void __iomem *ioaddr = tp->mmio_addr;
794 unsigned long flags;
795
796 spin_lock_irqsave(&tp->lock, flags);
797
798 if (data)
799 tp->cp_cmd |= RxChkSum;
800 else
801 tp->cp_cmd &= ~RxChkSum;
802
803 RTL_W16(CPlusCmd, tp->cp_cmd);
804 RTL_R16(CPlusCmd);
805
806 spin_unlock_irqrestore(&tp->lock, flags);
807
808 return 0;
809}
810
811#ifdef CONFIG_R8169_VLAN
812
813static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
814 struct sk_buff *skb)
815{
816 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
817 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
818}
819
820static void rtl8169_vlan_rx_register(struct net_device *dev,
821 struct vlan_group *grp)
822{
823 struct rtl8169_private *tp = netdev_priv(dev);
824 void __iomem *ioaddr = tp->mmio_addr;
825 unsigned long flags;
826
827 spin_lock_irqsave(&tp->lock, flags);
828 tp->vlgrp = grp;
829 if (tp->vlgrp)
830 tp->cp_cmd |= RxVlan;
831 else
832 tp->cp_cmd &= ~RxVlan;
833 RTL_W16(CPlusCmd, tp->cp_cmd);
834 RTL_R16(CPlusCmd);
835 spin_unlock_irqrestore(&tp->lock, flags);
836}
837
1da177e4
LT		 838static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
839 struct sk_buff *skb)
840{
841 u32 opts2 = le32_to_cpu(desc->opts2);
842 int ret;
843
844 if (tp->vlgrp && (opts2 & RxVlanTag)) {
07d3f51f 845 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, swab16(opts2 & 0xffff));
1da177e4
LT		 846 ret = 0;
847 } else
848 ret = -1;
849 desc->opts2 = 0;
850 return ret;
851}
852
853#else /* !CONFIG_R8169_VLAN */
854
855static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
856 struct sk_buff *skb)
857{
858 return 0;
859}
860
861static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
862 struct sk_buff *skb)
863{
864 return -1;
865}
866
867#endif
868
869static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
870{
871 struct rtl8169_private *tp = netdev_priv(dev);
872 void __iomem *ioaddr = tp->mmio_addr;
873 u32 status;
874
875 cmd->supported =
876 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
877 cmd->port = PORT_FIBRE;
878 cmd->transceiver = XCVR_INTERNAL;
879
880 status = RTL_R32(TBICSR);
881 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
882 cmd->autoneg = !!(status & TBINwEnable);
883
884 cmd->speed = SPEED_1000;
885 cmd->duplex = DUPLEX_FULL; /* Always set */
886}
887
888static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
889{
890 struct rtl8169_private *tp = netdev_priv(dev);
891 void __iomem *ioaddr = tp->mmio_addr;
892 u8 status;
893
894 cmd->supported = SUPPORTED_10baseT_Half |
895 SUPPORTED_10baseT_Full |
896 SUPPORTED_100baseT_Half |
897 SUPPORTED_100baseT_Full |
898 SUPPORTED_1000baseT_Full |
899 SUPPORTED_Autoneg |
5b0384f4 900 SUPPORTED_TP;
1da177e4
LT		 901
902 cmd->autoneg = 1;
903 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
904
64e4bfb4 905 if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
1da177e4 906 cmd->advertising |= ADVERTISED_10baseT_Half;
64e4bfb4 907 if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
1da177e4 908 cmd->advertising |= ADVERTISED_10baseT_Full;
64e4bfb4 909 if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
1da177e4 910 cmd->advertising |= ADVERTISED_100baseT_Half;
64e4bfb4 911 if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
1da177e4 912 cmd->advertising |= ADVERTISED_100baseT_Full;
64e4bfb4 913 if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
1da177e4
LT		 914 cmd->advertising |= ADVERTISED_1000baseT_Full;
915
916 status = RTL_R8(PHYstatus);
917
918 if (status & _1000bpsF)
919 cmd->speed = SPEED_1000;
920 else if (status & _100bps)
921 cmd->speed = SPEED_100;
922 else if (status & _10bps)
923 cmd->speed = SPEED_10;
924
623a1593
FR		 925 if (status & TxFlowCtrl)
926 cmd->advertising |= ADVERTISED_Asym_Pause;
927 if (status & RxFlowCtrl)
928 cmd->advertising |= ADVERTISED_Pause;
929
1da177e4
LT		 930 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
931 DUPLEX_FULL : DUPLEX_HALF;
932}
933
934static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
935{
936 struct rtl8169_private *tp = netdev_priv(dev);
937 unsigned long flags;
938
939 spin_lock_irqsave(&tp->lock, flags);
940
941 tp->get_settings(dev, cmd);
942
943 spin_unlock_irqrestore(&tp->lock, flags);
944 return 0;
945}
946
947static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
948 void *p)
949{
5b0384f4
FR		 950 struct rtl8169_private *tp = netdev_priv(dev);
951 unsigned long flags;
1da177e4 952
5b0384f4
FR		 953 if (regs->len > R8169_REGS_SIZE)
954 regs->len = R8169_REGS_SIZE;
1da177e4 955
5b0384f4
FR		 956 spin_lock_irqsave(&tp->lock, flags);
957 memcpy_fromio(p, tp->mmio_addr, regs->len);
958 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 959}
960
b57b7e5a
SH		 961static u32 rtl8169_get_msglevel(struct net_device *dev)
962{
963 struct rtl8169_private *tp = netdev_priv(dev);
964
965 return tp->msg_enable;
966}
967
968static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
969{
970 struct rtl8169_private *tp = netdev_priv(dev);
971
972 tp->msg_enable = value;
973}
974
d4a3a0fc
SH		 975static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
976 "tx_packets",
977 "rx_packets",
978 "tx_errors",
979 "rx_errors",
980 "rx_missed",
981 "align_errors",
982 "tx_single_collisions",
983 "tx_multi_collisions",
984 "unicast",
985 "broadcast",
986 "multicast",
987 "tx_aborted",
988 "tx_underrun",
989};
990
991struct rtl8169_counters {
b1eab701
AV		 992 __le64 tx_packets;
993 __le64 rx_packets;
994 __le64 tx_errors;
995 __le32 rx_errors;
996 __le16 rx_missed;
997 __le16 align_errors;
998 __le32 tx_one_collision;
999 __le32 tx_multi_collision;
1000 __le64 rx_unicast;
1001 __le64 rx_broadcast;
1002 __le32 rx_multicast;
1003 __le16 tx_aborted;
1004 __le16 tx_underun;
d4a3a0fc
SH		 1005};
1006
b9f2c044 1007static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1008{
b9f2c044
JG		 1009 switch (sset) {
1010 case ETH_SS_STATS:
1011 return ARRAY_SIZE(rtl8169_gstrings);
1012 default:
1013 return -EOPNOTSUPP;
1014 }
d4a3a0fc
SH		 1015}
1016
1017static void rtl8169_get_ethtool_stats(struct net_device *dev,
1018 struct ethtool_stats *stats, u64 *data)
1019{
1020 struct rtl8169_private *tp = netdev_priv(dev);
1021 void __iomem *ioaddr = tp->mmio_addr;
1022 struct rtl8169_counters *counters;
1023 dma_addr_t paddr;
1024 u32 cmd;
1025
1026 ASSERT_RTNL();
1027
1028 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1029 if (!counters)
1030 return;
1031
1032 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1033 cmd = (u64)paddr & DMA_32BIT_MASK;
1034 RTL_W32(CounterAddrLow, cmd);
1035 RTL_W32(CounterAddrLow, cmd | CounterDump);
1036
1037 while (RTL_R32(CounterAddrLow) & CounterDump) {
1038 if (msleep_interruptible(1))
1039 break;
1040 }
1041
1042 RTL_W32(CounterAddrLow, 0);
1043 RTL_W32(CounterAddrHigh, 0);
1044
5b0384f4 1045 data[0] = le64_to_cpu(counters->tx_packets);
d4a3a0fc
SH		 1046 data[1] = le64_to_cpu(counters->rx_packets);
1047 data[2] = le64_to_cpu(counters->tx_errors);
1048 data[3] = le32_to_cpu(counters->rx_errors);
1049 data[4] = le16_to_cpu(counters->rx_missed);
1050 data[5] = le16_to_cpu(counters->align_errors);
1051 data[6] = le32_to_cpu(counters->tx_one_collision);
1052 data[7] = le32_to_cpu(counters->tx_multi_collision);
1053 data[8] = le64_to_cpu(counters->rx_unicast);
1054 data[9] = le64_to_cpu(counters->rx_broadcast);
1055 data[10] = le32_to_cpu(counters->rx_multicast);
1056 data[11] = le16_to_cpu(counters->tx_aborted);
1057 data[12] = le16_to_cpu(counters->tx_underun);
1058
1059 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1060}
1061
1062static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1063{
1064 switch(stringset) {
1065 case ETH_SS_STATS:
1066 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1067 break;
1068 }
1069}
1070
7282d491 1071static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1072 .get_drvinfo = rtl8169_get_drvinfo,
1073 .get_regs_len = rtl8169_get_regs_len,
1074 .get_link = ethtool_op_get_link,
1075 .get_settings = rtl8169_get_settings,
1076 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1077 .get_msglevel = rtl8169_get_msglevel,
1078 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1079 .get_rx_csum = rtl8169_get_rx_csum,
1080 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1081 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1082 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1083 .set_tso = ethtool_op_set_tso,
1084 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1085 .get_wol = rtl8169_get_wol,
1086 .set_wol = rtl8169_set_wol,
d4a3a0fc 1087 .get_strings = rtl8169_get_strings,
b9f2c044 1088 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1089 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1090};
1091
07d3f51f
FR		 1092static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1093 int bitnum, int bitval)
1da177e4
LT		 1094{
1095 int val;
1096
1097 val = mdio_read(ioaddr, reg);
1098 val = (bitval == 1) ?
1099 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
5b0384f4 1100 mdio_write(ioaddr, reg, val & 0xffff);
1da177e4
LT		 1101}
1102
07d3f51f
FR		 1103static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1104 void __iomem *ioaddr)
1da177e4 1105{
0e485150
FR		 1106 /*
1107 * The driver currently handles the 8168Bf and the 8168Be identically
1108 * but they can be identified more specifically through the test below
1109 * if needed:
1110 *
1111 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1112 *
1113 * Same thing for the 8101Eb and the 8101Ec:
1114 *
1115 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1116 */
1da177e4
LT		 1117 const struct {
1118 u32 mask;
e3cf0cc0 1119 u32 val;
1da177e4
LT		 1120 int mac_version;
1121 } mac_info[] = {
e3cf0cc0
FR		 1122 /* 8168B family. */
1123 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1124 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1125 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1126 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20 },
1127
1128 /* 8168B family. */
1129 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1130 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1131 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1132 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1133
1134 /* 8101 family. */
1135 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1136 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1137 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1138 /* FIXME: where did these entries come from ? -- FR */
1139 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1140 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1141
1142 /* 8110 family. */
1143 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1144 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1145 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1146 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1147 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1148 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1149
1150 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1da177e4
LT		 1151 }, *p = mac_info;
1152 u32 reg;
1153
e3cf0cc0
FR		 1154 reg = RTL_R32(TxConfig);
1155 while ((reg & p->mask) != p->val)
1da177e4
LT		 1156 p++;
1157 tp->mac_version = p->mac_version;
e3cf0cc0
FR		 1158
1159 if (p->mask == 0x00000000) {
1160 struct pci_dev *pdev = tp->pci_dev;
1161
1162 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1163 }
1da177e4
LT		 1164}
1165
1166static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1167{
bcf0bf90 1168 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1169}
1170
867763c1
FR		 1171struct phy_reg {
1172 u16 reg;
1173 u16 val;
1174};
1175
1176static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1177{
1178 while (len-- > 0) {
1179 mdio_write(ioaddr, regs->reg, regs->val);
1180 regs++;
1181 }
1182}
1183
5615d9f1 1184static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1da177e4 1185{
1da177e4
LT		 1186 struct {
1187 u16 regs[5]; /* Beware of bit-sign propagation */
1188 } phy_magic[5] = { {
1189 { 0x0000, //w 4 15 12 0
1190 0x00a1, //w 3 15 0 00a1
1191 0x0008, //w 2 15 0 0008
1192 0x1020, //w 1 15 0 1020
1193 0x1000 } },{ //w 0 15 0 1000
1194 { 0x7000, //w 4 15 12 7
1195 0xff41, //w 3 15 0 ff41
1196 0xde60, //w 2 15 0 de60
1197 0x0140, //w 1 15 0 0140
1198 0x0077 } },{ //w 0 15 0 0077
1199 { 0xa000, //w 4 15 12 a
1200 0xdf01, //w 3 15 0 df01
1201 0xdf20, //w 2 15 0 df20
1202 0xff95, //w 1 15 0 ff95
1203 0xfa00 } },{ //w 0 15 0 fa00
1204 { 0xb000, //w 4 15 12 b
1205 0xff41, //w 3 15 0 ff41
1206 0xde20, //w 2 15 0 de20
1207 0x0140, //w 1 15 0 0140
1208 0x00bb } },{ //w 0 15 0 00bb
1209 { 0xf000, //w 4 15 12 f
1210 0xdf01, //w 3 15 0 df01
1211 0xdf20, //w 2 15 0 df20
1212 0xff95, //w 1 15 0 ff95
1213 0xbf00 } //w 0 15 0 bf00
1214 }
1215 }, *p = phy_magic;
07d3f51f 1216 unsigned int i;
1da177e4 1217
1da177e4
LT		 1218 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1219 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1220 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1221 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1222
1223 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1224 int val, pos = 4;
1225
1226 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1227 mdio_write(ioaddr, pos, val);
1228 while (--pos >= 0)
1229 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1230 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1231 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1232 }
1233 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1234}
1235
5615d9f1
FR		 1236static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1237{
1238 mdio_write(ioaddr, 31, 0x0002);
1239 mdio_write(ioaddr, 1, 0x90d0);
1240 mdio_write(ioaddr, 31, 0x0000);
1241}
1242
867763c1
FR		 1243static void rtl8168cp_hw_phy_config(void __iomem *ioaddr)
1244{
1245 struct phy_reg phy_reg_init[] = {
1246 { 0x1f, 0x0000 },
1247 { 0x1d, 0x0f00 },
1248 { 0x1f, 0x0002 },
1249 { 0x0c, 0x1ec8 },
1250 { 0x1f, 0x0000 }
1251 };
1252
1253 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1254}
1255
1256static void rtl8168c_hw_phy_config(void __iomem *ioaddr)
1257{
1258 struct phy_reg phy_reg_init[] = {
1259 { 0x1f, 0x0002 },
1260 { 0x00, 0x88d4 },
1261 { 0x01, 0x82b1 },
1262 { 0x03, 0x7002 },
1263 { 0x08, 0x9e30 },
1264 { 0x09, 0x01f0 },
1265 { 0x0a, 0x5500 },
1266 { 0x0c, 0x00c8 },
1267 { 0x1f, 0x0003 },
1268 { 0x12, 0xc096 },
1269 { 0x16, 0x000a },
1270 { 0x1f, 0x0000 }
1271 };
1272
1273 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1274}
1275
5615d9f1
FR		 1276static void rtl_hw_phy_config(struct net_device *dev)
1277{
1278 struct rtl8169_private *tp = netdev_priv(dev);
1279 void __iomem *ioaddr = tp->mmio_addr;
1280
1281 rtl8169_print_mac_version(tp);
1282
1283 switch (tp->mac_version) {
1284 case RTL_GIGA_MAC_VER_01:
1285 break;
1286 case RTL_GIGA_MAC_VER_02:
1287 case RTL_GIGA_MAC_VER_03:
1288 rtl8169s_hw_phy_config(ioaddr);
1289 break;
1290 case RTL_GIGA_MAC_VER_04:
1291 rtl8169sb_hw_phy_config(ioaddr);
1292 break;
867763c1
FR		 1293 case RTL_GIGA_MAC_VER_18:
1294 rtl8168cp_hw_phy_config(ioaddr);
1295 break;
1296 case RTL_GIGA_MAC_VER_19:
1297 rtl8168c_hw_phy_config(ioaddr);
1298 break;
5615d9f1
FR		 1299 default:
1300 break;
1301 }
1302}
1303
1da177e4
LT		 1304static void rtl8169_phy_timer(unsigned long __opaque)
1305{
1306 struct net_device *dev = (struct net_device *)__opaque;
1307 struct rtl8169_private *tp = netdev_priv(dev);
1308 struct timer_list *timer = &tp->timer;
1309 void __iomem *ioaddr = tp->mmio_addr;
1310 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1311
bcf0bf90 1312 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 1313
64e4bfb4 1314 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1315 return;
1316
1317 spin_lock_irq(&tp->lock);
1318
1319 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 1320 /*
1da177e4
LT		 1321 * A busy loop could burn quite a few cycles on nowadays CPU.
1322 * Let's delay the execution of the timer for a few ticks.
1323 */
1324 timeout = HZ/10;
1325 goto out_mod_timer;
1326 }
1327
1328 if (tp->link_ok(ioaddr))
1329 goto out_unlock;
1330
b57b7e5a
SH		 1331 if (netif_msg_link(tp))
1332 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1333
1334 tp->phy_reset_enable(ioaddr);
1335
1336out_mod_timer:
1337 mod_timer(timer, jiffies + timeout);
1338out_unlock:
1339 spin_unlock_irq(&tp->lock);
1340}
1341
1342static inline void rtl8169_delete_timer(struct net_device *dev)
1343{
1344 struct rtl8169_private *tp = netdev_priv(dev);
1345 struct timer_list *timer = &tp->timer;
1346
e179bb7b 1347 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1348 return;
1349
1350 del_timer_sync(timer);
1351}
1352
1353static inline void rtl8169_request_timer(struct net_device *dev)
1354{
1355 struct rtl8169_private *tp = netdev_priv(dev);
1356 struct timer_list *timer = &tp->timer;
1357
e179bb7b 1358 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1359 return;
1360
2efa53f3 1361 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 1362}
1363
1364#ifdef CONFIG_NET_POLL_CONTROLLER
1365/*
1366 * Polling 'interrupt' - used by things like netconsole to send skbs
1367 * without having to re-enable interrupts. It's not called while
1368 * the interrupt routine is executing.
1369 */
1370static void rtl8169_netpoll(struct net_device *dev)
1371{
1372 struct rtl8169_private *tp = netdev_priv(dev);
1373 struct pci_dev *pdev = tp->pci_dev;
1374
1375 disable_irq(pdev->irq);
7d12e780 1376 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 1377 enable_irq(pdev->irq);
1378}
1379#endif
1380
1381static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1382 void __iomem *ioaddr)
1383{
1384 iounmap(ioaddr);
1385 pci_release_regions(pdev);
1386 pci_disable_device(pdev);
1387 free_netdev(dev);
1388}
1389
bf793295
FR		 1390static void rtl8169_phy_reset(struct net_device *dev,
1391 struct rtl8169_private *tp)
1392{
1393 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1394 unsigned int i;
bf793295
FR		 1395
1396 tp->phy_reset_enable(ioaddr);
1397 for (i = 0; i < 100; i++) {
1398 if (!tp->phy_reset_pending(ioaddr))
1399 return;
1400 msleep(1);
1401 }
1402 if (netif_msg_link(tp))
1403 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1404}
1405
4ff96fa6
FR		 1406static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1407{
1408 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 1409
5615d9f1 1410 rtl_hw_phy_config(dev);
4ff96fa6
FR		 1411
1412 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1413 RTL_W8(0x82, 0x01);
1414
6dccd16b
FR		 1415 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1416
1417 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1418 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 1419
bcf0bf90 1420 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 1421 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1422 RTL_W8(0x82, 0x01);
1423 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1424 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1425 }
1426
bf793295
FR		 1427 rtl8169_phy_reset(dev, tp);
1428
901dda2b
FR		 1429 /*
1430 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1431 * only 8101. Don't panic.
1432 */
1433 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6
FR		 1434
1435 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1436 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1437}
1438
773d2021
FR		 1439static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1440{
1441 void __iomem *ioaddr = tp->mmio_addr;
1442 u32 high;
1443 u32 low;
1444
1445 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1446 high = addr[4] | (addr[5] << 8);
1447
1448 spin_lock_irq(&tp->lock);
1449
1450 RTL_W8(Cfg9346, Cfg9346_Unlock);
1451 RTL_W32(MAC0, low);
1452 RTL_W32(MAC4, high);
1453 RTL_W8(Cfg9346, Cfg9346_Lock);
1454
1455 spin_unlock_irq(&tp->lock);
1456}
1457
1458static int rtl_set_mac_address(struct net_device *dev, void *p)
1459{
1460 struct rtl8169_private *tp = netdev_priv(dev);
1461 struct sockaddr *addr = p;
1462
1463 if (!is_valid_ether_addr(addr->sa_data))
1464 return -EADDRNOTAVAIL;
1465
1466 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1467
1468 rtl_rar_set(tp, dev->dev_addr);
1469
1470 return 0;
1471}
1472
5f787a1a
FR		 1473static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1474{
1475 struct rtl8169_private *tp = netdev_priv(dev);
1476 struct mii_ioctl_data *data = if_mii(ifr);
1477
1478 if (!netif_running(dev))
1479 return -ENODEV;
1480
1481 switch (cmd) {
1482 case SIOCGMIIPHY:
1483 data->phy_id = 32; /* Internal PHY */
1484 return 0;
1485
1486 case SIOCGMIIREG:
1487 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1488 return 0;
1489
1490 case SIOCSMIIREG:
1491 if (!capable(CAP_NET_ADMIN))
1492 return -EPERM;
1493 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1494 return 0;
1495 }
1496 return -EOPNOTSUPP;
1497}
1498
0e485150
FR		 1499static const struct rtl_cfg_info {
1500 void (*hw_start)(struct net_device *);
1501 unsigned int region;
1502 unsigned int align;
1503 u16 intr_event;
1504 u16 napi_event;
fbac58fc 1505 unsigned msi;
0e485150
FR		 1506} rtl_cfg_infos [] = {
1507 [RTL_CFG_0] = {
1508 .hw_start = rtl_hw_start_8169,
1509 .region = 1,
e9f63f30 1510 .align = 0,
0e485150
FR		 1511 .intr_event = SYSErr | LinkChg | RxOverflow |
1512 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc
FR		 1513 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1514 .msi = 0
0e485150
FR		 1515 },
1516 [RTL_CFG_1] = {
1517 .hw_start = rtl_hw_start_8168,
1518 .region = 2,
1519 .align = 8,
1520 .intr_event = SYSErr | LinkChg | RxOverflow |
1521 TxErr | TxOK | RxOK | RxErr,
fbac58fc
FR		 1522 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
1523 .msi = RTL_FEATURE_MSI
0e485150
FR		 1524 },
1525 [RTL_CFG_2] = {
1526 .hw_start = rtl_hw_start_8101,
1527 .region = 2,
1528 .align = 8,
1529 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1530 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc
FR		 1531 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1532 .msi = RTL_FEATURE_MSI
0e485150
FR		 1533 }
1534};
1535
fbac58fc
FR		 1536/* Cfg9346_Unlock assumed. */
1537static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1538 const struct rtl_cfg_info *cfg)
1539{
1540 unsigned msi = 0;
1541 u8 cfg2;
1542
1543 cfg2 = RTL_R8(Config2) & ~MSIEnable;
1544 if (cfg->msi) {
1545 if (pci_enable_msi(pdev)) {
1546 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1547 } else {
1548 cfg2 |= MSIEnable;
1549 msi = RTL_FEATURE_MSI;
1550 }
1551 }
1552 RTL_W8(Config2, cfg2);
1553 return msi;
1554}
1555
1556static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1557{
1558 if (tp->features & RTL_FEATURE_MSI) {
1559 pci_disable_msi(pdev);
1560 tp->features &= ~RTL_FEATURE_MSI;
1561 }
1562}
1563
1da177e4 1564static int __devinit
4ff96fa6 1565rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1566{
0e485150
FR		 1567 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1568 const unsigned int region = cfg->region;
1da177e4 1569 struct rtl8169_private *tp;
4ff96fa6
FR		 1570 struct net_device *dev;
1571 void __iomem *ioaddr;
07d3f51f
FR		 1572 unsigned int i;
1573 int rc;
1da177e4 1574
4ff96fa6
FR		 1575 if (netif_msg_drv(&debug)) {
1576 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1577 MODULENAME, RTL8169_VERSION);
1578 }
1da177e4 1579
1da177e4 1580 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 1581 if (!dev) {
b57b7e5a 1582 if (netif_msg_drv(&debug))
9b91cf9d 1583 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 1584 rc = -ENOMEM;
1585 goto out;
1da177e4
LT		 1586 }
1587
1da177e4
LT		 1588 SET_NETDEV_DEV(dev, &pdev->dev);
1589 tp = netdev_priv(dev);
c4028958 1590 tp->dev = dev;
b57b7e5a 1591 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4
LT		 1592
1593 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1594 rc = pci_enable_device(pdev);
b57b7e5a 1595 if (rc < 0) {
2e8a538d 1596 if (netif_msg_probe(tp))
9b91cf9d 1597 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 1598 goto err_out_free_dev_1;
1da177e4
LT		 1599 }
1600
1601 rc = pci_set_mwi(pdev);
1602 if (rc < 0)
4ff96fa6 1603 goto err_out_disable_2;
1da177e4 1604
1da177e4 1605 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 1606 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 1607 if (netif_msg_probe(tp)) {
9b91cf9d 1608 dev_err(&pdev->dev,
bcf0bf90
FR		 1609 "region #%d not an MMIO resource, aborting\n",
1610 region);
4ff96fa6 1611 }
1da177e4 1612 rc = -ENODEV;
4ff96fa6 1613 goto err_out_mwi_3;
1da177e4 1614 }
4ff96fa6 1615
1da177e4 1616 /* check for weird/broken PCI region reporting */
bcf0bf90 1617 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 1618 if (netif_msg_probe(tp)) {
9b91cf9d 1619 dev_err(&pdev->dev,
4ff96fa6
FR		 1620 "Invalid PCI region size(s), aborting\n");
1621 }
1da177e4 1622 rc = -ENODEV;
4ff96fa6 1623 goto err_out_mwi_3;
1da177e4
LT		 1624 }
1625
1626 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 1627 if (rc < 0) {
2e8a538d 1628 if (netif_msg_probe(tp))
9b91cf9d 1629 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 1630 goto err_out_mwi_3;
1da177e4
LT		 1631 }
1632
1633 tp->cp_cmd = PCIMulRW | RxChkSum;
1634
1635 if ((sizeof(dma_addr_t) > 4) &&
1636 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1637 tp->cp_cmd |= PCIDAC;
1638 dev->features |= NETIF_F_HIGHDMA;
1639 } else {
1640 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1641 if (rc < 0) {
4ff96fa6 1642 if (netif_msg_probe(tp)) {
9b91cf9d 1643 dev_err(&pdev->dev,
4ff96fa6
FR		 1644 "DMA configuration failed.\n");
1645 }
1646 goto err_out_free_res_4;
1da177e4
LT		 1647 }
1648 }
1649
1650 pci_set_master(pdev);
1651
1652 /* ioremap MMIO region */
bcf0bf90 1653 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 1654 if (!ioaddr) {
b57b7e5a 1655 if (netif_msg_probe(tp))
9b91cf9d 1656 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 1657 rc = -EIO;
4ff96fa6 1658 goto err_out_free_res_4;
1da177e4
LT		 1659 }
1660
1661 /* Unneeded ? Don't mess with Mrs. Murphy. */
1662 rtl8169_irq_mask_and_ack(ioaddr);
1663
1664 /* Soft reset the chip. */
1665 RTL_W8(ChipCmd, CmdReset);
1666
1667 /* Check that the chip has finished the reset. */
07d3f51f 1668 for (i = 0; i < 100; i++) {
1da177e4
LT		 1669 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1670 break;
b518fa8e 1671 msleep_interruptible(1);
1da177e4
LT		 1672 }
1673
1674 /* Identify chip attached to board */
1675 rtl8169_get_mac_version(tp, ioaddr);
1da177e4
LT		 1676
1677 rtl8169_print_mac_version(tp);
1da177e4
LT		 1678
1679 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1680 if (tp->mac_version == rtl_chip_info[i].mac_version)
1681 break;
1682 }
1683 if (i < 0) {
1684 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a 1685 if (netif_msg_probe(tp)) {
2e8a538d 1686 dev_printk(KERN_DEBUG, &pdev->dev,
4ff96fa6
FR		 1687 "unknown chip version, assuming %s\n",
1688 rtl_chip_info[0].name);
b57b7e5a 1689 }
1da177e4
LT		 1690 i++;
1691 }
1692 tp->chipset = i;
1693
5d06a99f
FR		 1694 RTL_W8(Cfg9346, Cfg9346_Unlock);
1695 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1696 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
fbac58fc 1697 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 1698 RTL_W8(Cfg9346, Cfg9346_Lock);
1699
1da177e4
LT		 1700 if (RTL_R8(PHYstatus) & TBI_Enable) {
1701 tp->set_speed = rtl8169_set_speed_tbi;
1702 tp->get_settings = rtl8169_gset_tbi;
1703 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1704 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1705 tp->link_ok = rtl8169_tbi_link_ok;
1706
64e4bfb4 1707 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 1708 } else {
1709 tp->set_speed = rtl8169_set_speed_xmii;
1710 tp->get_settings = rtl8169_gset_xmii;
1711 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1712 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1713 tp->link_ok = rtl8169_xmii_link_ok;
5f787a1a
FR		 1714
1715 dev->do_ioctl = rtl8169_ioctl;
1da177e4
LT		 1716 }
1717
1718 /* Get MAC address. FIXME: read EEPROM */
1719 for (i = 0; i < MAC_ADDR_LEN; i++)
1720 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 1721 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1722
1723 dev->open = rtl8169_open;
1724 dev->hard_start_xmit = rtl8169_start_xmit;
1725 dev->get_stats = rtl8169_get_stats;
1726 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1727 dev->stop = rtl8169_close;
1728 dev->tx_timeout = rtl8169_tx_timeout;
07ce4064 1729 dev->set_multicast_list = rtl_set_rx_mode;
1da177e4
LT		 1730 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1731 dev->irq = pdev->irq;
1732 dev->base_addr = (unsigned long) ioaddr;
1733 dev->change_mtu = rtl8169_change_mtu;
773d2021 1734 dev->set_mac_address = rtl_set_mac_address;
1da177e4
LT		 1735
1736#ifdef CONFIG_R8169_NAPI
bea3348e 1737 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 1738#endif
1739
1740#ifdef CONFIG_R8169_VLAN
1741 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1742 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1da177e4
LT		 1743#endif
1744
1745#ifdef CONFIG_NET_POLL_CONTROLLER
1746 dev->poll_controller = rtl8169_netpoll;
1747#endif
1748
1749 tp->intr_mask = 0xffff;
1750 tp->pci_dev = pdev;
1751 tp->mmio_addr = ioaddr;
0e485150
FR		 1752 tp->align = cfg->align;
1753 tp->hw_start = cfg->hw_start;
1754 tp->intr_event = cfg->intr_event;
1755 tp->napi_event = cfg->napi_event;
1da177e4 1756
2efa53f3
FR		 1757 init_timer(&tp->timer);
1758 tp->timer.data = (unsigned long) dev;
1759 tp->timer.function = rtl8169_phy_timer;
1760
1da177e4
LT		 1761 spin_lock_init(&tp->lock);
1762
1763 rc = register_netdev(dev);
4ff96fa6 1764 if (rc < 0)
fbac58fc 1765 goto err_out_msi_5;
1da177e4
LT		 1766
1767 pci_set_drvdata(pdev, dev);
1768
b57b7e5a 1769 if (netif_msg_probe(tp)) {
96b9709c
FR		 1770 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1771
b57b7e5a
SH		 1772 printk(KERN_INFO "%s: %s at 0x%lx, "
1773 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
96b9709c 1774 "XID %08x IRQ %d\n",
b57b7e5a 1775 dev->name,
bcf0bf90 1776 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 1777 dev->base_addr,
1778 dev->dev_addr[0], dev->dev_addr[1],
1779 dev->dev_addr[2], dev->dev_addr[3],
96b9709c 1780 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
b57b7e5a 1781 }
1da177e4 1782
4ff96fa6 1783 rtl8169_init_phy(dev, tp);
1da177e4 1784
4ff96fa6
FR		 1785out:
1786 return rc;
1da177e4 1787
fbac58fc
FR		 1788err_out_msi_5:
1789 rtl_disable_msi(pdev, tp);
4ff96fa6
FR		 1790 iounmap(ioaddr);
1791err_out_free_res_4:
1792 pci_release_regions(pdev);
1793err_out_mwi_3:
1794 pci_clear_mwi(pdev);
1795err_out_disable_2:
1796 pci_disable_device(pdev);
1797err_out_free_dev_1:
1798 free_netdev(dev);
1799 goto out;
1da177e4
LT		 1800}
1801
07d3f51f 1802static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 1803{
1804 struct net_device *dev = pci_get_drvdata(pdev);
1805 struct rtl8169_private *tp = netdev_priv(dev);
1806
eb2a021c
FR		 1807 flush_scheduled_work();
1808
1da177e4 1809 unregister_netdev(dev);
fbac58fc 1810 rtl_disable_msi(pdev, tp);
1da177e4
LT		 1811 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1812 pci_set_drvdata(pdev, NULL);
1813}
1814
1da177e4
LT		 1815static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1816 struct net_device *dev)
1817{
1818 unsigned int mtu = dev->mtu;
1819
1820 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1821}
1822
1823static int rtl8169_open(struct net_device *dev)
1824{
1825 struct rtl8169_private *tp = netdev_priv(dev);
1826 struct pci_dev *pdev = tp->pci_dev;
99f252b0 1827 int retval = -ENOMEM;
1da177e4 1828
1da177e4 1829
99f252b0 1830 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 1831
1832 /*
1833 * Rx and Tx desscriptors needs 256 bytes alignment.
1834 * pci_alloc_consistent provides more.
1835 */
1836 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1837 &tp->TxPhyAddr);
1838 if (!tp->TxDescArray)
99f252b0 1839 goto out;
1da177e4
LT		 1840
1841 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1842 &tp->RxPhyAddr);
1843 if (!tp->RxDescArray)
99f252b0 1844 goto err_free_tx_0;
1da177e4
LT		 1845
1846 retval = rtl8169_init_ring(dev);
1847 if (retval < 0)
99f252b0 1848 goto err_free_rx_1;
1da177e4 1849
c4028958 1850 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 1851
99f252b0
FR		 1852 smp_mb();
1853
fbac58fc
FR		 1854 retval = request_irq(dev->irq, rtl8169_interrupt,
1855 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 1856 dev->name, dev);
1857 if (retval < 0)
1858 goto err_release_ring_2;
1859
bea3348e
SH		 1860#ifdef CONFIG_R8169_NAPI
1861 napi_enable(&tp->napi);
1862#endif
1863
07ce4064 1864 rtl_hw_start(dev);
1da177e4
LT		 1865
1866 rtl8169_request_timer(dev);
1867
1868 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1869out:
1870 return retval;
1871
99f252b0
FR		 1872err_release_ring_2:
1873 rtl8169_rx_clear(tp);
1874err_free_rx_1:
1da177e4
LT		 1875 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1876 tp->RxPhyAddr);
99f252b0 1877err_free_tx_0:
1da177e4
LT		 1878 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1879 tp->TxPhyAddr);
1da177e4
LT		 1880 goto out;
1881}
1882
1883static void rtl8169_hw_reset(void __iomem *ioaddr)
1884{
1885 /* Disable interrupts */
1886 rtl8169_irq_mask_and_ack(ioaddr);
1887
1888 /* Reset the chipset */
1889 RTL_W8(ChipCmd, CmdReset);
1890
1891 /* PCI commit */
1892 RTL_R8(ChipCmd);
1893}
1894
7f796d83 1895static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 1896{
1897 void __iomem *ioaddr = tp->mmio_addr;
1898 u32 cfg = rtl8169_rx_config;
1899
1900 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1901 RTL_W32(RxConfig, cfg);
1902
1903 /* Set DMA burst size and Interframe Gap Time */
1904 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1905 (InterFrameGap << TxInterFrameGapShift));
1906}
1907
07ce4064 1908static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 1909{
1910 struct rtl8169_private *tp = netdev_priv(dev);
1911 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1912 unsigned int i;
1da177e4
LT		 1913
1914 /* Soft reset the chip. */
1915 RTL_W8(ChipCmd, CmdReset);
1916
1917 /* Check that the chip has finished the reset. */
07d3f51f 1918 for (i = 0; i < 100; i++) {
1da177e4
LT		 1919 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1920 break;
b518fa8e 1921 msleep_interruptible(1);
1da177e4
LT		 1922 }
1923
07ce4064
FR		 1924 tp->hw_start(dev);
1925
07ce4064
FR		 1926 netif_start_queue(dev);
1927}
1928
1929
7f796d83
FR		 1930static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1931 void __iomem *ioaddr)
1932{
1933 /*
1934 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1935 * register to be written before TxDescAddrLow to work.
1936 * Switching from MMIO to I/O access fixes the issue as well.
1937 */
1938 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1939 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1940 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1941 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1942}
1943
1944static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1945{
1946 u16 cmd;
1947
1948 cmd = RTL_R16(CPlusCmd);
1949 RTL_W16(CPlusCmd, cmd);
1950 return cmd;
1951}
1952
1953static void rtl_set_rx_max_size(void __iomem *ioaddr)
1954{
1955 /* Low hurts. Let's disable the filtering. */
1956 RTL_W16(RxMaxSize, 16383);
1957}
1958
6dccd16b
FR		 1959static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1960{
1961 struct {
1962 u32 mac_version;
1963 u32 clk;
1964 u32 val;
1965 } cfg2_info [] = {
1966 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1967 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1968 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1969 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1970 }, *p = cfg2_info;
1971 unsigned int i;
1972 u32 clk;
1973
1974 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
1975 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
1976 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1977 RTL_W32(0x7c, p->val);
1978 break;
1979 }
1980 }
1981}
1982
07ce4064
FR		 1983static void rtl_hw_start_8169(struct net_device *dev)
1984{
1985 struct rtl8169_private *tp = netdev_priv(dev);
1986 void __iomem *ioaddr = tp->mmio_addr;
1987 struct pci_dev *pdev = tp->pci_dev;
07ce4064 1988
9cb427b6
FR		 1989 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1990 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1991 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1992 }
1993
1da177e4 1994 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 1995 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1996 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1997 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1998 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1999 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2000
1da177e4
LT		 2001 RTL_W8(EarlyTxThres, EarlyTxThld);
2002
7f796d83 2003 rtl_set_rx_max_size(ioaddr);
1da177e4 2004
c946b304
FR		 2005 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2006 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2007 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2008 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2009 rtl_set_rx_tx_config_registers(tp);
1da177e4 2010
7f796d83 2011 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 2012
bcf0bf90
FR		 2013 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2014 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 2015 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 2016 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 2017 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 2018 }
2019
bcf0bf90
FR		 2020 RTL_W16(CPlusCmd, tp->cp_cmd);
2021
6dccd16b
FR		 2022 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2023
1da177e4
LT		 2024 /*
2025 * Undocumented corner. Supposedly:
2026 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2027 */
2028 RTL_W16(IntrMitigate, 0x0000);
2029
7f796d83 2030 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 2031
c946b304
FR		 2032 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2033 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2034 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2035 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2036 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2037 rtl_set_rx_tx_config_registers(tp);
2038 }
2039
1da177e4 2040 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 2041
2042 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2043 RTL_R8(IntrMask);
1da177e4
LT		 2044
2045 RTL_W32(RxMissed, 0);
2046
07ce4064 2047 rtl_set_rx_mode(dev);
1da177e4
LT		 2048
2049 /* no early-rx interrupts */
2050 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 2051
2052 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 2053 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2054}
1da177e4 2055
07ce4064
FR		 2056static void rtl_hw_start_8168(struct net_device *dev)
2057{
2dd99530
FR		 2058 struct rtl8169_private *tp = netdev_priv(dev);
2059 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2060 struct pci_dev *pdev = tp->pci_dev;
2061 u8 ctl;
2dd99530
FR		 2062
2063 RTL_W8(Cfg9346, Cfg9346_Unlock);
2064
2065 RTL_W8(EarlyTxThres, EarlyTxThld);
2066
2067 rtl_set_rx_max_size(ioaddr);
2068
0e485150
FR		 2069 rtl_set_rx_tx_config_registers(tp);
2070
2071 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 2072
2073 RTL_W16(CPlusCmd, tp->cp_cmd);
2074
0e485150
FR		 2075 /* Tx performance tweak. */
2076 pci_read_config_byte(pdev, 0x69, &ctl);
2077 ctl = (ctl & ~0x70) | 0x50;
2078 pci_write_config_byte(pdev, 0x69, ctl);
2dd99530 2079
0e485150 2080 RTL_W16(IntrMitigate, 0x5151);
2dd99530 2081
0e485150
FR		 2082 /* Work around for RxFIFO overflow. */
2083 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2084 tp->intr_event |= RxFIFOOver | PCSTimeout;
2085 tp->intr_event &= ~RxOverflow;
2086 }
2087
2088 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530
FR		 2089
2090 RTL_W8(Cfg9346, Cfg9346_Lock);
2091
2092 RTL_R8(IntrMask);
2093
2094 RTL_W32(RxMissed, 0);
2095
2096 rtl_set_rx_mode(dev);
2097
0e485150
FR		 2098 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2099
2dd99530 2100 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 2101
0e485150 2102 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2103}
1da177e4 2104
07ce4064
FR		 2105static void rtl_hw_start_8101(struct net_device *dev)
2106{
cdf1a608
FR		 2107 struct rtl8169_private *tp = netdev_priv(dev);
2108 void __iomem *ioaddr = tp->mmio_addr;
2109 struct pci_dev *pdev = tp->pci_dev;
2110
e3cf0cc0
FR		 2111 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2112 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
cdf1a608
FR		 2113 pci_write_config_word(pdev, 0x68, 0x00);
2114 pci_write_config_word(pdev, 0x69, 0x08);
2115 }
2116
2117 RTL_W8(Cfg9346, Cfg9346_Unlock);
2118
2119 RTL_W8(EarlyTxThres, EarlyTxThld);
2120
2121 rtl_set_rx_max_size(ioaddr);
2122
2123 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2124
2125 RTL_W16(CPlusCmd, tp->cp_cmd);
2126
2127 RTL_W16(IntrMitigate, 0x0000);
2128
2129 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2130
2131 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2132 rtl_set_rx_tx_config_registers(tp);
2133
2134 RTL_W8(Cfg9346, Cfg9346_Lock);
2135
2136 RTL_R8(IntrMask);
2137
2138 RTL_W32(RxMissed, 0);
2139
2140 rtl_set_rx_mode(dev);
2141
0e485150
FR		 2142 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2143
cdf1a608 2144 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 2145
0e485150 2146 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2147}
2148
2149static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2150{
2151 struct rtl8169_private *tp = netdev_priv(dev);
2152 int ret = 0;
2153
2154 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2155 return -EINVAL;
2156
2157 dev->mtu = new_mtu;
2158
2159 if (!netif_running(dev))
2160 goto out;
2161
2162 rtl8169_down(dev);
2163
2164 rtl8169_set_rxbufsize(tp, dev);
2165
2166 ret = rtl8169_init_ring(dev);
2167 if (ret < 0)
2168 goto out;
2169
bea3348e
SH		 2170#ifdef CONFIG_R8169_NAPI
2171 napi_enable(&tp->napi);
2172#endif
1da177e4 2173
07ce4064 2174 rtl_hw_start(dev);
1da177e4
LT		 2175
2176 rtl8169_request_timer(dev);
2177
2178out:
2179 return ret;
2180}
2181
2182static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2183{
2184 desc->addr = 0x0badbadbadbadbadull;
2185 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2186}
2187
2188static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2189 struct sk_buff **sk_buff, struct RxDesc *desc)
2190{
2191 struct pci_dev *pdev = tp->pci_dev;
2192
2193 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2194 PCI_DMA_FROMDEVICE);
2195 dev_kfree_skb(*sk_buff);
2196 *sk_buff = NULL;
2197 rtl8169_make_unusable_by_asic(desc);
2198}
2199
2200static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2201{
2202 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2203
2204 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2205}
2206
2207static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2208 u32 rx_buf_sz)
2209{
2210 desc->addr = cpu_to_le64(mapping);
2211 wmb();
2212 rtl8169_mark_to_asic(desc, rx_buf_sz);
2213}
2214
15d31758
SH		 2215static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2216 struct net_device *dev,
2217 struct RxDesc *desc, int rx_buf_sz,
2218 unsigned int align)
1da177e4
LT		 2219{
2220 struct sk_buff *skb;
2221 dma_addr_t mapping;
e9f63f30 2222 unsigned int pad;
1da177e4 2223
e9f63f30
FR		 2224 pad = align ? align : NET_IP_ALIGN;
2225
2226 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
1da177e4
LT		 2227 if (!skb)
2228 goto err_out;
2229
e9f63f30 2230 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
1da177e4 2231
689be439 2232 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 2233 PCI_DMA_FROMDEVICE);
2234
2235 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 2236out:
15d31758 2237 return skb;
1da177e4
LT		 2238
2239err_out:
1da177e4
LT		 2240 rtl8169_make_unusable_by_asic(desc);
2241 goto out;
2242}
2243
2244static void rtl8169_rx_clear(struct rtl8169_private *tp)
2245{
07d3f51f 2246 unsigned int i;
1da177e4
LT		 2247
2248 for (i = 0; i < NUM_RX_DESC; i++) {
2249 if (tp->Rx_skbuff[i]) {
2250 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2251 tp->RxDescArray + i);
2252 }
2253 }
2254}
2255
2256static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2257 u32 start, u32 end)
2258{
2259 u32 cur;
5b0384f4 2260
4ae47c2d 2261 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 2262 struct sk_buff *skb;
2263 unsigned int i = cur % NUM_RX_DESC;
1da177e4 2264
4ae47c2d
FR		 2265 WARN_ON((s32)(end - cur) < 0);
2266
1da177e4
LT		 2267 if (tp->Rx_skbuff[i])
2268 continue;
bcf0bf90 2269
15d31758
SH		 2270 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2271 tp->RxDescArray + i,
2272 tp->rx_buf_sz, tp->align);
2273 if (!skb)
1da177e4 2274 break;
15d31758
SH		 2275
2276 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 2277 }
2278 return cur - start;
2279}
2280
2281static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2282{
2283 desc->opts1 |= cpu_to_le32(RingEnd);
2284}
2285
2286static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2287{
2288 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2289}
2290
2291static int rtl8169_init_ring(struct net_device *dev)
2292{
2293 struct rtl8169_private *tp = netdev_priv(dev);
2294
2295 rtl8169_init_ring_indexes(tp);
2296
2297 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2298 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2299
2300 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2301 goto err_out;
2302
2303 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2304
2305 return 0;
2306
2307err_out:
2308 rtl8169_rx_clear(tp);
2309 return -ENOMEM;
2310}
2311
2312static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2313 struct TxDesc *desc)
2314{
2315 unsigned int len = tx_skb->len;
2316
2317 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2318 desc->opts1 = 0x00;
2319 desc->opts2 = 0x00;
2320 desc->addr = 0x00;
2321 tx_skb->len = 0;
2322}
2323
2324static void rtl8169_tx_clear(struct rtl8169_private *tp)
2325{
2326 unsigned int i;
2327
2328 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2329 unsigned int entry = i % NUM_TX_DESC;
2330 struct ring_info *tx_skb = tp->tx_skb + entry;
2331 unsigned int len = tx_skb->len;
2332
2333 if (len) {
2334 struct sk_buff *skb = tx_skb->skb;
2335
2336 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2337 tp->TxDescArray + entry);
2338 if (skb) {
2339 dev_kfree_skb(skb);
2340 tx_skb->skb = NULL;
2341 }
cebf8cc7 2342 tp->dev->stats.tx_dropped++;
1da177e4
LT		 2343 }
2344 }
2345 tp->cur_tx = tp->dirty_tx = 0;
2346}
2347
c4028958 2348static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 2349{
2350 struct rtl8169_private *tp = netdev_priv(dev);
2351
c4028958 2352 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 2353 schedule_delayed_work(&tp->task, 4);
2354}
2355
2356static void rtl8169_wait_for_quiescence(struct net_device *dev)
2357{
2358 struct rtl8169_private *tp = netdev_priv(dev);
2359 void __iomem *ioaddr = tp->mmio_addr;
2360
2361 synchronize_irq(dev->irq);
2362
2363 /* Wait for any pending NAPI task to complete */
bea3348e
SH		 2364#ifdef CONFIG_R8169_NAPI
2365 napi_disable(&tp->napi);
2366#endif
1da177e4
LT		 2367
2368 rtl8169_irq_mask_and_ack(ioaddr);
2369
bea3348e
SH		 2370#ifdef CONFIG_R8169_NAPI
2371 napi_enable(&tp->napi);
2372#endif
1da177e4
LT		 2373}
2374
c4028958 2375static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 2376{
c4028958
DH		 2377 struct rtl8169_private *tp =
2378 container_of(work, struct rtl8169_private, task.work);
2379 struct net_device *dev = tp->dev;
1da177e4
LT		 2380 int ret;
2381
eb2a021c
FR		 2382 rtnl_lock();
2383
2384 if (!netif_running(dev))
2385 goto out_unlock;
2386
2387 rtl8169_wait_for_quiescence(dev);
2388 rtl8169_close(dev);
1da177e4
LT		 2389
2390 ret = rtl8169_open(dev);
2391 if (unlikely(ret < 0)) {
07d3f51f 2392 if (net_ratelimit() && netif_msg_drv(tp)) {
53edbecd 2393 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
07d3f51f 2394 " Rescheduling.\n", dev->name, ret);
1da177e4
LT		 2395 }
2396 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2397 }
eb2a021c
FR		 2398
2399out_unlock:
2400 rtnl_unlock();
1da177e4
LT		 2401}
2402
c4028958 2403static void rtl8169_reset_task(struct work_struct *work)
1da177e4 2404{
c4028958
DH		 2405 struct rtl8169_private *tp =
2406 container_of(work, struct rtl8169_private, task.work);
2407 struct net_device *dev = tp->dev;
1da177e4 2408
eb2a021c
FR		 2409 rtnl_lock();
2410
1da177e4 2411 if (!netif_running(dev))
eb2a021c 2412 goto out_unlock;
1da177e4
LT		 2413
2414 rtl8169_wait_for_quiescence(dev);
2415
bea3348e 2416 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 2417 rtl8169_tx_clear(tp);
2418
2419 if (tp->dirty_rx == tp->cur_rx) {
2420 rtl8169_init_ring_indexes(tp);
07ce4064 2421 rtl_hw_start(dev);
1da177e4 2422 netif_wake_queue(dev);
cebf8cc7 2423 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 2424 } else {
07d3f51f 2425 if (net_ratelimit() && netif_msg_intr(tp)) {
53edbecd 2426 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
07d3f51f 2427 dev->name);
1da177e4
LT		 2428 }
2429 rtl8169_schedule_work(dev, rtl8169_reset_task);
2430 }
eb2a021c
FR		 2431
2432out_unlock:
2433 rtnl_unlock();
1da177e4
LT		 2434}
2435
2436static void rtl8169_tx_timeout(struct net_device *dev)
2437{
2438 struct rtl8169_private *tp = netdev_priv(dev);
2439
2440 rtl8169_hw_reset(tp->mmio_addr);
2441
2442 /* Let's wait a bit while any (async) irq lands on */
2443 rtl8169_schedule_work(dev, rtl8169_reset_task);
2444}
2445
2446static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2447 u32 opts1)
2448{
2449 struct skb_shared_info *info = skb_shinfo(skb);
2450 unsigned int cur_frag, entry;
a6343afb 2451 struct TxDesc * uninitialized_var(txd);
1da177e4
LT		 2452
2453 entry = tp->cur_tx;
2454 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2455 skb_frag_t *frag = info->frags + cur_frag;
2456 dma_addr_t mapping;
2457 u32 status, len;
2458 void *addr;
2459
2460 entry = (entry + 1) % NUM_TX_DESC;
2461
2462 txd = tp->TxDescArray + entry;
2463 len = frag->size;
2464 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2465 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2466
2467 /* anti gcc 2.95.3 bugware (sic) */
2468 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2469
2470 txd->opts1 = cpu_to_le32(status);
2471 txd->addr = cpu_to_le64(mapping);
2472
2473 tp->tx_skb[entry].len = len;
2474 }
2475
2476 if (cur_frag) {
2477 tp->tx_skb[entry].skb = skb;
2478 txd->opts1 |= cpu_to_le32(LastFrag);
2479 }
2480
2481 return cur_frag;
2482}
2483
2484static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2485{
2486 if (dev->features & NETIF_F_TSO) {
7967168c 2487 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 2488
2489 if (mss)
2490 return LargeSend | ((mss & MSSMask) << MSSShift);
2491 }
84fa7933 2492 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 2493 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 2494
2495 if (ip->protocol == IPPROTO_TCP)
2496 return IPCS | TCPCS;
2497 else if (ip->protocol == IPPROTO_UDP)
2498 return IPCS | UDPCS;
2499 WARN_ON(1); /* we need a WARN() */
2500 }
2501 return 0;
2502}
2503
2504static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2505{
2506 struct rtl8169_private *tp = netdev_priv(dev);
2507 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2508 struct TxDesc *txd = tp->TxDescArray + entry;
2509 void __iomem *ioaddr = tp->mmio_addr;
2510 dma_addr_t mapping;
2511 u32 status, len;
2512 u32 opts1;
188f4af0 2513 int ret = NETDEV_TX_OK;
5b0384f4 2514
1da177e4 2515 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 2516 if (netif_msg_drv(tp)) {
2517 printk(KERN_ERR
2518 "%s: BUG! Tx Ring full when queue awake!\n",
2519 dev->name);
2520 }
1da177e4
LT		 2521 goto err_stop;
2522 }
2523
2524 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2525 goto err_stop;
2526
2527 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2528
2529 frags = rtl8169_xmit_frags(tp, skb, opts1);
2530 if (frags) {
2531 len = skb_headlen(skb);
2532 opts1 |= FirstFrag;
2533 } else {
2534 len = skb->len;
2535
2536 if (unlikely(len < ETH_ZLEN)) {
5b057c6b 2537 if (skb_padto(skb, ETH_ZLEN))
1da177e4
LT		 2538 goto err_update_stats;
2539 len = ETH_ZLEN;
2540 }
2541
2542 opts1 |= FirstFrag | LastFrag;
2543 tp->tx_skb[entry].skb = skb;
2544 }
2545
2546 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2547
2548 tp->tx_skb[entry].len = len;
2549 txd->addr = cpu_to_le64(mapping);
2550 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2551
2552 wmb();
2553
2554 /* anti gcc 2.95.3 bugware (sic) */
2555 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2556 txd->opts1 = cpu_to_le32(status);
2557
2558 dev->trans_start = jiffies;
2559
2560 tp->cur_tx += frags + 1;
2561
2562 smp_wmb();
2563
275391a4 2564 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 2565
2566 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2567 netif_stop_queue(dev);
2568 smp_rmb();
2569 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2570 netif_wake_queue(dev);
2571 }
2572
2573out:
2574 return ret;
2575
2576err_stop:
2577 netif_stop_queue(dev);
188f4af0 2578 ret = NETDEV_TX_BUSY;
1da177e4 2579err_update_stats:
cebf8cc7 2580 dev->stats.tx_dropped++;
1da177e4
LT		 2581 goto out;
2582}
2583
2584static void rtl8169_pcierr_interrupt(struct net_device *dev)
2585{
2586 struct rtl8169_private *tp = netdev_priv(dev);
2587 struct pci_dev *pdev = tp->pci_dev;
2588 void __iomem *ioaddr = tp->mmio_addr;
2589 u16 pci_status, pci_cmd;
2590
2591 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2592 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2593
b57b7e5a
SH		 2594 if (netif_msg_intr(tp)) {
2595 printk(KERN_ERR
2596 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2597 dev->name, pci_cmd, pci_status);
2598 }
1da177e4
LT		 2599
2600 /*
2601 * The recovery sequence below admits a very elaborated explanation:
2602 * - it seems to work;
d03902b8
FR		 2603 * - I did not see what else could be done;
2604 * - it makes iop3xx happy.
1da177e4
LT		 2605 *
2606 * Feel free to adjust to your needs.
2607 */
a27993f3 2608 if (pdev->broken_parity_status)
d03902b8
FR		 2609 pci_cmd &= ~PCI_COMMAND_PARITY;
2610 else
2611 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2612
2613 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 2614
2615 pci_write_config_word(pdev, PCI_STATUS,
2616 pci_status & (PCI_STATUS_DETECTED_PARITY |
2617 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2618 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2619
2620 /* The infamous DAC f*ckup only happens at boot time */
2621 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 2622 if (netif_msg_intr(tp))
2623 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 2624 tp->cp_cmd &= ~PCIDAC;
2625 RTL_W16(CPlusCmd, tp->cp_cmd);
2626 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 2627 }
2628
2629 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 2630
2631 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 2632}
2633
07d3f51f
FR		 2634static void rtl8169_tx_interrupt(struct net_device *dev,
2635 struct rtl8169_private *tp,
2636 void __iomem *ioaddr)
1da177e4
LT		 2637{
2638 unsigned int dirty_tx, tx_left;
2639
1da177e4
LT		 2640 dirty_tx = tp->dirty_tx;
2641 smp_rmb();
2642 tx_left = tp->cur_tx - dirty_tx;
2643
2644 while (tx_left > 0) {
2645 unsigned int entry = dirty_tx % NUM_TX_DESC;
2646 struct ring_info *tx_skb = tp->tx_skb + entry;
2647 u32 len = tx_skb->len;
2648 u32 status;
2649
2650 rmb();
2651 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2652 if (status & DescOwn)
2653 break;
2654
cebf8cc7
FR		 2655 dev->stats.tx_bytes += len;
2656 dev->stats.tx_packets++;
1da177e4
LT		 2657
2658 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2659
2660 if (status & LastFrag) {
2661 dev_kfree_skb_irq(tx_skb->skb);
2662 tx_skb->skb = NULL;
2663 }
2664 dirty_tx++;
2665 tx_left--;
2666 }
2667
2668 if (tp->dirty_tx != dirty_tx) {
2669 tp->dirty_tx = dirty_tx;
2670 smp_wmb();
2671 if (netif_queue_stopped(dev) &&
2672 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2673 netif_wake_queue(dev);
2674 }
d78ae2dc
FR		 2675 /*
2676 * 8168 hack: TxPoll requests are lost when the Tx packets are
2677 * too close. Let's kick an extra TxPoll request when a burst
2678 * of start_xmit activity is detected (if it is not detected,
2679 * it is slow enough). -- FR
2680 */
2681 smp_rmb();
2682 if (tp->cur_tx != dirty_tx)
2683 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 2684 }
2685}
2686
126fa4b9
FR		 2687static inline int rtl8169_fragmented_frame(u32 status)
2688{
2689 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2690}
2691
1da177e4
LT		 2692static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2693{
2694 u32 opts1 = le32_to_cpu(desc->opts1);
2695 u32 status = opts1 & RxProtoMask;
2696
2697 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2698 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2699 ((status == RxProtoIP) && !(opts1 & IPFail)))
2700 skb->ip_summed = CHECKSUM_UNNECESSARY;
2701 else
2702 skb->ip_summed = CHECKSUM_NONE;
2703}
2704
07d3f51f
FR		 2705static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2706 struct rtl8169_private *tp, int pkt_size,
2707 dma_addr_t addr)
1da177e4 2708{
b449655f
SH		 2709 struct sk_buff *skb;
2710 bool done = false;
1da177e4 2711
b449655f
SH		 2712 if (pkt_size >= rx_copybreak)
2713 goto out;
1da177e4 2714
07d3f51f 2715 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
b449655f
SH		 2716 if (!skb)
2717 goto out;
2718
07d3f51f
FR		 2719 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2720 PCI_DMA_FROMDEVICE);
86402234 2721 skb_reserve(skb, NET_IP_ALIGN);
b449655f
SH		 2722 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2723 *sk_buff = skb;
2724 done = true;
2725out:
2726 return done;
1da177e4
LT		 2727}
2728
07d3f51f
FR		 2729static int rtl8169_rx_interrupt(struct net_device *dev,
2730 struct rtl8169_private *tp,
bea3348e 2731 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 2732{
2733 unsigned int cur_rx, rx_left;
2734 unsigned int delta, count;
2735
1da177e4
LT		 2736 cur_rx = tp->cur_rx;
2737 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
bea3348e 2738 rx_left = rtl8169_rx_quota(rx_left, budget);
1da177e4 2739
4dcb7d33 2740 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 2741 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 2742 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 2743 u32 status;
2744
2745 rmb();
126fa4b9 2746 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 2747
2748 if (status & DescOwn)
2749 break;
4dcb7d33 2750 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 2751 if (netif_msg_rx_err(tp)) {
2752 printk(KERN_INFO
2753 "%s: Rx ERROR. status = %08x\n",
2754 dev->name, status);
2755 }
cebf8cc7 2756 dev->stats.rx_errors++;
1da177e4 2757 if (status & (RxRWT | RxRUNT))
cebf8cc7 2758 dev->stats.rx_length_errors++;
1da177e4 2759 if (status & RxCRC)
cebf8cc7 2760 dev->stats.rx_crc_errors++;
9dccf611
FR		 2761 if (status & RxFOVF) {
2762 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 2763 dev->stats.rx_fifo_errors++;
9dccf611 2764 }
126fa4b9 2765 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 2766 } else {
1da177e4 2767 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 2768 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 2769 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 2770 struct pci_dev *pdev = tp->pci_dev;
1da177e4 2771
126fa4b9
FR		 2772 /*
2773 * The driver does not support incoming fragmented
2774 * frames. They are seen as a symptom of over-mtu
2775 * sized frames.
2776 */
2777 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 2778 dev->stats.rx_dropped++;
2779 dev->stats.rx_length_errors++;
126fa4b9 2780 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 2781 continue;
126fa4b9
FR		 2782 }
2783
1da177e4 2784 rtl8169_rx_csum(skb, desc);
bcf0bf90 2785
07d3f51f 2786 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
b449655f
SH		 2787 pci_dma_sync_single_for_device(pdev, addr,
2788 pkt_size, PCI_DMA_FROMDEVICE);
2789 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2790 } else {
2791 pci_unmap_single(pdev, addr, pkt_size,
2792 PCI_DMA_FROMDEVICE);
1da177e4
LT		 2793 tp->Rx_skbuff[entry] = NULL;
2794 }
2795
1da177e4
LT		 2796 skb_put(skb, pkt_size);
2797 skb->protocol = eth_type_trans(skb, dev);
2798
2799 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2800 rtl8169_rx_skb(skb);
2801
2802 dev->last_rx = jiffies;
cebf8cc7
FR		 2803 dev->stats.rx_bytes += pkt_size;
2804 dev->stats.rx_packets++;
1da177e4 2805 }
6dccd16b
FR		 2806
2807 /* Work around for AMD plateform. */
2808 if ((desc->opts2 & 0xfffe000) &&
2809 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2810 desc->opts2 = 0;
2811 cur_rx++;
2812 }
1da177e4
LT		 2813 }
2814
2815 count = cur_rx - tp->cur_rx;
2816 tp->cur_rx = cur_rx;
2817
2818 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 2819 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 2820 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2821 tp->dirty_rx += delta;
2822
2823 /*
2824 * FIXME: until there is periodic timer to try and refill the ring,
2825 * a temporary shortage may definitely kill the Rx process.
2826 * - disable the asic to try and avoid an overflow and kick it again
2827 * after refill ?
2828 * - how do others driver handle this condition (Uh oh...).
2829 */
b57b7e5a 2830 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 2831 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2832
2833 return count;
2834}
2835
07d3f51f 2836static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 2837{
07d3f51f 2838 struct net_device *dev = dev_instance;
1da177e4
LT		 2839 struct rtl8169_private *tp = netdev_priv(dev);
2840 int boguscnt = max_interrupt_work;
2841 void __iomem *ioaddr = tp->mmio_addr;
2842 int status;
2843 int handled = 0;
2844
2845 do {
2846 status = RTL_R16(IntrStatus);
2847
2848 /* hotplug/major error/no more work/shared irq */
2849 if ((status == 0xFFFF) || !status)
2850 break;
2851
2852 handled = 1;
2853
2854 if (unlikely(!netif_running(dev))) {
2855 rtl8169_asic_down(ioaddr);
2856 goto out;
2857 }
2858
2859 status &= tp->intr_mask;
2860 RTL_W16(IntrStatus,
2861 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2862
0e485150
FR		 2863 if (!(status & tp->intr_event))
2864 break;
2865
2866 /* Work around for rx fifo overflow */
2867 if (unlikely(status & RxFIFOOver) &&
2868 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2869 netif_stop_queue(dev);
2870 rtl8169_tx_timeout(dev);
1da177e4 2871 break;
0e485150 2872 }
1da177e4
LT		 2873
2874 if (unlikely(status & SYSErr)) {
2875 rtl8169_pcierr_interrupt(dev);
2876 break;
2877 }
2878
2879 if (status & LinkChg)
2880 rtl8169_check_link_status(dev, tp, ioaddr);
2881
2882#ifdef CONFIG_R8169_NAPI
313b0305
FR		 2883 if (status & tp->napi_event) {
2884 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2885 tp->intr_mask = ~tp->napi_event;
2886
bea3348e
SH		 2887 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
2888 __netif_rx_schedule(dev, &tp->napi);
313b0305
FR		 2889 else if (netif_msg_intr(tp)) {
2890 printk(KERN_INFO "%s: interrupt %04x in poll\n",
2891 dev->name, status);
2892 }
1da177e4
LT		 2893 }
2894 break;
2895#else
2896 /* Rx interrupt */
07d3f51f 2897 if (status & (RxOK | RxOverflow | RxFIFOOver))
bea3348e 2898 rtl8169_rx_interrupt(dev, tp, ioaddr, ~(u32)0);
07d3f51f 2899
1da177e4
LT		 2900 /* Tx interrupt */
2901 if (status & (TxOK | TxErr))
2902 rtl8169_tx_interrupt(dev, tp, ioaddr);
2903#endif
2904
2905 boguscnt--;
2906 } while (boguscnt > 0);
2907
2908 if (boguscnt <= 0) {
7c8b2eb4 2909 if (netif_msg_intr(tp) && net_ratelimit() ) {
b57b7e5a
SH		 2910 printk(KERN_WARNING
2911 "%s: Too much work at interrupt!\n", dev->name);
2912 }
1da177e4
LT		 2913 /* Clear all interrupt sources. */
2914 RTL_W16(IntrStatus, 0xffff);
2915 }
2916out:
2917 return IRQ_RETVAL(handled);
2918}
2919
2920#ifdef CONFIG_R8169_NAPI
bea3348e 2921static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 2922{
bea3348e
SH		 2923 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
2924 struct net_device *dev = tp->dev;
1da177e4 2925 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 2926 int work_done;
1da177e4 2927
bea3348e 2928 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 2929 rtl8169_tx_interrupt(dev, tp, ioaddr);
2930
bea3348e
SH		 2931 if (work_done < budget) {
2932 netif_rx_complete(dev, napi);
1da177e4
LT		 2933 tp->intr_mask = 0xffff;
2934 /*
2935 * 20040426: the barrier is not strictly required but the
2936 * behavior of the irq handler could be less predictable
2937 * without it. Btw, the lack of flush for the posted pci
2938 * write is safe - FR
2939 */
2940 smp_wmb();
0e485150 2941 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2942 }
2943
bea3348e 2944 return work_done;
1da177e4
LT		 2945}
2946#endif
2947
2948static void rtl8169_down(struct net_device *dev)
2949{
2950 struct rtl8169_private *tp = netdev_priv(dev);
2951 void __iomem *ioaddr = tp->mmio_addr;
2952 unsigned int poll_locked = 0;
733b736c 2953 unsigned int intrmask;
1da177e4
LT		 2954
2955 rtl8169_delete_timer(dev);
2956
2957 netif_stop_queue(dev);
2958
1da177e4
LT		 2959core_down:
2960 spin_lock_irq(&tp->lock);
2961
2962 rtl8169_asic_down(ioaddr);
2963
2964 /* Update the error counts. */
cebf8cc7 2965 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
1da177e4
LT		 2966 RTL_W32(RxMissed, 0);
2967
2968 spin_unlock_irq(&tp->lock);
2969
2970 synchronize_irq(dev->irq);
2971
2972 if (!poll_locked) {
bea3348e 2973 napi_disable(&tp->napi);
1da177e4
LT		 2974 poll_locked++;
2975 }
2976
2977 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 2978 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 2979
2980 /*
2981 * And now for the 50k$ question: are IRQ disabled or not ?
2982 *
2983 * Two paths lead here:
2984 * 1) dev->close
2985 * -> netif_running() is available to sync the current code and the
2986 * IRQ handler. See rtl8169_interrupt for details.
2987 * 2) dev->change_mtu
2988 * -> rtl8169_poll can not be issued again and re-enable the
2989 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 2990 *
2991 * No loop if hotpluged or major error (0xffff).
1da177e4 2992 */
733b736c
AP		 2993 intrmask = RTL_R16(IntrMask);
2994 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 2995 goto core_down;
2996
2997 rtl8169_tx_clear(tp);
2998
2999 rtl8169_rx_clear(tp);
3000}
3001
3002static int rtl8169_close(struct net_device *dev)
3003{
3004 struct rtl8169_private *tp = netdev_priv(dev);
3005 struct pci_dev *pdev = tp->pci_dev;
3006
3007 rtl8169_down(dev);
3008
3009 free_irq(dev->irq, dev);
3010
1da177e4
LT		 3011 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3012 tp->RxPhyAddr);
3013 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3014 tp->TxPhyAddr);
3015 tp->TxDescArray = NULL;
3016 tp->RxDescArray = NULL;
3017
3018 return 0;
3019}
3020
07ce4064 3021static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 3022{
3023 struct rtl8169_private *tp = netdev_priv(dev);
3024 void __iomem *ioaddr = tp->mmio_addr;
3025 unsigned long flags;
3026 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 3027 int rx_mode;
1da177e4
LT		 3028 u32 tmp = 0;
3029
3030 if (dev->flags & IFF_PROMISC) {
3031 /* Unconditionally log net taps. */
b57b7e5a
SH		 3032 if (netif_msg_link(tp)) {
3033 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3034 dev->name);
3035 }
1da177e4
LT		 3036 rx_mode =
3037 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3038 AcceptAllPhys;
3039 mc_filter[1] = mc_filter[0] = 0xffffffff;
3040 } else if ((dev->mc_count > multicast_filter_limit)
3041 || (dev->flags & IFF_ALLMULTI)) {
3042 /* Too many to filter perfectly -- accept all multicasts. */
3043 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3044 mc_filter[1] = mc_filter[0] = 0xffffffff;
3045 } else {
3046 struct dev_mc_list *mclist;
07d3f51f
FR		 3047 unsigned int i;
3048
1da177e4
LT		 3049 rx_mode = AcceptBroadcast | AcceptMyPhys;
3050 mc_filter[1] = mc_filter[0] = 0;
3051 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3052 i++, mclist = mclist->next) {
3053 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3054 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3055 rx_mode |= AcceptMulticast;
3056 }
3057 }
3058
3059 spin_lock_irqsave(&tp->lock, flags);
3060
3061 tmp = rtl8169_rx_config | rx_mode |
3062 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3063
bcf0bf90
FR		 3064 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
3065 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
3066 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3067 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
e3cf0cc0
FR		 3068 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
3069 (tp->mac_version == RTL_GIGA_MAC_VER_16) ||
3070 (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
bcf0bf90
FR		 3071 mc_filter[0] = 0xffffffff;
3072 mc_filter[1] = 0xffffffff;
3073 }
3074
1da177e4
LT		 3075 RTL_W32(MAR0 + 0, mc_filter[0]);
3076 RTL_W32(MAR0 + 4, mc_filter[1]);
3077
57a9f236
FR		 3078 RTL_W32(RxConfig, tmp);
3079
1da177e4
LT		 3080 spin_unlock_irqrestore(&tp->lock, flags);
3081}
3082
3083/**
3084 * rtl8169_get_stats - Get rtl8169 read/write statistics
3085 * @dev: The Ethernet Device to get statistics for
3086 *
3087 * Get TX/RX statistics for rtl8169
3088 */
3089static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3090{
3091 struct rtl8169_private *tp = netdev_priv(dev);
3092 void __iomem *ioaddr = tp->mmio_addr;
3093 unsigned long flags;
3094
3095 if (netif_running(dev)) {
3096 spin_lock_irqsave(&tp->lock, flags);
cebf8cc7 3097 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
1da177e4
LT		 3098 RTL_W32(RxMissed, 0);
3099 spin_unlock_irqrestore(&tp->lock, flags);
3100 }
5b0384f4 3101
cebf8cc7 3102 return &dev->stats;
1da177e4
LT		 3103}
3104
5d06a99f
FR		 3105#ifdef CONFIG_PM
3106
3107static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3108{
3109 struct net_device *dev = pci_get_drvdata(pdev);
3110 struct rtl8169_private *tp = netdev_priv(dev);
3111 void __iomem *ioaddr = tp->mmio_addr;
3112
3113 if (!netif_running(dev))
1371fa6d 3114 goto out_pci_suspend;
5d06a99f
FR		 3115
3116 netif_device_detach(dev);
3117 netif_stop_queue(dev);
3118
3119 spin_lock_irq(&tp->lock);
3120
3121 rtl8169_asic_down(ioaddr);
3122
cebf8cc7 3123 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
5d06a99f
FR		 3124 RTL_W32(RxMissed, 0);
3125
3126 spin_unlock_irq(&tp->lock);
3127
1371fa6d 3128out_pci_suspend:
5d06a99f 3129 pci_save_state(pdev);
f23e7fda
FR		 3130 pci_enable_wake(pdev, pci_choose_state(pdev, state),
3131 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
5d06a99f 3132 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1371fa6d 3133
5d06a99f
FR		 3134 return 0;
3135}
3136
3137static int rtl8169_resume(struct pci_dev *pdev)
3138{
3139 struct net_device *dev = pci_get_drvdata(pdev);
3140
1371fa6d
FR		 3141 pci_set_power_state(pdev, PCI_D0);
3142 pci_restore_state(pdev);
3143 pci_enable_wake(pdev, PCI_D0, 0);
3144
5d06a99f
FR		 3145 if (!netif_running(dev))
3146 goto out;
3147
3148 netif_device_attach(dev);
3149
5d06a99f
FR		 3150 rtl8169_schedule_work(dev, rtl8169_reset_task);
3151out:
3152 return 0;
3153}
3154
3155#endif /* CONFIG_PM */
3156
1da177e4
LT		 3157static struct pci_driver rtl8169_pci_driver = {
3158 .name = MODULENAME,
3159 .id_table = rtl8169_pci_tbl,
3160 .probe = rtl8169_init_one,
3161 .remove = __devexit_p(rtl8169_remove_one),
3162#ifdef CONFIG_PM
3163 .suspend = rtl8169_suspend,
3164 .resume = rtl8169_resume,
3165#endif
3166};
3167
07d3f51f 3168static int __init rtl8169_init_module(void)
1da177e4 3169{
29917620 3170 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 3171}
3172
07d3f51f 3173static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 3174{
3175 pci_unregister_driver(&rtl8169_pci_driver);
3176}
3177
3178module_init(rtl8169_init_module);
3179module_exit(rtl8169_cleanup_module);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git