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r8169: don't enable rx when shutdown.
[thirdparty/kernel/stable.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
a6b7a407 25#include <linux/interrupt.h>
1da177e4 26#include <linux/dma-mapping.h>
e1759441 27#include <linux/pm_runtime.h>
bca03d5f 28#include <linux/firmware.h>
ba04c7c9 29#include <linux/pci-aspm.h>
70c71606 30#include <linux/prefetch.h>
1da177e4 31
99f252b0 32#include <asm/system.h>
1da177e4
LT		 33#include <asm/io.h>
34#include <asm/irq.h>
35
865c652d 36#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 37#define MODULENAME "r8169"
38#define PFX MODULENAME ": "
39
bca03d5f 40#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 42#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 44#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
5a5e4443 45#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
bca03d5f 46
1da177e4
LT		 47#ifdef RTL8169_DEBUG
48#define assert(expr) \
5b0384f4
FR		 49 if (!(expr)) { \
50 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 51 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 52 }
06fa7358
JP		 53#define dprintk(fmt, args...) \
54 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 55#else
56#define assert(expr) do {} while (0)
57#define dprintk(fmt, args...) do {} while (0)
58#endif /* RTL8169_DEBUG */
59
b57b7e5a 60#define R8169_MSG_DEFAULT \
f0e837d9 61 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 62
1da177e4
LT		 63#define TX_BUFFS_AVAIL(tp) \
64 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
65
1da177e4
LT		 66/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
67 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 68static const int multicast_filter_limit = 32;
1da177e4
LT		 69
70/* MAC address length */
71#define MAC_ADDR_LEN 6
72
9c14ceaf 73#define MAX_READ_REQUEST_SHIFT 12
1da177e4 74#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
1da177e4
LT		 75#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
76#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
77
78#define R8169_REGS_SIZE 256
79#define R8169_NAPI_WEIGHT 64
80#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
81#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
82#define RX_BUF_SIZE 1536 /* Rx Buffer size */
83#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
84#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
85
86#define RTL8169_TX_TIMEOUT (6*HZ)
87#define RTL8169_PHY_TIMEOUT (10*HZ)
88
ea8dbdd1 89#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
90#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 91#define RTL_EEPROM_SIG_ADDR 0x0000
92
1da177e4
LT		 93/* write/read MMIO register */
94#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
95#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
96#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
97#define RTL_R8(reg) readb (ioaddr + (reg))
98#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 99#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 100
101enum mac_version {
85bffe6c
FR		 102 RTL_GIGA_MAC_VER_01 = 0,
103 RTL_GIGA_MAC_VER_02,
104 RTL_GIGA_MAC_VER_03,
105 RTL_GIGA_MAC_VER_04,
106 RTL_GIGA_MAC_VER_05,
107 RTL_GIGA_MAC_VER_06,
108 RTL_GIGA_MAC_VER_07,
109 RTL_GIGA_MAC_VER_08,
110 RTL_GIGA_MAC_VER_09,
111 RTL_GIGA_MAC_VER_10,
112 RTL_GIGA_MAC_VER_11,
113 RTL_GIGA_MAC_VER_12,
114 RTL_GIGA_MAC_VER_13,
115 RTL_GIGA_MAC_VER_14,
116 RTL_GIGA_MAC_VER_15,
117 RTL_GIGA_MAC_VER_16,
118 RTL_GIGA_MAC_VER_17,
119 RTL_GIGA_MAC_VER_18,
120 RTL_GIGA_MAC_VER_19,
121 RTL_GIGA_MAC_VER_20,
122 RTL_GIGA_MAC_VER_21,
123 RTL_GIGA_MAC_VER_22,
124 RTL_GIGA_MAC_VER_23,
125 RTL_GIGA_MAC_VER_24,
126 RTL_GIGA_MAC_VER_25,
127 RTL_GIGA_MAC_VER_26,
128 RTL_GIGA_MAC_VER_27,
129 RTL_GIGA_MAC_VER_28,
130 RTL_GIGA_MAC_VER_29,
131 RTL_GIGA_MAC_VER_30,
132 RTL_GIGA_MAC_VER_31,
133 RTL_GIGA_MAC_VER_32,
134 RTL_GIGA_MAC_VER_33,
70090424 135 RTL_GIGA_MAC_VER_34,
85bffe6c 136 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 137};
138
2b7b4318
FR		 139enum rtl_tx_desc_version {
140 RTL_TD_0 = 0,
141 RTL_TD_1 = 1,
142};
143
85bffe6c
FR		 144#define _R(NAME,TD,FW) \
145 { .name = NAME, .txd_version = TD, .fw_name = FW }
1da177e4 146
3c6bee1d 147static const struct {
1da177e4 148 const char *name;
2b7b4318 149 enum rtl_tx_desc_version txd_version;
953a12cc 150 const char *fw_name;
85bffe6c
FR		 151} rtl_chip_infos[] = {
152 /* PCI devices. */
153 [RTL_GIGA_MAC_VER_01] =
154 _R("RTL8169", RTL_TD_0, NULL),
155 [RTL_GIGA_MAC_VER_02] =
156 _R("RTL8169s", RTL_TD_0, NULL),
157 [RTL_GIGA_MAC_VER_03] =
158 _R("RTL8110s", RTL_TD_0, NULL),
159 [RTL_GIGA_MAC_VER_04] =
160 _R("RTL8169sb/8110sb", RTL_TD_0, NULL),
161 [RTL_GIGA_MAC_VER_05] =
162 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
163 [RTL_GIGA_MAC_VER_06] =
164 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
165 /* PCI-E devices. */
166 [RTL_GIGA_MAC_VER_07] =
167 _R("RTL8102e", RTL_TD_1, NULL),
168 [RTL_GIGA_MAC_VER_08] =
169 _R("RTL8102e", RTL_TD_1, NULL),
170 [RTL_GIGA_MAC_VER_09] =
171 _R("RTL8102e", RTL_TD_1, NULL),
172 [RTL_GIGA_MAC_VER_10] =
173 _R("RTL8101e", RTL_TD_0, NULL),
174 [RTL_GIGA_MAC_VER_11] =
175 _R("RTL8168b/8111b", RTL_TD_0, NULL),
176 [RTL_GIGA_MAC_VER_12] =
177 _R("RTL8168b/8111b", RTL_TD_0, NULL),
178 [RTL_GIGA_MAC_VER_13] =
179 _R("RTL8101e", RTL_TD_0, NULL),
180 [RTL_GIGA_MAC_VER_14] =
181 _R("RTL8100e", RTL_TD_0, NULL),
182 [RTL_GIGA_MAC_VER_15] =
183 _R("RTL8100e", RTL_TD_0, NULL),
184 [RTL_GIGA_MAC_VER_16] =
185 _R("RTL8101e", RTL_TD_0, NULL),
186 [RTL_GIGA_MAC_VER_17] =
187 _R("RTL8168b/8111b", RTL_TD_0, NULL),
188 [RTL_GIGA_MAC_VER_18] =
189 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
190 [RTL_GIGA_MAC_VER_19] =
191 _R("RTL8168c/8111c", RTL_TD_1, NULL),
192 [RTL_GIGA_MAC_VER_20] =
193 _R("RTL8168c/8111c", RTL_TD_1, NULL),
194 [RTL_GIGA_MAC_VER_21] =
195 _R("RTL8168c/8111c", RTL_TD_1, NULL),
196 [RTL_GIGA_MAC_VER_22] =
197 _R("RTL8168c/8111c", RTL_TD_1, NULL),
198 [RTL_GIGA_MAC_VER_23] =
199 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
200 [RTL_GIGA_MAC_VER_24] =
201 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
202 [RTL_GIGA_MAC_VER_25] =
203 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1),
204 [RTL_GIGA_MAC_VER_26] =
205 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2),
206 [RTL_GIGA_MAC_VER_27] =
207 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
208 [RTL_GIGA_MAC_VER_28] =
209 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
210 [RTL_GIGA_MAC_VER_29] =
211 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
212 [RTL_GIGA_MAC_VER_30] =
213 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
214 [RTL_GIGA_MAC_VER_31] =
215 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
216 [RTL_GIGA_MAC_VER_32] =
217 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1),
218 [RTL_GIGA_MAC_VER_33] =
70090424
HW		 219 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2),
220 [RTL_GIGA_MAC_VER_34] =
221 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3)
953a12cc 222};
85bffe6c 223#undef _R
953a12cc 224
bcf0bf90
FR		 225enum cfg_version {
226 RTL_CFG_0 = 0x00,
227 RTL_CFG_1,
228 RTL_CFG_2
229};
230
07ce4064
FR		 231static void rtl_hw_start_8169(struct net_device *);
232static void rtl_hw_start_8168(struct net_device *);
233static void rtl_hw_start_8101(struct net_device *);
234
a3aa1884 235static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 236 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 237 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 238 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 239 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 240 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
241 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 242 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 243 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
244 { PCI_VENDOR_ID_LINKSYS, 0x1032,
245 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 246 { 0x0001, 0x8168,
247 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 248 {0,},
249};
250
251MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
252
6f0333b8 253static int rx_buf_sz = 16383;
4300e8c7 254static int use_dac;
b57b7e5a
SH		 255static struct {
256 u32 msg_enable;
257} debug = { -1 };
1da177e4 258
07d3f51f
FR		 259enum rtl_registers {
260 MAC0 = 0, /* Ethernet hardware address. */
773d2021 261 MAC4 = 4,
07d3f51f
FR		 262 MAR0 = 8, /* Multicast filter. */
263 CounterAddrLow = 0x10,
264 CounterAddrHigh = 0x14,
265 TxDescStartAddrLow = 0x20,
266 TxDescStartAddrHigh = 0x24,
267 TxHDescStartAddrLow = 0x28,
268 TxHDescStartAddrHigh = 0x2c,
269 FLASH = 0x30,
270 ERSR = 0x36,
271 ChipCmd = 0x37,
272 TxPoll = 0x38,
273 IntrMask = 0x3c,
274 IntrStatus = 0x3e,
4f6b00e5 275
07d3f51f 276 TxConfig = 0x40,
4f6b00e5
HW		 277#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
278#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 279
4f6b00e5
HW		 280 RxConfig = 0x44,
281#define RX128_INT_EN (1 << 15) /* 8111c and later */
282#define RX_MULTI_EN (1 << 14) /* 8111c only */
283#define RXCFG_FIFO_SHIFT 13
284 /* No threshold before first PCI xfer */
285#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
286#define RXCFG_DMA_SHIFT 8
287 /* Unlimited maximum PCI burst. */
288#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318
FR		 289#define RTL_RX_CONFIG_MASK 0xff7e1880u
290
07d3f51f
FR		 291 RxMissed = 0x4c,
292 Cfg9346 = 0x50,
293 Config0 = 0x51,
294 Config1 = 0x52,
295 Config2 = 0x53,
296 Config3 = 0x54,
297 Config4 = 0x55,
298 Config5 = 0x56,
299 MultiIntr = 0x5c,
300 PHYAR = 0x60,
07d3f51f
FR		 301 PHYstatus = 0x6c,
302 RxMaxSize = 0xda,
303 CPlusCmd = 0xe0,
304 IntrMitigate = 0xe2,
305 RxDescAddrLow = 0xe4,
306 RxDescAddrHigh = 0xe8,
f0298f81 307 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
308
309#define NoEarlyTx 0x3f /* Max value : no early transmit. */
310
311 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
312
313#define TxPacketMax (8064 >> 7)
314
07d3f51f
FR		 315 FuncEvent = 0xf0,
316 FuncEventMask = 0xf4,
317 FuncPresetState = 0xf8,
318 FuncForceEvent = 0xfc,
1da177e4
LT		 319};
320
f162a5d1
FR		 321enum rtl8110_registers {
322 TBICSR = 0x64,
323 TBI_ANAR = 0x68,
324 TBI_LPAR = 0x6a,
325};
326
327enum rtl8168_8101_registers {
328 CSIDR = 0x64,
329 CSIAR = 0x68,
330#define CSIAR_FLAG 0x80000000
331#define CSIAR_WRITE_CMD 0x80000000
332#define CSIAR_BYTE_ENABLE 0x0f
333#define CSIAR_BYTE_ENABLE_SHIFT 12
334#define CSIAR_ADDR_MASK 0x0fff
065c27c1 335 PMCH = 0x6f,
f162a5d1
FR		 336 EPHYAR = 0x80,
337#define EPHYAR_FLAG 0x80000000
338#define EPHYAR_WRITE_CMD 0x80000000
339#define EPHYAR_REG_MASK 0x1f
340#define EPHYAR_REG_SHIFT 16
341#define EPHYAR_DATA_MASK 0xffff
5a5e4443 342 DLLPR = 0xd0,
4f6b00e5 343#define PFM_EN (1 << 6)
f162a5d1
FR		 344 DBG_REG = 0xd1,
345#define FIX_NAK_1 (1 << 4)
346#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 347 TWSI = 0xd2,
348 MCU = 0xd3,
4f6b00e5 349#define NOW_IS_OOB (1 << 7)
5a5e4443
HW		 350#define EN_NDP (1 << 3)
351#define EN_OOB_RESET (1 << 2)
daf9df6d 352 EFUSEAR = 0xdc,
353#define EFUSEAR_FLAG 0x80000000
354#define EFUSEAR_WRITE_CMD 0x80000000
355#define EFUSEAR_READ_CMD 0x00000000
356#define EFUSEAR_REG_MASK 0x03ff
357#define EFUSEAR_REG_SHIFT 8
358#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 359};
360
c0e45c1c 361enum rtl8168_registers {
4f6b00e5
HW		 362 LED_FREQ = 0x1a,
363 EEE_LED = 0x1b,
b646d900 364 ERIDR = 0x70,
365 ERIAR = 0x74,
366#define ERIAR_FLAG 0x80000000
367#define ERIAR_WRITE_CMD 0x80000000
368#define ERIAR_READ_CMD 0x00000000
369#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 370#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 371#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
372#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
373#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
374#define ERIAR_MASK_SHIFT 12
375#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
376#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
377#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 378 EPHY_RXER_NUM = 0x7c,
379 OCPDR = 0xb0, /* OCP GPHY access */
380#define OCPDR_WRITE_CMD 0x80000000
381#define OCPDR_READ_CMD 0x00000000
382#define OCPDR_REG_MASK 0x7f
383#define OCPDR_GPHY_REG_SHIFT 16
384#define OCPDR_DATA_MASK 0xffff
385 OCPAR = 0xb4,
386#define OCPAR_FLAG 0x80000000
387#define OCPAR_GPHY_WRITE_CMD 0x8000f060
388#define OCPAR_GPHY_READ_CMD 0x0000f060
01dc7fec 389 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
390 MISC = 0xf0, /* 8168e only. */
cecb5fd7 391#define TXPLA_RST (1 << 29)
4f6b00e5 392#define PWM_EN (1 << 22)
c0e45c1c 393};
394
07d3f51f 395enum rtl_register_content {
1da177e4 396 /* InterruptStatusBits */
07d3f51f
FR		 397 SYSErr = 0x8000,
398 PCSTimeout = 0x4000,
399 SWInt = 0x0100,
400 TxDescUnavail = 0x0080,
401 RxFIFOOver = 0x0040,
402 LinkChg = 0x0020,
403 RxOverflow = 0x0010,
404 TxErr = 0x0008,
405 TxOK = 0x0004,
406 RxErr = 0x0002,
407 RxOK = 0x0001,
1da177e4
LT		 408
409 /* RxStatusDesc */
9dccf611
FR		 410 RxFOVF = (1 << 23),
411 RxRWT = (1 << 22),
412 RxRES = (1 << 21),
413 RxRUNT = (1 << 20),
414 RxCRC = (1 << 19),
1da177e4
LT		 415
416 /* ChipCmdBits */
4f6b00e5 417 StopReq = 0x80,
07d3f51f
FR		 418 CmdReset = 0x10,
419 CmdRxEnb = 0x08,
420 CmdTxEnb = 0x04,
421 RxBufEmpty = 0x01,
1da177e4 422
275391a4
FR		 423 /* TXPoll register p.5 */
424 HPQ = 0x80, /* Poll cmd on the high prio queue */
425 NPQ = 0x40, /* Poll cmd on the low prio queue */
426 FSWInt = 0x01, /* Forced software interrupt */
427
1da177e4 428 /* Cfg9346Bits */
07d3f51f
FR		 429 Cfg9346_Lock = 0x00,
430 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 431
432 /* rx_mode_bits */
07d3f51f
FR		 433 AcceptErr = 0x20,
434 AcceptRunt = 0x10,
435 AcceptBroadcast = 0x08,
436 AcceptMulticast = 0x04,
437 AcceptMyPhys = 0x02,
438 AcceptAllPhys = 0x01,
1da177e4 439
1da177e4
LT		 440 /* TxConfigBits */
441 TxInterFrameGapShift = 24,
442 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
443
5d06a99f 444 /* Config1 register p.24 */
f162a5d1
FR		 445 LEDS1 = (1 << 7),
446 LEDS0 = (1 << 6),
fbac58fc 447 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 448 Speed_down = (1 << 4),
449 MEMMAP = (1 << 3),
450 IOMAP = (1 << 2),
451 VPD = (1 << 1),
5d06a99f
FR		 452 PMEnable = (1 << 0), /* Power Management Enable */
453
6dccd16b
FR		 454 /* Config2 register p. 25 */
455 PCI_Clock_66MHz = 0x01,
456 PCI_Clock_33MHz = 0x00,
457
61a4dcc2
FR		 458 /* Config3 register p.25 */
459 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
460 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 461 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 462
5d06a99f 463 /* Config5 register p.27 */
61a4dcc2
FR		 464 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
465 MWF = (1 << 5), /* Accept Multicast wakeup frame */
466 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 467 Spi_en = (1 << 3),
61a4dcc2 468 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 469 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
470
1da177e4
LT		 471 /* TBICSR p.28 */
472 TBIReset = 0x80000000,
473 TBILoopback = 0x40000000,
474 TBINwEnable = 0x20000000,
475 TBINwRestart = 0x10000000,
476 TBILinkOk = 0x02000000,
477 TBINwComplete = 0x01000000,
478
479 /* CPlusCmd p.31 */
f162a5d1
FR		 480 EnableBist = (1 << 15), // 8168 8101
481 Mac_dbgo_oe = (1 << 14), // 8168 8101
482 Normal_mode = (1 << 13), // unused
483 Force_half_dup = (1 << 12), // 8168 8101
484 Force_rxflow_en = (1 << 11), // 8168 8101
485 Force_txflow_en = (1 << 10), // 8168 8101
486 Cxpl_dbg_sel = (1 << 9), // 8168 8101
487 ASF = (1 << 8), // 8168 8101
488 PktCntrDisable = (1 << 7), // 8168 8101
489 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 490 RxVlan = (1 << 6),
491 RxChkSum = (1 << 5),
492 PCIDAC = (1 << 4),
493 PCIMulRW = (1 << 3),
0e485150
FR		 494 INTT_0 = 0x0000, // 8168
495 INTT_1 = 0x0001, // 8168
496 INTT_2 = 0x0002, // 8168
497 INTT_3 = 0x0003, // 8168
1da177e4
LT		 498
499 /* rtl8169_PHYstatus */
07d3f51f
FR		 500 TBI_Enable = 0x80,
501 TxFlowCtrl = 0x40,
502 RxFlowCtrl = 0x20,
503 _1000bpsF = 0x10,
504 _100bps = 0x08,
505 _10bps = 0x04,
506 LinkStatus = 0x02,
507 FullDup = 0x01,
1da177e4 508
1da177e4 509 /* _TBICSRBit */
07d3f51f 510 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 511
512 /* DumpCounterCommand */
07d3f51f 513 CounterDump = 0x8,
1da177e4
LT		 514};
515
2b7b4318
FR		 516enum rtl_desc_bit {
517 /* First doubleword. */
1da177e4
LT		 518 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
519 RingEnd = (1 << 30), /* End of descriptor ring */
520 FirstFrag = (1 << 29), /* First segment of a packet */
521 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 522};
523
524/* Generic case. */
525enum rtl_tx_desc_bit {
526 /* First doubleword. */
527 TD_LSO = (1 << 27), /* Large Send Offload */
528#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 529
2b7b4318
FR		 530 /* Second doubleword. */
531 TxVlanTag = (1 << 17), /* Add VLAN tag */
532};
533
534/* 8169, 8168b and 810x except 8102e. */
535enum rtl_tx_desc_bit_0 {
536 /* First doubleword. */
537#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
538 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
539 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
540 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
541};
542
543/* 8102e, 8168c and beyond. */
544enum rtl_tx_desc_bit_1 {
545 /* Second doubleword. */
546#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
547 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
548 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
549 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
550};
1da177e4 551
2b7b4318
FR		 552static const struct rtl_tx_desc_info {
553 struct {
554 u32 udp;
555 u32 tcp;
556 } checksum;
557 u16 mss_shift;
558 u16 opts_offset;
559} tx_desc_info [] = {
560 [RTL_TD_0] = {
561 .checksum = {
562 .udp = TD0_IP_CS | TD0_UDP_CS,
563 .tcp = TD0_IP_CS | TD0_TCP_CS
564 },
565 .mss_shift = TD0_MSS_SHIFT,
566 .opts_offset = 0
567 },
568 [RTL_TD_1] = {
569 .checksum = {
570 .udp = TD1_IP_CS | TD1_UDP_CS,
571 .tcp = TD1_IP_CS | TD1_TCP_CS
572 },
573 .mss_shift = TD1_MSS_SHIFT,
574 .opts_offset = 1
575 }
576};
577
578enum rtl_rx_desc_bit {
1da177e4
LT		 579 /* Rx private */
580 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
581 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
582
583#define RxProtoUDP (PID1)
584#define RxProtoTCP (PID0)
585#define RxProtoIP (PID1 | PID0)
586#define RxProtoMask RxProtoIP
587
588 IPFail = (1 << 16), /* IP checksum failed */
589 UDPFail = (1 << 15), /* UDP/IP checksum failed */
590 TCPFail = (1 << 14), /* TCP/IP checksum failed */
591 RxVlanTag = (1 << 16), /* VLAN tag available */
592};
593
594#define RsvdMask 0x3fffc000
595
596struct TxDesc {
6cccd6e7
REB		 597 __le32 opts1;
598 __le32 opts2;
599 __le64 addr;
1da177e4
LT		 600};
601
602struct RxDesc {
6cccd6e7
REB		 603 __le32 opts1;
604 __le32 opts2;
605 __le64 addr;
1da177e4
LT		 606};
607
608struct ring_info {
609 struct sk_buff *skb;
610 u32 len;
611 u8 __pad[sizeof(void *) - sizeof(u32)];
612};
613
f23e7fda 614enum features {
ccdffb9a
FR		 615 RTL_FEATURE_WOL = (1 << 0),
616 RTL_FEATURE_MSI = (1 << 1),
617 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 618};
619
355423d0
IV		 620struct rtl8169_counters {
621 __le64 tx_packets;
622 __le64 rx_packets;
623 __le64 tx_errors;
624 __le32 rx_errors;
625 __le16 rx_missed;
626 __le16 align_errors;
627 __le32 tx_one_collision;
628 __le32 tx_multi_collision;
629 __le64 rx_unicast;
630 __le64 rx_broadcast;
631 __le32 rx_multicast;
632 __le16 tx_aborted;
633 __le16 tx_underun;
634};
635
1da177e4
LT		 636struct rtl8169_private {
637 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 638 struct pci_dev *pci_dev;
c4028958 639 struct net_device *dev;
bea3348e 640 struct napi_struct napi;
cecb5fd7 641 spinlock_t lock;
b57b7e5a 642 u32 msg_enable;
2b7b4318
FR		 643 u16 txd_version;
644 u16 mac_version;
1da177e4
LT		 645 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
646 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
647 u32 dirty_rx;
648 u32 dirty_tx;
649 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
650 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
651 dma_addr_t TxPhyAddr;
652 dma_addr_t RxPhyAddr;
6f0333b8 653 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 654 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 655 struct timer_list timer;
656 u16 cp_cmd;
0e485150
FR		 657 u16 intr_event;
658 u16 napi_event;
1da177e4 659 u16 intr_mask;
c0e45c1c 660
661 struct mdio_ops {
662 void (*write)(void __iomem *, int, int);
663 int (*read)(void __iomem *, int);
664 } mdio_ops;
665
065c27c1 666 struct pll_power_ops {
667 void (*down)(struct rtl8169_private *);
668 void (*up)(struct rtl8169_private *);
669 } pll_power_ops;
670
54405cde 671 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 672 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 673 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 674 void (*hw_start)(struct net_device *);
4da19633 675 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 676 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 677 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
c4028958 678 struct delayed_work task;
f23e7fda 679 unsigned features;
ccdffb9a
FR		 680
681 struct mii_if_info mii;
355423d0 682 struct rtl8169_counters counters;
e1759441 683 u32 saved_wolopts;
f1e02ed1 684
b6ffd97f
FR		 685 struct rtl_fw {
686 const struct firmware *fw;
1c361efb
FR		 687
688#define RTL_VER_SIZE 32
689
690 char version[RTL_VER_SIZE];
691
692 struct rtl_fw_phy_action {
693 __le32 *code;
694 size_t size;
695 } phy_action;
b6ffd97f 696 } *rtl_fw;
953a12cc 697#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN);
1da177e4
LT		 698};
699
979b6c13 700MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 701MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 702module_param(use_dac, int, 0);
4300e8c7 703MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 704module_param_named(debug, debug.msg_enable, int, 0);
705MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 706MODULE_LICENSE("GPL");
707MODULE_VERSION(RTL8169_VERSION);
bca03d5f 708MODULE_FIRMWARE(FIRMWARE_8168D_1);
709MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 710MODULE_FIRMWARE(FIRMWARE_8168E_1);
711MODULE_FIRMWARE(FIRMWARE_8168E_2);
5a5e4443 712MODULE_FIRMWARE(FIRMWARE_8105E_1);
1da177e4
LT		 713
714static int rtl8169_open(struct net_device *dev);
61357325
SH		 715static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
716 struct net_device *dev);
7d12e780 717static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 718static int rtl8169_init_ring(struct net_device *dev);
07ce4064 719static void rtl_hw_start(struct net_device *dev);
1da177e4 720static int rtl8169_close(struct net_device *dev);
07ce4064 721static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 722static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 723static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 724static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 725 void __iomem *, u32 budget);
4dcb7d33 726static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 727static void rtl8169_down(struct net_device *dev);
99f252b0 728static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 729static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 730
4f6b00e5 731static const unsigned int rtl8169_rx_config = RX_FIFO_THRESH | RX_DMA_BURST;
1da177e4 732
b646d900 733static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
734{
735 void __iomem *ioaddr = tp->mmio_addr;
736 int i;
737
738 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
739 for (i = 0; i < 20; i++) {
740 udelay(100);
741 if (RTL_R32(OCPAR) & OCPAR_FLAG)
742 break;
743 }
744 return RTL_R32(OCPDR);
745}
746
747static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
748{
749 void __iomem *ioaddr = tp->mmio_addr;
750 int i;
751
752 RTL_W32(OCPDR, data);
753 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
754 for (i = 0; i < 20; i++) {
755 udelay(100);
756 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
757 break;
758 }
759}
760
fac5b3ca 761static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 762{
fac5b3ca 763 void __iomem *ioaddr = tp->mmio_addr;
b646d900 764 int i;
765
766 RTL_W8(ERIDR, cmd);
767 RTL_W32(ERIAR, 0x800010e8);
768 msleep(2);
769 for (i = 0; i < 5; i++) {
770 udelay(100);
1e4e82ba 771 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
b646d900 772 break;
773 }
774
fac5b3ca 775 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 776}
777
778#define OOB_CMD_RESET 0x00
779#define OOB_CMD_DRIVER_START 0x05
780#define OOB_CMD_DRIVER_STOP 0x06
781
cecb5fd7
FR		 782static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
783{
784 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
785}
786
b646d900 787static void rtl8168_driver_start(struct rtl8169_private *tp)
788{
cecb5fd7 789 u16 reg;
b646d900 790 int i;
791
792 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
793
cecb5fd7 794 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 795
b646d900 796 for (i = 0; i < 10; i++) {
797 msleep(10);
4804b3b3 798 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
b646d900 799 break;
800 }
801}
802
803static void rtl8168_driver_stop(struct rtl8169_private *tp)
804{
cecb5fd7 805 u16 reg;
b646d900 806 int i;
807
808 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
809
cecb5fd7 810 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 811
b646d900 812 for (i = 0; i < 10; i++) {
813 msleep(10);
4804b3b3 814 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
b646d900 815 break;
816 }
817}
818
4804b3b3 819static int r8168dp_check_dash(struct rtl8169_private *tp)
820{
cecb5fd7 821 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 822
cecb5fd7 823 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 824}
b646d900 825
4da19633 826static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 827{
828 int i;
829
a6baf3af 830 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 831
2371408c 832 for (i = 20; i > 0; i--) {
07d3f51f
FR		 833 /*
834 * Check if the RTL8169 has completed writing to the specified
835 * MII register.
836 */
5b0384f4 837 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 838 break;
2371408c 839 udelay(25);
1da177e4 840 }
024a07ba 841 /*
81a95f04
TT		 842 * According to hardware specs a 20us delay is required after write
843 * complete indication, but before sending next command.
024a07ba 844 */
81a95f04 845 udelay(20);
1da177e4
LT		 846}
847
4da19633 848static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 849{
850 int i, value = -1;
851
a6baf3af 852 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 853
2371408c 854 for (i = 20; i > 0; i--) {
07d3f51f
FR		 855 /*
856 * Check if the RTL8169 has completed retrieving data from
857 * the specified MII register.
858 */
1da177e4 859 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 860 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 861 break;
862 }
2371408c 863 udelay(25);
1da177e4 864 }
81a95f04
TT		 865 /*
866 * According to hardware specs a 20us delay is required after read
867 * complete indication, but before sending next command.
868 */
869 udelay(20);
870
1da177e4
LT		 871 return value;
872}
873
c0e45c1c 874static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
875{
876 int i;
877
878 RTL_W32(OCPDR, data |
879 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
880 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
881 RTL_W32(EPHY_RXER_NUM, 0);
882
883 for (i = 0; i < 100; i++) {
884 mdelay(1);
885 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
886 break;
887 }
888}
889
890static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
891{
892 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
893 (value & OCPDR_DATA_MASK));
894}
895
896static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
897{
898 int i;
899
900 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
901
902 mdelay(1);
903 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
904 RTL_W32(EPHY_RXER_NUM, 0);
905
906 for (i = 0; i < 100; i++) {
907 mdelay(1);
908 if (RTL_R32(OCPAR) & OCPAR_FLAG)
909 break;
910 }
911
912 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
913}
914
e6de30d6 915#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
916
917static void r8168dp_2_mdio_start(void __iomem *ioaddr)
918{
919 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
920}
921
922static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
923{
924 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
925}
926
927static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
928{
929 r8168dp_2_mdio_start(ioaddr);
930
931 r8169_mdio_write(ioaddr, reg_addr, value);
932
933 r8168dp_2_mdio_stop(ioaddr);
934}
935
936static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
937{
938 int value;
939
940 r8168dp_2_mdio_start(ioaddr);
941
942 value = r8169_mdio_read(ioaddr, reg_addr);
943
944 r8168dp_2_mdio_stop(ioaddr);
945
946 return value;
947}
948
4da19633 949static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 950{
c0e45c1c 951 tp->mdio_ops.write(tp->mmio_addr, location, val);
dacf8154
FR		 952}
953
4da19633 954static int rtl_readphy(struct rtl8169_private *tp, int location)
955{
c0e45c1c 956 return tp->mdio_ops.read(tp->mmio_addr, location);
4da19633 957}
958
959static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
960{
961 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
962}
963
964static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 965{
966 int val;
967
4da19633 968 val = rtl_readphy(tp, reg_addr);
969 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 970}
971
ccdffb9a
FR		 972static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
973 int val)
974{
975 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 976
4da19633 977 rtl_writephy(tp, location, val);
ccdffb9a
FR		 978}
979
980static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
981{
982 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 983
4da19633 984 return rtl_readphy(tp, location);
ccdffb9a
FR		 985}
986
dacf8154
FR		 987static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
988{
989 unsigned int i;
990
991 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
992 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
993
994 for (i = 0; i < 100; i++) {
995 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
996 break;
997 udelay(10);
998 }
999}
1000
1001static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1002{
1003 u16 value = 0xffff;
1004 unsigned int i;
1005
1006 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1007
1008 for (i = 0; i < 100; i++) {
1009 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1010 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1011 break;
1012 }
1013 udelay(10);
1014 }
1015
1016 return value;
1017}
1018
1019static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1020{
1021 unsigned int i;
1022
1023 RTL_W32(CSIDR, value);
1024 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1025 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1026
1027 for (i = 0; i < 100; i++) {
1028 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1029 break;
1030 udelay(10);
1031 }
1032}
1033
1034static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1035{
1036 u32 value = ~0x00;
1037 unsigned int i;
1038
1039 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1040 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1041
1042 for (i = 0; i < 100; i++) {
1043 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1044 value = RTL_R32(CSIDR);
1045 break;
1046 }
1047 udelay(10);
1048 }
1049
1050 return value;
1051}
1052
133ac40a
HW		 1053static
1054void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1055{
1056 unsigned int i;
1057
1058 BUG_ON((addr & 3) || (mask == 0));
1059 RTL_W32(ERIDR, val);
1060 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1061
1062 for (i = 0; i < 100; i++) {
1063 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1064 break;
1065 udelay(100);
1066 }
1067}
1068
1069static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1070{
1071 u32 value = ~0x00;
1072 unsigned int i;
1073
1074 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1075
1076 for (i = 0; i < 100; i++) {
1077 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1078 value = RTL_R32(ERIDR);
1079 break;
1080 }
1081 udelay(100);
1082 }
1083
1084 return value;
1085}
1086
1087static void
1088rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1089{
1090 u32 val;
1091
1092 val = rtl_eri_read(ioaddr, addr, type);
1093 rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1094}
1095
daf9df6d 1096static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1097{
1098 u8 value = 0xff;
1099 unsigned int i;
1100
1101 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1102
1103 for (i = 0; i < 300; i++) {
1104 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1105 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1106 break;
1107 }
1108 udelay(100);
1109 }
1110
1111 return value;
1112}
1113
1da177e4
LT		 1114static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1115{
1116 RTL_W16(IntrMask, 0x0000);
1117
1118 RTL_W16(IntrStatus, 0xffff);
1119}
1120
4da19633 1121static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1122{
4da19633 1123 void __iomem *ioaddr = tp->mmio_addr;
1124
1da177e4
LT		 1125 return RTL_R32(TBICSR) & TBIReset;
1126}
1127
4da19633 1128static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1129{
4da19633 1130 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1131}
1132
1133static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1134{
1135 return RTL_R32(TBICSR) & TBILinkOk;
1136}
1137
1138static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1139{
1140 return RTL_R8(PHYstatus) & LinkStatus;
1141}
1142
4da19633 1143static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1144{
4da19633 1145 void __iomem *ioaddr = tp->mmio_addr;
1146
1da177e4
LT		 1147 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1148}
1149
4da19633 1150static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1151{
1152 unsigned int val;
1153
4da19633 1154 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1155 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1156}
1157
70090424
HW		 1158static void rtl_link_chg_patch(struct rtl8169_private *tp)
1159{
1160 void __iomem *ioaddr = tp->mmio_addr;
1161 struct net_device *dev = tp->dev;
1162
1163 if (!netif_running(dev))
1164 return;
1165
1166 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1167 if (RTL_R8(PHYstatus) & _1000bpsF) {
1168 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1169 0x00000011, ERIAR_EXGMAC);
1170 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1171 0x00000005, ERIAR_EXGMAC);
1172 } else if (RTL_R8(PHYstatus) & _100bps) {
1173 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1174 0x0000001f, ERIAR_EXGMAC);
1175 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1176 0x00000005, ERIAR_EXGMAC);
1177 } else {
1178 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1179 0x0000001f, ERIAR_EXGMAC);
1180 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1181 0x0000003f, ERIAR_EXGMAC);
1182 }
1183 /* Reset packet filter */
1184 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1185 ERIAR_EXGMAC);
1186 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1187 ERIAR_EXGMAC);
1188 }
1189}
1190
e4fbce74 1191static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1192 struct rtl8169_private *tp,
1193 void __iomem *ioaddr, bool pm)
1da177e4
LT		 1194{
1195 unsigned long flags;
1196
1197 spin_lock_irqsave(&tp->lock, flags);
1198 if (tp->link_ok(ioaddr)) {
70090424 1199 rtl_link_chg_patch(tp);
e1759441 1200 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1201 if (pm)
1202 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1203 netif_carrier_on(dev);
1519e57f
FR		 1204 if (net_ratelimit())
1205 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1206 } else {
1da177e4 1207 netif_carrier_off(dev);
bf82c189 1208 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74
RW		 1209 if (pm)
1210 pm_schedule_suspend(&tp->pci_dev->dev, 100);
b57b7e5a 1211 }
1da177e4
LT		 1212 spin_unlock_irqrestore(&tp->lock, flags);
1213}
1214
e4fbce74
RW		 1215static void rtl8169_check_link_status(struct net_device *dev,
1216 struct rtl8169_private *tp,
1217 void __iomem *ioaddr)
1218{
1219 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1220}
1221
e1759441
RW		 1222#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1223
1224static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1225{
61a4dcc2
FR		 1226 void __iomem *ioaddr = tp->mmio_addr;
1227 u8 options;
e1759441 1228 u32 wolopts = 0;
61a4dcc2
FR		 1229
1230 options = RTL_R8(Config1);
1231 if (!(options & PMEnable))
e1759441 1232 return 0;
61a4dcc2
FR		 1233
1234 options = RTL_R8(Config3);
1235 if (options & LinkUp)
e1759441 1236 wolopts |= WAKE_PHY;
61a4dcc2 1237 if (options & MagicPacket)
e1759441 1238 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1239
1240 options = RTL_R8(Config5);
1241 if (options & UWF)
e1759441 1242 wolopts |= WAKE_UCAST;
61a4dcc2 1243 if (options & BWF)
e1759441 1244 wolopts |= WAKE_BCAST;
61a4dcc2 1245 if (options & MWF)
e1759441 1246 wolopts |= WAKE_MCAST;
61a4dcc2 1247
e1759441 1248 return wolopts;
61a4dcc2
FR		 1249}
1250
e1759441 1251static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1252{
1253 struct rtl8169_private *tp = netdev_priv(dev);
e1759441
RW		 1254
1255 spin_lock_irq(&tp->lock);
1256
1257 wol->supported = WAKE_ANY;
1258 wol->wolopts = __rtl8169_get_wol(tp);
1259
1260 spin_unlock_irq(&tp->lock);
1261}
1262
1263static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1264{
61a4dcc2 1265 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1266 unsigned int i;
350f7596 1267 static const struct {
61a4dcc2
FR		 1268 u32 opt;
1269 u16 reg;
1270 u8 mask;
1271 } cfg[] = {
1272 { WAKE_ANY, Config1, PMEnable },
1273 { WAKE_PHY, Config3, LinkUp },
1274 { WAKE_MAGIC, Config3, MagicPacket },
1275 { WAKE_UCAST, Config5, UWF },
1276 { WAKE_BCAST, Config5, BWF },
1277 { WAKE_MCAST, Config5, MWF },
1278 { WAKE_ANY, Config5, LanWake }
1279 };
1280
61a4dcc2
FR		 1281 RTL_W8(Cfg9346, Cfg9346_Unlock);
1282
1283 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1284 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1285 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1286 options |= cfg[i].mask;
1287 RTL_W8(cfg[i].reg, options);
1288 }
1289
1290 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1291}
1292
1293static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1294{
1295 struct rtl8169_private *tp = netdev_priv(dev);
1296
1297 spin_lock_irq(&tp->lock);
61a4dcc2 1298
f23e7fda
FR		 1299 if (wol->wolopts)
1300 tp->features |= RTL_FEATURE_WOL;
1301 else
1302 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1303 __rtl8169_set_wol(tp, wol->wolopts);
61a4dcc2
FR		 1304 spin_unlock_irq(&tp->lock);
1305
ea80907f 1306 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1307
61a4dcc2
FR		 1308 return 0;
1309}
1310
31bd204f
FR		 1311static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1312{
85bffe6c 1313 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1314}
1315
1da177e4
LT		 1316static void rtl8169_get_drvinfo(struct net_device *dev,
1317 struct ethtool_drvinfo *info)
1318{
1319 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1320 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4
LT		 1321
1322 strcpy(info->driver, MODULENAME);
1323 strcpy(info->version, RTL8169_VERSION);
1324 strcpy(info->bus_info, pci_name(tp->pci_dev));
1c361efb
FR		 1325 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1326 strcpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" :
1327 rtl_fw->version);
1da177e4
LT		 1328}
1329
1330static int rtl8169_get_regs_len(struct net_device *dev)
1331{
1332 return R8169_REGS_SIZE;
1333}
1334
1335static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1336 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1337{
1338 struct rtl8169_private *tp = netdev_priv(dev);
1339 void __iomem *ioaddr = tp->mmio_addr;
1340 int ret = 0;
1341 u32 reg;
1342
1343 reg = RTL_R32(TBICSR);
1344 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1345 (duplex == DUPLEX_FULL)) {
1346 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1347 } else if (autoneg == AUTONEG_ENABLE)
1348 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1349 else {
bf82c189
JP		 1350 netif_warn(tp, link, dev,
1351 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1352 ret = -EOPNOTSUPP;
1353 }
1354
1355 return ret;
1356}
1357
1358static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1359 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1360{
1361 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1362 int giga_ctrl, bmcr;
54405cde 1363 int rc = -EINVAL;
1da177e4 1364
716b50a3 1365 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1366
1367 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1368 int auto_nego;
1369
4da19633 1370 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1371 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1372 ADVERTISE_100HALF | ADVERTISE_100FULL);
1373
1374 if (adv & ADVERTISED_10baseT_Half)
1375 auto_nego |= ADVERTISE_10HALF;
1376 if (adv & ADVERTISED_10baseT_Full)
1377 auto_nego |= ADVERTISE_10FULL;
1378 if (adv & ADVERTISED_100baseT_Half)
1379 auto_nego |= ADVERTISE_100HALF;
1380 if (adv & ADVERTISED_100baseT_Full)
1381 auto_nego |= ADVERTISE_100FULL;
1382
3577aa1b 1383 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1384
4da19633 1385 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1386 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1387
3577aa1b 1388 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1389 if (tp->mii.supports_gmii) {
54405cde
ON		 1390 if (adv & ADVERTISED_1000baseT_Half)
1391 giga_ctrl |= ADVERTISE_1000HALF;
1392 if (adv & ADVERTISED_1000baseT_Full)
1393 giga_ctrl |= ADVERTISE_1000FULL;
1394 } else if (adv & (ADVERTISED_1000baseT_Half |
1395 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1396 netif_info(tp, link, dev,
1397 "PHY does not support 1000Mbps\n");
54405cde 1398 goto out;
bcf0bf90 1399 }
1da177e4 1400
3577aa1b 1401 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1402
4da19633 1403 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1404 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1405 } else {
1406 giga_ctrl = 0;
1407
1408 if (speed == SPEED_10)
1409 bmcr = 0;
1410 else if (speed == SPEED_100)
1411 bmcr = BMCR_SPEED100;
1412 else
54405cde 1413 goto out;
3577aa1b 1414
1415 if (duplex == DUPLEX_FULL)
1416 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1417 }
1418
4da19633 1419 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1420
cecb5fd7
FR		 1421 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1422 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1423 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1424 rtl_writephy(tp, 0x17, 0x2138);
1425 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1426 } else {
4da19633 1427 rtl_writephy(tp, 0x17, 0x2108);
1428 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1429 }
1430 }
1431
54405cde
ON		 1432 rc = 0;
1433out:
1434 return rc;
1da177e4
LT		 1435}
1436
1437static int rtl8169_set_speed(struct net_device *dev,
54405cde 1438 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1439{
1440 struct rtl8169_private *tp = netdev_priv(dev);
1441 int ret;
1442
54405cde 1443 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1444 if (ret < 0)
1445 goto out;
1da177e4 1446
4876cc1e
FR		 1447 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1448 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1449 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1450 }
1451out:
1da177e4
LT		 1452 return ret;
1453}
1454
1455static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1456{
1457 struct rtl8169_private *tp = netdev_priv(dev);
1458 unsigned long flags;
1459 int ret;
1460
4876cc1e
FR		 1461 del_timer_sync(&tp->timer);
1462
1da177e4 1463 spin_lock_irqsave(&tp->lock, flags);
cecb5fd7 1464 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1465 cmd->duplex, cmd->advertising);
1da177e4 1466 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 1467
1da177e4
LT		 1468 return ret;
1469}
1470
350fb32a 1471static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1da177e4 1472{
2b7b4318 1473 if (dev->mtu > TD_MSS_MAX)
350fb32a 1474 features &= ~NETIF_F_ALL_TSO;
1da177e4 1475
350fb32a 1476 return features;
1da177e4
LT		 1477}
1478
350fb32a 1479static int rtl8169_set_features(struct net_device *dev, u32 features)
1da177e4
LT		 1480{
1481 struct rtl8169_private *tp = netdev_priv(dev);
1482 void __iomem *ioaddr = tp->mmio_addr;
1483 unsigned long flags;
1484
1485 spin_lock_irqsave(&tp->lock, flags);
1486
350fb32a 1487 if (features & NETIF_F_RXCSUM)
1da177e4
LT		 1488 tp->cp_cmd |= RxChkSum;
1489 else
1490 tp->cp_cmd &= ~RxChkSum;
1491
350fb32a
MM		 1492 if (dev->features & NETIF_F_HW_VLAN_RX)
1493 tp->cp_cmd |= RxVlan;
1494 else
1495 tp->cp_cmd &= ~RxVlan;
1496
1da177e4
LT		 1497 RTL_W16(CPlusCmd, tp->cp_cmd);
1498 RTL_R16(CPlusCmd);
1499
1500 spin_unlock_irqrestore(&tp->lock, flags);
1501
1502 return 0;
1503}
1504
1da177e4
LT		 1505static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1506 struct sk_buff *skb)
1507{
eab6d18d 1508 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1509 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1510}
1511
7a8fc77b 1512static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1513{
1514 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1515
7a8fc77b
FR		 1516 if (opts2 & RxVlanTag)
1517 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
2edae08e 1518
1da177e4 1519 desc->opts2 = 0;
1da177e4
LT		 1520}
1521
ccdffb9a 1522static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1523{
1524 struct rtl8169_private *tp = netdev_priv(dev);
1525 void __iomem *ioaddr = tp->mmio_addr;
1526 u32 status;
1527
1528 cmd->supported =
1529 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1530 cmd->port = PORT_FIBRE;
1531 cmd->transceiver = XCVR_INTERNAL;
1532
1533 status = RTL_R32(TBICSR);
1534 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1535 cmd->autoneg = !!(status & TBINwEnable);
1536
70739497 1537 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1538 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1539
1540 return 0;
1da177e4
LT		 1541}
1542
ccdffb9a 1543static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1544{
1545 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1546
1547 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1548}
1549
1550static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1551{
1552 struct rtl8169_private *tp = netdev_priv(dev);
1553 unsigned long flags;
ccdffb9a 1554 int rc;
1da177e4
LT		 1555
1556 spin_lock_irqsave(&tp->lock, flags);
1557
ccdffb9a 1558 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1559
1560 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1561 return rc;
1da177e4
LT		 1562}
1563
1564static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1565 void *p)
1566{
5b0384f4
FR		 1567 struct rtl8169_private *tp = netdev_priv(dev);
1568 unsigned long flags;
1da177e4 1569
5b0384f4
FR		 1570 if (regs->len > R8169_REGS_SIZE)
1571 regs->len = R8169_REGS_SIZE;
1da177e4 1572
5b0384f4
FR		 1573 spin_lock_irqsave(&tp->lock, flags);
1574 memcpy_fromio(p, tp->mmio_addr, regs->len);
1575 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1576}
1577
b57b7e5a
SH		 1578static u32 rtl8169_get_msglevel(struct net_device *dev)
1579{
1580 struct rtl8169_private *tp = netdev_priv(dev);
1581
1582 return tp->msg_enable;
1583}
1584
1585static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1586{
1587 struct rtl8169_private *tp = netdev_priv(dev);
1588
1589 tp->msg_enable = value;
1590}
1591
d4a3a0fc
SH		 1592static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1593 "tx_packets",
1594 "rx_packets",
1595 "tx_errors",
1596 "rx_errors",
1597 "rx_missed",
1598 "align_errors",
1599 "tx_single_collisions",
1600 "tx_multi_collisions",
1601 "unicast",
1602 "broadcast",
1603 "multicast",
1604 "tx_aborted",
1605 "tx_underrun",
1606};
1607
b9f2c044 1608static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1609{
b9f2c044
JG		 1610 switch (sset) {
1611 case ETH_SS_STATS:
1612 return ARRAY_SIZE(rtl8169_gstrings);
1613 default:
1614 return -EOPNOTSUPP;
1615 }
d4a3a0fc
SH		 1616}
1617
355423d0 1618static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1619{
1620 struct rtl8169_private *tp = netdev_priv(dev);
1621 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 1622 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 1623 struct rtl8169_counters *counters;
1624 dma_addr_t paddr;
1625 u32 cmd;
355423d0 1626 int wait = 1000;
d4a3a0fc 1627
355423d0
IV		 1628 /*
1629 * Some chips are unable to dump tally counters when the receiver
1630 * is disabled.
1631 */
1632 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1633 return;
d4a3a0fc 1634
48addcc9 1635 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1636 if (!counters)
1637 return;
1638
1639 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1640 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1641 RTL_W32(CounterAddrLow, cmd);
1642 RTL_W32(CounterAddrLow, cmd | CounterDump);
1643
355423d0
IV		 1644 while (wait--) {
1645 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
355423d0 1646 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1647 break;
355423d0
IV		 1648 }
1649 udelay(10);
d4a3a0fc
SH		 1650 }
1651
1652 RTL_W32(CounterAddrLow, 0);
1653 RTL_W32(CounterAddrHigh, 0);
1654
48addcc9 1655 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1656}
1657
355423d0
IV		 1658static void rtl8169_get_ethtool_stats(struct net_device *dev,
1659 struct ethtool_stats *stats, u64 *data)
1660{
1661 struct rtl8169_private *tp = netdev_priv(dev);
1662
1663 ASSERT_RTNL();
1664
1665 rtl8169_update_counters(dev);
1666
1667 data[0] = le64_to_cpu(tp->counters.tx_packets);
1668 data[1] = le64_to_cpu(tp->counters.rx_packets);
1669 data[2] = le64_to_cpu(tp->counters.tx_errors);
1670 data[3] = le32_to_cpu(tp->counters.rx_errors);
1671 data[4] = le16_to_cpu(tp->counters.rx_missed);
1672 data[5] = le16_to_cpu(tp->counters.align_errors);
1673 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1674 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1675 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1676 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1677 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1678 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1679 data[12] = le16_to_cpu(tp->counters.tx_underun);
1680}
1681
d4a3a0fc
SH		 1682static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1683{
1684 switch(stringset) {
1685 case ETH_SS_STATS:
1686 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1687 break;
1688 }
1689}
1690
7282d491 1691static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1692 .get_drvinfo = rtl8169_get_drvinfo,
1693 .get_regs_len = rtl8169_get_regs_len,
1694 .get_link = ethtool_op_get_link,
1695 .get_settings = rtl8169_get_settings,
1696 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1697 .get_msglevel = rtl8169_get_msglevel,
1698 .set_msglevel = rtl8169_set_msglevel,
1da177e4 1699 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1700 .get_wol = rtl8169_get_wol,
1701 .set_wol = rtl8169_set_wol,
d4a3a0fc 1702 .get_strings = rtl8169_get_strings,
b9f2c044 1703 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1704 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1705};
1706
07d3f51f 1707static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 1708 struct net_device *dev, u8 default_version)
1da177e4 1709{
5d320a20 1710 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 1711 /*
1712 * The driver currently handles the 8168Bf and the 8168Be identically
1713 * but they can be identified more specifically through the test below
1714 * if needed:
1715 *
1716 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1717 *
1718 * Same thing for the 8101Eb and the 8101Ec:
1719 *
1720 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1721 */
3744100e 1722 static const struct rtl_mac_info {
1da177e4 1723 u32 mask;
e3cf0cc0 1724 u32 val;
1da177e4
LT		 1725 int mac_version;
1726 } mac_info[] = {
01dc7fec 1727 /* 8168E family. */
70090424 1728 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 1729 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1730 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1731 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1732
5b538df9 1733 /* 8168D family. */
daf9df6d 1734 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1735 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 1736 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1737
e6de30d6 1738 /* 8168DP family. */
1739 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1740 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 1741 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 1742
ef808d50 1743 /* 8168C family. */
17c99297 1744 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1745 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1746 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1747 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1748 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1749 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1750 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1751 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1752 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1753
1754 /* 8168B family. */
1755 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1756 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1757 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1758 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1759
1760 /* 8101 family. */
36a0e6c2 1761 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 1762 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1763 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1764 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 1765 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1766 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1767 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1768 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1769 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1770 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1771 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1772 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1773 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1774 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1775 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1776 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1777 /* FIXME: where did these entries come from ? -- FR */
1778 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1779 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1780
1781 /* 8110 family. */
1782 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1783 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1784 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1785 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1786 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1787 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1788
f21b75e9
JD		 1789 /* Catch-all */
1790 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 1791 };
1792 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 1793 u32 reg;
1794
e3cf0cc0
FR		 1795 reg = RTL_R32(TxConfig);
1796 while ((reg & p->mask) != p->val)
1da177e4
LT		 1797 p++;
1798 tp->mac_version = p->mac_version;
5d320a20
FR		 1799
1800 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1801 netif_notice(tp, probe, dev,
1802 "unknown MAC, using family default\n");
1803 tp->mac_version = default_version;
1804 }
1da177e4
LT		 1805}
1806
1807static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1808{
bcf0bf90 1809 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1810}
1811
867763c1
FR		 1812struct phy_reg {
1813 u16 reg;
1814 u16 val;
1815};
1816
4da19633 1817static void rtl_writephy_batch(struct rtl8169_private *tp,
1818 const struct phy_reg *regs, int len)
867763c1
FR		 1819{
1820 while (len-- > 0) {
4da19633 1821 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 1822 regs++;
1823 }
1824}
1825
bca03d5f 1826#define PHY_READ 0x00000000
1827#define PHY_DATA_OR 0x10000000
1828#define PHY_DATA_AND 0x20000000
1829#define PHY_BJMPN 0x30000000
1830#define PHY_READ_EFUSE 0x40000000
1831#define PHY_READ_MAC_BYTE 0x50000000
1832#define PHY_WRITE_MAC_BYTE 0x60000000
1833#define PHY_CLEAR_READCOUNT 0x70000000
1834#define PHY_WRITE 0x80000000
1835#define PHY_READCOUNT_EQ_SKIP 0x90000000
1836#define PHY_COMP_EQ_SKIPN 0xa0000000
1837#define PHY_COMP_NEQ_SKIPN 0xb0000000
1838#define PHY_WRITE_PREVIOUS 0xc0000000
1839#define PHY_SKIPN 0xd0000000
1840#define PHY_DELAY_MS 0xe0000000
1841#define PHY_WRITE_ERI_WORD 0xf0000000
1842
960aee6c
HW		 1843struct fw_info {
1844 u32 magic;
1845 char version[RTL_VER_SIZE];
1846 __le32 fw_start;
1847 __le32 fw_len;
1848 u8 chksum;
1849} __packed;
1850
1c361efb
FR		 1851#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1852
1853static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 1854{
b6ffd97f 1855 const struct firmware *fw = rtl_fw->fw;
960aee6c 1856 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 1857 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1858 char *version = rtl_fw->version;
1859 bool rc = false;
1860
1861 if (fw->size < FW_OPCODE_SIZE)
1862 goto out;
960aee6c
HW		 1863
1864 if (!fw_info->magic) {
1865 size_t i, size, start;
1866 u8 checksum = 0;
1867
1868 if (fw->size < sizeof(*fw_info))
1869 goto out;
1870
1871 for (i = 0; i < fw->size; i++)
1872 checksum += fw->data[i];
1873 if (checksum != 0)
1874 goto out;
1875
1876 start = le32_to_cpu(fw_info->fw_start);
1877 if (start > fw->size)
1878 goto out;
1879
1880 size = le32_to_cpu(fw_info->fw_len);
1881 if (size > (fw->size - start) / FW_OPCODE_SIZE)
1882 goto out;
1883
1884 memcpy(version, fw_info->version, RTL_VER_SIZE);
1885
1886 pa->code = (__le32 *)(fw->data + start);
1887 pa->size = size;
1888 } else {
1c361efb
FR		 1889 if (fw->size % FW_OPCODE_SIZE)
1890 goto out;
1891
1892 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
1893
1894 pa->code = (__le32 *)fw->data;
1895 pa->size = fw->size / FW_OPCODE_SIZE;
1896 }
1897 version[RTL_VER_SIZE - 1] = 0;
1898
1899 rc = true;
1900out:
1901 return rc;
1902}
1903
fd112f2e
FR		 1904static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
1905 struct rtl_fw_phy_action *pa)
1c361efb 1906{
fd112f2e 1907 bool rc = false;
1c361efb 1908 size_t index;
bca03d5f 1909
1c361efb
FR		 1910 for (index = 0; index < pa->size; index++) {
1911 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 1912 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 1913
42b82dc1 1914 switch(action & 0xf0000000) {
1915 case PHY_READ:
1916 case PHY_DATA_OR:
1917 case PHY_DATA_AND:
1918 case PHY_READ_EFUSE:
1919 case PHY_CLEAR_READCOUNT:
1920 case PHY_WRITE:
1921 case PHY_WRITE_PREVIOUS:
1922 case PHY_DELAY_MS:
1923 break;
1924
1925 case PHY_BJMPN:
1926 if (regno > index) {
fd112f2e 1927 netif_err(tp, ifup, tp->dev,
cecb5fd7 1928 "Out of range of firmware\n");
fd112f2e 1929 goto out;
42b82dc1 1930 }
1931 break;
1932 case PHY_READCOUNT_EQ_SKIP:
1c361efb 1933 if (index + 2 >= pa->size) {
fd112f2e 1934 netif_err(tp, ifup, tp->dev,
cecb5fd7 1935 "Out of range of firmware\n");
fd112f2e 1936 goto out;
42b82dc1 1937 }
1938 break;
1939 case PHY_COMP_EQ_SKIPN:
1940 case PHY_COMP_NEQ_SKIPN:
1941 case PHY_SKIPN:
1c361efb 1942 if (index + 1 + regno >= pa->size) {
fd112f2e 1943 netif_err(tp, ifup, tp->dev,
cecb5fd7 1944 "Out of range of firmware\n");
fd112f2e 1945 goto out;
42b82dc1 1946 }
bca03d5f 1947 break;
1948
42b82dc1 1949 case PHY_READ_MAC_BYTE:
1950 case PHY_WRITE_MAC_BYTE:
1951 case PHY_WRITE_ERI_WORD:
1952 default:
fd112f2e 1953 netif_err(tp, ifup, tp->dev,
42b82dc1 1954 "Invalid action 0x%08x\n", action);
fd112f2e 1955 goto out;
bca03d5f 1956 }
1957 }
fd112f2e
FR		 1958 rc = true;
1959out:
1960 return rc;
1961}
bca03d5f 1962
fd112f2e
FR		 1963static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1964{
1965 struct net_device *dev = tp->dev;
1966 int rc = -EINVAL;
1967
1968 if (!rtl_fw_format_ok(tp, rtl_fw)) {
1969 netif_err(tp, ifup, dev, "invalid firwmare\n");
1970 goto out;
1971 }
1972
1973 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
1974 rc = 0;
1975out:
1976 return rc;
1977}
1978
1979static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1980{
1981 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1982 u32 predata, count;
1983 size_t index;
1984
1985 predata = count = 0;
42b82dc1 1986
1c361efb
FR		 1987 for (index = 0; index < pa->size; ) {
1988 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 1989 u32 data = action & 0x0000ffff;
42b82dc1 1990 u32 regno = (action & 0x0fff0000) >> 16;
1991
1992 if (!action)
1993 break;
bca03d5f 1994
1995 switch(action & 0xf0000000) {
42b82dc1 1996 case PHY_READ:
1997 predata = rtl_readphy(tp, regno);
1998 count++;
1999 index++;
2000 break;
2001 case PHY_DATA_OR:
2002 predata |= data;
2003 index++;
2004 break;
2005 case PHY_DATA_AND:
2006 predata &= data;
2007 index++;
2008 break;
2009 case PHY_BJMPN:
2010 index -= regno;
2011 break;
2012 case PHY_READ_EFUSE:
2013 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2014 index++;
2015 break;
2016 case PHY_CLEAR_READCOUNT:
2017 count = 0;
2018 index++;
2019 break;
bca03d5f 2020 case PHY_WRITE:
42b82dc1 2021 rtl_writephy(tp, regno, data);
2022 index++;
2023 break;
2024 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2025 index += (count == data) ? 2 : 1;
bca03d5f 2026 break;
42b82dc1 2027 case PHY_COMP_EQ_SKIPN:
2028 if (predata == data)
2029 index += regno;
2030 index++;
2031 break;
2032 case PHY_COMP_NEQ_SKIPN:
2033 if (predata != data)
2034 index += regno;
2035 index++;
2036 break;
2037 case PHY_WRITE_PREVIOUS:
2038 rtl_writephy(tp, regno, predata);
2039 index++;
2040 break;
2041 case PHY_SKIPN:
2042 index += regno + 1;
2043 break;
2044 case PHY_DELAY_MS:
2045 mdelay(data);
2046 index++;
2047 break;
2048
2049 case PHY_READ_MAC_BYTE:
2050 case PHY_WRITE_MAC_BYTE:
2051 case PHY_WRITE_ERI_WORD:
bca03d5f 2052 default:
2053 BUG();
2054 }
2055 }
2056}
2057
f1e02ed1 2058static void rtl_release_firmware(struct rtl8169_private *tp)
2059{
b6ffd97f
FR		 2060 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2061 release_firmware(tp->rtl_fw->fw);
2062 kfree(tp->rtl_fw);
2063 }
2064 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2065}
2066
953a12cc 2067static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2068{
b6ffd97f 2069 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2070
2071 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
b6ffd97f
FR		 2072 if (!IS_ERR_OR_NULL(rtl_fw))
2073 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2074}
2075
2076static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2077{
2078 if (rtl_readphy(tp, reg) != val)
2079 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2080 else
2081 rtl_apply_firmware(tp);
f1e02ed1 2082}
2083
4da19633 2084static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2085{
350f7596 2086 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2087 { 0x1f, 0x0001 },
2088 { 0x06, 0x006e },
2089 { 0x08, 0x0708 },
2090 { 0x15, 0x4000 },
2091 { 0x18, 0x65c7 },
1da177e4 2092
0b9b571d 2093 { 0x1f, 0x0001 },
2094 { 0x03, 0x00a1 },
2095 { 0x02, 0x0008 },
2096 { 0x01, 0x0120 },
2097 { 0x00, 0x1000 },
2098 { 0x04, 0x0800 },
2099 { 0x04, 0x0000 },
1da177e4 2100
0b9b571d 2101 { 0x03, 0xff41 },
2102 { 0x02, 0xdf60 },
2103 { 0x01, 0x0140 },
2104 { 0x00, 0x0077 },
2105 { 0x04, 0x7800 },
2106 { 0x04, 0x7000 },
2107
2108 { 0x03, 0x802f },
2109 { 0x02, 0x4f02 },
2110 { 0x01, 0x0409 },
2111 { 0x00, 0xf0f9 },
2112 { 0x04, 0x9800 },
2113 { 0x04, 0x9000 },
2114
2115 { 0x03, 0xdf01 },
2116 { 0x02, 0xdf20 },
2117 { 0x01, 0xff95 },
2118 { 0x00, 0xba00 },
2119 { 0x04, 0xa800 },
2120 { 0x04, 0xa000 },
2121
2122 { 0x03, 0xff41 },
2123 { 0x02, 0xdf20 },
2124 { 0x01, 0x0140 },
2125 { 0x00, 0x00bb },
2126 { 0x04, 0xb800 },
2127 { 0x04, 0xb000 },
2128
2129 { 0x03, 0xdf41 },
2130 { 0x02, 0xdc60 },
2131 { 0x01, 0x6340 },
2132 { 0x00, 0x007d },
2133 { 0x04, 0xd800 },
2134 { 0x04, 0xd000 },
2135
2136 { 0x03, 0xdf01 },
2137 { 0x02, 0xdf20 },
2138 { 0x01, 0x100a },
2139 { 0x00, 0xa0ff },
2140 { 0x04, 0xf800 },
2141 { 0x04, 0xf000 },
2142
2143 { 0x1f, 0x0000 },
2144 { 0x0b, 0x0000 },
2145 { 0x00, 0x9200 }
2146 };
1da177e4 2147
4da19633 2148 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2149}
2150
4da19633 2151static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2152{
350f7596 2153 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2154 { 0x1f, 0x0002 },
2155 { 0x01, 0x90d0 },
2156 { 0x1f, 0x0000 }
2157 };
2158
4da19633 2159 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2160}
2161
4da19633 2162static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2163{
2164 struct pci_dev *pdev = tp->pci_dev;
2165 u16 vendor_id, device_id;
2166
2167 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
2168 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
2169
2170 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
2171 return;
2172
4da19633 2173 rtl_writephy(tp, 0x1f, 0x0001);
2174 rtl_writephy(tp, 0x10, 0xf01b);
2175 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2176}
2177
4da19633 2178static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2179{
350f7596 2180 static const struct phy_reg phy_reg_init[] = {
2e955856 2181 { 0x1f, 0x0001 },
2182 { 0x04, 0x0000 },
2183 { 0x03, 0x00a1 },
2184 { 0x02, 0x0008 },
2185 { 0x01, 0x0120 },
2186 { 0x00, 0x1000 },
2187 { 0x04, 0x0800 },
2188 { 0x04, 0x9000 },
2189 { 0x03, 0x802f },
2190 { 0x02, 0x4f02 },
2191 { 0x01, 0x0409 },
2192 { 0x00, 0xf099 },
2193 { 0x04, 0x9800 },
2194 { 0x04, 0xa000 },
2195 { 0x03, 0xdf01 },
2196 { 0x02, 0xdf20 },
2197 { 0x01, 0xff95 },
2198 { 0x00, 0xba00 },
2199 { 0x04, 0xa800 },
2200 { 0x04, 0xf000 },
2201 { 0x03, 0xdf01 },
2202 { 0x02, 0xdf20 },
2203 { 0x01, 0x101a },
2204 { 0x00, 0xa0ff },
2205 { 0x04, 0xf800 },
2206 { 0x04, 0x0000 },
2207 { 0x1f, 0x0000 },
2208
2209 { 0x1f, 0x0001 },
2210 { 0x10, 0xf41b },
2211 { 0x14, 0xfb54 },
2212 { 0x18, 0xf5c7 },
2213 { 0x1f, 0x0000 },
2214
2215 { 0x1f, 0x0001 },
2216 { 0x17, 0x0cc0 },
2217 { 0x1f, 0x0000 }
2218 };
2219
4da19633 2220 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2221
4da19633 2222 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2223}
2224
4da19633 2225static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2226{
350f7596 2227 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2228 { 0x1f, 0x0001 },
2229 { 0x04, 0x0000 },
2230 { 0x03, 0x00a1 },
2231 { 0x02, 0x0008 },
2232 { 0x01, 0x0120 },
2233 { 0x00, 0x1000 },
2234 { 0x04, 0x0800 },
2235 { 0x04, 0x9000 },
2236 { 0x03, 0x802f },
2237 { 0x02, 0x4f02 },
2238 { 0x01, 0x0409 },
2239 { 0x00, 0xf099 },
2240 { 0x04, 0x9800 },
2241 { 0x04, 0xa000 },
2242 { 0x03, 0xdf01 },
2243 { 0x02, 0xdf20 },
2244 { 0x01, 0xff95 },
2245 { 0x00, 0xba00 },
2246 { 0x04, 0xa800 },
2247 { 0x04, 0xf000 },
2248 { 0x03, 0xdf01 },
2249 { 0x02, 0xdf20 },
2250 { 0x01, 0x101a },
2251 { 0x00, 0xa0ff },
2252 { 0x04, 0xf800 },
2253 { 0x04, 0x0000 },
2254 { 0x1f, 0x0000 },
2255
2256 { 0x1f, 0x0001 },
2257 { 0x0b, 0x8480 },
2258 { 0x1f, 0x0000 },
2259
2260 { 0x1f, 0x0001 },
2261 { 0x18, 0x67c7 },
2262 { 0x04, 0x2000 },
2263 { 0x03, 0x002f },
2264 { 0x02, 0x4360 },
2265 { 0x01, 0x0109 },
2266 { 0x00, 0x3022 },
2267 { 0x04, 0x2800 },
2268 { 0x1f, 0x0000 },
2269
2270 { 0x1f, 0x0001 },
2271 { 0x17, 0x0cc0 },
2272 { 0x1f, 0x0000 }
2273 };
2274
4da19633 2275 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2276}
2277
4da19633 2278static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2279{
350f7596 2280 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2281 { 0x10, 0xf41b },
2282 { 0x1f, 0x0000 }
2283 };
2284
4da19633 2285 rtl_writephy(tp, 0x1f, 0x0001);
2286 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2287
4da19633 2288 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2289}
2290
4da19633 2291static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2292{
350f7596 2293 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2294 { 0x1f, 0x0001 },
2295 { 0x10, 0xf41b },
2296 { 0x1f, 0x0000 }
2297 };
2298
4da19633 2299 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2300}
2301
4da19633 2302static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2303{
350f7596 2304 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2305 { 0x1f, 0x0000 },
2306 { 0x1d, 0x0f00 },
2307 { 0x1f, 0x0002 },
2308 { 0x0c, 0x1ec8 },
2309 { 0x1f, 0x0000 }
2310 };
2311
4da19633 2312 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2313}
2314
4da19633 2315static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2316{
350f7596 2317 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2318 { 0x1f, 0x0001 },
2319 { 0x1d, 0x3d98 },
2320 { 0x1f, 0x0000 }
2321 };
2322
4da19633 2323 rtl_writephy(tp, 0x1f, 0x0000);
2324 rtl_patchphy(tp, 0x14, 1 << 5);
2325 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2326
4da19633 2327 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2328}
2329
4da19633 2330static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2331{
350f7596 2332 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2333 { 0x1f, 0x0001 },
2334 { 0x12, 0x2300 },
867763c1
FR		 2335 { 0x1f, 0x0002 },
2336 { 0x00, 0x88d4 },
2337 { 0x01, 0x82b1 },
2338 { 0x03, 0x7002 },
2339 { 0x08, 0x9e30 },
2340 { 0x09, 0x01f0 },
2341 { 0x0a, 0x5500 },
2342 { 0x0c, 0x00c8 },
2343 { 0x1f, 0x0003 },
2344 { 0x12, 0xc096 },
2345 { 0x16, 0x000a },
f50d4275
FR		 2346 { 0x1f, 0x0000 },
2347 { 0x1f, 0x0000 },
2348 { 0x09, 0x2000 },
2349 { 0x09, 0x0000 }
867763c1
FR		 2350 };
2351
4da19633 2352 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2353
4da19633 2354 rtl_patchphy(tp, 0x14, 1 << 5);
2355 rtl_patchphy(tp, 0x0d, 1 << 5);
2356 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2357}
2358
4da19633 2359static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2360{
350f7596 2361 static const struct phy_reg phy_reg_init[] = {
f50d4275 2362 { 0x1f, 0x0001 },
7da97ec9 2363 { 0x12, 0x2300 },
f50d4275
FR		 2364 { 0x03, 0x802f },
2365 { 0x02, 0x4f02 },
2366 { 0x01, 0x0409 },
2367 { 0x00, 0xf099 },
2368 { 0x04, 0x9800 },
2369 { 0x04, 0x9000 },
2370 { 0x1d, 0x3d98 },
7da97ec9
FR		 2371 { 0x1f, 0x0002 },
2372 { 0x0c, 0x7eb8 },
f50d4275
FR		 2373 { 0x06, 0x0761 },
2374 { 0x1f, 0x0003 },
2375 { 0x16, 0x0f0a },
7da97ec9
FR		 2376 { 0x1f, 0x0000 }
2377 };
2378
4da19633 2379 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2380
4da19633 2381 rtl_patchphy(tp, 0x16, 1 << 0);
2382 rtl_patchphy(tp, 0x14, 1 << 5);
2383 rtl_patchphy(tp, 0x0d, 1 << 5);
2384 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2385}
2386
4da19633 2387static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2388{
350f7596 2389 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2390 { 0x1f, 0x0001 },
2391 { 0x12, 0x2300 },
2392 { 0x1d, 0x3d98 },
2393 { 0x1f, 0x0002 },
2394 { 0x0c, 0x7eb8 },
2395 { 0x06, 0x5461 },
2396 { 0x1f, 0x0003 },
2397 { 0x16, 0x0f0a },
2398 { 0x1f, 0x0000 }
2399 };
2400
4da19633 2401 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2402
4da19633 2403 rtl_patchphy(tp, 0x16, 1 << 0);
2404 rtl_patchphy(tp, 0x14, 1 << 5);
2405 rtl_patchphy(tp, 0x0d, 1 << 5);
2406 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2407}
2408
4da19633 2409static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2410{
4da19633 2411 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2412}
2413
bca03d5f 2414static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2415{
350f7596 2416 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2417 /* Channel Estimation */
5b538df9 2418 { 0x1f, 0x0001 },
daf9df6d 2419 { 0x06, 0x4064 },
2420 { 0x07, 0x2863 },
2421 { 0x08, 0x059c },
2422 { 0x09, 0x26b4 },
2423 { 0x0a, 0x6a19 },
2424 { 0x0b, 0xdcc8 },
2425 { 0x10, 0xf06d },
2426 { 0x14, 0x7f68 },
2427 { 0x18, 0x7fd9 },
2428 { 0x1c, 0xf0ff },
2429 { 0x1d, 0x3d9c },
5b538df9 2430 { 0x1f, 0x0003 },
daf9df6d 2431 { 0x12, 0xf49f },
2432 { 0x13, 0x070b },
2433 { 0x1a, 0x05ad },
bca03d5f 2434 { 0x14, 0x94c0 },
2435
2436 /*
2437 * Tx Error Issue
cecb5fd7 2438 * Enhance line driver power
bca03d5f 2439 */
5b538df9 2440 { 0x1f, 0x0002 },
daf9df6d 2441 { 0x06, 0x5561 },
2442 { 0x1f, 0x0005 },
2443 { 0x05, 0x8332 },
bca03d5f 2444 { 0x06, 0x5561 },
2445
2446 /*
2447 * Can not link to 1Gbps with bad cable
2448 * Decrease SNR threshold form 21.07dB to 19.04dB
2449 */
2450 { 0x1f, 0x0001 },
2451 { 0x17, 0x0cc0 },
daf9df6d 2452
5b538df9 2453 { 0x1f, 0x0000 },
bca03d5f 2454 { 0x0d, 0xf880 }
daf9df6d 2455 };
bca03d5f 2456 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 2457
4da19633 2458 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2459
bca03d5f 2460 /*
2461 * Rx Error Issue
2462 * Fine Tune Switching regulator parameter
2463 */
4da19633 2464 rtl_writephy(tp, 0x1f, 0x0002);
2465 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2466 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2467
daf9df6d 2468 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2469 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2470 { 0x1f, 0x0002 },
2471 { 0x05, 0x669a },
2472 { 0x1f, 0x0005 },
2473 { 0x05, 0x8330 },
2474 { 0x06, 0x669a },
2475 { 0x1f, 0x0002 }
2476 };
2477 int val;
2478
4da19633 2479 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2480
4da19633 2481 val = rtl_readphy(tp, 0x0d);
daf9df6d 2482
2483 if ((val & 0x00ff) != 0x006c) {
350f7596 2484 static const u32 set[] = {
daf9df6d 2485 0x0065, 0x0066, 0x0067, 0x0068,
2486 0x0069, 0x006a, 0x006b, 0x006c
2487 };
2488 int i;
2489
4da19633 2490 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2491
2492 val &= 0xff00;
2493 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2494 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2495 }
2496 } else {
350f7596 2497 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2498 { 0x1f, 0x0002 },
2499 { 0x05, 0x6662 },
2500 { 0x1f, 0x0005 },
2501 { 0x05, 0x8330 },
2502 { 0x06, 0x6662 }
2503 };
2504
4da19633 2505 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2506 }
2507
bca03d5f 2508 /* RSET couple improve */
4da19633 2509 rtl_writephy(tp, 0x1f, 0x0002);
2510 rtl_patchphy(tp, 0x0d, 0x0300);
2511 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2512
bca03d5f 2513 /* Fine tune PLL performance */
4da19633 2514 rtl_writephy(tp, 0x1f, 0x0002);
2515 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2516 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2517
4da19633 2518 rtl_writephy(tp, 0x1f, 0x0005);
2519 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2520
2521 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2522
4da19633 2523 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2524}
2525
bca03d5f 2526static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2527{
350f7596 2528 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2529 /* Channel Estimation */
daf9df6d 2530 { 0x1f, 0x0001 },
2531 { 0x06, 0x4064 },
2532 { 0x07, 0x2863 },
2533 { 0x08, 0x059c },
2534 { 0x09, 0x26b4 },
2535 { 0x0a, 0x6a19 },
2536 { 0x0b, 0xdcc8 },
2537 { 0x10, 0xf06d },
2538 { 0x14, 0x7f68 },
2539 { 0x18, 0x7fd9 },
2540 { 0x1c, 0xf0ff },
2541 { 0x1d, 0x3d9c },
2542 { 0x1f, 0x0003 },
2543 { 0x12, 0xf49f },
2544 { 0x13, 0x070b },
2545 { 0x1a, 0x05ad },
2546 { 0x14, 0x94c0 },
2547
bca03d5f 2548 /*
2549 * Tx Error Issue
cecb5fd7 2550 * Enhance line driver power
bca03d5f 2551 */
daf9df6d 2552 { 0x1f, 0x0002 },
2553 { 0x06, 0x5561 },
2554 { 0x1f, 0x0005 },
2555 { 0x05, 0x8332 },
bca03d5f 2556 { 0x06, 0x5561 },
2557
2558 /*
2559 * Can not link to 1Gbps with bad cable
2560 * Decrease SNR threshold form 21.07dB to 19.04dB
2561 */
2562 { 0x1f, 0x0001 },
2563 { 0x17, 0x0cc0 },
daf9df6d 2564
2565 { 0x1f, 0x0000 },
bca03d5f 2566 { 0x0d, 0xf880 }
5b538df9 2567 };
bca03d5f 2568 void __iomem *ioaddr = tp->mmio_addr;
5b538df9 2569
4da19633 2570 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2571
daf9df6d 2572 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2573 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2574 { 0x1f, 0x0002 },
2575 { 0x05, 0x669a },
5b538df9 2576 { 0x1f, 0x0005 },
daf9df6d 2577 { 0x05, 0x8330 },
2578 { 0x06, 0x669a },
2579
2580 { 0x1f, 0x0002 }
2581 };
2582 int val;
2583
4da19633 2584 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2585
4da19633 2586 val = rtl_readphy(tp, 0x0d);
daf9df6d 2587 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2588 static const u32 set[] = {
daf9df6d 2589 0x0065, 0x0066, 0x0067, 0x0068,
2590 0x0069, 0x006a, 0x006b, 0x006c
2591 };
2592 int i;
2593
4da19633 2594 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2595
2596 val &= 0xff00;
2597 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2598 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2599 }
2600 } else {
350f7596 2601 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2602 { 0x1f, 0x0002 },
2603 { 0x05, 0x2642 },
5b538df9 2604 { 0x1f, 0x0005 },
daf9df6d 2605 { 0x05, 0x8330 },
2606 { 0x06, 0x2642 }
5b538df9
FR		 2607 };
2608
4da19633 2609 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2610 }
2611
bca03d5f 2612 /* Fine tune PLL performance */
4da19633 2613 rtl_writephy(tp, 0x1f, 0x0002);
2614 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2615 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2616
bca03d5f 2617 /* Switching regulator Slew rate */
4da19633 2618 rtl_writephy(tp, 0x1f, 0x0002);
2619 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2620
4da19633 2621 rtl_writephy(tp, 0x1f, 0x0005);
2622 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2623
2624 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2625
4da19633 2626 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2627}
2628
4da19633 2629static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2630{
350f7596 2631 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2632 { 0x1f, 0x0002 },
2633 { 0x10, 0x0008 },
2634 { 0x0d, 0x006c },
2635
2636 { 0x1f, 0x0000 },
2637 { 0x0d, 0xf880 },
2638
2639 { 0x1f, 0x0001 },
2640 { 0x17, 0x0cc0 },
2641
2642 { 0x1f, 0x0001 },
2643 { 0x0b, 0xa4d8 },
2644 { 0x09, 0x281c },
2645 { 0x07, 0x2883 },
2646 { 0x0a, 0x6b35 },
2647 { 0x1d, 0x3da4 },
2648 { 0x1c, 0xeffd },
2649 { 0x14, 0x7f52 },
2650 { 0x18, 0x7fc6 },
2651 { 0x08, 0x0601 },
2652 { 0x06, 0x4063 },
2653 { 0x10, 0xf074 },
2654 { 0x1f, 0x0003 },
2655 { 0x13, 0x0789 },
2656 { 0x12, 0xf4bd },
2657 { 0x1a, 0x04fd },
2658 { 0x14, 0x84b0 },
2659 { 0x1f, 0x0000 },
2660 { 0x00, 0x9200 },
2661
2662 { 0x1f, 0x0005 },
2663 { 0x01, 0x0340 },
2664 { 0x1f, 0x0001 },
2665 { 0x04, 0x4000 },
2666 { 0x03, 0x1d21 },
2667 { 0x02, 0x0c32 },
2668 { 0x01, 0x0200 },
2669 { 0x00, 0x5554 },
2670 { 0x04, 0x4800 },
2671 { 0x04, 0x4000 },
2672 { 0x04, 0xf000 },
2673 { 0x03, 0xdf01 },
2674 { 0x02, 0xdf20 },
2675 { 0x01, 0x101a },
2676 { 0x00, 0xa0ff },
2677 { 0x04, 0xf800 },
2678 { 0x04, 0xf000 },
2679 { 0x1f, 0x0000 },
2680
2681 { 0x1f, 0x0007 },
2682 { 0x1e, 0x0023 },
2683 { 0x16, 0x0000 },
2684 { 0x1f, 0x0000 }
2685 };
2686
4da19633 2687 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2688}
2689
e6de30d6 2690static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2691{
2692 static const struct phy_reg phy_reg_init[] = {
2693 { 0x1f, 0x0001 },
2694 { 0x17, 0x0cc0 },
2695
2696 { 0x1f, 0x0007 },
2697 { 0x1e, 0x002d },
2698 { 0x18, 0x0040 },
2699 { 0x1f, 0x0000 }
2700 };
2701
2702 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2703 rtl_patchphy(tp, 0x0d, 1 << 5);
2704}
2705
70090424 2706static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 2707{
2708 static const struct phy_reg phy_reg_init[] = {
2709 /* Enable Delay cap */
2710 { 0x1f, 0x0005 },
2711 { 0x05, 0x8b80 },
2712 { 0x06, 0xc896 },
2713 { 0x1f, 0x0000 },
2714
2715 /* Channel estimation fine tune */
2716 { 0x1f, 0x0001 },
2717 { 0x0b, 0x6c20 },
2718 { 0x07, 0x2872 },
2719 { 0x1c, 0xefff },
2720 { 0x1f, 0x0003 },
2721 { 0x14, 0x6420 },
2722 { 0x1f, 0x0000 },
2723
2724 /* Update PFM & 10M TX idle timer */
2725 { 0x1f, 0x0007 },
2726 { 0x1e, 0x002f },
2727 { 0x15, 0x1919 },
2728 { 0x1f, 0x0000 },
2729
2730 { 0x1f, 0x0007 },
2731 { 0x1e, 0x00ac },
2732 { 0x18, 0x0006 },
2733 { 0x1f, 0x0000 }
2734 };
2735
15ecd039
FR		 2736 rtl_apply_firmware(tp);
2737
01dc7fec 2738 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2739
2740 /* DCO enable for 10M IDLE Power */
2741 rtl_writephy(tp, 0x1f, 0x0007);
2742 rtl_writephy(tp, 0x1e, 0x0023);
2743 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2744 rtl_writephy(tp, 0x1f, 0x0000);
2745
2746 /* For impedance matching */
2747 rtl_writephy(tp, 0x1f, 0x0002);
2748 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 2749 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 2750
2751 /* PHY auto speed down */
2752 rtl_writephy(tp, 0x1f, 0x0007);
2753 rtl_writephy(tp, 0x1e, 0x002d);
2754 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2755 rtl_writephy(tp, 0x1f, 0x0000);
2756 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2757
2758 rtl_writephy(tp, 0x1f, 0x0005);
2759 rtl_writephy(tp, 0x05, 0x8b86);
2760 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2761 rtl_writephy(tp, 0x1f, 0x0000);
2762
2763 rtl_writephy(tp, 0x1f, 0x0005);
2764 rtl_writephy(tp, 0x05, 0x8b85);
2765 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2766 rtl_writephy(tp, 0x1f, 0x0007);
2767 rtl_writephy(tp, 0x1e, 0x0020);
2768 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2769 rtl_writephy(tp, 0x1f, 0x0006);
2770 rtl_writephy(tp, 0x00, 0x5a00);
2771 rtl_writephy(tp, 0x1f, 0x0000);
2772 rtl_writephy(tp, 0x0d, 0x0007);
2773 rtl_writephy(tp, 0x0e, 0x003c);
2774 rtl_writephy(tp, 0x0d, 0x4007);
2775 rtl_writephy(tp, 0x0e, 0x0000);
2776 rtl_writephy(tp, 0x0d, 0x0000);
2777}
2778
70090424
HW		 2779static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2780{
2781 static const struct phy_reg phy_reg_init[] = {
2782 /* Enable Delay cap */
2783 { 0x1f, 0x0004 },
2784 { 0x1f, 0x0007 },
2785 { 0x1e, 0x00ac },
2786 { 0x18, 0x0006 },
2787 { 0x1f, 0x0002 },
2788 { 0x1f, 0x0000 },
2789 { 0x1f, 0x0000 },
2790
2791 /* Channel estimation fine tune */
2792 { 0x1f, 0x0003 },
2793 { 0x09, 0xa20f },
2794 { 0x1f, 0x0000 },
2795 { 0x1f, 0x0000 },
2796
2797 /* Green Setting */
2798 { 0x1f, 0x0005 },
2799 { 0x05, 0x8b5b },
2800 { 0x06, 0x9222 },
2801 { 0x05, 0x8b6d },
2802 { 0x06, 0x8000 },
2803 { 0x05, 0x8b76 },
2804 { 0x06, 0x8000 },
2805 { 0x1f, 0x0000 }
2806 };
2807
2808 rtl_apply_firmware(tp);
2809
2810 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2811
2812 /* For 4-corner performance improve */
2813 rtl_writephy(tp, 0x1f, 0x0005);
2814 rtl_writephy(tp, 0x05, 0x8b80);
2815 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2816 rtl_writephy(tp, 0x1f, 0x0000);
2817
2818 /* PHY auto speed down */
2819 rtl_writephy(tp, 0x1f, 0x0004);
2820 rtl_writephy(tp, 0x1f, 0x0007);
2821 rtl_writephy(tp, 0x1e, 0x002d);
2822 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2823 rtl_writephy(tp, 0x1f, 0x0002);
2824 rtl_writephy(tp, 0x1f, 0x0000);
2825 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2826
2827 /* improve 10M EEE waveform */
2828 rtl_writephy(tp, 0x1f, 0x0005);
2829 rtl_writephy(tp, 0x05, 0x8b86);
2830 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2831 rtl_writephy(tp, 0x1f, 0x0000);
2832
2833 /* Improve 2-pair detection performance */
2834 rtl_writephy(tp, 0x1f, 0x0005);
2835 rtl_writephy(tp, 0x05, 0x8b85);
2836 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2837 rtl_writephy(tp, 0x1f, 0x0000);
2838
2839 /* EEE setting */
2840 rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
2841 ERIAR_EXGMAC);
2842 rtl_writephy(tp, 0x1f, 0x0005);
2843 rtl_writephy(tp, 0x05, 0x8b85);
2844 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2845 rtl_writephy(tp, 0x1f, 0x0004);
2846 rtl_writephy(tp, 0x1f, 0x0007);
2847 rtl_writephy(tp, 0x1e, 0x0020);
2848 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
2849 rtl_writephy(tp, 0x1f, 0x0002);
2850 rtl_writephy(tp, 0x1f, 0x0000);
2851 rtl_writephy(tp, 0x0d, 0x0007);
2852 rtl_writephy(tp, 0x0e, 0x003c);
2853 rtl_writephy(tp, 0x0d, 0x4007);
2854 rtl_writephy(tp, 0x0e, 0x0000);
2855 rtl_writephy(tp, 0x0d, 0x0000);
2856
2857 /* Green feature */
2858 rtl_writephy(tp, 0x1f, 0x0003);
2859 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
2860 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
2861 rtl_writephy(tp, 0x1f, 0x0000);
2862}
2863
4da19633 2864static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 2865{
350f7596 2866 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 2867 { 0x1f, 0x0003 },
2868 { 0x08, 0x441d },
2869 { 0x01, 0x9100 },
2870 { 0x1f, 0x0000 }
2871 };
2872
4da19633 2873 rtl_writephy(tp, 0x1f, 0x0000);
2874 rtl_patchphy(tp, 0x11, 1 << 12);
2875 rtl_patchphy(tp, 0x19, 1 << 13);
2876 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 2877
4da19633 2878 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 2879}
2880
5a5e4443
HW		 2881static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2882{
2883 static const struct phy_reg phy_reg_init[] = {
2884 { 0x1f, 0x0005 },
2885 { 0x1a, 0x0000 },
2886 { 0x1f, 0x0000 },
2887
2888 { 0x1f, 0x0004 },
2889 { 0x1c, 0x0000 },
2890 { 0x1f, 0x0000 },
2891
2892 { 0x1f, 0x0001 },
2893 { 0x15, 0x7701 },
2894 { 0x1f, 0x0000 }
2895 };
2896
2897 /* Disable ALDPS before ram code */
2898 rtl_writephy(tp, 0x1f, 0x0000);
2899 rtl_writephy(tp, 0x18, 0x0310);
2900 msleep(100);
2901
953a12cc 2902 rtl_apply_firmware(tp);
5a5e4443
HW		 2903
2904 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2905}
2906
5615d9f1
FR		 2907static void rtl_hw_phy_config(struct net_device *dev)
2908{
2909 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 2910
2911 rtl8169_print_mac_version(tp);
2912
2913 switch (tp->mac_version) {
2914 case RTL_GIGA_MAC_VER_01:
2915 break;
2916 case RTL_GIGA_MAC_VER_02:
2917 case RTL_GIGA_MAC_VER_03:
4da19633 2918 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 2919 break;
2920 case RTL_GIGA_MAC_VER_04:
4da19633 2921 rtl8169sb_hw_phy_config(tp);
5615d9f1 2922 break;
2e955856 2923 case RTL_GIGA_MAC_VER_05:
4da19633 2924 rtl8169scd_hw_phy_config(tp);
2e955856 2925 break;
8c7006aa 2926 case RTL_GIGA_MAC_VER_06:
4da19633 2927 rtl8169sce_hw_phy_config(tp);
8c7006aa 2928 break;
2857ffb7
FR		 2929 case RTL_GIGA_MAC_VER_07:
2930 case RTL_GIGA_MAC_VER_08:
2931 case RTL_GIGA_MAC_VER_09:
4da19633 2932 rtl8102e_hw_phy_config(tp);
2857ffb7 2933 break;
236b8082 2934 case RTL_GIGA_MAC_VER_11:
4da19633 2935 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 2936 break;
2937 case RTL_GIGA_MAC_VER_12:
4da19633 2938 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 2939 break;
2940 case RTL_GIGA_MAC_VER_17:
4da19633 2941 rtl8168bef_hw_phy_config(tp);
236b8082 2942 break;
867763c1 2943 case RTL_GIGA_MAC_VER_18:
4da19633 2944 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 2945 break;
2946 case RTL_GIGA_MAC_VER_19:
4da19633 2947 rtl8168c_1_hw_phy_config(tp);
867763c1 2948 break;
7da97ec9 2949 case RTL_GIGA_MAC_VER_20:
4da19633 2950 rtl8168c_2_hw_phy_config(tp);
7da97ec9 2951 break;
197ff761 2952 case RTL_GIGA_MAC_VER_21:
4da19633 2953 rtl8168c_3_hw_phy_config(tp);
197ff761 2954 break;
6fb07058 2955 case RTL_GIGA_MAC_VER_22:
4da19633 2956 rtl8168c_4_hw_phy_config(tp);
6fb07058 2957 break;
ef3386f0 2958 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 2959 case RTL_GIGA_MAC_VER_24:
4da19633 2960 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 2961 break;
5b538df9 2962 case RTL_GIGA_MAC_VER_25:
bca03d5f 2963 rtl8168d_1_hw_phy_config(tp);
daf9df6d 2964 break;
2965 case RTL_GIGA_MAC_VER_26:
bca03d5f 2966 rtl8168d_2_hw_phy_config(tp);
daf9df6d 2967 break;
2968 case RTL_GIGA_MAC_VER_27:
4da19633 2969 rtl8168d_3_hw_phy_config(tp);
5b538df9 2970 break;
e6de30d6 2971 case RTL_GIGA_MAC_VER_28:
2972 rtl8168d_4_hw_phy_config(tp);
2973 break;
5a5e4443
HW		 2974 case RTL_GIGA_MAC_VER_29:
2975 case RTL_GIGA_MAC_VER_30:
2976 rtl8105e_hw_phy_config(tp);
2977 break;
cecb5fd7
FR		 2978 case RTL_GIGA_MAC_VER_31:
2979 /* None. */
2980 break;
01dc7fec 2981 case RTL_GIGA_MAC_VER_32:
01dc7fec 2982 case RTL_GIGA_MAC_VER_33:
70090424
HW		 2983 rtl8168e_1_hw_phy_config(tp);
2984 break;
2985 case RTL_GIGA_MAC_VER_34:
2986 rtl8168e_2_hw_phy_config(tp);
01dc7fec 2987 break;
ef3386f0 2988
5615d9f1
FR		 2989 default:
2990 break;
2991 }
2992}
2993
1da177e4
LT		 2994static void rtl8169_phy_timer(unsigned long __opaque)
2995{
2996 struct net_device *dev = (struct net_device *)__opaque;
2997 struct rtl8169_private *tp = netdev_priv(dev);
2998 struct timer_list *timer = &tp->timer;
2999 void __iomem *ioaddr = tp->mmio_addr;
3000 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3001
bcf0bf90 3002 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 3003
1da177e4
LT		 3004 spin_lock_irq(&tp->lock);
3005
4da19633 3006 if (tp->phy_reset_pending(tp)) {
5b0384f4 3007 /*
1da177e4
LT		 3008 * A busy loop could burn quite a few cycles on nowadays CPU.
3009 * Let's delay the execution of the timer for a few ticks.
3010 */
3011 timeout = HZ/10;
3012 goto out_mod_timer;
3013 }
3014
3015 if (tp->link_ok(ioaddr))
3016 goto out_unlock;
3017
bf82c189 3018 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4 3019
4da19633 3020 tp->phy_reset_enable(tp);
1da177e4
LT		 3021
3022out_mod_timer:
3023 mod_timer(timer, jiffies + timeout);
3024out_unlock:
3025 spin_unlock_irq(&tp->lock);
3026}
3027
1da177e4
LT		 3028#ifdef CONFIG_NET_POLL_CONTROLLER
3029/*
3030 * Polling 'interrupt' - used by things like netconsole to send skbs
3031 * without having to re-enable interrupts. It's not called while
3032 * the interrupt routine is executing.
3033 */
3034static void rtl8169_netpoll(struct net_device *dev)
3035{
3036 struct rtl8169_private *tp = netdev_priv(dev);
3037 struct pci_dev *pdev = tp->pci_dev;
3038
3039 disable_irq(pdev->irq);
7d12e780 3040 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 3041 enable_irq(pdev->irq);
3042}
3043#endif
3044
3045static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3046 void __iomem *ioaddr)
3047{
3048 iounmap(ioaddr);
3049 pci_release_regions(pdev);
87aeec76 3050 pci_clear_mwi(pdev);
1da177e4
LT		 3051 pci_disable_device(pdev);
3052 free_netdev(dev);
3053}
3054
bf793295
FR		 3055static void rtl8169_phy_reset(struct net_device *dev,
3056 struct rtl8169_private *tp)
3057{
07d3f51f 3058 unsigned int i;
bf793295 3059
4da19633 3060 tp->phy_reset_enable(tp);
bf793295 3061 for (i = 0; i < 100; i++) {
4da19633 3062 if (!tp->phy_reset_pending(tp))
bf793295
FR		 3063 return;
3064 msleep(1);
3065 }
bf82c189 3066 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 3067}
3068
4ff96fa6
FR		 3069static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3070{
3071 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 3072
5615d9f1 3073 rtl_hw_phy_config(dev);
4ff96fa6 3074
77332894
MS		 3075 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3076 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3077 RTL_W8(0x82, 0x01);
3078 }
4ff96fa6 3079
6dccd16b
FR		 3080 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3081
3082 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3083 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 3084
bcf0bf90 3085 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 3086 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3087 RTL_W8(0x82, 0x01);
3088 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 3089 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 3090 }
3091
bf793295
FR		 3092 rtl8169_phy_reset(dev, tp);
3093
54405cde 3094 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 3095 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3096 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3097 (tp->mii.supports_gmii ?
3098 ADVERTISED_1000baseT_Half |
3099 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 3100
bf82c189
JP		 3101 if (RTL_R8(PHYstatus) & TBI_Enable)
3102 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 3103}
3104
773d2021
FR		 3105static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3106{
3107 void __iomem *ioaddr = tp->mmio_addr;
3108 u32 high;
3109 u32 low;
3110
3111 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3112 high = addr[4] | (addr[5] << 8);
3113
3114 spin_lock_irq(&tp->lock);
3115
3116 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 3117
773d2021 3118 RTL_W32(MAC4, high);
908ba2bf 3119 RTL_R32(MAC4);
3120
78f1cd02 3121 RTL_W32(MAC0, low);
908ba2bf 3122 RTL_R32(MAC0);
3123
773d2021
FR		 3124 RTL_W8(Cfg9346, Cfg9346_Lock);
3125
3126 spin_unlock_irq(&tp->lock);
3127}
3128
3129static int rtl_set_mac_address(struct net_device *dev, void *p)
3130{
3131 struct rtl8169_private *tp = netdev_priv(dev);
3132 struct sockaddr *addr = p;
3133
3134 if (!is_valid_ether_addr(addr->sa_data))
3135 return -EADDRNOTAVAIL;
3136
3137 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3138
3139 rtl_rar_set(tp, dev->dev_addr);
3140
3141 return 0;
3142}
3143
5f787a1a
FR		 3144static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3145{
3146 struct rtl8169_private *tp = netdev_priv(dev);
3147 struct mii_ioctl_data *data = if_mii(ifr);
3148
8b4ab28d
FR		 3149 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3150}
5f787a1a 3151
cecb5fd7
FR		 3152static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3153 struct mii_ioctl_data *data, int cmd)
8b4ab28d 3154{
5f787a1a
FR		 3155 switch (cmd) {
3156 case SIOCGMIIPHY:
3157 data->phy_id = 32; /* Internal PHY */
3158 return 0;
3159
3160 case SIOCGMIIREG:
4da19633 3161 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 3162 return 0;
3163
3164 case SIOCSMIIREG:
4da19633 3165 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 3166 return 0;
3167 }
3168 return -EOPNOTSUPP;
3169}
3170
8b4ab28d
FR		 3171static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3172{
3173 return -EOPNOTSUPP;
3174}
3175
0e485150
FR		 3176static const struct rtl_cfg_info {
3177 void (*hw_start)(struct net_device *);
3178 unsigned int region;
3179 unsigned int align;
3180 u16 intr_event;
3181 u16 napi_event;
ccdffb9a 3182 unsigned features;
f21b75e9 3183 u8 default_ver;
0e485150
FR		 3184} rtl_cfg_infos [] = {
3185 [RTL_CFG_0] = {
3186 .hw_start = rtl_hw_start_8169,
3187 .region = 1,
e9f63f30 3188 .align = 0,
0e485150
FR		 3189 .intr_event = SYSErr | LinkChg | RxOverflow |
3190 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 3191 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 3192 .features = RTL_FEATURE_GMII,
3193 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 3194 },
3195 [RTL_CFG_1] = {
3196 .hw_start = rtl_hw_start_8168,
3197 .region = 2,
3198 .align = 8,
53f57357 3199 .intr_event = SYSErr | LinkChg | RxOverflow |
0e485150 3200 TxErr | TxOK | RxOK | RxErr,
fbac58fc 3201 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 3202 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3203 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 3204 },
3205 [RTL_CFG_2] = {
3206 .hw_start = rtl_hw_start_8101,
3207 .region = 2,
3208 .align = 8,
3209 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
3210 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 3211 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 3212 .features = RTL_FEATURE_MSI,
3213 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 3214 }
3215};
3216
fbac58fc
FR		 3217/* Cfg9346_Unlock assumed. */
3218static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
3219 const struct rtl_cfg_info *cfg)
3220{
3221 unsigned msi = 0;
3222 u8 cfg2;
3223
3224 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 3225 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 3226 if (pci_enable_msi(pdev)) {
3227 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
3228 } else {
3229 cfg2 |= MSIEnable;
3230 msi = RTL_FEATURE_MSI;
3231 }
3232 }
3233 RTL_W8(Config2, cfg2);
3234 return msi;
3235}
3236
3237static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3238{
3239 if (tp->features & RTL_FEATURE_MSI) {
3240 pci_disable_msi(pdev);
3241 tp->features &= ~RTL_FEATURE_MSI;
3242 }
3243}
3244
8b4ab28d
FR		 3245static const struct net_device_ops rtl8169_netdev_ops = {
3246 .ndo_open = rtl8169_open,
3247 .ndo_stop = rtl8169_close,
3248 .ndo_get_stats = rtl8169_get_stats,
00829823 3249 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 3250 .ndo_tx_timeout = rtl8169_tx_timeout,
3251 .ndo_validate_addr = eth_validate_addr,
3252 .ndo_change_mtu = rtl8169_change_mtu,
350fb32a
MM		 3253 .ndo_fix_features = rtl8169_fix_features,
3254 .ndo_set_features = rtl8169_set_features,
8b4ab28d
FR		 3255 .ndo_set_mac_address = rtl_set_mac_address,
3256 .ndo_do_ioctl = rtl8169_ioctl,
3257 .ndo_set_multicast_list = rtl_set_rx_mode,
8b4ab28d
FR		 3258#ifdef CONFIG_NET_POLL_CONTROLLER
3259 .ndo_poll_controller = rtl8169_netpoll,
3260#endif
3261
3262};
3263
c0e45c1c 3264static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3265{
3266 struct mdio_ops *ops = &tp->mdio_ops;
3267
3268 switch (tp->mac_version) {
3269 case RTL_GIGA_MAC_VER_27:
3270 ops->write = r8168dp_1_mdio_write;
3271 ops->read = r8168dp_1_mdio_read;
3272 break;
e6de30d6 3273 case RTL_GIGA_MAC_VER_28:
4804b3b3 3274 case RTL_GIGA_MAC_VER_31:
e6de30d6 3275 ops->write = r8168dp_2_mdio_write;
3276 ops->read = r8168dp_2_mdio_read;
3277 break;
c0e45c1c 3278 default:
3279 ops->write = r8169_mdio_write;
3280 ops->read = r8169_mdio_read;
3281 break;
3282 }
3283}
3284
065c27c1 3285static void r810x_phy_power_down(struct rtl8169_private *tp)
3286{
3287 rtl_writephy(tp, 0x1f, 0x0000);
3288 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3289}
3290
3291static void r810x_phy_power_up(struct rtl8169_private *tp)
3292{
3293 rtl_writephy(tp, 0x1f, 0x0000);
3294 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3295}
3296
3297static void r810x_pll_power_down(struct rtl8169_private *tp)
3298{
3299 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3300 rtl_writephy(tp, 0x1f, 0x0000);
3301 rtl_writephy(tp, MII_BMCR, 0x0000);
3302 return;
3303 }
3304
3305 r810x_phy_power_down(tp);
3306}
3307
3308static void r810x_pll_power_up(struct rtl8169_private *tp)
3309{
3310 r810x_phy_power_up(tp);
3311}
3312
3313static void r8168_phy_power_up(struct rtl8169_private *tp)
3314{
3315 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3316 switch (tp->mac_version) {
3317 case RTL_GIGA_MAC_VER_11:
3318 case RTL_GIGA_MAC_VER_12:
3319 case RTL_GIGA_MAC_VER_17:
3320 case RTL_GIGA_MAC_VER_18:
3321 case RTL_GIGA_MAC_VER_19:
3322 case RTL_GIGA_MAC_VER_20:
3323 case RTL_GIGA_MAC_VER_21:
3324 case RTL_GIGA_MAC_VER_22:
3325 case RTL_GIGA_MAC_VER_23:
3326 case RTL_GIGA_MAC_VER_24:
3327 case RTL_GIGA_MAC_VER_25:
3328 case RTL_GIGA_MAC_VER_26:
3329 case RTL_GIGA_MAC_VER_27:
3330 case RTL_GIGA_MAC_VER_28:
3331 case RTL_GIGA_MAC_VER_31:
3332 rtl_writephy(tp, 0x0e, 0x0000);
3333 break;
3334 default:
3335 break;
3336 }
065c27c1 3337 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3338}
3339
3340static void r8168_phy_power_down(struct rtl8169_private *tp)
3341{
3342 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3343 switch (tp->mac_version) {
3344 case RTL_GIGA_MAC_VER_32:
3345 case RTL_GIGA_MAC_VER_33:
3346 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3347 break;
3348
3349 case RTL_GIGA_MAC_VER_11:
3350 case RTL_GIGA_MAC_VER_12:
3351 case RTL_GIGA_MAC_VER_17:
3352 case RTL_GIGA_MAC_VER_18:
3353 case RTL_GIGA_MAC_VER_19:
3354 case RTL_GIGA_MAC_VER_20:
3355 case RTL_GIGA_MAC_VER_21:
3356 case RTL_GIGA_MAC_VER_22:
3357 case RTL_GIGA_MAC_VER_23:
3358 case RTL_GIGA_MAC_VER_24:
3359 case RTL_GIGA_MAC_VER_25:
3360 case RTL_GIGA_MAC_VER_26:
3361 case RTL_GIGA_MAC_VER_27:
3362 case RTL_GIGA_MAC_VER_28:
3363 case RTL_GIGA_MAC_VER_31:
3364 rtl_writephy(tp, 0x0e, 0x0200);
3365 default:
3366 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3367 break;
3368 }
065c27c1 3369}
3370
3371static void r8168_pll_power_down(struct rtl8169_private *tp)
3372{
3373 void __iomem *ioaddr = tp->mmio_addr;
3374
cecb5fd7
FR		 3375 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3376 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3377 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3378 r8168dp_check_dash(tp)) {
065c27c1 3379 return;
5d2e1957 3380 }
065c27c1 3381
cecb5fd7
FR		 3382 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3383 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 3384 (RTL_R16(CPlusCmd) & ASF)) {
3385 return;
3386 }
3387
01dc7fec 3388 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3389 tp->mac_version == RTL_GIGA_MAC_VER_33)
3390 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3391
065c27c1 3392 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3393 rtl_writephy(tp, 0x1f, 0x0000);
3394 rtl_writephy(tp, MII_BMCR, 0x0000);
3395
d4ed95d7
HW		 3396 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3397 tp->mac_version == RTL_GIGA_MAC_VER_33)
3398 RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast |
3399 AcceptMulticast | AcceptMyPhys);
065c27c1 3400 return;
3401 }
3402
3403 r8168_phy_power_down(tp);
3404
3405 switch (tp->mac_version) {
3406 case RTL_GIGA_MAC_VER_25:
3407 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3408 case RTL_GIGA_MAC_VER_27:
3409 case RTL_GIGA_MAC_VER_28:
4804b3b3 3410 case RTL_GIGA_MAC_VER_31:
01dc7fec 3411 case RTL_GIGA_MAC_VER_32:
3412 case RTL_GIGA_MAC_VER_33:
065c27c1 3413 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3414 break;
3415 }
3416}
3417
3418static void r8168_pll_power_up(struct rtl8169_private *tp)
3419{
3420 void __iomem *ioaddr = tp->mmio_addr;
3421
cecb5fd7
FR		 3422 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3423 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3424 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3425 r8168dp_check_dash(tp)) {
065c27c1 3426 return;
5d2e1957 3427 }
065c27c1 3428
3429 switch (tp->mac_version) {
3430 case RTL_GIGA_MAC_VER_25:
3431 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3432 case RTL_GIGA_MAC_VER_27:
3433 case RTL_GIGA_MAC_VER_28:
4804b3b3 3434 case RTL_GIGA_MAC_VER_31:
01dc7fec 3435 case RTL_GIGA_MAC_VER_32:
3436 case RTL_GIGA_MAC_VER_33:
065c27c1 3437 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3438 break;
3439 }
3440
3441 r8168_phy_power_up(tp);
3442}
3443
3444static void rtl_pll_power_op(struct rtl8169_private *tp,
3445 void (*op)(struct rtl8169_private *))
3446{
3447 if (op)
3448 op(tp);
3449}
3450
3451static void rtl_pll_power_down(struct rtl8169_private *tp)
3452{
3453 rtl_pll_power_op(tp, tp->pll_power_ops.down);
3454}
3455
3456static void rtl_pll_power_up(struct rtl8169_private *tp)
3457{
3458 rtl_pll_power_op(tp, tp->pll_power_ops.up);
3459}
3460
3461static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3462{
3463 struct pll_power_ops *ops = &tp->pll_power_ops;
3464
3465 switch (tp->mac_version) {
3466 case RTL_GIGA_MAC_VER_07:
3467 case RTL_GIGA_MAC_VER_08:
3468 case RTL_GIGA_MAC_VER_09:
3469 case RTL_GIGA_MAC_VER_10:
3470 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 3471 case RTL_GIGA_MAC_VER_29:
3472 case RTL_GIGA_MAC_VER_30:
065c27c1 3473 ops->down = r810x_pll_power_down;
3474 ops->up = r810x_pll_power_up;
3475 break;
3476
3477 case RTL_GIGA_MAC_VER_11:
3478 case RTL_GIGA_MAC_VER_12:
3479 case RTL_GIGA_MAC_VER_17:
3480 case RTL_GIGA_MAC_VER_18:
3481 case RTL_GIGA_MAC_VER_19:
3482 case RTL_GIGA_MAC_VER_20:
3483 case RTL_GIGA_MAC_VER_21:
3484 case RTL_GIGA_MAC_VER_22:
3485 case RTL_GIGA_MAC_VER_23:
3486 case RTL_GIGA_MAC_VER_24:
3487 case RTL_GIGA_MAC_VER_25:
3488 case RTL_GIGA_MAC_VER_26:
3489 case RTL_GIGA_MAC_VER_27:
e6de30d6 3490 case RTL_GIGA_MAC_VER_28:
4804b3b3 3491 case RTL_GIGA_MAC_VER_31:
01dc7fec 3492 case RTL_GIGA_MAC_VER_32:
3493 case RTL_GIGA_MAC_VER_33:
70090424 3494 case RTL_GIGA_MAC_VER_34:
065c27c1 3495 ops->down = r8168_pll_power_down;
3496 ops->up = r8168_pll_power_up;
3497 break;
3498
3499 default:
3500 ops->down = NULL;
3501 ops->up = NULL;
3502 break;
3503 }
3504}
3505
92fc43b4
HW		 3506static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3507{
3508 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3509}
3510
6f43adc8
FR		 3511static void rtl_hw_reset(struct rtl8169_private *tp)
3512{
3513 void __iomem *ioaddr = tp->mmio_addr;
3514 int i;
3515
3516 /* Soft reset the chip. */
3517 RTL_W8(ChipCmd, CmdReset);
3518
3519 /* Check that the chip has finished the reset. */
3520 for (i = 0; i < 100; i++) {
3521 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3522 break;
92fc43b4 3523 udelay(100);
6f43adc8 3524 }
92fc43b4
HW		 3525
3526 rtl8169_init_ring_indexes(tp);
6f43adc8
FR		 3527}
3528
1da177e4 3529static int __devinit
4ff96fa6 3530rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 3531{
0e485150
FR		 3532 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3533 const unsigned int region = cfg->region;
1da177e4 3534 struct rtl8169_private *tp;
ccdffb9a 3535 struct mii_if_info *mii;
4ff96fa6
FR		 3536 struct net_device *dev;
3537 void __iomem *ioaddr;
2b7b4318 3538 int chipset, i;
07d3f51f 3539 int rc;
1da177e4 3540
4ff96fa6
FR		 3541 if (netif_msg_drv(&debug)) {
3542 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3543 MODULENAME, RTL8169_VERSION);
3544 }
1da177e4 3545
1da177e4 3546 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 3547 if (!dev) {
b57b7e5a 3548 if (netif_msg_drv(&debug))
9b91cf9d 3549 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 3550 rc = -ENOMEM;
3551 goto out;
1da177e4
LT		 3552 }
3553
1da177e4 3554 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 3555 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 3556 tp = netdev_priv(dev);
c4028958 3557 tp->dev = dev;
21e197f2 3558 tp->pci_dev = pdev;
b57b7e5a 3559 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 3560
ccdffb9a
FR		 3561 mii = &tp->mii;
3562 mii->dev = dev;
3563 mii->mdio_read = rtl_mdio_read;
3564 mii->mdio_write = rtl_mdio_write;
3565 mii->phy_id_mask = 0x1f;
3566 mii->reg_num_mask = 0x1f;
3567 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3568
ba04c7c9
SG		 3569 /* disable ASPM completely as that cause random device stop working
3570 * problems as well as full system hangs for some PCIe devices users */
3571 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3572 PCIE_LINK_STATE_CLKPM);
3573
1da177e4
LT		 3574 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3575 rc = pci_enable_device(pdev);
b57b7e5a 3576 if (rc < 0) {
bf82c189 3577 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 3578 goto err_out_free_dev_1;
1da177e4
LT		 3579 }
3580
87aeec76 3581 if (pci_set_mwi(pdev) < 0)
3582 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 3583
1da177e4 3584 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 3585 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 3586 netif_err(tp, probe, dev,
3587 "region #%d not an MMIO resource, aborting\n",
3588 region);
1da177e4 3589 rc = -ENODEV;
87aeec76 3590 goto err_out_mwi_2;
1da177e4 3591 }
4ff96fa6 3592
1da177e4 3593 /* check for weird/broken PCI region reporting */
bcf0bf90 3594 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 3595 netif_err(tp, probe, dev,
3596 "Invalid PCI region size(s), aborting\n");
1da177e4 3597 rc = -ENODEV;
87aeec76 3598 goto err_out_mwi_2;
1da177e4
LT		 3599 }
3600
3601 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 3602 if (rc < 0) {
bf82c189 3603 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 3604 goto err_out_mwi_2;
1da177e4
LT		 3605 }
3606
d24e9aaf 3607 tp->cp_cmd = RxChkSum;
1da177e4
LT		 3608
3609 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 3610 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 3611 tp->cp_cmd |= PCIDAC;
3612 dev->features |= NETIF_F_HIGHDMA;
3613 } else {
284901a9 3614 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 3615 if (rc < 0) {
bf82c189 3616 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 3617 goto err_out_free_res_3;
1da177e4
LT		 3618 }
3619 }
3620
1da177e4 3621 /* ioremap MMIO region */
bcf0bf90 3622 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 3623 if (!ioaddr) {
bf82c189 3624 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 3625 rc = -EIO;
87aeec76 3626 goto err_out_free_res_3;
1da177e4 3627 }
6f43adc8 3628 tp->mmio_addr = ioaddr;
1da177e4 3629
e44daade
JM		 3630 if (!pci_is_pcie(pdev))
3631 netif_info(tp, probe, dev, "not PCI Express\n");
4300e8c7 3632
d78ad8cb 3633 RTL_W16(IntrMask, 0x0000);
1da177e4 3634
6f43adc8 3635 rtl_hw_reset(tp);
1da177e4 3636
d78ad8cb
KW		 3637 RTL_W16(IntrStatus, 0xffff);
3638
ca52efd5 3639 pci_set_master(pdev);
3640
1da177e4 3641 /* Identify chip attached to board */
5d320a20 3642 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
1da177e4 3643
7a8fc77b
FR		 3644 /*
3645 * Pretend we are using VLANs; This bypasses a nasty bug where
3646 * Interrupts stop flowing on high load on 8110SCd controllers.
3647 */
3648 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3649 tp->cp_cmd |= RxVlan;
3650
c0e45c1c 3651 rtl_init_mdio_ops(tp);
065c27c1 3652 rtl_init_pll_power_ops(tp);
c0e45c1c 3653
1da177e4 3654 rtl8169_print_mac_version(tp);
1da177e4 3655
85bffe6c
FR		 3656 chipset = tp->mac_version;
3657 tp->txd_version = rtl_chip_infos[chipset].txd_version;
1da177e4 3658
5d06a99f
FR		 3659 RTL_W8(Cfg9346, Cfg9346_Unlock);
3660 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3661 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 3662 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3663 tp->features |= RTL_FEATURE_WOL;
3664 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3665 tp->features |= RTL_FEATURE_WOL;
fbac58fc 3666 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 3667 RTL_W8(Cfg9346, Cfg9346_Lock);
3668
66ec5d4f
FR		 3669 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3670 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 3671 tp->set_speed = rtl8169_set_speed_tbi;
3672 tp->get_settings = rtl8169_gset_tbi;
3673 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3674 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3675 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 3676 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4
LT		 3677 } else {
3678 tp->set_speed = rtl8169_set_speed_xmii;
3679 tp->get_settings = rtl8169_gset_xmii;
3680 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3681 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3682 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 3683 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 3684 }
3685
df58ef51
FR		 3686 spin_lock_init(&tp->lock);
3687
7bf6bf48 3688 /* Get MAC address */
1da177e4
LT		 3689 for (i = 0; i < MAC_ADDR_LEN; i++)
3690 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 3691 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 3692
1da177e4 3693 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 3694 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3695 dev->irq = pdev->irq;
3696 dev->base_addr = (unsigned long) ioaddr;
1da177e4 3697
bea3348e 3698 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4 3699
350fb32a
MM		 3700 /* don't enable SG, IP_CSUM and TSO by default - it might not work
3701 * properly for all devices */
3702 dev->features |= NETIF_F_RXCSUM |
3703 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3704
3705 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3706 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3707 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3708 NETIF_F_HIGHDMA;
3709
3710 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3711 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3712 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
1da177e4
LT		 3713
3714 tp->intr_mask = 0xffff;
0e485150
FR		 3715 tp->hw_start = cfg->hw_start;
3716 tp->intr_event = cfg->intr_event;
3717 tp->napi_event = cfg->napi_event;
1da177e4 3718
2efa53f3
FR		 3719 init_timer(&tp->timer);
3720 tp->timer.data = (unsigned long) dev;
3721 tp->timer.function = rtl8169_phy_timer;
3722
b6ffd97f 3723 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
953a12cc 3724
1da177e4 3725 rc = register_netdev(dev);
4ff96fa6 3726 if (rc < 0)
87aeec76 3727 goto err_out_msi_4;
1da177e4
LT		 3728
3729 pci_set_drvdata(pdev, dev);
3730
bf82c189 3731 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
85bffe6c 3732 rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
bf82c189 3733 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
1da177e4 3734
cecb5fd7
FR		 3735 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3736 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3737 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 3738 rtl8168_driver_start(tp);
e6de30d6 3739 }
b646d900 3740
8b76ab39 3741 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 3742
f3ec4f87
AS		 3743 if (pci_dev_run_wake(pdev))
3744 pm_runtime_put_noidle(&pdev->dev);
e1759441 3745
0d672e9f
IV		 3746 netif_carrier_off(dev);
3747
4ff96fa6
FR		 3748out:
3749 return rc;
1da177e4 3750
87aeec76 3751err_out_msi_4:
fbac58fc 3752 rtl_disable_msi(pdev, tp);
4ff96fa6 3753 iounmap(ioaddr);
87aeec76 3754err_out_free_res_3:
4ff96fa6 3755 pci_release_regions(pdev);
87aeec76 3756err_out_mwi_2:
4ff96fa6 3757 pci_clear_mwi(pdev);
4ff96fa6
FR		 3758 pci_disable_device(pdev);
3759err_out_free_dev_1:
3760 free_netdev(dev);
3761 goto out;
1da177e4
LT		 3762}
3763
07d3f51f 3764static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3765{
3766 struct net_device *dev = pci_get_drvdata(pdev);
3767 struct rtl8169_private *tp = netdev_priv(dev);
3768
cecb5fd7
FR		 3769 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3770 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3771 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 3772 rtl8168_driver_stop(tp);
e6de30d6 3773 }
b646d900 3774
23f333a2 3775 cancel_delayed_work_sync(&tp->task);
eb2a021c 3776
1da177e4 3777 unregister_netdev(dev);
cc098dc7 3778
953a12cc
FR		 3779 rtl_release_firmware(tp);
3780
f3ec4f87
AS		 3781 if (pci_dev_run_wake(pdev))
3782 pm_runtime_get_noresume(&pdev->dev);
e1759441 3783
cc098dc7
IV		 3784 /* restore original MAC address */
3785 rtl_rar_set(tp, dev->perm_addr);
3786
fbac58fc 3787 rtl_disable_msi(pdev, tp);
1da177e4
LT		 3788 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3789 pci_set_drvdata(pdev, NULL);
3790}
3791
b6ffd97f 3792static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 3793{
b6ffd97f
FR		 3794 struct rtl_fw *rtl_fw;
3795 const char *name;
3796 int rc = -ENOMEM;
953a12cc 3797
b6ffd97f
FR		 3798 name = rtl_lookup_firmware_name(tp);
3799 if (!name)
3800 goto out_no_firmware;
953a12cc 3801
b6ffd97f
FR		 3802 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3803 if (!rtl_fw)
3804 goto err_warn;
31bd204f 3805
b6ffd97f
FR		 3806 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3807 if (rc < 0)
3808 goto err_free;
3809
fd112f2e
FR		 3810 rc = rtl_check_firmware(tp, rtl_fw);
3811 if (rc < 0)
3812 goto err_release_firmware;
3813
b6ffd97f
FR		 3814 tp->rtl_fw = rtl_fw;
3815out:
3816 return;
3817
fd112f2e
FR		 3818err_release_firmware:
3819 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 3820err_free:
3821 kfree(rtl_fw);
3822err_warn:
3823 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3824 name, rc);
3825out_no_firmware:
3826 tp->rtl_fw = NULL;
3827 goto out;
3828}
3829
3830static void rtl_request_firmware(struct rtl8169_private *tp)
3831{
3832 if (IS_ERR(tp->rtl_fw))
3833 rtl_request_uncached_firmware(tp);
953a12cc
FR		 3834}
3835
1da177e4
LT		 3836static int rtl8169_open(struct net_device *dev)
3837{
3838 struct rtl8169_private *tp = netdev_priv(dev);
eee3a96c 3839 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 3840 struct pci_dev *pdev = tp->pci_dev;
99f252b0 3841 int retval = -ENOMEM;
1da177e4 3842
e1759441 3843 pm_runtime_get_sync(&pdev->dev);
1da177e4 3844
1da177e4
LT		 3845 /*
3846 * Rx and Tx desscriptors needs 256 bytes alignment.
82553bb6 3847 * dma_alloc_coherent provides more.
1da177e4 3848 */
82553bb6
SG		 3849 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3850 &tp->TxPhyAddr, GFP_KERNEL);
1da177e4 3851 if (!tp->TxDescArray)
e1759441 3852 goto err_pm_runtime_put;
1da177e4 3853
82553bb6
SG		 3854 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3855 &tp->RxPhyAddr, GFP_KERNEL);
1da177e4 3856 if (!tp->RxDescArray)
99f252b0 3857 goto err_free_tx_0;
1da177e4
LT		 3858
3859 retval = rtl8169_init_ring(dev);
3860 if (retval < 0)
99f252b0 3861 goto err_free_rx_1;
1da177e4 3862
c4028958 3863 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 3864
99f252b0
FR		 3865 smp_mb();
3866
953a12cc
FR		 3867 rtl_request_firmware(tp);
3868
fbac58fc
FR		 3869 retval = request_irq(dev->irq, rtl8169_interrupt,
3870 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 3871 dev->name, dev);
3872 if (retval < 0)
953a12cc 3873 goto err_release_fw_2;
99f252b0 3874
bea3348e 3875 napi_enable(&tp->napi);
bea3348e 3876
eee3a96c 3877 rtl8169_init_phy(dev, tp);
3878
350fb32a 3879 rtl8169_set_features(dev, dev->features);
eee3a96c 3880
065c27c1 3881 rtl_pll_power_up(tp);
3882
07ce4064 3883 rtl_hw_start(dev);
1da177e4 3884
e1759441
RW		 3885 tp->saved_wolopts = 0;
3886 pm_runtime_put_noidle(&pdev->dev);
3887
eee3a96c 3888 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4
LT		 3889out:
3890 return retval;
3891
953a12cc
FR		 3892err_release_fw_2:
3893 rtl_release_firmware(tp);
99f252b0
FR		 3894 rtl8169_rx_clear(tp);
3895err_free_rx_1:
82553bb6
SG		 3896 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3897 tp->RxPhyAddr);
e1759441 3898 tp->RxDescArray = NULL;
99f252b0 3899err_free_tx_0:
82553bb6
SG		 3900 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3901 tp->TxPhyAddr);
e1759441
RW		 3902 tp->TxDescArray = NULL;
3903err_pm_runtime_put:
3904 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 3905 goto out;
3906}
3907
92fc43b4
HW		 3908static void rtl_rx_close(struct rtl8169_private *tp)
3909{
3910 void __iomem *ioaddr = tp->mmio_addr;
3911 u32 rxcfg = RTL_R32(RxConfig);
3912
3913 rxcfg &= ~(AcceptErr | AcceptRunt | AcceptBroadcast | AcceptMulticast |
3914 AcceptMyPhys | AcceptAllPhys);
3915 RTL_W32(RxConfig, rxcfg);
3916}
3917
e6de30d6 3918static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 3919{
e6de30d6 3920 void __iomem *ioaddr = tp->mmio_addr;
3921
1da177e4
LT		 3922 /* Disable interrupts */
3923 rtl8169_irq_mask_and_ack(ioaddr);
3924
92fc43b4
HW		 3925 rtl_rx_close(tp);
3926
5d2e1957 3927 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 3928 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3929 tp->mac_version == RTL_GIGA_MAC_VER_31) {
e6de30d6 3930 while (RTL_R8(TxPoll) & NPQ)
3931 udelay(20);
70090424
HW		 3932 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3933 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
3934 udelay(100);
92fc43b4
HW		 3935 } else {
3936 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
3937 udelay(100);
e6de30d6 3938 }
3939
92fc43b4 3940 rtl_hw_reset(tp);
1da177e4
LT		 3941}
3942
7f796d83 3943static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 3944{
3945 void __iomem *ioaddr = tp->mmio_addr;
3946 u32 cfg = rtl8169_rx_config;
3947
2b7b4318 3948 cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
9cb427b6
FR		 3949 RTL_W32(RxConfig, cfg);
3950
3951 /* Set DMA burst size and Interframe Gap Time */
3952 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3953 (InterFrameGap << TxInterFrameGapShift));
3954}
3955
07ce4064 3956static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 3957{
3958 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 3959
07ce4064
FR		 3960 tp->hw_start(dev);
3961
07ce4064
FR		 3962 netif_start_queue(dev);
3963}
3964
7f796d83
FR		 3965static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3966 void __iomem *ioaddr)
3967{
3968 /*
3969 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3970 * register to be written before TxDescAddrLow to work.
3971 * Switching from MMIO to I/O access fixes the issue as well.
3972 */
3973 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 3974 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 3975 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 3976 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 3977}
3978
3979static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3980{
3981 u16 cmd;
3982
3983 cmd = RTL_R16(CPlusCmd);
3984 RTL_W16(CPlusCmd, cmd);
3985 return cmd;
3986}
3987
fdd7b4c3 3988static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 3989{
3990 /* Low hurts. Let's disable the filtering. */
207d6e87 3991 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 3992}
3993
6dccd16b
FR		 3994static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3995{
3744100e 3996 static const struct rtl_cfg2_info {
6dccd16b
FR		 3997 u32 mac_version;
3998 u32 clk;
3999 u32 val;
4000 } cfg2_info [] = {
4001 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4002 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4003 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4004 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4005 };
4006 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4007 unsigned int i;
4008 u32 clk;
4009
4010 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 4011 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 4012 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4013 RTL_W32(0x7c, p->val);
4014 break;
4015 }
4016 }
4017}
4018
07ce4064
FR		 4019static void rtl_hw_start_8169(struct net_device *dev)
4020{
4021 struct rtl8169_private *tp = netdev_priv(dev);
4022 void __iomem *ioaddr = tp->mmio_addr;
4023 struct pci_dev *pdev = tp->pci_dev;
07ce4064 4024
9cb427b6
FR		 4025 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4026 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4027 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4028 }
4029
1da177e4 4030 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 4031 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4032 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4033 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4034 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 4035 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4036
f0298f81 4037 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 4038
6f0333b8 4039 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 4040
cecb5fd7
FR		 4041 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4042 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4043 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4044 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 4045 rtl_set_rx_tx_config_registers(tp);
1da177e4 4046
7f796d83 4047 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 4048
cecb5fd7
FR		 4049 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4050 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 4051 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 4052 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 4053 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4054 }
4055
bcf0bf90
FR		 4056 RTL_W16(CPlusCmd, tp->cp_cmd);
4057
6dccd16b
FR		 4058 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4059
1da177e4
LT		 4060 /*
4061 * Undocumented corner. Supposedly:
4062 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4063 */
4064 RTL_W16(IntrMitigate, 0x0000);
4065
7f796d83 4066 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 4067
cecb5fd7
FR		 4068 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4069 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4070 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4071 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 4072 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4073 rtl_set_rx_tx_config_registers(tp);
4074 }
4075
1da177e4 4076 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 4077
4078 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4079 RTL_R8(IntrMask);
1da177e4
LT		 4080
4081 RTL_W32(RxMissed, 0);
4082
07ce4064 4083 rtl_set_rx_mode(dev);
1da177e4
LT		 4084
4085 /* no early-rx interrupts */
4086 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 4087
4088 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 4089 RTL_W16(IntrMask, tp->intr_event);
07ce4064 4090}
1da177e4 4091
9c14ceaf 4092static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 4093{
e44daade 4094 int cap = pci_pcie_cap(pdev);
9c14ceaf
FR		 4095
4096 if (cap) {
4097 u16 ctl;
458a9f61 4098
9c14ceaf
FR		 4099 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
4100 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
4101 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
4102 }
458a9f61
FR		 4103}
4104
650e8d5d 4105static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
dacf8154
FR		 4106{
4107 u32 csi;
4108
4109 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
650e8d5d 4110 rtl_csi_write(ioaddr, 0x070c, csi | bits);
4111}
4112
e6de30d6 4113static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4114{
4115 rtl_csi_access_enable(ioaddr, 0x17000000);
4116}
4117
650e8d5d 4118static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4119{
4120 rtl_csi_access_enable(ioaddr, 0x27000000);
dacf8154
FR		 4121}
4122
4123struct ephy_info {
4124 unsigned int offset;
4125 u16 mask;
4126 u16 bits;
4127};
4128
350f7596 4129static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 4130{
4131 u16 w;
4132
4133 while (len-- > 0) {
4134 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4135 rtl_ephy_write(ioaddr, e->offset, w);
4136 e++;
4137 }
4138}
4139
b726e493
FR		 4140static void rtl_disable_clock_request(struct pci_dev *pdev)
4141{
e44daade 4142 int cap = pci_pcie_cap(pdev);
b726e493
FR		 4143
4144 if (cap) {
4145 u16 ctl;
4146
4147 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4148 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4149 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4150 }
4151}
4152
e6de30d6 4153static void rtl_enable_clock_request(struct pci_dev *pdev)
4154{
e44daade 4155 int cap = pci_pcie_cap(pdev);
e6de30d6 4156
4157 if (cap) {
4158 u16 ctl;
4159
4160 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4161 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4162 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4163 }
4164}
4165
b726e493
FR		 4166#define R8168_CPCMD_QUIRK_MASK (\
4167 EnableBist | \
4168 Mac_dbgo_oe | \
4169 Force_half_dup | \
4170 Force_rxflow_en | \
4171 Force_txflow_en | \
4172 Cxpl_dbg_sel | \
4173 ASF | \
4174 PktCntrDisable | \
4175 Mac_dbgo_sel)
4176
219a1e9d
FR		 4177static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4178{
b726e493
FR		 4179 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4180
4181 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4182
2e68ae44
FR		 4183 rtl_tx_performance_tweak(pdev,
4184 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 4185}
4186
4187static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4188{
4189 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493 4190
f0298f81 4191 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 4192
4193 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 4194}
4195
4196static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4197{
b726e493
FR		 4198 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4199
4200 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4201
219a1e9d 4202 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 4203
4204 rtl_disable_clock_request(pdev);
4205
4206 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 4207}
4208
ef3386f0 4209static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 4210{
350f7596 4211 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4212 { 0x01, 0, 0x0001 },
4213 { 0x02, 0x0800, 0x1000 },
4214 { 0x03, 0, 0x0042 },
4215 { 0x06, 0x0080, 0x0000 },
4216 { 0x07, 0, 0x2000 }
4217 };
4218
650e8d5d 4219 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4220
4221 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4222
219a1e9d
FR		 4223 __rtl_hw_start_8168cp(ioaddr, pdev);
4224}
4225
ef3386f0
FR		 4226static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4227{
650e8d5d 4228 rtl_csi_access_enable_2(ioaddr);
ef3386f0
FR		 4229
4230 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4231
4232 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4233
4234 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4235}
4236
7f3e3d3a
FR		 4237static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4238{
650e8d5d 4239 rtl_csi_access_enable_2(ioaddr);
7f3e3d3a
FR		 4240
4241 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4242
4243 /* Magic. */
4244 RTL_W8(DBG_REG, 0x20);
4245
f0298f81 4246 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 4247
4248 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4249
4250 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4251}
4252
219a1e9d
FR		 4253static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4254{
350f7596 4255 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4256 { 0x02, 0x0800, 0x1000 },
4257 { 0x03, 0, 0x0002 },
4258 { 0x06, 0x0080, 0x0000 }
4259 };
4260
650e8d5d 4261 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4262
4263 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4264
4265 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4266
219a1e9d
FR		 4267 __rtl_hw_start_8168cp(ioaddr, pdev);
4268}
4269
4270static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4271{
350f7596 4272 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 4273 { 0x01, 0, 0x0001 },
4274 { 0x03, 0x0400, 0x0220 }
4275 };
4276
650e8d5d 4277 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4278
4279 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4280
219a1e9d
FR		 4281 __rtl_hw_start_8168cp(ioaddr, pdev);
4282}
4283
197ff761
FR		 4284static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4285{
4286 rtl_hw_start_8168c_2(ioaddr, pdev);
4287}
4288
6fb07058
FR		 4289static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4290{
650e8d5d 4291 rtl_csi_access_enable_2(ioaddr);
6fb07058
FR		 4292
4293 __rtl_hw_start_8168cp(ioaddr, pdev);
4294}
4295
5b538df9
FR		 4296static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4297{
650e8d5d 4298 rtl_csi_access_enable_2(ioaddr);
5b538df9
FR		 4299
4300 rtl_disable_clock_request(pdev);
4301
f0298f81 4302 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 4303
4304 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4305
4306 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4307}
4308
4804b3b3 4309static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4310{
4311 rtl_csi_access_enable_1(ioaddr);
4312
4313 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4314
4315 RTL_W8(MaxTxPacketSize, TxPacketMax);
4316
4317 rtl_disable_clock_request(pdev);
4318}
4319
e6de30d6 4320static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4321{
4322 static const struct ephy_info e_info_8168d_4[] = {
4323 { 0x0b, ~0, 0x48 },
4324 { 0x19, 0x20, 0x50 },
4325 { 0x0c, ~0, 0x20 }
4326 };
4327 int i;
4328
4329 rtl_csi_access_enable_1(ioaddr);
4330
4331 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4332
4333 RTL_W8(MaxTxPacketSize, TxPacketMax);
4334
4335 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4336 const struct ephy_info *e = e_info_8168d_4 + i;
4337 u16 w;
4338
4339 w = rtl_ephy_read(ioaddr, e->offset);
4340 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4341 }
4342
4343 rtl_enable_clock_request(pdev);
4344}
4345
70090424 4346static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
01dc7fec 4347{
70090424 4348 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 4349 { 0x00, 0x0200, 0x0100 },
4350 { 0x00, 0x0000, 0x0004 },
4351 { 0x06, 0x0002, 0x0001 },
4352 { 0x06, 0x0000, 0x0030 },
4353 { 0x07, 0x0000, 0x2000 },
4354 { 0x00, 0x0000, 0x0020 },
4355 { 0x03, 0x5800, 0x2000 },
4356 { 0x03, 0x0000, 0x0001 },
4357 { 0x01, 0x0800, 0x1000 },
4358 { 0x07, 0x0000, 0x4000 },
4359 { 0x1e, 0x0000, 0x2000 },
4360 { 0x19, 0xffff, 0xfe6c },
4361 { 0x0a, 0x0000, 0x0040 }
4362 };
4363
4364 rtl_csi_access_enable_2(ioaddr);
4365
70090424 4366 rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 4367
4368 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4369
4370 RTL_W8(MaxTxPacketSize, TxPacketMax);
4371
4372 rtl_disable_clock_request(pdev);
4373
4374 /* Reset tx FIFO pointer */
cecb5fd7
FR		 4375 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4376 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 4377
cecb5fd7 4378 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 4379}
4380
70090424
HW		 4381static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4382{
4383 static const struct ephy_info e_info_8168e_2[] = {
4384 { 0x09, 0x0000, 0x0080 },
4385 { 0x19, 0x0000, 0x0224 }
4386 };
4387
4388 rtl_csi_access_enable_1(ioaddr);
4389
4390 rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4391
4392 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4393
4394 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4395 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4396 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4397 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4398 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4399 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4400 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4401 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4402 ERIAR_EXGMAC);
4403
4404 RTL_W8(MaxTxPacketSize, 0x27);
4405
4406 rtl_disable_clock_request(pdev);
4407
4408 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4409 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4410
4411 /* Adjust EEE LED frequency */
4412 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4413
4414 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4415 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4416 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4417}
4418
07ce4064
FR		 4419static void rtl_hw_start_8168(struct net_device *dev)
4420{
2dd99530
FR		 4421 struct rtl8169_private *tp = netdev_priv(dev);
4422 void __iomem *ioaddr = tp->mmio_addr;
0e485150 4423 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 4424
4425 RTL_W8(Cfg9346, Cfg9346_Unlock);
4426
f0298f81 4427 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 4428
6f0333b8 4429 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 4430
0e485150 4431 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 4432
4433 RTL_W16(CPlusCmd, tp->cp_cmd);
4434
0e485150 4435 RTL_W16(IntrMitigate, 0x5151);
2dd99530 4436
0e485150 4437 /* Work around for RxFIFO overflow. */
b5ba6d12
IV		 4438 if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4439 tp->mac_version == RTL_GIGA_MAC_VER_22) {
0e485150
FR		 4440 tp->intr_event |= RxFIFOOver | PCSTimeout;
4441 tp->intr_event &= ~RxOverflow;
4442 }
4443
4444 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 4445
b8363901
FR		 4446 rtl_set_rx_mode(dev);
4447
4448 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4449 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 4450
4451 RTL_R8(IntrMask);
4452
219a1e9d
FR		 4453 switch (tp->mac_version) {
4454 case RTL_GIGA_MAC_VER_11:
4455 rtl_hw_start_8168bb(ioaddr, pdev);
4804b3b3 4456 break;
219a1e9d
FR		 4457
4458 case RTL_GIGA_MAC_VER_12:
4459 case RTL_GIGA_MAC_VER_17:
4460 rtl_hw_start_8168bef(ioaddr, pdev);
4804b3b3 4461 break;
219a1e9d
FR		 4462
4463 case RTL_GIGA_MAC_VER_18:
ef3386f0 4464 rtl_hw_start_8168cp_1(ioaddr, pdev);
4804b3b3 4465 break;
219a1e9d
FR		 4466
4467 case RTL_GIGA_MAC_VER_19:
4468 rtl_hw_start_8168c_1(ioaddr, pdev);
4804b3b3 4469 break;
219a1e9d
FR		 4470
4471 case RTL_GIGA_MAC_VER_20:
4472 rtl_hw_start_8168c_2(ioaddr, pdev);
4804b3b3 4473 break;
219a1e9d 4474
197ff761
FR		 4475 case RTL_GIGA_MAC_VER_21:
4476 rtl_hw_start_8168c_3(ioaddr, pdev);
4804b3b3 4477 break;
197ff761 4478
6fb07058
FR		 4479 case RTL_GIGA_MAC_VER_22:
4480 rtl_hw_start_8168c_4(ioaddr, pdev);
4804b3b3 4481 break;
6fb07058 4482
ef3386f0
FR		 4483 case RTL_GIGA_MAC_VER_23:
4484 rtl_hw_start_8168cp_2(ioaddr, pdev);
4804b3b3 4485 break;
ef3386f0 4486
7f3e3d3a
FR		 4487 case RTL_GIGA_MAC_VER_24:
4488 rtl_hw_start_8168cp_3(ioaddr, pdev);
4804b3b3 4489 break;
7f3e3d3a 4490
5b538df9 4491 case RTL_GIGA_MAC_VER_25:
daf9df6d 4492 case RTL_GIGA_MAC_VER_26:
4493 case RTL_GIGA_MAC_VER_27:
5b538df9 4494 rtl_hw_start_8168d(ioaddr, pdev);
4804b3b3 4495 break;
5b538df9 4496
e6de30d6 4497 case RTL_GIGA_MAC_VER_28:
4498 rtl_hw_start_8168d_4(ioaddr, pdev);
4804b3b3 4499 break;
cecb5fd7 4500
4804b3b3 4501 case RTL_GIGA_MAC_VER_31:
4502 rtl_hw_start_8168dp(ioaddr, pdev);
4503 break;
4504
01dc7fec 4505 case RTL_GIGA_MAC_VER_32:
4506 case RTL_GIGA_MAC_VER_33:
70090424
HW		 4507 rtl_hw_start_8168e_1(ioaddr, pdev);
4508 break;
4509 case RTL_GIGA_MAC_VER_34:
4510 rtl_hw_start_8168e_2(ioaddr, pdev);
01dc7fec 4511 break;
e6de30d6 4512
219a1e9d
FR		 4513 default:
4514 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4515 dev->name, tp->mac_version);
4804b3b3 4516 break;
219a1e9d 4517 }
2dd99530 4518
0e485150
FR		 4519 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4520
b8363901
FR		 4521 RTL_W8(Cfg9346, Cfg9346_Lock);
4522
2dd99530 4523 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 4524
0e485150 4525 RTL_W16(IntrMask, tp->intr_event);
07ce4064 4526}
1da177e4 4527
2857ffb7
FR		 4528#define R810X_CPCMD_QUIRK_MASK (\
4529 EnableBist | \
4530 Mac_dbgo_oe | \
4531 Force_half_dup | \
5edcc537 4532 Force_rxflow_en | \
2857ffb7
FR		 4533 Force_txflow_en | \
4534 Cxpl_dbg_sel | \
4535 ASF | \
4536 PktCntrDisable | \
d24e9aaf 4537 Mac_dbgo_sel)
2857ffb7
FR		 4538
4539static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4540{
350f7596 4541 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 4542 { 0x01, 0, 0x6e65 },
4543 { 0x02, 0, 0x091f },
4544 { 0x03, 0, 0xc2f9 },
4545 { 0x06, 0, 0xafb5 },
4546 { 0x07, 0, 0x0e00 },
4547 { 0x19, 0, 0xec80 },
4548 { 0x01, 0, 0x2e65 },
4549 { 0x01, 0, 0x6e65 }
4550 };
4551 u8 cfg1;
4552
650e8d5d 4553 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 4554
4555 RTL_W8(DBG_REG, FIX_NAK_1);
4556
4557 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4558
4559 RTL_W8(Config1,
4560 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4561 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4562
4563 cfg1 = RTL_R8(Config1);
4564 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4565 RTL_W8(Config1, cfg1 & ~LEDS0);
4566
2857ffb7
FR		 4567 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4568}
4569
4570static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4571{
650e8d5d 4572 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 4573
4574 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4575
4576 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4577 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 4578}
4579
4580static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4581{
4582 rtl_hw_start_8102e_2(ioaddr, pdev);
4583
4584 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4585}
4586
5a5e4443
HW		 4587static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4588{
4589 static const struct ephy_info e_info_8105e_1[] = {
4590 { 0x07, 0, 0x4000 },
4591 { 0x19, 0, 0x0200 },
4592 { 0x19, 0, 0x0020 },
4593 { 0x1e, 0, 0x2000 },
4594 { 0x03, 0, 0x0001 },
4595 { 0x19, 0, 0x0100 },
4596 { 0x19, 0, 0x0004 },
4597 { 0x0a, 0, 0x0020 }
4598 };
4599
cecb5fd7 4600 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 4601 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4602
cecb5fd7 4603 /* Disable Early Tally Counter */
5a5e4443
HW		 4604 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4605
4606 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 4607 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443
HW		 4608
4609 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4610}
4611
4612static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4613{
4614 rtl_hw_start_8105e_1(ioaddr, pdev);
4615 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4616}
4617
07ce4064
FR		 4618static void rtl_hw_start_8101(struct net_device *dev)
4619{
cdf1a608
FR		 4620 struct rtl8169_private *tp = netdev_priv(dev);
4621 void __iomem *ioaddr = tp->mmio_addr;
4622 struct pci_dev *pdev = tp->pci_dev;
4623
cecb5fd7
FR		 4624 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4625 tp->mac_version == RTL_GIGA_MAC_VER_16) {
e44daade 4626 int cap = pci_pcie_cap(pdev);
9c14ceaf
FR		 4627
4628 if (cap) {
4629 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4630 PCI_EXP_DEVCTL_NOSNOOP_EN);
4631 }
cdf1a608
FR		 4632 }
4633
d24e9aaf
HW		 4634 RTL_W8(Cfg9346, Cfg9346_Unlock);
4635
2857ffb7
FR		 4636 switch (tp->mac_version) {
4637 case RTL_GIGA_MAC_VER_07:
4638 rtl_hw_start_8102e_1(ioaddr, pdev);
4639 break;
4640
4641 case RTL_GIGA_MAC_VER_08:
4642 rtl_hw_start_8102e_3(ioaddr, pdev);
4643 break;
4644
4645 case RTL_GIGA_MAC_VER_09:
4646 rtl_hw_start_8102e_2(ioaddr, pdev);
4647 break;
5a5e4443
HW		 4648
4649 case RTL_GIGA_MAC_VER_29:
4650 rtl_hw_start_8105e_1(ioaddr, pdev);
4651 break;
4652 case RTL_GIGA_MAC_VER_30:
4653 rtl_hw_start_8105e_2(ioaddr, pdev);
4654 break;
cdf1a608
FR		 4655 }
4656
d24e9aaf 4657 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 4658
f0298f81 4659 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 4660
6f0333b8 4661 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 4662
d24e9aaf 4663 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 4664 RTL_W16(CPlusCmd, tp->cp_cmd);
4665
4666 RTL_W16(IntrMitigate, 0x0000);
4667
4668 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4669
4670 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4671 rtl_set_rx_tx_config_registers(tp);
4672
cdf1a608
FR		 4673 RTL_R8(IntrMask);
4674
cdf1a608
FR		 4675 rtl_set_rx_mode(dev);
4676
4677 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 4678
0e485150 4679 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4680}
4681
4682static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4683{
1da177e4
LT		 4684 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4685 return -EINVAL;
4686
4687 dev->mtu = new_mtu;
350fb32a
MM		 4688 netdev_update_features(dev);
4689
323bb685 4690 return 0;
1da177e4
LT		 4691}
4692
4693static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4694{
95e0918d 4695 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 4696 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4697}
4698
6f0333b8
ED		 4699static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4700 void **data_buff, struct RxDesc *desc)
1da177e4 4701{
48addcc9 4702 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 4703 DMA_FROM_DEVICE);
48addcc9 4704
6f0333b8
ED		 4705 kfree(*data_buff);
4706 *data_buff = NULL;
1da177e4
LT		 4707 rtl8169_make_unusable_by_asic(desc);
4708}
4709
4710static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4711{
4712 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4713
4714 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4715}
4716
4717static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4718 u32 rx_buf_sz)
4719{
4720 desc->addr = cpu_to_le64(mapping);
4721 wmb();
4722 rtl8169_mark_to_asic(desc, rx_buf_sz);
4723}
4724
6f0333b8
ED		 4725static inline void *rtl8169_align(void *data)
4726{
4727 return (void *)ALIGN((long)data, 16);
4728}
4729
0ecbe1ca
SG		 4730static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4731 struct RxDesc *desc)
1da177e4 4732{
6f0333b8 4733 void *data;
1da177e4 4734 dma_addr_t mapping;
48addcc9 4735 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 4736 struct net_device *dev = tp->dev;
6f0333b8 4737 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 4738
6f0333b8
ED		 4739 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4740 if (!data)
4741 return NULL;
e9f63f30 4742
6f0333b8
ED		 4743 if (rtl8169_align(data) != data) {
4744 kfree(data);
4745 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4746 if (!data)
4747 return NULL;
4748 }
3eafe507 4749
48addcc9 4750 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 4751 DMA_FROM_DEVICE);
d827d86b
SG		 4752 if (unlikely(dma_mapping_error(d, mapping))) {
4753 if (net_ratelimit())
4754 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 4755 goto err_out;
d827d86b 4756 }
1da177e4
LT		 4757
4758 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 4759 return data;
3eafe507
SG		 4760
4761err_out:
4762 kfree(data);
4763 return NULL;
1da177e4
LT		 4764}
4765
4766static void rtl8169_rx_clear(struct rtl8169_private *tp)
4767{
07d3f51f 4768 unsigned int i;
1da177e4
LT		 4769
4770 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 4771 if (tp->Rx_databuff[i]) {
4772 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 4773 tp->RxDescArray + i);
4774 }
4775 }
4776}
4777
0ecbe1ca 4778static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 4779{
0ecbe1ca
SG		 4780 desc->opts1 |= cpu_to_le32(RingEnd);
4781}
5b0384f4 4782
0ecbe1ca
SG		 4783static int rtl8169_rx_fill(struct rtl8169_private *tp)
4784{
4785 unsigned int i;
1da177e4 4786
0ecbe1ca
SG		 4787 for (i = 0; i < NUM_RX_DESC; i++) {
4788 void *data;
4ae47c2d 4789
6f0333b8 4790 if (tp->Rx_databuff[i])
1da177e4 4791 continue;
bcf0bf90 4792
0ecbe1ca 4793 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 4794 if (!data) {
4795 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 4796 goto err_out;
6f0333b8
ED		 4797 }
4798 tp->Rx_databuff[i] = data;
1da177e4 4799 }
1da177e4 4800
0ecbe1ca
SG		 4801 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4802 return 0;
4803
4804err_out:
4805 rtl8169_rx_clear(tp);
4806 return -ENOMEM;
1da177e4
LT		 4807}
4808
1da177e4
LT		 4809static int rtl8169_init_ring(struct net_device *dev)
4810{
4811 struct rtl8169_private *tp = netdev_priv(dev);
4812
4813 rtl8169_init_ring_indexes(tp);
4814
4815 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 4816 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 4817
0ecbe1ca 4818 return rtl8169_rx_fill(tp);
1da177e4
LT		 4819}
4820
48addcc9 4821static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 4822 struct TxDesc *desc)
4823{
4824 unsigned int len = tx_skb->len;
4825
48addcc9
SG		 4826 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4827
1da177e4
LT		 4828 desc->opts1 = 0x00;
4829 desc->opts2 = 0x00;
4830 desc->addr = 0x00;
4831 tx_skb->len = 0;
4832}
4833
3eafe507
SG		 4834static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4835 unsigned int n)
1da177e4
LT		 4836{
4837 unsigned int i;
4838
3eafe507
SG		 4839 for (i = 0; i < n; i++) {
4840 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 4841 struct ring_info *tx_skb = tp->tx_skb + entry;
4842 unsigned int len = tx_skb->len;
4843
4844 if (len) {
4845 struct sk_buff *skb = tx_skb->skb;
4846
48addcc9 4847 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 4848 tp->TxDescArray + entry);
4849 if (skb) {
cac4b22f 4850 tp->dev->stats.tx_dropped++;
1da177e4
LT		 4851 dev_kfree_skb(skb);
4852 tx_skb->skb = NULL;
4853 }
1da177e4
LT		 4854 }
4855 }
3eafe507
SG		 4856}
4857
4858static void rtl8169_tx_clear(struct rtl8169_private *tp)
4859{
4860 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 4861 tp->cur_tx = tp->dirty_tx = 0;
4862}
4863
c4028958 4864static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 4865{
4866 struct rtl8169_private *tp = netdev_priv(dev);
4867
c4028958 4868 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 4869 schedule_delayed_work(&tp->task, 4);
4870}
4871
4872static void rtl8169_wait_for_quiescence(struct net_device *dev)
4873{
4874 struct rtl8169_private *tp = netdev_priv(dev);
4875 void __iomem *ioaddr = tp->mmio_addr;
4876
4877 synchronize_irq(dev->irq);
4878
4879 /* Wait for any pending NAPI task to complete */
bea3348e 4880 napi_disable(&tp->napi);
1da177e4
LT		 4881
4882 rtl8169_irq_mask_and_ack(ioaddr);
4883
d1d08d12
DM		 4884 tp->intr_mask = 0xffff;
4885 RTL_W16(IntrMask, tp->intr_event);
bea3348e 4886 napi_enable(&tp->napi);
1da177e4
LT		 4887}
4888
c4028958 4889static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 4890{
c4028958
DH		 4891 struct rtl8169_private *tp =
4892 container_of(work, struct rtl8169_private, task.work);
4893 struct net_device *dev = tp->dev;
1da177e4
LT		 4894 int ret;
4895
eb2a021c
FR		 4896 rtnl_lock();
4897
4898 if (!netif_running(dev))
4899 goto out_unlock;
4900
4901 rtl8169_wait_for_quiescence(dev);
4902 rtl8169_close(dev);
1da177e4
LT		 4903
4904 ret = rtl8169_open(dev);
4905 if (unlikely(ret < 0)) {
bf82c189
JP		 4906 if (net_ratelimit())
4907 netif_err(tp, drv, dev,
4908 "reinit failure (status = %d). Rescheduling\n",
4909 ret);
1da177e4
LT		 4910 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4911 }
eb2a021c
FR		 4912
4913out_unlock:
4914 rtnl_unlock();
1da177e4
LT		 4915}
4916
c4028958 4917static void rtl8169_reset_task(struct work_struct *work)
1da177e4 4918{
c4028958
DH		 4919 struct rtl8169_private *tp =
4920 container_of(work, struct rtl8169_private, task.work);
4921 struct net_device *dev = tp->dev;
56de414c 4922 int i;
1da177e4 4923
eb2a021c
FR		 4924 rtnl_lock();
4925
1da177e4 4926 if (!netif_running(dev))
eb2a021c 4927 goto out_unlock;
1da177e4
LT		 4928
4929 rtl8169_wait_for_quiescence(dev);
4930
56de414c
FR		 4931 for (i = 0; i < NUM_RX_DESC; i++)
4932 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4933
1da177e4
LT		 4934 rtl8169_tx_clear(tp);
4935
92fc43b4 4936 rtl8169_hw_reset(tp);
56de414c
FR		 4937 rtl_hw_start(dev);
4938 netif_wake_queue(dev);
4939 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
eb2a021c
FR		 4940
4941out_unlock:
4942 rtnl_unlock();
1da177e4
LT		 4943}
4944
4945static void rtl8169_tx_timeout(struct net_device *dev)
4946{
4947 struct rtl8169_private *tp = netdev_priv(dev);
4948
e6de30d6 4949 rtl8169_hw_reset(tp);
1da177e4
LT		 4950
4951 /* Let's wait a bit while any (async) irq lands on */
4952 rtl8169_schedule_work(dev, rtl8169_reset_task);
4953}
4954
4955static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 4956 u32 *opts)
1da177e4
LT		 4957{
4958 struct skb_shared_info *info = skb_shinfo(skb);
4959 unsigned int cur_frag, entry;
a6343afb 4960 struct TxDesc * uninitialized_var(txd);
48addcc9 4961 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4962
4963 entry = tp->cur_tx;
4964 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4965 skb_frag_t *frag = info->frags + cur_frag;
4966 dma_addr_t mapping;
4967 u32 status, len;
4968 void *addr;
4969
4970 entry = (entry + 1) % NUM_TX_DESC;
4971
4972 txd = tp->TxDescArray + entry;
4973 len = frag->size;
4974 addr = ((void *) page_address(frag->page)) + frag->page_offset;
48addcc9 4975 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 4976 if (unlikely(dma_mapping_error(d, mapping))) {
4977 if (net_ratelimit())
4978 netif_err(tp, drv, tp->dev,
4979 "Failed to map TX fragments DMA!\n");
3eafe507 4980 goto err_out;
d827d86b 4981 }
1da177e4 4982
cecb5fd7 4983 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 4984 status = opts[0] | len |
4985 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 4986
4987 txd->opts1 = cpu_to_le32(status);
2b7b4318 4988 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 4989 txd->addr = cpu_to_le64(mapping);
4990
4991 tp->tx_skb[entry].len = len;
4992 }
4993
4994 if (cur_frag) {
4995 tp->tx_skb[entry].skb = skb;
4996 txd->opts1 |= cpu_to_le32(LastFrag);
4997 }
4998
4999 return cur_frag;
3eafe507
SG		 5000
5001err_out:
5002 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5003 return -EIO;
1da177e4
LT		 5004}
5005
2b7b4318
FR		 5006static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5007 struct sk_buff *skb, u32 *opts)
1da177e4 5008{
2b7b4318 5009 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 5010 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 5011 int offset = info->opts_offset;
350fb32a 5012
2b7b4318
FR		 5013 if (mss) {
5014 opts[0] |= TD_LSO;
5015 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5016 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 5017 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 5018
5019 if (ip->protocol == IPPROTO_TCP)
2b7b4318 5020 opts[offset] |= info->checksum.tcp;
1da177e4 5021 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 5022 opts[offset] |= info->checksum.udp;
5023 else
5024 WARN_ON_ONCE(1);
1da177e4 5025 }
1da177e4
LT		 5026}
5027
61357325
SH		 5028static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5029 struct net_device *dev)
1da177e4
LT		 5030{
5031 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 5032 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 5033 struct TxDesc *txd = tp->TxDescArray + entry;
5034 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 5035 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5036 dma_addr_t mapping;
5037 u32 status, len;
2b7b4318 5038 u32 opts[2];
3eafe507 5039 int frags;
5b0384f4 5040
1da177e4 5041 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 5042 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 5043 goto err_stop_0;
1da177e4
LT		 5044 }
5045
5046 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 5047 goto err_stop_0;
5048
5049 len = skb_headlen(skb);
48addcc9 5050 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 5051 if (unlikely(dma_mapping_error(d, mapping))) {
5052 if (net_ratelimit())
5053 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 5054 goto err_dma_0;
d827d86b 5055 }
3eafe507
SG		 5056
5057 tp->tx_skb[entry].len = len;
5058 txd->addr = cpu_to_le64(mapping);
1da177e4 5059
2b7b4318
FR		 5060 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5061 opts[0] = DescOwn;
1da177e4 5062
2b7b4318
FR		 5063 rtl8169_tso_csum(tp, skb, opts);
5064
5065 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 5066 if (frags < 0)
5067 goto err_dma_1;
5068 else if (frags)
2b7b4318 5069 opts[0] |= FirstFrag;
3eafe507 5070 else {
2b7b4318 5071 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 5072 tp->tx_skb[entry].skb = skb;
5073 }
5074
2b7b4318
FR		 5075 txd->opts2 = cpu_to_le32(opts[1]);
5076
1da177e4
LT		 5077 wmb();
5078
cecb5fd7 5079 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 5080 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5081 txd->opts1 = cpu_to_le32(status);
5082
1da177e4
LT		 5083 tp->cur_tx += frags + 1;
5084
4c020a96 5085 wmb();
1da177e4 5086
cecb5fd7 5087 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 5088
5089 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
5090 netif_stop_queue(dev);
5091 smp_rmb();
5092 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
5093 netif_wake_queue(dev);
5094 }
5095
61357325 5096 return NETDEV_TX_OK;
1da177e4 5097
3eafe507 5098err_dma_1:
48addcc9 5099 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 5100err_dma_0:
5101 dev_kfree_skb(skb);
5102 dev->stats.tx_dropped++;
5103 return NETDEV_TX_OK;
5104
5105err_stop_0:
1da177e4 5106 netif_stop_queue(dev);
cebf8cc7 5107 dev->stats.tx_dropped++;
61357325 5108 return NETDEV_TX_BUSY;
1da177e4
LT		 5109}
5110
5111static void rtl8169_pcierr_interrupt(struct net_device *dev)
5112{
5113 struct rtl8169_private *tp = netdev_priv(dev);
5114 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 5115 u16 pci_status, pci_cmd;
5116
5117 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5118 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5119
bf82c189
JP		 5120 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5121 pci_cmd, pci_status);
1da177e4
LT		 5122
5123 /*
5124 * The recovery sequence below admits a very elaborated explanation:
5125 * - it seems to work;
d03902b8
FR		 5126 * - I did not see what else could be done;
5127 * - it makes iop3xx happy.
1da177e4
LT		 5128 *
5129 * Feel free to adjust to your needs.
5130 */
a27993f3 5131 if (pdev->broken_parity_status)
d03902b8
FR		 5132 pci_cmd &= ~PCI_COMMAND_PARITY;
5133 else
5134 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5135
5136 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 5137
5138 pci_write_config_word(pdev, PCI_STATUS,
5139 pci_status & (PCI_STATUS_DETECTED_PARITY |
5140 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5141 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5142
5143 /* The infamous DAC f*ckup only happens at boot time */
5144 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 5145 void __iomem *ioaddr = tp->mmio_addr;
5146
bf82c189 5147 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 5148 tp->cp_cmd &= ~PCIDAC;
5149 RTL_W16(CPlusCmd, tp->cp_cmd);
5150 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 5151 }
5152
e6de30d6 5153 rtl8169_hw_reset(tp);
d03902b8
FR		 5154
5155 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 5156}
5157
07d3f51f
FR		 5158static void rtl8169_tx_interrupt(struct net_device *dev,
5159 struct rtl8169_private *tp,
5160 void __iomem *ioaddr)
1da177e4
LT		 5161{
5162 unsigned int dirty_tx, tx_left;
5163
1da177e4
LT		 5164 dirty_tx = tp->dirty_tx;
5165 smp_rmb();
5166 tx_left = tp->cur_tx - dirty_tx;
5167
5168 while (tx_left > 0) {
5169 unsigned int entry = dirty_tx % NUM_TX_DESC;
5170 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 5171 u32 status;
5172
5173 rmb();
5174 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5175 if (status & DescOwn)
5176 break;
5177
48addcc9
SG		 5178 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5179 tp->TxDescArray + entry);
1da177e4 5180 if (status & LastFrag) {
cac4b22f
SG		 5181 dev->stats.tx_packets++;
5182 dev->stats.tx_bytes += tx_skb->skb->len;
87433bfc 5183 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 5184 tx_skb->skb = NULL;
5185 }
5186 dirty_tx++;
5187 tx_left--;
5188 }
5189
5190 if (tp->dirty_tx != dirty_tx) {
5191 tp->dirty_tx = dirty_tx;
5192 smp_wmb();
5193 if (netif_queue_stopped(dev) &&
5194 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5195 netif_wake_queue(dev);
5196 }
d78ae2dc
FR		 5197 /*
5198 * 8168 hack: TxPoll requests are lost when the Tx packets are
5199 * too close. Let's kick an extra TxPoll request when a burst
5200 * of start_xmit activity is detected (if it is not detected,
5201 * it is slow enough). -- FR
5202 */
5203 smp_rmb();
5204 if (tp->cur_tx != dirty_tx)
5205 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 5206 }
5207}
5208
126fa4b9
FR		 5209static inline int rtl8169_fragmented_frame(u32 status)
5210{
5211 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5212}
5213
adea1ac7 5214static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 5215{
1da177e4
LT		 5216 u32 status = opts1 & RxProtoMask;
5217
5218 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 5219 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 5220 skb->ip_summed = CHECKSUM_UNNECESSARY;
5221 else
bc8acf2c 5222 skb_checksum_none_assert(skb);
1da177e4
LT		 5223}
5224
6f0333b8
ED		 5225static struct sk_buff *rtl8169_try_rx_copy(void *data,
5226 struct rtl8169_private *tp,
5227 int pkt_size,
5228 dma_addr_t addr)
1da177e4 5229{
b449655f 5230 struct sk_buff *skb;
48addcc9 5231 struct device *d = &tp->pci_dev->dev;
b449655f 5232
6f0333b8 5233 data = rtl8169_align(data);
48addcc9 5234 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 5235 prefetch(data);
5236 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5237 if (skb)
5238 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 5239 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5240
6f0333b8 5241 return skb;
1da177e4
LT		 5242}
5243
07d3f51f
FR		 5244static int rtl8169_rx_interrupt(struct net_device *dev,
5245 struct rtl8169_private *tp,
bea3348e 5246 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 5247{
5248 unsigned int cur_rx, rx_left;
6f0333b8 5249 unsigned int count;
1da177e4 5250
1da177e4
LT		 5251 cur_rx = tp->cur_rx;
5252 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 5253 rx_left = min(rx_left, budget);
1da177e4 5254
4dcb7d33 5255 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 5256 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 5257 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 5258 u32 status;
5259
5260 rmb();
126fa4b9 5261 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 5262
5263 if (status & DescOwn)
5264 break;
4dcb7d33 5265 if (unlikely(status & RxRES)) {
bf82c189
JP		 5266 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5267 status);
cebf8cc7 5268 dev->stats.rx_errors++;
1da177e4 5269 if (status & (RxRWT | RxRUNT))
cebf8cc7 5270 dev->stats.rx_length_errors++;
1da177e4 5271 if (status & RxCRC)
cebf8cc7 5272 dev->stats.rx_crc_errors++;
9dccf611
FR		 5273 if (status & RxFOVF) {
5274 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 5275 dev->stats.rx_fifo_errors++;
9dccf611 5276 }
6f0333b8 5277 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 5278 } else {
6f0333b8 5279 struct sk_buff *skb;
b449655f 5280 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 5281 int pkt_size = (status & 0x00001FFF) - 4;
1da177e4 5282
126fa4b9
FR		 5283 /*
5284 * The driver does not support incoming fragmented
5285 * frames. They are seen as a symptom of over-mtu
5286 * sized frames.
5287 */
5288 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 5289 dev->stats.rx_dropped++;
5290 dev->stats.rx_length_errors++;
6f0333b8 5291 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 5292 continue;
126fa4b9
FR		 5293 }
5294
6f0333b8
ED		 5295 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5296 tp, pkt_size, addr);
5297 rtl8169_mark_to_asic(desc, rx_buf_sz);
5298 if (!skb) {
5299 dev->stats.rx_dropped++;
5300 continue;
1da177e4
LT		 5301 }
5302
adea1ac7 5303 rtl8169_rx_csum(skb, status);
1da177e4
LT		 5304 skb_put(skb, pkt_size);
5305 skb->protocol = eth_type_trans(skb, dev);
5306
7a8fc77b
FR		 5307 rtl8169_rx_vlan_tag(desc, skb);
5308
56de414c 5309 napi_gro_receive(&tp->napi, skb);
1da177e4 5310
cebf8cc7
FR		 5311 dev->stats.rx_bytes += pkt_size;
5312 dev->stats.rx_packets++;
1da177e4 5313 }
6dccd16b
FR		 5314
5315 /* Work around for AMD plateform. */
95e0918d 5316 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 5317 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5318 desc->opts2 = 0;
5319 cur_rx++;
5320 }
1da177e4
LT		 5321 }
5322
5323 count = cur_rx - tp->cur_rx;
5324 tp->cur_rx = cur_rx;
5325
6f0333b8 5326 tp->dirty_rx += count;
1da177e4
LT		 5327
5328 return count;
5329}
5330
07d3f51f 5331static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 5332{
07d3f51f 5333 struct net_device *dev = dev_instance;
1da177e4 5334 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 5335 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 5336 int handled = 0;
865c652d 5337 int status;
1da177e4 5338
f11a377b
DD		 5339 /* loop handling interrupts until we have no new ones or
5340 * we hit a invalid/hotplug case.
5341 */
865c652d 5342 status = RTL_R16(IntrStatus);
f11a377b
DD		 5343 while (status && status != 0xffff) {
5344 handled = 1;
1da177e4 5345
f11a377b
DD		 5346 /* Handle all of the error cases first. These will reset
5347 * the chip, so just exit the loop.
5348 */
5349 if (unlikely(!netif_running(dev))) {
92fc43b4 5350 rtl8169_hw_reset(tp);
f11a377b
DD		 5351 break;
5352 }
1da177e4 5353
1519e57f
FR		 5354 if (unlikely(status & RxFIFOOver)) {
5355 switch (tp->mac_version) {
5356 /* Work around for rx fifo overflow */
5357 case RTL_GIGA_MAC_VER_11:
5358 case RTL_GIGA_MAC_VER_22:
5359 case RTL_GIGA_MAC_VER_26:
5360 netif_stop_queue(dev);
5361 rtl8169_tx_timeout(dev);
5362 goto done;
f60ac8e7
FR		 5363 /* Testers needed. */
5364 case RTL_GIGA_MAC_VER_17:
5365 case RTL_GIGA_MAC_VER_19:
5366 case RTL_GIGA_MAC_VER_20:
5367 case RTL_GIGA_MAC_VER_21:
5368 case RTL_GIGA_MAC_VER_23:
5369 case RTL_GIGA_MAC_VER_24:
5370 case RTL_GIGA_MAC_VER_27:
5371 case RTL_GIGA_MAC_VER_28:
4804b3b3 5372 case RTL_GIGA_MAC_VER_31:
1519e57f
FR		 5373 /* Experimental science. Pktgen proof. */
5374 case RTL_GIGA_MAC_VER_12:
5375 case RTL_GIGA_MAC_VER_25:
5376 if (status == RxFIFOOver)
5377 goto done;
5378 break;
5379 default:
5380 break;
5381 }
f11a377b 5382 }
1da177e4 5383
f11a377b
DD		 5384 if (unlikely(status & SYSErr)) {
5385 rtl8169_pcierr_interrupt(dev);
5386 break;
5387 }
1da177e4 5388
f11a377b 5389 if (status & LinkChg)
e4fbce74 5390 __rtl8169_check_link_status(dev, tp, ioaddr, true);
0e485150 5391
f11a377b
DD		 5392 /* We need to see the lastest version of tp->intr_mask to
5393 * avoid ignoring an MSI interrupt and having to wait for
5394 * another event which may never come.
5395 */
5396 smp_rmb();
5397 if (status & tp->intr_mask & tp->napi_event) {
5398 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5399 tp->intr_mask = ~tp->napi_event;
5400
5401 if (likely(napi_schedule_prep(&tp->napi)))
5402 __napi_schedule(&tp->napi);
bf82c189
JP		 5403 else
5404 netif_info(tp, intr, dev,
5405 "interrupt %04x in poll\n", status);
f11a377b 5406 }
1da177e4 5407
f11a377b
DD		 5408 /* We only get a new MSI interrupt when all active irq
5409 * sources on the chip have been acknowledged. So, ack
5410 * everything we've seen and check if new sources have become
5411 * active to avoid blocking all interrupts from the chip.
5412 */
5413 RTL_W16(IntrStatus,
5414 (status & RxFIFOOver) ? (status | RxOverflow) : status);
5415 status = RTL_R16(IntrStatus);
865c652d 5416 }
1519e57f 5417done:
1da177e4
LT		 5418 return IRQ_RETVAL(handled);
5419}
5420
bea3348e 5421static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 5422{
bea3348e
SH		 5423 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5424 struct net_device *dev = tp->dev;
1da177e4 5425 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 5426 int work_done;
1da177e4 5427
bea3348e 5428 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 5429 rtl8169_tx_interrupt(dev, tp, ioaddr);
5430
bea3348e 5431 if (work_done < budget) {
288379f0 5432 napi_complete(napi);
f11a377b
DD		 5433
5434 /* We need for force the visibility of tp->intr_mask
5435 * for other CPUs, as we can loose an MSI interrupt
5436 * and potentially wait for a retransmit timeout if we don't.
5437 * The posted write to IntrMask is safe, as it will
5438 * eventually make it to the chip and we won't loose anything
5439 * until it does.
1da177e4 5440 */
f11a377b 5441 tp->intr_mask = 0xffff;
4c020a96 5442 wmb();
0e485150 5443 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 5444 }
5445
bea3348e 5446 return work_done;
1da177e4 5447}
1da177e4 5448
523a6094
FR		 5449static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5450{
5451 struct rtl8169_private *tp = netdev_priv(dev);
5452
5453 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5454 return;
5455
5456 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5457 RTL_W32(RxMissed, 0);
5458}
5459
1da177e4
LT		 5460static void rtl8169_down(struct net_device *dev)
5461{
5462 struct rtl8169_private *tp = netdev_priv(dev);
5463 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 5464
4876cc1e 5465 del_timer_sync(&tp->timer);
1da177e4
LT		 5466
5467 netif_stop_queue(dev);
5468
93dd79e8 5469 napi_disable(&tp->napi);
93dd79e8 5470
1da177e4
LT		 5471 spin_lock_irq(&tp->lock);
5472
92fc43b4 5473 rtl8169_hw_reset(tp);
323bb685
SG		 5474 /*
5475 * At this point device interrupts can not be enabled in any function,
5476 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5477 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5478 */
523a6094 5479 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 5480
5481 spin_unlock_irq(&tp->lock);
5482
5483 synchronize_irq(dev->irq);
5484
1da177e4 5485 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 5486 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4 5487
1da177e4
LT		 5488 rtl8169_tx_clear(tp);
5489
5490 rtl8169_rx_clear(tp);
065c27c1 5491
5492 rtl_pll_power_down(tp);
1da177e4
LT		 5493}
5494
5495static int rtl8169_close(struct net_device *dev)
5496{
5497 struct rtl8169_private *tp = netdev_priv(dev);
5498 struct pci_dev *pdev = tp->pci_dev;
5499
e1759441
RW		 5500 pm_runtime_get_sync(&pdev->dev);
5501
cecb5fd7 5502 /* Update counters before going down */
355423d0
IV		 5503 rtl8169_update_counters(dev);
5504
1da177e4
LT		 5505 rtl8169_down(dev);
5506
5507 free_irq(dev->irq, dev);
5508
82553bb6
SG		 5509 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5510 tp->RxPhyAddr);
5511 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5512 tp->TxPhyAddr);
1da177e4
LT		 5513 tp->TxDescArray = NULL;
5514 tp->RxDescArray = NULL;
5515
e1759441
RW		 5516 pm_runtime_put_sync(&pdev->dev);
5517
1da177e4
LT		 5518 return 0;
5519}
5520
07ce4064 5521static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 5522{
5523 struct rtl8169_private *tp = netdev_priv(dev);
5524 void __iomem *ioaddr = tp->mmio_addr;
5525 unsigned long flags;
5526 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 5527 int rx_mode;
1da177e4
LT		 5528 u32 tmp = 0;
5529
5530 if (dev->flags & IFF_PROMISC) {
5531 /* Unconditionally log net taps. */
bf82c189 5532 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 5533 rx_mode =
5534 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5535 AcceptAllPhys;
5536 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 5537 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 5538 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 5539 /* Too many to filter perfectly -- accept all multicasts. */
5540 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5541 mc_filter[1] = mc_filter[0] = 0xffffffff;
5542 } else {
22bedad3 5543 struct netdev_hw_addr *ha;
07d3f51f 5544
1da177e4
LT		 5545 rx_mode = AcceptBroadcast | AcceptMyPhys;
5546 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 5547 netdev_for_each_mc_addr(ha, dev) {
5548 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 5549 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5550 rx_mode |= AcceptMulticast;
5551 }
5552 }
5553
5554 spin_lock_irqsave(&tp->lock, flags);
5555
5556 tmp = rtl8169_rx_config | rx_mode |
2b7b4318 5557 (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
1da177e4 5558
f887cce8 5559 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 5560 u32 data = mc_filter[0];
5561
5562 mc_filter[0] = swab32(mc_filter[1]);
5563 mc_filter[1] = swab32(data);
bcf0bf90
FR		 5564 }
5565
1da177e4 5566 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 5567 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 5568
57a9f236
FR		 5569 RTL_W32(RxConfig, tmp);
5570
1da177e4
LT		 5571 spin_unlock_irqrestore(&tp->lock, flags);
5572}
5573
5574/**
5575 * rtl8169_get_stats - Get rtl8169 read/write statistics
5576 * @dev: The Ethernet Device to get statistics for
5577 *
5578 * Get TX/RX statistics for rtl8169
5579 */
5580static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5581{
5582 struct rtl8169_private *tp = netdev_priv(dev);
5583 void __iomem *ioaddr = tp->mmio_addr;
5584 unsigned long flags;
5585
5586 if (netif_running(dev)) {
5587 spin_lock_irqsave(&tp->lock, flags);
523a6094 5588 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 5589 spin_unlock_irqrestore(&tp->lock, flags);
5590 }
5b0384f4 5591
cebf8cc7 5592 return &dev->stats;
1da177e4
LT		 5593}
5594
861ab440 5595static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 5596{
065c27c1 5597 struct rtl8169_private *tp = netdev_priv(dev);
5598
5d06a99f 5599 if (!netif_running(dev))
861ab440 5600 return;
5d06a99f 5601
065c27c1 5602 rtl_pll_power_down(tp);
5603
5d06a99f
FR		 5604 netif_device_detach(dev);
5605 netif_stop_queue(dev);
861ab440
RW		 5606}
5607
5608#ifdef CONFIG_PM
5609
5610static int rtl8169_suspend(struct device *device)
5611{
5612 struct pci_dev *pdev = to_pci_dev(device);
5613 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 5614
861ab440 5615 rtl8169_net_suspend(dev);
1371fa6d 5616
5d06a99f
FR		 5617 return 0;
5618}
5619
e1759441
RW		 5620static void __rtl8169_resume(struct net_device *dev)
5621{
065c27c1 5622 struct rtl8169_private *tp = netdev_priv(dev);
5623
e1759441 5624 netif_device_attach(dev);
065c27c1 5625
5626 rtl_pll_power_up(tp);
5627
e1759441
RW		 5628 rtl8169_schedule_work(dev, rtl8169_reset_task);
5629}
5630
861ab440 5631static int rtl8169_resume(struct device *device)
5d06a99f 5632{
861ab440 5633 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 5634 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 5635 struct rtl8169_private *tp = netdev_priv(dev);
5636
5637 rtl8169_init_phy(dev, tp);
5d06a99f 5638
e1759441
RW		 5639 if (netif_running(dev))
5640 __rtl8169_resume(dev);
5d06a99f 5641
e1759441
RW		 5642 return 0;
5643}
5644
5645static int rtl8169_runtime_suspend(struct device *device)
5646{
5647 struct pci_dev *pdev = to_pci_dev(device);
5648 struct net_device *dev = pci_get_drvdata(pdev);
5649 struct rtl8169_private *tp = netdev_priv(dev);
5650
5651 if (!tp->TxDescArray)
5652 return 0;
5653
5654 spin_lock_irq(&tp->lock);
5655 tp->saved_wolopts = __rtl8169_get_wol(tp);
5656 __rtl8169_set_wol(tp, WAKE_ANY);
5657 spin_unlock_irq(&tp->lock);
5658
5659 rtl8169_net_suspend(dev);
5660
5661 return 0;
5662}
5663
5664static int rtl8169_runtime_resume(struct device *device)
5665{
5666 struct pci_dev *pdev = to_pci_dev(device);
5667 struct net_device *dev = pci_get_drvdata(pdev);
5668 struct rtl8169_private *tp = netdev_priv(dev);
5669
5670 if (!tp->TxDescArray)
5671 return 0;
5672
5673 spin_lock_irq(&tp->lock);
5674 __rtl8169_set_wol(tp, tp->saved_wolopts);
5675 tp->saved_wolopts = 0;
5676 spin_unlock_irq(&tp->lock);
5677
fccec10b
SG		 5678 rtl8169_init_phy(dev, tp);
5679
e1759441 5680 __rtl8169_resume(dev);
5d06a99f 5681
5d06a99f
FR		 5682 return 0;
5683}
5684
e1759441
RW		 5685static int rtl8169_runtime_idle(struct device *device)
5686{
5687 struct pci_dev *pdev = to_pci_dev(device);
5688 struct net_device *dev = pci_get_drvdata(pdev);
5689 struct rtl8169_private *tp = netdev_priv(dev);
5690
e4fbce74 5691 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 5692}
5693
47145210 5694static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 5695 .suspend = rtl8169_suspend,
5696 .resume = rtl8169_resume,
5697 .freeze = rtl8169_suspend,
5698 .thaw = rtl8169_resume,
5699 .poweroff = rtl8169_suspend,
5700 .restore = rtl8169_resume,
5701 .runtime_suspend = rtl8169_runtime_suspend,
5702 .runtime_resume = rtl8169_runtime_resume,
5703 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 5704};
5705
5706#define RTL8169_PM_OPS (&rtl8169_pm_ops)
5707
5708#else /* !CONFIG_PM */
5709
5710#define RTL8169_PM_OPS NULL
5711
5712#endif /* !CONFIG_PM */
5713
1765f95d
FR		 5714static void rtl_shutdown(struct pci_dev *pdev)
5715{
861ab440 5716 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 5717 struct rtl8169_private *tp = netdev_priv(dev);
5718 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 5719
5720 rtl8169_net_suspend(dev);
1765f95d 5721
cecb5fd7 5722 /* Restore original MAC address */
cc098dc7
IV		 5723 rtl_rar_set(tp, dev->perm_addr);
5724
4bb3f522 5725 spin_lock_irq(&tp->lock);
5726
92fc43b4 5727 rtl8169_hw_reset(tp);
4bb3f522 5728
5729 spin_unlock_irq(&tp->lock);
5730
861ab440 5731 if (system_state == SYSTEM_POWER_OFF) {
aaa89c08
HW		 5732 /* WoL fails with 8168b when the receiver is disabled. */
5733 if ((tp->mac_version == RTL_GIGA_MAC_VER_11 ||
5734 tp->mac_version == RTL_GIGA_MAC_VER_12 ||
5735 tp->mac_version == RTL_GIGA_MAC_VER_17) &&
5736 (tp->features & RTL_FEATURE_WOL)) {
ca52efd5 5737 pci_clear_master(pdev);
5738
5739 RTL_W8(ChipCmd, CmdRxEnb);
5740 /* PCI commit */
5741 RTL_R8(ChipCmd);
5742 }
5743
861ab440
RW		 5744 pci_wake_from_d3(pdev, true);
5745 pci_set_power_state(pdev, PCI_D3hot);
5746 }
5747}
5d06a99f 5748
1da177e4
LT		 5749static struct pci_driver rtl8169_pci_driver = {
5750 .name = MODULENAME,
5751 .id_table = rtl8169_pci_tbl,
5752 .probe = rtl8169_init_one,
5753 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 5754 .shutdown = rtl_shutdown,
861ab440 5755 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 5756};
5757
07d3f51f 5758static int __init rtl8169_init_module(void)
1da177e4 5759{
29917620 5760 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 5761}
5762
07d3f51f 5763static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 5764{
5765 pci_unregister_driver(&rtl8169_pci_driver);
5766}
5767
5768module_init(rtl8169_init_module);
5769module_exit(rtl8169_cleanup_module);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git