[people/ms/u-boot.git] / drivers / net / ravb.c

/*
 * drivers/net/ravb.c
 *     This file is driver for Renesas Ethernet AVB.
 *
 * Copyright (C) 2015-2017  Renesas Electronics Corporation
 *
 * Based on the SuperH Ethernet driver.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <errno.h>
#include <miiphy.h>
#include <malloc.h>
#include <linux/mii.h>
#include <wait_bit.h>
#include <asm/io.h>

/* Registers */
#define RAVB_REG_CCC		0x000
#define RAVB_REG_DBAT		0x004
#define RAVB_REG_CSR		0x00C
#define RAVB_REG_APSR		0x08C
#define RAVB_REG_RCR		0x090
#define RAVB_REG_TGC		0x300
#define RAVB_REG_TCCR		0x304
#define RAVB_REG_RIC0		0x360
#define RAVB_REG_RIC1		0x368
#define RAVB_REG_RIC2		0x370
#define RAVB_REG_TIC		0x378
#define RAVB_REG_ECMR		0x500
#define RAVB_REG_RFLR		0x508
#define RAVB_REG_ECSIPR		0x518
#define RAVB_REG_PIR		0x520
#define RAVB_REG_GECMR		0x5b0
#define RAVB_REG_MAHR		0x5c0
#define RAVB_REG_MALR		0x5c8

#define CCC_OPC_CONFIG		BIT(0)
#define CCC_OPC_OPERATION	BIT(1)
#define CCC_BOC			BIT(20)

#define CSR_OPS			0x0000000F
#define CSR_OPS_CONFIG		BIT(1)

#define TCCR_TSRQ0		BIT(0)

#define RFLR_RFL_MIN		0x05EE

#define PIR_MDI			BIT(3)
#define PIR_MDO			BIT(2)
#define PIR_MMD			BIT(1)
#define PIR_MDC			BIT(0)

#define ECMR_TRCCM		BIT(26)
#define ECMR_RZPF		BIT(20)
#define ECMR_PFR		BIT(18)
#define ECMR_RXF		BIT(17)
#define ECMR_RE			BIT(6)
#define ECMR_TE			BIT(5)
#define ECMR_DM			BIT(1)
#define ECMR_CHG_DM		(ECMR_TRCCM | ECMR_RZPF | ECMR_PFR | ECMR_RXF)

/* DMA Descriptors */
#define RAVB_NUM_BASE_DESC		16
#define RAVB_NUM_TX_DESC		8
#define RAVB_NUM_RX_DESC		8

#define RAVB_TX_QUEUE_OFFSET		0
#define RAVB_RX_QUEUE_OFFSET		4

#define RAVB_DESC_DT(n)			((n) << 28)
#define RAVB_DESC_DT_FSINGLE		RAVB_DESC_DT(0x7)
#define RAVB_DESC_DT_LINKFIX		RAVB_DESC_DT(0x9)
#define RAVB_DESC_DT_EOS		RAVB_DESC_DT(0xa)
#define RAVB_DESC_DT_FEMPTY		RAVB_DESC_DT(0xc)
#define RAVB_DESC_DT_EEMPTY		RAVB_DESC_DT(0x3)
#define RAVB_DESC_DT_MASK		RAVB_DESC_DT(0xf)

#define RAVB_DESC_DS(n)			(((n) & 0xfff) << 0)
#define RAVB_DESC_DS_MASK		0xfff

#define RAVB_RX_DESC_MSC_MC		BIT(23)
#define RAVB_RX_DESC_MSC_CEEF		BIT(22)
#define RAVB_RX_DESC_MSC_CRL		BIT(21)
#define RAVB_RX_DESC_MSC_FRE		BIT(20)
#define RAVB_RX_DESC_MSC_RTLF		BIT(19)
#define RAVB_RX_DESC_MSC_RTSF		BIT(18)
#define RAVB_RX_DESC_MSC_RFE		BIT(17)
#define RAVB_RX_DESC_MSC_CRC		BIT(16)
#define RAVB_RX_DESC_MSC_MASK		(0xff << 16)

#define RAVB_RX_DESC_MSC_RX_ERR_MASK \
	(RAVB_RX_DESC_MSC_CRC | RAVB_RX_DESC_MSC_RFE | RAVB_RX_DESC_MSC_RTLF | \
	 RAVB_RX_DESC_MSC_RTSF | RAVB_RX_DESC_MSC_CEEF)

#define RAVB_TX_TIMEOUT_MS		1000

struct ravb_desc {
	u32	ctrl;
	u32	dptr;
};

struct ravb_rxdesc {
	struct ravb_desc	data;
	struct ravb_desc	link;
	u8			__pad[48];
	u8			packet[PKTSIZE_ALIGN];
};

struct ravb_priv {
	struct ravb_desc	base_desc[RAVB_NUM_BASE_DESC];
	struct ravb_desc	tx_desc[RAVB_NUM_TX_DESC];
	struct ravb_rxdesc	rx_desc[RAVB_NUM_RX_DESC];
	u32			rx_desc_idx;
	u32			tx_desc_idx;

	struct phy_device	*phydev;
	struct mii_dev		*bus;
	void __iomem		*iobase;
	struct clk		clk;
};

static inline void ravb_flush_dcache(u32 addr, u32 len)
{
	flush_dcache_range(addr, addr + len);
}

static inline void ravb_invalidate_dcache(u32 addr, u32 len)
{
	u32 start = addr & ~((uintptr_t)ARCH_DMA_MINALIGN - 1);
	u32 end = roundup(addr + len, ARCH_DMA_MINALIGN);
	invalidate_dcache_range(start, end);
}

static int ravb_send(struct udevice *dev, void *packet, int len)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct ravb_desc *desc = &eth->tx_desc[eth->tx_desc_idx];
	unsigned int start;

	/* Update TX descriptor */
	ravb_flush_dcache((uintptr_t)packet, len);
	memset(desc, 0x0, sizeof(*desc));
	desc->ctrl = RAVB_DESC_DT_FSINGLE | RAVB_DESC_DS(len);
	desc->dptr = (uintptr_t)packet;
	ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));

	/* Restart the transmitter if disabled */
	if (!(readl(eth->iobase + RAVB_REG_TCCR) & TCCR_TSRQ0))
		setbits_le32(eth->iobase + RAVB_REG_TCCR, TCCR_TSRQ0);

	/* Wait until packet is transmitted */
	start = get_timer(0);
	while (get_timer(start) < RAVB_TX_TIMEOUT_MS) {
		ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
		if ((desc->ctrl & RAVB_DESC_DT_MASK) != RAVB_DESC_DT_FSINGLE)
			break;
		udelay(10);
	};

	if (get_timer(start) >= RAVB_TX_TIMEOUT_MS)
		return -ETIMEDOUT;

	eth->tx_desc_idx = (eth->tx_desc_idx + 1) % (RAVB_NUM_TX_DESC - 1);
	return 0;
}

static int ravb_recv(struct udevice *dev, int flags, uchar **packetp)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct ravb_rxdesc *desc = &eth->rx_desc[eth->rx_desc_idx];
	int len;
	u8 *packet;

	/* Check if the rx descriptor is ready */
	ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
	if ((desc->data.ctrl & RAVB_DESC_DT_MASK) == RAVB_DESC_DT_FEMPTY)
		return -EAGAIN;

	/* Check for errors */
	if (desc->data.ctrl & RAVB_RX_DESC_MSC_RX_ERR_MASK) {
		desc->data.ctrl &= ~RAVB_RX_DESC_MSC_MASK;
		return -EAGAIN;
	}

	len = desc->data.ctrl & RAVB_DESC_DS_MASK;
	packet = (u8 *)(uintptr_t)desc->data.dptr;
	ravb_invalidate_dcache((uintptr_t)packet, len);

	*packetp = packet;
	return len;
}

static int ravb_free_pkt(struct udevice *dev, uchar *packet, int length)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct ravb_rxdesc *desc = &eth->rx_desc[eth->rx_desc_idx];

	/* Make current descriptor available again */
	desc->data.ctrl = RAVB_DESC_DT_FEMPTY | RAVB_DESC_DS(PKTSIZE_ALIGN);
	ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));

	/* Point to the next descriptor */
	eth->rx_desc_idx = (eth->rx_desc_idx + 1) % RAVB_NUM_RX_DESC;
	desc = &eth->rx_desc[eth->rx_desc_idx];
	ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));

	return 0;
}

static int ravb_reset(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);

	/* Set config mode */
	writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC);

	/* Check the operating mode is changed to the config mode. */
	return wait_for_bit(dev->name, (void *)eth->iobase + RAVB_REG_CSR,
			    CSR_OPS_CONFIG, true, 100, true);
}

static void ravb_base_desc_init(struct ravb_priv *eth)
{
	const u32 desc_size = RAVB_NUM_BASE_DESC * sizeof(struct ravb_desc);
	int i;

	/* Initialize all descriptors */
	memset(eth->base_desc, 0x0, desc_size);

	for (i = 0; i < RAVB_NUM_BASE_DESC; i++)
		eth->base_desc[i].ctrl = RAVB_DESC_DT_EOS;

	ravb_flush_dcache((uintptr_t)eth->base_desc, desc_size);

	/* Register the descriptor base address table */
	writel((uintptr_t)eth->base_desc, eth->iobase + RAVB_REG_DBAT);
}

static void ravb_tx_desc_init(struct ravb_priv *eth)
{
	const u32 desc_size = RAVB_NUM_TX_DESC * sizeof(struct ravb_desc);
	int i;

	/* Initialize all descriptors */
	memset(eth->tx_desc, 0x0, desc_size);
	eth->tx_desc_idx = 0;

	for (i = 0; i < RAVB_NUM_TX_DESC; i++)
		eth->tx_desc[i].ctrl = RAVB_DESC_DT_EEMPTY;

	/* Mark the end of the descriptors */
	eth->tx_desc[RAVB_NUM_TX_DESC - 1].ctrl = RAVB_DESC_DT_LINKFIX;
	eth->tx_desc[RAVB_NUM_TX_DESC - 1].dptr = (uintptr_t)eth->tx_desc;
	ravb_flush_dcache((uintptr_t)eth->tx_desc, desc_size);

	/* Point the controller to the TX descriptor list. */
	eth->base_desc[RAVB_TX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
	eth->base_desc[RAVB_TX_QUEUE_OFFSET].dptr = (uintptr_t)eth->tx_desc;
	ravb_flush_dcache((uintptr_t)&eth->base_desc[RAVB_TX_QUEUE_OFFSET],
			  sizeof(struct ravb_desc));
}

static void ravb_rx_desc_init(struct ravb_priv *eth)
{
	const u32 desc_size = RAVB_NUM_RX_DESC * sizeof(struct ravb_rxdesc);
	int i;

	/* Initialize all descriptors */
	memset(eth->rx_desc, 0x0, desc_size);
	eth->rx_desc_idx = 0;

	for (i = 0; i < RAVB_NUM_RX_DESC; i++) {
		eth->rx_desc[i].data.ctrl = RAVB_DESC_DT_EEMPTY |
					    RAVB_DESC_DS(PKTSIZE_ALIGN);
		eth->rx_desc[i].data.dptr = (uintptr_t)eth->rx_desc[i].packet;

		eth->rx_desc[i].link.ctrl = RAVB_DESC_DT_LINKFIX;
		eth->rx_desc[i].link.dptr = (uintptr_t)&eth->rx_desc[i + 1];
	}

	/* Mark the end of the descriptors */
	eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.ctrl = RAVB_DESC_DT_LINKFIX;
	eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.dptr = (uintptr_t)eth->rx_desc;
	ravb_flush_dcache((uintptr_t)eth->rx_desc, desc_size);

	/* Point the controller to the rx descriptor list */
	eth->base_desc[RAVB_RX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
	eth->base_desc[RAVB_RX_QUEUE_OFFSET].dptr = (uintptr_t)eth->rx_desc;
	ravb_flush_dcache((uintptr_t)&eth->base_desc[RAVB_RX_QUEUE_OFFSET],
			  sizeof(struct ravb_desc));
}

static int ravb_phy_config(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_platdata(dev);
	struct phy_device *phydev;
	int mask = 0xffffffff, reg;

	phydev = phy_find_by_mask(eth->bus, mask, pdata->phy_interface);
	if (!phydev)
		return -ENODEV;

	phy_connect_dev(phydev, dev);

	eth->phydev = phydev;

	/* 10BASE is not supported for Ethernet AVB MAC */
	phydev->supported &= ~(SUPPORTED_10baseT_Full
			       | SUPPORTED_10baseT_Half);
	if (pdata->max_speed != 1000) {
		phydev->supported &= ~(SUPPORTED_1000baseT_Half
				       | SUPPORTED_1000baseT_Full);
		reg = phy_read(phydev, -1, MII_CTRL1000);
		reg &= ~(BIT(9) | BIT(8));
		phy_write(phydev, -1, MII_CTRL1000, reg);
	}

	phy_config(phydev);

	return 0;
}

/* Set Mac address */
static int ravb_write_hwaddr(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_platdata(dev);
	unsigned char *mac = pdata->enetaddr;

	writel((mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3],
	       eth->iobase + RAVB_REG_MAHR);

	writel((mac[4] << 8) | mac[5], eth->iobase + RAVB_REG_MALR);

	return 0;
}

/* E-MAC init function */
static int ravb_mac_init(struct ravb_priv *eth)
{
	/* Disable MAC Interrupt */
	writel(0, eth->iobase + RAVB_REG_ECSIPR);

	/* Recv frame limit set register */
	writel(RFLR_RFL_MIN, eth->iobase + RAVB_REG_RFLR);

	return 0;
}

/* AVB-DMAC init function */
static int ravb_dmac_init(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_platdata(dev);
	int ret = 0;

	/* Set CONFIG mode */
	ret = ravb_reset(dev);
	if (ret)
		return ret;

	/* Disable all interrupts */
	writel(0, eth->iobase + RAVB_REG_RIC0);
	writel(0, eth->iobase + RAVB_REG_RIC1);
	writel(0, eth->iobase + RAVB_REG_RIC2);
	writel(0, eth->iobase + RAVB_REG_TIC);

	/* Set little endian */
	clrbits_le32(eth->iobase + RAVB_REG_CCC, CCC_BOC);

	/* AVB rx set */
	writel(0x18000001, eth->iobase + RAVB_REG_RCR);

	/* FIFO size set */
	writel(0x00222210, eth->iobase + RAVB_REG_TGC);

	/* Delay CLK: 2ns */
	if (pdata->max_speed == 1000)
		writel(BIT(14), eth->iobase + RAVB_REG_APSR);

	return 0;
}

static int ravb_config(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct phy_device *phy;
	u32 mask = ECMR_CHG_DM | ECMR_RE | ECMR_TE;
	int ret;

	/* Configure AVB-DMAC register */
	ravb_dmac_init(dev);

	/* Configure E-MAC registers */
	ravb_mac_init(eth);
	ravb_write_hwaddr(dev);

	/* Configure phy */
	ret = ravb_phy_config(dev);
	if (ret)
		return ret;

	phy = eth->phydev;

	ret = phy_startup(phy);
	if (ret)
		return ret;

	/* Set the transfer speed */
	if (phy->speed == 100)
		writel(0, eth->iobase + RAVB_REG_GECMR);
	else if (phy->speed == 1000)
		writel(1, eth->iobase + RAVB_REG_GECMR);

	/* Check if full duplex mode is supported by the phy */
	if (phy->duplex)
		mask |= ECMR_DM;

	writel(mask, eth->iobase + RAVB_REG_ECMR);

	phy->drv->writeext(phy, -1, 0x02, 0x08, (0x0f << 5) | 0x19);

	return 0;
}

int ravb_start(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	int ret;

	ret = clk_enable(&eth->clk);
	if (ret)
		return ret;

	ret = ravb_reset(dev);
	if (ret)
		goto err;

	ravb_base_desc_init(eth);
	ravb_tx_desc_init(eth);
	ravb_rx_desc_init(eth);

	ret = ravb_config(dev);
	if (ret)
		goto err;

	/* Setting the control will start the AVB-DMAC process. */
	writel(CCC_OPC_OPERATION, eth->iobase + RAVB_REG_CCC);

	return 0;

err:
	clk_disable(&eth->clk);
	return ret;
}

static void ravb_stop(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);

	ravb_reset(dev);
	clk_disable(&eth->clk);
}

static int ravb_probe(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_platdata(dev);
	struct ravb_priv *eth = dev_get_priv(dev);
	struct mii_dev *mdiodev;
	void __iomem *iobase;
	int ret;

	iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
	eth->iobase = iobase;

	ret = clk_get_by_index(dev, 0, &eth->clk);
	if (ret < 0)
		goto err_mdio_alloc;

	mdiodev = mdio_alloc();
	if (!mdiodev) {
		ret = -ENOMEM;
		goto err_mdio_alloc;
	}

	mdiodev->read = bb_miiphy_read;
	mdiodev->write = bb_miiphy_write;
	bb_miiphy_buses[0].priv = eth;
	snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);

	ret = mdio_register(mdiodev);
	if (ret < 0)
		goto err_mdio_register;

	eth->bus = miiphy_get_dev_by_name(dev->name);

	return 0;

err_mdio_register:
	mdio_free(mdiodev);
err_mdio_alloc:
	unmap_physmem(eth->iobase, MAP_NOCACHE);
	return ret;
}

static int ravb_remove(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);

	free(eth->phydev);
	mdio_unregister(eth->bus);
	mdio_free(eth->bus);
	unmap_physmem(eth->iobase, MAP_NOCACHE);

	return 0;
}

int ravb_bb_init(struct bb_miiphy_bus *bus)
{
	return 0;
}

int ravb_bb_mdio_active(struct bb_miiphy_bus *bus)
{
	struct ravb_priv *eth = bus->priv;

	setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);

	return 0;
}

int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus)
{
	struct ravb_priv *eth = bus->priv;

	clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);

	return 0;
}

int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
{
	struct ravb_priv *eth = bus->priv;

	if (v)
		setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
	else
		clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);

	return 0;
}

int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
{
	struct ravb_priv *eth = bus->priv;

	*v = (readl(eth->iobase + RAVB_REG_PIR) & PIR_MDI) >> 3;

	return 0;
}

int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
{
	struct ravb_priv *eth = bus->priv;

	if (v)
		setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
	else
		clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);

	return 0;
}

int ravb_bb_delay(struct bb_miiphy_bus *bus)
{
	udelay(10);

	return 0;
}

struct bb_miiphy_bus bb_miiphy_buses[] = {
	{
		.name		= "ravb",
		.init		= ravb_bb_init,
		.mdio_active	= ravb_bb_mdio_active,
		.mdio_tristate	= ravb_bb_mdio_tristate,
		.set_mdio	= ravb_bb_set_mdio,
		.get_mdio	= ravb_bb_get_mdio,
		.set_mdc	= ravb_bb_set_mdc,
		.delay		= ravb_bb_delay,
	},
};
int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);

static const struct eth_ops ravb_ops = {
	.start			= ravb_start,
	.send			= ravb_send,
	.recv			= ravb_recv,
	.free_pkt		= ravb_free_pkt,
	.stop			= ravb_stop,
	.write_hwaddr		= ravb_write_hwaddr,
};

int ravb_ofdata_to_platdata(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_platdata(dev);
	const char *phy_mode;
	const fdt32_t *cell;
	int ret = 0;

	pdata->iobase = devfdt_get_addr(dev);
	pdata->phy_interface = -1;
	phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
			       NULL);
	if (phy_mode)
		pdata->phy_interface = phy_get_interface_by_name(phy_mode);
	if (pdata->phy_interface == -1) {
		debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
		return -EINVAL;
	}

	pdata->max_speed = 1000;
	cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
	if (cell)
		pdata->max_speed = fdt32_to_cpu(*cell);

	sprintf(bb_miiphy_buses[0].name, dev->name);

	return ret;
}

static const struct udevice_id ravb_ids[] = {
	{ .compatible = "renesas,etheravb-r8a7795" },
	{ .compatible = "renesas,etheravb-r8a7796" },
	{ .compatible = "renesas,etheravb-rcar-gen3" },
	{ }
};

U_BOOT_DRIVER(eth_ravb) = {
	.name		= "ravb",
	.id		= UCLASS_ETH,
	.of_match	= ravb_ids,
	.ofdata_to_platdata = ravb_ofdata_to_platdata,
	.probe		= ravb_probe,
	.remove		= ravb_remove,
	.ops		= &ravb_ops,
	.priv_auto_alloc_size = sizeof(struct ravb_priv),
	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
	.flags		= DM_FLAG_ALLOC_PRIV_DMA,
};
Commit	Line	Data
8ae51b6f MV	1	/*
	2	* drivers/net/ravb.c
	3	* This file is driver for Renesas Ethernet AVB.
	4	*
	5	* Copyright (C) 2015-2017 Renesas Electronics Corporation
	6	*
	7	* Based on the SuperH Ethernet driver.
	8	*
	9	* SPDX-License-Identifier: GPL-2.0+
	10	*/
	11
	12	#include <common.h>
1fea9e25	13	#include <clk.h>
8ae51b6f MV	14	#include <dm.h>
	15	#include <errno.h>
	16	#include <miiphy.h>
	17	#include <malloc.h>
	18	#include <linux/mii.h>
	19	#include <wait_bit.h>
	20	#include <asm/io.h>
	21
	22	/* Registers */
	23	#define RAVB_REG_CCC 0x000
	24	#define RAVB_REG_DBAT 0x004
	25	#define RAVB_REG_CSR 0x00C
	26	#define RAVB_REG_APSR 0x08C
	27	#define RAVB_REG_RCR 0x090
	28	#define RAVB_REG_TGC 0x300
	29	#define RAVB_REG_TCCR 0x304
	30	#define RAVB_REG_RIC0 0x360
	31	#define RAVB_REG_RIC1 0x368
	32	#define RAVB_REG_RIC2 0x370
	33	#define RAVB_REG_TIC 0x378
	34	#define RAVB_REG_ECMR 0x500
	35	#define RAVB_REG_RFLR 0x508
	36	#define RAVB_REG_ECSIPR 0x518
	37	#define RAVB_REG_PIR 0x520
	38	#define RAVB_REG_GECMR 0x5b0
	39	#define RAVB_REG_MAHR 0x5c0
	40	#define RAVB_REG_MALR 0x5c8
	41
	42	#define CCC_OPC_CONFIG BIT(0)
	43	#define CCC_OPC_OPERATION BIT(1)
	44	#define CCC_BOC BIT(20)
	45
	46	#define CSR_OPS 0x0000000F
	47	#define CSR_OPS_CONFIG BIT(1)
	48
	49	#define TCCR_TSRQ0 BIT(0)
	50
	51	#define RFLR_RFL_MIN 0x05EE
	52
	53	#define PIR_MDI BIT(3)
	54	#define PIR_MDO BIT(2)
	55	#define PIR_MMD BIT(1)
	56	#define PIR_MDC BIT(0)
	57
	58	#define ECMR_TRCCM BIT(26)
	59	#define ECMR_RZPF BIT(20)
	60	#define ECMR_PFR BIT(18)
	61	#define ECMR_RXF BIT(17)
	62	#define ECMR_RE BIT(6)
	63	#define ECMR_TE BIT(5)
	64	#define ECMR_DM BIT(1)
	65	#define ECMR_CHG_DM (ECMR_TRCCM \| ECMR_RZPF \| ECMR_PFR \| ECMR_RXF)
	66
	67	/* DMA Descriptors */
	68	#define RAVB_NUM_BASE_DESC 16
	69	#define RAVB_NUM_TX_DESC 8
	70	#define RAVB_NUM_RX_DESC 8
	71
	72	#define RAVB_TX_QUEUE_OFFSET 0
	73	#define RAVB_RX_QUEUE_OFFSET 4
	74
	75	#define RAVB_DESC_DT(n) ((n) << 28)
	76	#define RAVB_DESC_DT_FSINGLE RAVB_DESC_DT(0x7)
	77	#define RAVB_DESC_DT_LINKFIX RAVB_DESC_DT(0x9)
78	#define RAVB_DESC_DT_EOS RAVB_DESC_DT(0xa)
79	#define RAVB_DESC_DT_FEMPTY RAVB_DESC_DT(0xc)
80	#define RAVB_DESC_DT_EEMPTY RAVB_DESC_DT(0x3)
81	#define RAVB_DESC_DT_MASK RAVB_DESC_DT(0xf)
82
83	#define RAVB_DESC_DS(n) (((n) & 0xfff) << 0)
84	#define RAVB_DESC_DS_MASK 0xfff
85
86	#define RAVB_RX_DESC_MSC_MC BIT(23)
87	#define RAVB_RX_DESC_MSC_CEEF BIT(22)
88	#define RAVB_RX_DESC_MSC_CRL BIT(21)
89	#define RAVB_RX_DESC_MSC_FRE BIT(20)
90	#define RAVB_RX_DESC_MSC_RTLF BIT(19)
91	#define RAVB_RX_DESC_MSC_RTSF BIT(18)
92	#define RAVB_RX_DESC_MSC_RFE BIT(17)
93	#define RAVB_RX_DESC_MSC_CRC BIT(16)
94	#define RAVB_RX_DESC_MSC_MASK (0xff << 16)
95
96	#define RAVB_RX_DESC_MSC_RX_ERR_MASK \
97	(RAVB_RX_DESC_MSC_CRC \| RAVB_RX_DESC_MSC_RFE \| RAVB_RX_DESC_MSC_RTLF \| \
98	RAVB_RX_DESC_MSC_RTSF \| RAVB_RX_DESC_MSC_CEEF)
99
100	#define RAVB_TX_TIMEOUT_MS 1000
101
102	struct ravb_desc {
103	u32 ctrl;
104	u32 dptr;
105	};
106
107	struct ravb_rxdesc {
108	struct ravb_desc data;
109	struct ravb_desc link;
110	u8 __pad[48];
111	u8 packet[PKTSIZE_ALIGN];
112	};
113
114	struct ravb_priv {
115	struct ravb_desc base_desc[RAVB_NUM_BASE_DESC];
116	struct ravb_desc tx_desc[RAVB_NUM_TX_DESC];
117	struct ravb_rxdesc rx_desc[RAVB_NUM_RX_DESC];
118	u32 rx_desc_idx;
119	u32 tx_desc_idx;
120
121	struct phy_device *phydev;
122	struct mii_dev *bus;
123	void __iomem *iobase;
1fea9e25	124	struct clk clk;
8ae51b6f MV	125	};
	126
	127	static inline void ravb_flush_dcache(u32 addr, u32 len)
	128	{
	129	flush_dcache_range(addr, addr + len);
	130	}
	131
	132	static inline void ravb_invalidate_dcache(u32 addr, u32 len)
	133	{
	134	u32 start = addr & ~((uintptr_t)ARCH_DMA_MINALIGN - 1);
	135	u32 end = roundup(addr + len, ARCH_DMA_MINALIGN);
	136	invalidate_dcache_range(start, end);
	137	}
	138
	139	static int ravb_send(struct udevice dev, void packet, int len)
	140	{
	141	struct ravb_priv *eth = dev_get_priv(dev);
	142	struct ravb_desc *desc = &eth->tx_desc[eth->tx_desc_idx];
	143	unsigned int start;
	144
	145	/* Update TX descriptor */
	146	ravb_flush_dcache((uintptr_t)packet, len);
	147	memset(desc, 0x0, sizeof(*desc));
	148	desc->ctrl = RAVB_DESC_DT_FSINGLE \| RAVB_DESC_DS(len);
	149	desc->dptr = (uintptr_t)packet;
	150	ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));
	151
	152	/* Restart the transmitter if disabled */
	153	if (!(readl(eth->iobase + RAVB_REG_TCCR) & TCCR_TSRQ0))
	154	setbits_le32(eth->iobase + RAVB_REG_TCCR, TCCR_TSRQ0);
	155
	156	/* Wait until packet is transmitted */
	157	start = get_timer(0);
	158	while (get_timer(start) < RAVB_TX_TIMEOUT_MS) {
	159	ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
	160	if ((desc->ctrl & RAVB_DESC_DT_MASK) != RAVB_DESC_DT_FSINGLE)
	161	break;
	162	udelay(10);
	163	};
	164
	165	if (get_timer(start) >= RAVB_TX_TIMEOUT_MS)
	166	return -ETIMEDOUT;
	167
	168	eth->tx_desc_idx = (eth->tx_desc_idx + 1) % (RAVB_NUM_TX_DESC - 1);
	169	return 0;
	170	}
	171
	172	static int ravb_recv(struct udevice dev, int flags, uchar *packetp)
	173	{
	174	struct ravb_priv *eth = dev_get_priv(dev);
	175	struct ravb_rxdesc *desc = &eth->rx_desc[eth->rx_desc_idx];
	176	int len;
	177	u8 *packet;
	178
	179	/* Check if the rx descriptor is ready */
	180	ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
	181	if ((desc->data.ctrl & RAVB_DESC_DT_MASK) == RAVB_DESC_DT_FEMPTY)
	182	return -EAGAIN;
	183
	184	/* Check for errors */
	185	if (desc->data.ctrl & RAVB_RX_DESC_MSC_RX_ERR_MASK) {
	186	desc->data.ctrl &= ~RAVB_RX_DESC_MSC_MASK;
	187	return -EAGAIN;
	188	}
189
190	len = desc->data.ctrl & RAVB_DESC_DS_MASK;
191	packet = (u8 *)(uintptr_t)desc->data.dptr;
192	ravb_invalidate_dcache((uintptr_t)packet, len);
193
194	*packetp = packet;
195	return len;
196	}
197
198	static int ravb_free_pkt(struct udevice dev, uchar packet, int length)
199	{
200	struct ravb_priv *eth = dev_get_priv(dev);
201	struct ravb_rxdesc *desc = &eth->rx_desc[eth->rx_desc_idx];
202
203	/* Make current descriptor available again */
204	desc->data.ctrl = RAVB_DESC_DT_FEMPTY \| RAVB_DESC_DS(PKTSIZE_ALIGN);
205	ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));
206
207	/* Point to the next descriptor */
208	eth->rx_desc_idx = (eth->rx_desc_idx + 1) % RAVB_NUM_RX_DESC;
209	desc = &eth->rx_desc[eth->rx_desc_idx];
210	ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
211
212	return 0;
213	}
214
215	static int ravb_reset(struct udevice *dev)
216	{
217	struct ravb_priv *eth = dev_get_priv(dev);
218
219	/* Set config mode */
220	writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC);
221
222	/* Check the operating mode is changed to the config mode. */
223	return wait_for_bit(dev->name, (void *)eth->iobase + RAVB_REG_CSR,
224	CSR_OPS_CONFIG, true, 100, true);
225	}
226
227	static void ravb_base_desc_init(struct ravb_priv *eth)
228	{
229	const u32 desc_size = RAVB_NUM_BASE_DESC * sizeof(struct ravb_desc);
230	int i;
231
232	/* Initialize all descriptors */
233	memset(eth->base_desc, 0x0, desc_size);
234
235	for (i = 0; i < RAVB_NUM_BASE_DESC; i++)
236	eth->base_desc[i].ctrl = RAVB_DESC_DT_EOS;
237
238	ravb_flush_dcache((uintptr_t)eth->base_desc, desc_size);
239
240	/* Register the descriptor base address table */
241	writel((uintptr_t)eth->base_desc, eth->iobase + RAVB_REG_DBAT);
242	}
243
244	static void ravb_tx_desc_init(struct ravb_priv *eth)
245	{
246	const u32 desc_size = RAVB_NUM_TX_DESC * sizeof(struct ravb_desc);
247	int i;
248
249	/* Initialize all descriptors */
250	memset(eth->tx_desc, 0x0, desc_size);
251	eth->tx_desc_idx = 0;
252
253	for (i = 0; i < RAVB_NUM_TX_DESC; i++)
254	eth->tx_desc[i].ctrl = RAVB_DESC_DT_EEMPTY;
255
256	/* Mark the end of the descriptors */
257	eth->tx_desc[RAVB_NUM_TX_DESC - 1].ctrl = RAVB_DESC_DT_LINKFIX;
258	eth->tx_desc[RAVB_NUM_TX_DESC - 1].dptr = (uintptr_t)eth->tx_desc;
259	ravb_flush_dcache((uintptr_t)eth->tx_desc, desc_size);
260
261	/* Point the controller to the TX descriptor list. */
262	eth->base_desc[RAVB_TX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
263	eth->base_desc[RAVB_TX_QUEUE_OFFSET].dptr = (uintptr_t)eth->tx_desc;
264	ravb_flush_dcache((uintptr_t)&eth->base_desc[RAVB_TX_QUEUE_OFFSET],
265	sizeof(struct ravb_desc));
266	}
267
268	static void ravb_rx_desc_init(struct ravb_priv *eth)
269	{
270	const u32 desc_size = RAVB_NUM_RX_DESC * sizeof(struct ravb_rxdesc);
271	int i;
272
273	/* Initialize all descriptors */
274	memset(eth->rx_desc, 0x0, desc_size);
275	eth->rx_desc_idx = 0;
276
277	for (i = 0; i < RAVB_NUM_RX_DESC; i++) {
278	eth->rx_desc[i].data.ctrl = RAVB_DESC_DT_EEMPTY \|
279	RAVB_DESC_DS(PKTSIZE_ALIGN);
280	eth->rx_desc[i].data.dptr = (uintptr_t)eth->rx_desc[i].packet;
281
282	eth->rx_desc[i].link.ctrl = RAVB_DESC_DT_LINKFIX;
283	eth->rx_desc[i].link.dptr = (uintptr_t)&eth->rx_desc[i + 1];
284	}
285
286	/* Mark the end of the descriptors */
287	eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.ctrl = RAVB_DESC_DT_LINKFIX;
288	eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.dptr = (uintptr_t)eth->rx_desc;
289	ravb_flush_dcache((uintptr_t)eth->rx_desc, desc_size);
290
291	/* Point the controller to the rx descriptor list */
292	eth->base_desc[RAVB_RX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
293	eth->base_desc[RAVB_RX_QUEUE_OFFSET].dptr = (uintptr_t)eth->rx_desc;
294	ravb_flush_dcache((uintptr_t)&eth->base_desc[RAVB_RX_QUEUE_OFFSET],
295	sizeof(struct ravb_desc));
296	}
297
298	static int ravb_phy_config(struct udevice *dev)
299	{
300	struct ravb_priv *eth = dev_get_priv(dev);
301	struct eth_pdata *pdata = dev_get_platdata(dev);
302	struct phy_device *phydev;
e821a7bd	303	int mask = 0xffffffff, reg;
8ae51b6f	304
e821a7bd	305	phydev = phy_find_by_mask(eth->bus, mask, pdata->phy_interface);
8ae51b6f MV	306	if (!phydev)
	307	return -ENODEV;
	308
e821a7bd MV	309	phy_connect_dev(phydev, dev);
e821a7bd MV	310
8ae51b6f MV	311	eth->phydev = phydev;
	312
	313	/* 10BASE is not supported for Ethernet AVB MAC */
	314	phydev->supported &= ~(SUPPORTED_10baseT_Full
	315	\| SUPPORTED_10baseT_Half);
	316	if (pdata->max_speed != 1000) {
	317	phydev->supported &= ~(SUPPORTED_1000baseT_Half
	318	\| SUPPORTED_1000baseT_Full);
	319	reg = phy_read(phydev, -1, MII_CTRL1000);
	320	reg &= ~(BIT(9) \| BIT(8));
	321	phy_write(phydev, -1, MII_CTRL1000, reg);
	322	}
	323
	324	phy_config(phydev);
	325
	326	return 0;
	327	}
	328
	329	/* Set Mac address */
	330	static int ravb_write_hwaddr(struct udevice *dev)
	331	{
	332	struct ravb_priv *eth = dev_get_priv(dev);
	333	struct eth_pdata *pdata = dev_get_platdata(dev);
	334	unsigned char *mac = pdata->enetaddr;
	335
	336	writel((mac[0] << 24) \| (mac[1] << 16) \| (mac[2] << 8) \| mac[3],
	337	eth->iobase + RAVB_REG_MAHR);
	338
	339	writel((mac[4] << 8) \| mac[5], eth->iobase + RAVB_REG_MALR);
	340
	341	return 0;
	342	}
	343
	344	/* E-MAC init function */
	345	static int ravb_mac_init(struct ravb_priv *eth)
	346	{
	347	/* Disable MAC Interrupt */
	348	writel(0, eth->iobase + RAVB_REG_ECSIPR);
	349
	350	/* Recv frame limit set register */
	351	writel(RFLR_RFL_MIN, eth->iobase + RAVB_REG_RFLR);
	352
	353	return 0;
	354	}
	355
	356	/* AVB-DMAC init function */
	357	static int ravb_dmac_init(struct udevice *dev)
	358	{
	359	struct ravb_priv *eth = dev_get_priv(dev);
	360	struct eth_pdata *pdata = dev_get_platdata(dev);
	361	int ret = 0;
	362
	363	/* Set CONFIG mode */
	364	ret = ravb_reset(dev);
	365	if (ret)
	366	return ret;
	367
	368	/* Disable all interrupts */
	369	writel(0, eth->iobase + RAVB_REG_RIC0);
	370	writel(0, eth->iobase + RAVB_REG_RIC1);
	371	writel(0, eth->iobase + RAVB_REG_RIC2);
	372	writel(0, eth->iobase + RAVB_REG_TIC);
	373
	374	/* Set little endian */
375	clrbits_le32(eth->iobase + RAVB_REG_CCC, CCC_BOC);
376
377	/* AVB rx set */
378	writel(0x18000001, eth->iobase + RAVB_REG_RCR);
379
380	/* FIFO size set */
381	writel(0x00222210, eth->iobase + RAVB_REG_TGC);
382
383	/* Delay CLK: 2ns */
384	if (pdata->max_speed == 1000)
385	writel(BIT(14), eth->iobase + RAVB_REG_APSR);
386
387	return 0;
388	}
389
390	static int ravb_config(struct udevice *dev)
391	{
392	struct ravb_priv *eth = dev_get_priv(dev);
393	struct phy_device *phy;
394	u32 mask = ECMR_CHG_DM \| ECMR_RE \| ECMR_TE;
395	int ret;
396
397	/* Configure AVB-DMAC register */
398	ravb_dmac_init(dev);
399
400	/* Configure E-MAC registers */
401	ravb_mac_init(eth);
402	ravb_write_hwaddr(dev);
403
404	/* Configure phy */
405	ret = ravb_phy_config(dev);
406	if (ret)
407	return ret;
408
409	phy = eth->phydev;
410
411	ret = phy_startup(phy);
412	if (ret)
413	return ret;
414
415	/* Set the transfer speed */
416	if (phy->speed == 100)
417	writel(0, eth->iobase + RAVB_REG_GECMR);
418	else if (phy->speed == 1000)
419	writel(1, eth->iobase + RAVB_REG_GECMR);
420
421	/* Check if full duplex mode is supported by the phy */
422	if (phy->duplex)
423	mask \|= ECMR_DM;
424
425	writel(mask, eth->iobase + RAVB_REG_ECMR);
426
427	phy->drv->writeext(phy, -1, 0x02, 0x08, (0x0f << 5) \| 0x19);
428
429	return 0;
430	}
431
432	int ravb_start(struct udevice *dev)
433	{
434	struct ravb_priv *eth = dev_get_priv(dev);
435	int ret;
436
1fea9e25	437	ret = clk_enable(&eth->clk);
8ae51b6f MV	438	if (ret)
	439	return ret;
	440
1fea9e25 MV	441	ret = ravb_reset(dev);
	442	if (ret)
	443	goto err;
	444
8ae51b6f MV	445	ravb_base_desc_init(eth);
	446	ravb_tx_desc_init(eth);
	447	ravb_rx_desc_init(eth);
	448
	449	ret = ravb_config(dev);
	450	if (ret)
1fea9e25	451	goto err;
8ae51b6f MV	452
	453	/* Setting the control will start the AVB-DMAC process. */
	454	writel(CCC_OPC_OPERATION, eth->iobase + RAVB_REG_CCC);
	455
	456	return 0;
1fea9e25 MV	457
	458	err:
	459	clk_disable(&eth->clk);
	460	return ret;
8ae51b6f MV	461	}
	462
	463	static void ravb_stop(struct udevice *dev)
	464	{
1fea9e25 MV	465	struct ravb_priv *eth = dev_get_priv(dev);
1fea9e25 MV	466
8ae51b6f	467	ravb_reset(dev);
1fea9e25	468	clk_disable(&eth->clk);
8ae51b6f MV	469	}
	470
	471	static int ravb_probe(struct udevice *dev)
	472	{
	473	struct eth_pdata *pdata = dev_get_platdata(dev);
	474	struct ravb_priv *eth = dev_get_priv(dev);
	475	struct mii_dev *mdiodev;
	476	void __iomem *iobase;
	477	int ret;
	478
	479	iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
	480	eth->iobase = iobase;
	481
1fea9e25 MV	482	ret = clk_get_by_index(dev, 0, &eth->clk);
	483	if (ret < 0)
	484	goto err_mdio_alloc;
	485
8ae51b6f MV	486	mdiodev = mdio_alloc();
	487	if (!mdiodev) {
	488	ret = -ENOMEM;
	489	goto err_mdio_alloc;
	490	}
	491
	492	mdiodev->read = bb_miiphy_read;
	493	mdiodev->write = bb_miiphy_write;
	494	bb_miiphy_buses[0].priv = eth;
	495	snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);
	496
	497	ret = mdio_register(mdiodev);
	498	if (ret < 0)
	499	goto err_mdio_register;
	500
	501	eth->bus = miiphy_get_dev_by_name(dev->name);
	502
	503	return 0;
	504
	505	err_mdio_register:
	506	mdio_free(mdiodev);
	507	err_mdio_alloc:
	508	unmap_physmem(eth->iobase, MAP_NOCACHE);
	509	return ret;
	510	}
	511
	512	static int ravb_remove(struct udevice *dev)
	513	{
	514	struct ravb_priv *eth = dev_get_priv(dev);
	515
	516	free(eth->phydev);
	517	mdio_unregister(eth->bus);
	518	mdio_free(eth->bus);
	519	unmap_physmem(eth->iobase, MAP_NOCACHE);
	520
	521	return 0;
	522	}
	523
	524	int ravb_bb_init(struct bb_miiphy_bus *bus)
	525	{
	526	return 0;
	527	}
	528
	529	int ravb_bb_mdio_active(struct bb_miiphy_bus *bus)
	530	{
	531	struct ravb_priv *eth = bus->priv;
	532
	533	setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
	534
	535	return 0;
	536	}
	537
	538	int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus)
	539	{
	540	struct ravb_priv *eth = bus->priv;
	541
	542	clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
	543
	544	return 0;
	545	}
	546
	547	int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
	548	{
	549	struct ravb_priv *eth = bus->priv;
550
551	if (v)
552	setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
553	else
554	clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
555
556	return 0;
557	}
558
559	int ravb_bb_get_mdio(struct bb_miiphy_bus bus, int v)
560	{
561	struct ravb_priv *eth = bus->priv;
562
563	*v = (readl(eth->iobase + RAVB_REG_PIR) & PIR_MDI) >> 3;
564
565	return 0;
566	}
567
568	int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
569	{
570	struct ravb_priv *eth = bus->priv;
571
572	if (v)
573	setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
574	else
575	clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
576
577	return 0;
578	}
579
580	int ravb_bb_delay(struct bb_miiphy_bus *bus)
581	{
582	udelay(10);
583
584	return 0;
585	}
586
587	struct bb_miiphy_bus bb_miiphy_buses[] = {
588	{
589	.name = "ravb",
590	.init = ravb_bb_init,
591	.mdio_active = ravb_bb_mdio_active,
592	.mdio_tristate = ravb_bb_mdio_tristate,
593	.set_mdio = ravb_bb_set_mdio,
594	.get_mdio = ravb_bb_get_mdio,
595	.set_mdc = ravb_bb_set_mdc,
596	.delay = ravb_bb_delay,
597	},
598	};
599	int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
600
601	static const struct eth_ops ravb_ops = {
602	.start = ravb_start,
603	.send = ravb_send,
604	.recv = ravb_recv,
605	.free_pkt = ravb_free_pkt,
606	.stop = ravb_stop,
607	.write_hwaddr = ravb_write_hwaddr,
608	};
609
5ee8b4d7 MV	610	int ravb_ofdata_to_platdata(struct udevice *dev)
	611	{
	612	struct eth_pdata *pdata = dev_get_platdata(dev);
	613	const char *phy_mode;
	614	const fdt32_t *cell;
	615	int ret = 0;
	616
	617	pdata->iobase = devfdt_get_addr(dev);
	618	pdata->phy_interface = -1;
	619	phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
	620	NULL);
	621	if (phy_mode)
	622	pdata->phy_interface = phy_get_interface_by_name(phy_mode);
	623	if (pdata->phy_interface == -1) {
	624	debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
	625	return -EINVAL;
	626	}
	627
	628	pdata->max_speed = 1000;
	629	cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
	630	if (cell)
	631	pdata->max_speed = fdt32_to_cpu(*cell);
	632
	633	sprintf(bb_miiphy_buses[0].name, dev->name);
	634
	635	return ret;
	636	}
	637
	638	static const struct udevice_id ravb_ids[] = {
	639	{ .compatible = "renesas,etheravb-r8a7795" },
	640	{ .compatible = "renesas,etheravb-r8a7796" },
	641	{ .compatible = "renesas,etheravb-rcar-gen3" },
	642	{ }
	643	};
	644
8ae51b6f MV	645	U_BOOT_DRIVER(eth_ravb) = {
	646	.name = "ravb",
	647	.id = UCLASS_ETH,
5ee8b4d7 MV	648	.of_match = ravb_ids,
5ee8b4d7 MV	649	.ofdata_to_platdata = ravb_ofdata_to_platdata,
8ae51b6f MV	650	.probe = ravb_probe,
	651	.remove = ravb_remove,
	652	.ops = &ravb_ops,
	653	.priv_auto_alloc_size = sizeof(struct ravb_priv),
	654	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
	655	.flags = DM_FLAG_ALLOC_PRIV_DMA,
	656	};