[thirdparty/u-boot.git] / drivers / net / ravb.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * drivers/net/ravb.c
 *     This file is driver for Renesas Ethernet AVB.
 *
 * Copyright (C) 2015-2017  Renesas Electronics Corporation
 *
 * Based on the SuperH Ethernet driver.
 */

#include <common.h>
#include <clk.h>
#include <cpu_func.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
#include <miiphy.h>
#include <malloc.h>
#include <asm/cache.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/mii.h>
#include <wait_bit.h>
#include <asm/io.h>
#include <asm/global_data.h>
#include <asm/gpio.h>

/* Registers */
#define RAVB_REG_CCC		0x000
#define RAVB_REG_DBAT		0x004
#define RAVB_REG_CSR		0x00C
#define RAVB_REG_APSR		0x08C
#define RAVB_REG_RCR		0x090
#define RAVB_REG_TGC		0x300
#define RAVB_REG_TCCR		0x304
#define RAVB_REG_RIC0		0x360
#define RAVB_REG_RIC1		0x368
#define RAVB_REG_RIC2		0x370
#define RAVB_REG_TIC		0x378
#define RAVB_REG_ECMR		0x500
#define RAVB_REG_RFLR		0x508
#define RAVB_REG_ECSIPR		0x518
#define RAVB_REG_PIR		0x520
#define RAVB_REG_GECMR		0x5b0
#define RAVB_REG_MAHR		0x5c0
#define RAVB_REG_MALR		0x5c8

#define CCC_OPC_CONFIG		BIT(0)
#define CCC_OPC_OPERATION	BIT(1)
#define CCC_BOC			BIT(20)

#define CSR_OPS			0x0000000F
#define CSR_OPS_CONFIG		BIT(1)

#define APSR_RDM		BIT(13)
#define APSR_TDM		BIT(14)

#define TCCR_TSRQ0		BIT(0)

#define RFLR_RFL_MIN		0x05EE

#define PIR_MDI			BIT(3)
#define PIR_MDO			BIT(2)
#define PIR_MMD			BIT(1)
#define PIR_MDC			BIT(0)

#define ECMR_TRCCM		BIT(26)
#define ECMR_RZPF		BIT(20)
#define ECMR_PFR		BIT(18)
#define ECMR_RXF		BIT(17)
#define ECMR_RE			BIT(6)
#define ECMR_TE			BIT(5)
#define ECMR_DM			BIT(1)
#define ECMR_CHG_DM		(ECMR_TRCCM | ECMR_RZPF | ECMR_PFR | ECMR_RXF)

/* DMA Descriptors */
#define RAVB_NUM_BASE_DESC		16
#define RAVB_NUM_TX_DESC		8
#define RAVB_NUM_RX_DESC		8

#define RAVB_TX_QUEUE_OFFSET		0
#define RAVB_RX_QUEUE_OFFSET		4

#define RAVB_DESC_DT(n)			((n) << 28)
#define RAVB_DESC_DT_FSINGLE		RAVB_DESC_DT(0x7)
#define RAVB_DESC_DT_LINKFIX		RAVB_DESC_DT(0x9)
#define RAVB_DESC_DT_EOS		RAVB_DESC_DT(0xa)
#define RAVB_DESC_DT_FEMPTY		RAVB_DESC_DT(0xc)
#define RAVB_DESC_DT_EEMPTY		RAVB_DESC_DT(0x3)
#define RAVB_DESC_DT_MASK		RAVB_DESC_DT(0xf)

#define RAVB_DESC_DS(n)			(((n) & 0xfff) << 0)
#define RAVB_DESC_DS_MASK		0xfff

#define RAVB_RX_DESC_MSC_MC		BIT(23)
#define RAVB_RX_DESC_MSC_CEEF		BIT(22)
#define RAVB_RX_DESC_MSC_CRL		BIT(21)
#define RAVB_RX_DESC_MSC_FRE		BIT(20)
#define RAVB_RX_DESC_MSC_RTLF		BIT(19)
#define RAVB_RX_DESC_MSC_RTSF		BIT(18)
#define RAVB_RX_DESC_MSC_RFE		BIT(17)
#define RAVB_RX_DESC_MSC_CRC		BIT(16)
#define RAVB_RX_DESC_MSC_MASK		(0xff << 16)

#define RAVB_RX_DESC_MSC_RX_ERR_MASK \
	(RAVB_RX_DESC_MSC_CRC | RAVB_RX_DESC_MSC_RFE | RAVB_RX_DESC_MSC_RTLF | \
	 RAVB_RX_DESC_MSC_RTSF | RAVB_RX_DESC_MSC_CEEF)

#define RAVB_TX_TIMEOUT_MS		1000

struct ravb_desc {
	u32	ctrl;
	u32	dptr;
};

struct ravb_rxdesc {
	struct ravb_desc	data;
	struct ravb_desc	link;
	u8			__pad[48];
	u8			packet[PKTSIZE_ALIGN];
};

struct ravb_priv {
	struct ravb_desc	base_desc[RAVB_NUM_BASE_DESC];
	struct ravb_desc	tx_desc[RAVB_NUM_TX_DESC];
	struct ravb_rxdesc	rx_desc[RAVB_NUM_RX_DESC];
	u32			rx_desc_idx;
	u32			tx_desc_idx;

	struct phy_device	*phydev;
	struct mii_dev		*bus;
	void __iomem		*iobase;
	struct clk_bulk		clks;
	struct gpio_desc	reset_gpio;
};

static inline void ravb_flush_dcache(u32 addr, u32 len)
{
	flush_dcache_range(addr, addr + len);
}

static inline void ravb_invalidate_dcache(u32 addr, u32 len)
{
	u32 start = addr & ~((uintptr_t)ARCH_DMA_MINALIGN - 1);
	u32 end = roundup(addr + len, ARCH_DMA_MINALIGN);
	invalidate_dcache_range(start, end);
}

static int ravb_send(struct udevice *dev, void *packet, int len)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct ravb_desc *desc = &eth->tx_desc[eth->tx_desc_idx];
	unsigned int start;

	/* Update TX descriptor */
	ravb_flush_dcache((uintptr_t)packet, len);
	memset(desc, 0x0, sizeof(*desc));
	desc->ctrl = RAVB_DESC_DT_FSINGLE | RAVB_DESC_DS(len);
	desc->dptr = (uintptr_t)packet;
	ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));

	/* Restart the transmitter if disabled */
	if (!(readl(eth->iobase + RAVB_REG_TCCR) & TCCR_TSRQ0))
		setbits_le32(eth->iobase + RAVB_REG_TCCR, TCCR_TSRQ0);

	/* Wait until packet is transmitted */
	start = get_timer(0);
	while (get_timer(start) < RAVB_TX_TIMEOUT_MS) {
		ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
		if ((desc->ctrl & RAVB_DESC_DT_MASK) != RAVB_DESC_DT_FSINGLE)
			break;
		udelay(10);
	};

	if (get_timer(start) >= RAVB_TX_TIMEOUT_MS)
		return -ETIMEDOUT;

	eth->tx_desc_idx = (eth->tx_desc_idx + 1) % (RAVB_NUM_TX_DESC - 1);
	return 0;
}

static int ravb_recv(struct udevice *dev, int flags, uchar **packetp)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct ravb_rxdesc *desc = &eth->rx_desc[eth->rx_desc_idx];
	int len;
	u8 *packet;

	/* Check if the rx descriptor is ready */
	ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
	if ((desc->data.ctrl & RAVB_DESC_DT_MASK) == RAVB_DESC_DT_FEMPTY)
		return -EAGAIN;

	/* Check for errors */
	if (desc->data.ctrl & RAVB_RX_DESC_MSC_RX_ERR_MASK) {
		desc->data.ctrl &= ~RAVB_RX_DESC_MSC_MASK;
		return -EAGAIN;
	}

	len = desc->data.ctrl & RAVB_DESC_DS_MASK;
	packet = (u8 *)(uintptr_t)desc->data.dptr;
	ravb_invalidate_dcache((uintptr_t)packet, len);

	*packetp = packet;
	return len;
}

static int ravb_free_pkt(struct udevice *dev, uchar *packet, int length)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct ravb_rxdesc *desc = &eth->rx_desc[eth->rx_desc_idx];

	/* Make current descriptor available again */
	desc->data.ctrl = RAVB_DESC_DT_FEMPTY | RAVB_DESC_DS(PKTSIZE_ALIGN);
	ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));

	/* Point to the next descriptor */
	eth->rx_desc_idx = (eth->rx_desc_idx + 1) % RAVB_NUM_RX_DESC;
	desc = &eth->rx_desc[eth->rx_desc_idx];
	ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));

	return 0;
}

static int ravb_reset(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);

	/* Set config mode */
	writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC);

	/* Check the operating mode is changed to the config mode. */
	return wait_for_bit_le32(eth->iobase + RAVB_REG_CSR,
				 CSR_OPS_CONFIG, true, 100, true);
}

static void ravb_base_desc_init(struct ravb_priv *eth)
{
	const u32 desc_size = RAVB_NUM_BASE_DESC * sizeof(struct ravb_desc);
	int i;

	/* Initialize all descriptors */
	memset(eth->base_desc, 0x0, desc_size);

	for (i = 0; i < RAVB_NUM_BASE_DESC; i++)
		eth->base_desc[i].ctrl = RAVB_DESC_DT_EOS;

	ravb_flush_dcache((uintptr_t)eth->base_desc, desc_size);

	/* Register the descriptor base address table */
	writel((uintptr_t)eth->base_desc, eth->iobase + RAVB_REG_DBAT);
}

static void ravb_tx_desc_init(struct ravb_priv *eth)
{
	const u32 desc_size = RAVB_NUM_TX_DESC * sizeof(struct ravb_desc);
	int i;

	/* Initialize all descriptors */
	memset(eth->tx_desc, 0x0, desc_size);
	eth->tx_desc_idx = 0;

	for (i = 0; i < RAVB_NUM_TX_DESC; i++)
		eth->tx_desc[i].ctrl = RAVB_DESC_DT_EEMPTY;

	/* Mark the end of the descriptors */
	eth->tx_desc[RAVB_NUM_TX_DESC - 1].ctrl = RAVB_DESC_DT_LINKFIX;
	eth->tx_desc[RAVB_NUM_TX_DESC - 1].dptr = (uintptr_t)eth->tx_desc;
	ravb_flush_dcache((uintptr_t)eth->tx_desc, desc_size);

	/* Point the controller to the TX descriptor list. */
	eth->base_desc[RAVB_TX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
	eth->base_desc[RAVB_TX_QUEUE_OFFSET].dptr = (uintptr_t)eth->tx_desc;
	ravb_flush_dcache((uintptr_t)&eth->base_desc[RAVB_TX_QUEUE_OFFSET],
			  sizeof(struct ravb_desc));
}

static void ravb_rx_desc_init(struct ravb_priv *eth)
{
	const u32 desc_size = RAVB_NUM_RX_DESC * sizeof(struct ravb_rxdesc);
	int i;

	/* Initialize all descriptors */
	memset(eth->rx_desc, 0x0, desc_size);
	eth->rx_desc_idx = 0;

	for (i = 0; i < RAVB_NUM_RX_DESC; i++) {
		eth->rx_desc[i].data.ctrl = RAVB_DESC_DT_EEMPTY |
					    RAVB_DESC_DS(PKTSIZE_ALIGN);
		eth->rx_desc[i].data.dptr = (uintptr_t)eth->rx_desc[i].packet;

		eth->rx_desc[i].link.ctrl = RAVB_DESC_DT_LINKFIX;
		eth->rx_desc[i].link.dptr = (uintptr_t)&eth->rx_desc[i + 1];
	}

	/* Mark the end of the descriptors */
	eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.ctrl = RAVB_DESC_DT_LINKFIX;
	eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.dptr = (uintptr_t)eth->rx_desc;
	ravb_flush_dcache((uintptr_t)eth->rx_desc, desc_size);

	/* Point the controller to the rx descriptor list */
	eth->base_desc[RAVB_RX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
	eth->base_desc[RAVB_RX_QUEUE_OFFSET].dptr = (uintptr_t)eth->rx_desc;
	ravb_flush_dcache((uintptr_t)&eth->base_desc[RAVB_RX_QUEUE_OFFSET],
			  sizeof(struct ravb_desc));
}

static int ravb_phy_config(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct phy_device *phydev;
	int reg;

	if (dm_gpio_is_valid(&eth->reset_gpio)) {
		dm_gpio_set_value(&eth->reset_gpio, 1);
		mdelay(20);
		dm_gpio_set_value(&eth->reset_gpio, 0);
		mdelay(1);
	}

	phydev = phy_connect(eth->bus, -1, dev, pdata->phy_interface);
	if (!phydev)
		return -ENODEV;

	eth->phydev = phydev;

	phydev->supported &= SUPPORTED_100baseT_Full |
			     SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
			     SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_Pause |
			     SUPPORTED_Asym_Pause;

	if (pdata->max_speed != 1000) {
		phydev->supported &= ~SUPPORTED_1000baseT_Full;
		reg = phy_read(phydev, -1, MII_CTRL1000);
		reg &= ~(BIT(9) | BIT(8));
		phy_write(phydev, -1, MII_CTRL1000, reg);
	}

	phy_config(phydev);

	return 0;
}

/* Set Mac address */
static int ravb_write_hwaddr(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_plat(dev);
	unsigned char *mac = pdata->enetaddr;

	writel((mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3],
	       eth->iobase + RAVB_REG_MAHR);

	writel((mac[4] << 8) | mac[5], eth->iobase + RAVB_REG_MALR);

	return 0;
}

/* E-MAC init function */
static int ravb_mac_init(struct ravb_priv *eth)
{
	/* Disable MAC Interrupt */
	writel(0, eth->iobase + RAVB_REG_ECSIPR);

	/* Recv frame limit set register */
	writel(RFLR_RFL_MIN, eth->iobase + RAVB_REG_RFLR);

	return 0;
}

/* AVB-DMAC init function */
static int ravb_dmac_init(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_plat(dev);
	int ret = 0;
	int mode = 0;
	unsigned int delay;
	bool explicit_delay = false;

	/* Set CONFIG mode */
	ret = ravb_reset(dev);
	if (ret)
		return ret;

	/* Disable all interrupts */
	writel(0, eth->iobase + RAVB_REG_RIC0);
	writel(0, eth->iobase + RAVB_REG_RIC1);
	writel(0, eth->iobase + RAVB_REG_RIC2);
	writel(0, eth->iobase + RAVB_REG_TIC);

	/* Set little endian */
	clrbits_le32(eth->iobase + RAVB_REG_CCC, CCC_BOC);

	/* AVB rx set */
	writel(0x18000001, eth->iobase + RAVB_REG_RCR);

	/* FIFO size set */
	writel(0x00222210, eth->iobase + RAVB_REG_TGC);

	/* Delay CLK: 2ns (not applicable on R-Car E3/D3) */
	if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) ||
	    (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77995))
		return 0;

	if (!dev_read_u32(dev, "rx-internal-delay-ps", &delay)) {
		/* Valid values are 0 and 1800, according to DT bindings */
		if (delay) {
			mode |= APSR_RDM;
			explicit_delay = true;
		}
	}

	if (!dev_read_u32(dev, "tx-internal-delay-ps", &delay)) {
		/* Valid values are 0 and 2000, according to DT bindings */
		if (delay) {
			mode |= APSR_TDM;
			explicit_delay = true;
		}
	}

	if (!explicit_delay) {
		if (pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
		    pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID)
			mode |= APSR_RDM;

		if (pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
		    pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
			mode |= APSR_TDM;
	}

	writel(mode, eth->iobase + RAVB_REG_APSR);

	return 0;
}

static int ravb_config(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct phy_device *phy = eth->phydev;
	u32 mask = ECMR_CHG_DM | ECMR_RE | ECMR_TE;
	int ret;

	/* Configure AVB-DMAC register */
	ravb_dmac_init(dev);

	/* Configure E-MAC registers */
	ravb_mac_init(eth);
	ravb_write_hwaddr(dev);

	ret = phy_startup(phy);
	if (ret)
		return ret;

	/* Set the transfer speed */
	if (phy->speed == 100)
		writel(0, eth->iobase + RAVB_REG_GECMR);
	else if (phy->speed == 1000)
		writel(1, eth->iobase + RAVB_REG_GECMR);

	/* Check if full duplex mode is supported by the phy */
	if (phy->duplex)
		mask |= ECMR_DM;

	writel(mask, eth->iobase + RAVB_REG_ECMR);

	return 0;
}

static int ravb_start(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	int ret;

	ret = ravb_reset(dev);
	if (ret)
		return ret;

	ravb_base_desc_init(eth);
	ravb_tx_desc_init(eth);
	ravb_rx_desc_init(eth);

	ret = ravb_config(dev);
	if (ret)
		return ret;

	/* Setting the control will start the AVB-DMAC process. */
	writel(CCC_OPC_OPERATION, eth->iobase + RAVB_REG_CCC);

	return 0;
}

static void ravb_stop(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);

	phy_shutdown(eth->phydev);
	ravb_reset(dev);
}

static int ravb_probe(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct ravb_priv *eth = dev_get_priv(dev);
	struct ofnode_phandle_args phandle_args;
	struct mii_dev *mdiodev;
	void __iomem *iobase;
	int ret;

	iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
	eth->iobase = iobase;

	ret = clk_get_bulk(dev, &eth->clks);
	if (ret < 0)
		goto err_mdio_alloc;

	ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &phandle_args);
	if (!ret) {
		gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0,
					   &eth->reset_gpio, GPIOD_IS_OUT);
	}

	if (!dm_gpio_is_valid(&eth->reset_gpio)) {
		gpio_request_by_name(dev, "reset-gpios", 0, &eth->reset_gpio,
				     GPIOD_IS_OUT);
	}

	mdiodev = mdio_alloc();
	if (!mdiodev) {
		ret = -ENOMEM;
		goto err_mdio_alloc;
	}

	mdiodev->read = bb_miiphy_read;
	mdiodev->write = bb_miiphy_write;
	bb_miiphy_buses[0].priv = eth;
	snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);

	ret = mdio_register(mdiodev);
	if (ret < 0)
		goto err_mdio_register;

	eth->bus = miiphy_get_dev_by_name(dev->name);

	/* Bring up PHY */
	ret = clk_enable_bulk(&eth->clks);
	if (ret)
		goto err_mdio_register;

	ret = ravb_reset(dev);
	if (ret)
		goto err_mdio_reset;

	ret = ravb_phy_config(dev);
	if (ret)
		goto err_mdio_reset;

	return 0;

err_mdio_reset:
	clk_release_bulk(&eth->clks);
err_mdio_register:
	mdio_free(mdiodev);
err_mdio_alloc:
	unmap_physmem(eth->iobase, MAP_NOCACHE);
	return ret;
}

static int ravb_remove(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);

	clk_release_bulk(&eth->clks);

	free(eth->phydev);
	mdio_unregister(eth->bus);
	mdio_free(eth->bus);
	if (dm_gpio_is_valid(&eth->reset_gpio))
		dm_gpio_free(dev, &eth->reset_gpio);
	unmap_physmem(eth->iobase, MAP_NOCACHE);

	return 0;
}

int ravb_bb_init(struct bb_miiphy_bus *bus)
{
	return 0;
}

int ravb_bb_mdio_active(struct bb_miiphy_bus *bus)
{
	struct ravb_priv *eth = bus->priv;

	setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);

	return 0;
}

int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus)
{
	struct ravb_priv *eth = bus->priv;

	clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);

	return 0;
}

int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
{
	struct ravb_priv *eth = bus->priv;

	if (v)
		setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
	else
		clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);

	return 0;
}

int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
{
	struct ravb_priv *eth = bus->priv;

	*v = (readl(eth->iobase + RAVB_REG_PIR) & PIR_MDI) >> 3;

	return 0;
}

int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
{
	struct ravb_priv *eth = bus->priv;

	if (v)
		setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
	else
		clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);

	return 0;
}

int ravb_bb_delay(struct bb_miiphy_bus *bus)
{
	udelay(10);

	return 0;
}

struct bb_miiphy_bus bb_miiphy_buses[] = {
	{
		.name		= "ravb",
		.init		= ravb_bb_init,
		.mdio_active	= ravb_bb_mdio_active,
		.mdio_tristate	= ravb_bb_mdio_tristate,
		.set_mdio	= ravb_bb_set_mdio,
		.get_mdio	= ravb_bb_get_mdio,
		.set_mdc	= ravb_bb_set_mdc,
		.delay		= ravb_bb_delay,
	},
};
int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);

static const struct eth_ops ravb_ops = {
	.start			= ravb_start,
	.send			= ravb_send,
	.recv			= ravb_recv,
	.free_pkt		= ravb_free_pkt,
	.stop			= ravb_stop,
	.write_hwaddr		= ravb_write_hwaddr,
};

int ravb_of_to_plat(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_plat(dev);
	const fdt32_t *cell;

	pdata->iobase = dev_read_addr(dev);

	pdata->phy_interface = dev_read_phy_mode(dev);
	if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
		return -EINVAL;

	pdata->max_speed = 1000;
	cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
	if (cell)
		pdata->max_speed = fdt32_to_cpu(*cell);

	sprintf(bb_miiphy_buses[0].name, dev->name);

	return 0;
}

static const struct udevice_id ravb_ids[] = {
	{ .compatible = "renesas,etheravb-rcar-gen3" },
	{ }
};

U_BOOT_DRIVER(eth_ravb) = {
	.name		= "ravb",
	.id		= UCLASS_ETH,
	.of_match	= ravb_ids,
	.of_to_plat = ravb_of_to_plat,
	.probe		= ravb_probe,
	.remove		= ravb_remove,
	.ops		= &ravb_ops,
	.priv_auto	= sizeof(struct ravb_priv),
	.plat_auto	= sizeof(struct eth_pdata),
	.flags		= DM_FLAG_ALLOC_PRIV_DMA,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
8ae51b6f MV	2	/*
	3	* drivers/net/ravb.c
	4	* This file is driver for Renesas Ethernet AVB.
	5	*
	6	* Copyright (C) 2015-2017 Renesas Electronics Corporation
	7	*
	8	* Based on the SuperH Ethernet driver.
8ae51b6f MV	9	*/
	10
	11	#include <common.h>
1fea9e25	12	#include <clk.h>
1eb69ae4	13	#include <cpu_func.h>
8ae51b6f MV	14	#include <dm.h>
8ae51b6f MV	15	#include <errno.h>
f7ae49fc	16	#include <log.h>
8ae51b6f MV	17	#include <miiphy.h>
8ae51b6f MV	18	#include <malloc.h>
90526e9f	19	#include <asm/cache.h>
cd93d625	20	#include <linux/bitops.h>
c05ed00a	21	#include <linux/delay.h>
8ae51b6f MV	22	#include <linux/mii.h>
	23	#include <wait_bit.h>
	24	#include <asm/io.h>
401d1c4f	25	#include <asm/global_data.h>
bddb44e9	26	#include <asm/gpio.h>
8ae51b6f MV	27
	28	/* Registers */
	29	#define RAVB_REG_CCC 0x000
	30	#define RAVB_REG_DBAT 0x004
	31	#define RAVB_REG_CSR 0x00C
	32	#define RAVB_REG_APSR 0x08C
	33	#define RAVB_REG_RCR 0x090
	34	#define RAVB_REG_TGC 0x300
	35	#define RAVB_REG_TCCR 0x304
	36	#define RAVB_REG_RIC0 0x360
	37	#define RAVB_REG_RIC1 0x368
	38	#define RAVB_REG_RIC2 0x370
	39	#define RAVB_REG_TIC 0x378
	40	#define RAVB_REG_ECMR 0x500
	41	#define RAVB_REG_RFLR 0x508
	42	#define RAVB_REG_ECSIPR 0x518
	43	#define RAVB_REG_PIR 0x520
	44	#define RAVB_REG_GECMR 0x5b0
	45	#define RAVB_REG_MAHR 0x5c0
	46	#define RAVB_REG_MALR 0x5c8
	47
	48	#define CCC_OPC_CONFIG BIT(0)
	49	#define CCC_OPC_OPERATION BIT(1)
	50	#define CCC_BOC BIT(20)
	51
	52	#define CSR_OPS 0x0000000F
	53	#define CSR_OPS_CONFIG BIT(1)
	54
a26c2b15	55	#define APSR_RDM BIT(13)
ef8c8781 MV	56	#define APSR_TDM BIT(14)
ef8c8781 MV	57
8ae51b6f MV	58	#define TCCR_TSRQ0 BIT(0)
	59
	60	#define RFLR_RFL_MIN 0x05EE
	61
	62	#define PIR_MDI BIT(3)
	63	#define PIR_MDO BIT(2)
	64	#define PIR_MMD BIT(1)
	65	#define PIR_MDC BIT(0)
	66
	67	#define ECMR_TRCCM BIT(26)
	68	#define ECMR_RZPF BIT(20)
	69	#define ECMR_PFR BIT(18)
	70	#define ECMR_RXF BIT(17)
	71	#define ECMR_RE BIT(6)
	72	#define ECMR_TE BIT(5)
	73	#define ECMR_DM BIT(1)
	74	#define ECMR_CHG_DM (ECMR_TRCCM \| ECMR_RZPF \| ECMR_PFR \| ECMR_RXF)
	75
	76	/* DMA Descriptors */
	77	#define RAVB_NUM_BASE_DESC 16
	78	#define RAVB_NUM_TX_DESC 8
	79	#define RAVB_NUM_RX_DESC 8
	80
	81	#define RAVB_TX_QUEUE_OFFSET 0
	82	#define RAVB_RX_QUEUE_OFFSET 4
	83
	84	#define RAVB_DESC_DT(n) ((n) << 28)
	85	#define RAVB_DESC_DT_FSINGLE RAVB_DESC_DT(0x7)
	86	#define RAVB_DESC_DT_LINKFIX RAVB_DESC_DT(0x9)
	87	#define RAVB_DESC_DT_EOS RAVB_DESC_DT(0xa)
	88	#define RAVB_DESC_DT_FEMPTY RAVB_DESC_DT(0xc)
	89	#define RAVB_DESC_DT_EEMPTY RAVB_DESC_DT(0x3)
	90	#define RAVB_DESC_DT_MASK RAVB_DESC_DT(0xf)
	91
	92	#define RAVB_DESC_DS(n) (((n) & 0xfff) << 0)
	93	#define RAVB_DESC_DS_MASK 0xfff
	94
	95	#define RAVB_RX_DESC_MSC_MC BIT(23)
	96	#define RAVB_RX_DESC_MSC_CEEF BIT(22)
	97	#define RAVB_RX_DESC_MSC_CRL BIT(21)
	98	#define RAVB_RX_DESC_MSC_FRE BIT(20)
	99	#define RAVB_RX_DESC_MSC_RTLF BIT(19)
	100	#define RAVB_RX_DESC_MSC_RTSF BIT(18)
	101	#define RAVB_RX_DESC_MSC_RFE BIT(17)
	102	#define RAVB_RX_DESC_MSC_CRC BIT(16)
	103	#define RAVB_RX_DESC_MSC_MASK (0xff << 16)
	104
	105	#define RAVB_RX_DESC_MSC_RX_ERR_MASK \
	106	(RAVB_RX_DESC_MSC_CRC \| RAVB_RX_DESC_MSC_RFE \| RAVB_RX_DESC_MSC_RTLF \| \
	107	RAVB_RX_DESC_MSC_RTSF \| RAVB_RX_DESC_MSC_CEEF)
	108
	109	#define RAVB_TX_TIMEOUT_MS 1000
	110
	111	struct ravb_desc {
	112	u32 ctrl;
	113	u32 dptr;
	114	};
	115
	116	struct ravb_rxdesc {
	117	struct ravb_desc data;
	118	struct ravb_desc link;
	119	u8 __pad[48];
	120	u8 packet[PKTSIZE_ALIGN];
	121	};
122
123	struct ravb_priv {
124	struct ravb_desc base_desc[RAVB_NUM_BASE_DESC];
125	struct ravb_desc tx_desc[RAVB_NUM_TX_DESC];
126	struct ravb_rxdesc rx_desc[RAVB_NUM_RX_DESC];
127	u32 rx_desc_idx;
128	u32 tx_desc_idx;
129
130	struct phy_device *phydev;
131	struct mii_dev *bus;
132	void __iomem *iobase;
182754f4	133	struct clk_bulk clks;
bddb44e9	134	struct gpio_desc reset_gpio;
8ae51b6f MV	135	};
	136
	137	static inline void ravb_flush_dcache(u32 addr, u32 len)
	138	{
	139	flush_dcache_range(addr, addr + len);
	140	}
	141
	142	static inline void ravb_invalidate_dcache(u32 addr, u32 len)
	143	{
	144	u32 start = addr & ~((uintptr_t)ARCH_DMA_MINALIGN - 1);
	145	u32 end = roundup(addr + len, ARCH_DMA_MINALIGN);
	146	invalidate_dcache_range(start, end);
	147	}
	148
	149	static int ravb_send(struct udevice dev, void packet, int len)
	150	{
	151	struct ravb_priv *eth = dev_get_priv(dev);
	152	struct ravb_desc *desc = &eth->tx_desc[eth->tx_desc_idx];
	153	unsigned int start;
	154
	155	/* Update TX descriptor */
	156	ravb_flush_dcache((uintptr_t)packet, len);
	157	memset(desc, 0x0, sizeof(*desc));
	158	desc->ctrl = RAVB_DESC_DT_FSINGLE \| RAVB_DESC_DS(len);
	159	desc->dptr = (uintptr_t)packet;
	160	ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));
	161
	162	/* Restart the transmitter if disabled */
	163	if (!(readl(eth->iobase + RAVB_REG_TCCR) & TCCR_TSRQ0))
	164	setbits_le32(eth->iobase + RAVB_REG_TCCR, TCCR_TSRQ0);
	165
	166	/* Wait until packet is transmitted */
	167	start = get_timer(0);
	168	while (get_timer(start) < RAVB_TX_TIMEOUT_MS) {
	169	ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
	170	if ((desc->ctrl & RAVB_DESC_DT_MASK) != RAVB_DESC_DT_FSINGLE)
	171	break;
	172	udelay(10);
	173	};
	174
	175	if (get_timer(start) >= RAVB_TX_TIMEOUT_MS)
	176	return -ETIMEDOUT;
	177
	178	eth->tx_desc_idx = (eth->tx_desc_idx + 1) % (RAVB_NUM_TX_DESC - 1);
	179	return 0;
	180	}
	181
	182	static int ravb_recv(struct udevice dev, int flags, uchar *packetp)
	183	{
	184	struct ravb_priv *eth = dev_get_priv(dev);
	185	struct ravb_rxdesc *desc = &eth->rx_desc[eth->rx_desc_idx];
	186	int len;
	187	u8 *packet;
	188
	189	/* Check if the rx descriptor is ready */
	190	ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
	191	if ((desc->data.ctrl & RAVB_DESC_DT_MASK) == RAVB_DESC_DT_FEMPTY)
	192	return -EAGAIN;
	193
	194	/* Check for errors */
	195	if (desc->data.ctrl & RAVB_RX_DESC_MSC_RX_ERR_MASK) {
	196	desc->data.ctrl &= ~RAVB_RX_DESC_MSC_MASK;
	197	return -EAGAIN;
	198	}
199
200	len = desc->data.ctrl & RAVB_DESC_DS_MASK;
201	packet = (u8 *)(uintptr_t)desc->data.dptr;
202	ravb_invalidate_dcache((uintptr_t)packet, len);
203
204	*packetp = packet;
205	return len;
206	}
207
208	static int ravb_free_pkt(struct udevice dev, uchar packet, int length)
209	{
210	struct ravb_priv *eth = dev_get_priv(dev);
211	struct ravb_rxdesc *desc = &eth->rx_desc[eth->rx_desc_idx];
212
213	/* Make current descriptor available again */
214	desc->data.ctrl = RAVB_DESC_DT_FEMPTY \| RAVB_DESC_DS(PKTSIZE_ALIGN);
215	ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));
216
217	/* Point to the next descriptor */
218	eth->rx_desc_idx = (eth->rx_desc_idx + 1) % RAVB_NUM_RX_DESC;
219	desc = &eth->rx_desc[eth->rx_desc_idx];
220	ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
221
222	return 0;
223	}
224
225	static int ravb_reset(struct udevice *dev)
226	{
227	struct ravb_priv *eth = dev_get_priv(dev);
228
229	/* Set config mode */
230	writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC);
231
232	/* Check the operating mode is changed to the config mode. */
48263504 ÁFR	233	return wait_for_bit_le32(eth->iobase + RAVB_REG_CSR,
48263504 ÁFR	234	CSR_OPS_CONFIG, true, 100, true);
8ae51b6f MV	235	}
	236
	237	static void ravb_base_desc_init(struct ravb_priv *eth)
	238	{
	239	const u32 desc_size = RAVB_NUM_BASE_DESC * sizeof(struct ravb_desc);
	240	int i;
	241
	242	/* Initialize all descriptors */
	243	memset(eth->base_desc, 0x0, desc_size);
	244
	245	for (i = 0; i < RAVB_NUM_BASE_DESC; i++)
	246	eth->base_desc[i].ctrl = RAVB_DESC_DT_EOS;
	247
	248	ravb_flush_dcache((uintptr_t)eth->base_desc, desc_size);
	249
	250	/* Register the descriptor base address table */
	251	writel((uintptr_t)eth->base_desc, eth->iobase + RAVB_REG_DBAT);
	252	}
	253
	254	static void ravb_tx_desc_init(struct ravb_priv *eth)
	255	{
	256	const u32 desc_size = RAVB_NUM_TX_DESC * sizeof(struct ravb_desc);
	257	int i;
	258
	259	/* Initialize all descriptors */
	260	memset(eth->tx_desc, 0x0, desc_size);
	261	eth->tx_desc_idx = 0;
	262
	263	for (i = 0; i < RAVB_NUM_TX_DESC; i++)
	264	eth->tx_desc[i].ctrl = RAVB_DESC_DT_EEMPTY;
	265
	266	/* Mark the end of the descriptors */
	267	eth->tx_desc[RAVB_NUM_TX_DESC - 1].ctrl = RAVB_DESC_DT_LINKFIX;
	268	eth->tx_desc[RAVB_NUM_TX_DESC - 1].dptr = (uintptr_t)eth->tx_desc;
	269	ravb_flush_dcache((uintptr_t)eth->tx_desc, desc_size);
	270
	271	/* Point the controller to the TX descriptor list. */
	272	eth->base_desc[RAVB_TX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
	273	eth->base_desc[RAVB_TX_QUEUE_OFFSET].dptr = (uintptr_t)eth->tx_desc;
	274	ravb_flush_dcache((uintptr_t)&eth->base_desc[RAVB_TX_QUEUE_OFFSET],
	275	sizeof(struct ravb_desc));
	276	}
	277
	278	static void ravb_rx_desc_init(struct ravb_priv *eth)
	279	{
	280	const u32 desc_size = RAVB_NUM_RX_DESC * sizeof(struct ravb_rxdesc);
	281	int i;
	282
	283	/* Initialize all descriptors */
	284	memset(eth->rx_desc, 0x0, desc_size);
	285	eth->rx_desc_idx = 0;
	286
	287	for (i = 0; i < RAVB_NUM_RX_DESC; i++) {
	288	eth->rx_desc[i].data.ctrl = RAVB_DESC_DT_EEMPTY \|
	289	RAVB_DESC_DS(PKTSIZE_ALIGN);
	290	eth->rx_desc[i].data.dptr = (uintptr_t)eth->rx_desc[i].packet;
	291
	292	eth->rx_desc[i].link.ctrl = RAVB_DESC_DT_LINKFIX;
	293	eth->rx_desc[i].link.dptr = (uintptr_t)&eth->rx_desc[i + 1];
	294	}
	295
	296	/* Mark the end of the descriptors */
	297	eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.ctrl = RAVB_DESC_DT_LINKFIX;
	298	eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.dptr = (uintptr_t)eth->rx_desc;
299	ravb_flush_dcache((uintptr_t)eth->rx_desc, desc_size);
300
301	/* Point the controller to the rx descriptor list */
302	eth->base_desc[RAVB_RX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
303	eth->base_desc[RAVB_RX_QUEUE_OFFSET].dptr = (uintptr_t)eth->rx_desc;
304	ravb_flush_dcache((uintptr_t)&eth->base_desc[RAVB_RX_QUEUE_OFFSET],
305	sizeof(struct ravb_desc));
306	}
307
308	static int ravb_phy_config(struct udevice *dev)
309	{
310	struct ravb_priv *eth = dev_get_priv(dev);
c69cda25	311	struct eth_pdata *pdata = dev_get_plat(dev);
8ae51b6f	312	struct phy_device *phydev;
d797a8cc	313	int reg;
8ae51b6f	314
bddb44e9 MV	315	if (dm_gpio_is_valid(&eth->reset_gpio)) {
	316	dm_gpio_set_value(&eth->reset_gpio, 1);
	317	mdelay(20);
	318	dm_gpio_set_value(&eth->reset_gpio, 0);
	319	mdelay(1);
	320	}
	321
d797a8cc	322	phydev = phy_connect(eth->bus, -1, dev, pdata->phy_interface);
8ae51b6f MV	323	if (!phydev)
	324	return -ENODEV;
	325
	326	eth->phydev = phydev;
	327
536fb5d4 MV	328	phydev->supported &= SUPPORTED_100baseT_Full \|
	329	SUPPORTED_1000baseT_Full \| SUPPORTED_Autoneg \|
	330	SUPPORTED_TP \| SUPPORTED_MII \| SUPPORTED_Pause \|
	331	SUPPORTED_Asym_Pause;
	332
8ae51b6f	333	if (pdata->max_speed != 1000) {
536fb5d4	334	phydev->supported &= ~SUPPORTED_1000baseT_Full;
8ae51b6f MV	335	reg = phy_read(phydev, -1, MII_CTRL1000);
	336	reg &= ~(BIT(9) \| BIT(8));
	337	phy_write(phydev, -1, MII_CTRL1000, reg);
	338	}
	339
	340	phy_config(phydev);
	341
	342	return 0;
	343	}
	344
	345	/* Set Mac address */
	346	static int ravb_write_hwaddr(struct udevice *dev)
	347	{
	348	struct ravb_priv *eth = dev_get_priv(dev);
c69cda25	349	struct eth_pdata *pdata = dev_get_plat(dev);
8ae51b6f MV	350	unsigned char *mac = pdata->enetaddr;
	351
	352	writel((mac[0] << 24) \| (mac[1] << 16) \| (mac[2] << 8) \| mac[3],
	353	eth->iobase + RAVB_REG_MAHR);
	354
	355	writel((mac[4] << 8) \| mac[5], eth->iobase + RAVB_REG_MALR);
	356
	357	return 0;
	358	}
	359
	360	/* E-MAC init function */
	361	static int ravb_mac_init(struct ravb_priv *eth)
	362	{
	363	/* Disable MAC Interrupt */
	364	writel(0, eth->iobase + RAVB_REG_ECSIPR);
	365
	366	/* Recv frame limit set register */
	367	writel(RFLR_RFL_MIN, eth->iobase + RAVB_REG_RFLR);
	368
	369	return 0;
	370	}
	371
	372	/* AVB-DMAC init function */
	373	static int ravb_dmac_init(struct udevice *dev)
	374	{
	375	struct ravb_priv *eth = dev_get_priv(dev);
c69cda25	376	struct eth_pdata *pdata = dev_get_plat(dev);
8ae51b6f	377	int ret = 0;
a26c2b15 AF	378	int mode = 0;
	379	unsigned int delay;
	380	bool explicit_delay = false;
8ae51b6f MV	381
	382	/* Set CONFIG mode */
	383	ret = ravb_reset(dev);
	384	if (ret)
	385	return ret;
	386
	387	/* Disable all interrupts */
	388	writel(0, eth->iobase + RAVB_REG_RIC0);
	389	writel(0, eth->iobase + RAVB_REG_RIC1);
	390	writel(0, eth->iobase + RAVB_REG_RIC2);
	391	writel(0, eth->iobase + RAVB_REG_TIC);
	392
	393	/* Set little endian */
	394	clrbits_le32(eth->iobase + RAVB_REG_CCC, CCC_BOC);
	395
	396	/* AVB rx set */
	397	writel(0x18000001, eth->iobase + RAVB_REG_RCR);
	398
	399	/* FIFO size set */
	400	writel(0x00222210, eth->iobase + RAVB_REG_TGC);
	401
ef8c8781 MV	402	/* Delay CLK: 2ns (not applicable on R-Car E3/D3) */
	403	if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) \|\|
	404	(rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77995))
	405	return 0;
	406
a26c2b15 AF	407	if (!dev_read_u32(dev, "rx-internal-delay-ps", &delay)) {
	408	/* Valid values are 0 and 1800, according to DT bindings */
	409	if (delay) {
	410	mode \|= APSR_RDM;
	411	explicit_delay = true;
	412	}
	413	}
	414
	415	if (!dev_read_u32(dev, "tx-internal-delay-ps", &delay)) {
	416	/* Valid values are 0 and 2000, according to DT bindings */
	417	if (delay) {
	418	mode \|= APSR_TDM;
	419	explicit_delay = true;
	420	}
	421	}
	422
	423	if (!explicit_delay) {
	424	if (pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID \|\|
	425	pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID)
	426	mode \|= APSR_RDM;
	427
	428	if (pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID \|\|
	429	pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
	430	mode \|= APSR_TDM;
	431	}
	432
	433	writel(mode, eth->iobase + RAVB_REG_APSR);
8ae51b6f MV	434
	435	return 0;
	436	}
	437
	438	static int ravb_config(struct udevice *dev)
	439	{
	440	struct ravb_priv *eth = dev_get_priv(dev);
d64c7894	441	struct phy_device *phy = eth->phydev;
8ae51b6f MV	442	u32 mask = ECMR_CHG_DM \| ECMR_RE \| ECMR_TE;
	443	int ret;
	444
	445	/* Configure AVB-DMAC register */
	446	ravb_dmac_init(dev);
	447
	448	/* Configure E-MAC registers */
	449	ravb_mac_init(eth);
	450	ravb_write_hwaddr(dev);
	451
8ae51b6f MV	452	ret = phy_startup(phy);
	453	if (ret)
	454	return ret;
	455
	456	/* Set the transfer speed */
	457	if (phy->speed == 100)
	458	writel(0, eth->iobase + RAVB_REG_GECMR);
	459	else if (phy->speed == 1000)
	460	writel(1, eth->iobase + RAVB_REG_GECMR);
	461
	462	/* Check if full duplex mode is supported by the phy */
	463	if (phy->duplex)
	464	mask \|= ECMR_DM;
	465
	466	writel(mask, eth->iobase + RAVB_REG_ECMR);
	467
8ae51b6f MV	468	return 0;
	469	}
	470
e3105eac	471	static int ravb_start(struct udevice *dev)
8ae51b6f MV	472	{
	473	struct ravb_priv *eth = dev_get_priv(dev);
	474	int ret;
	475
1fea9e25 MV	476	ret = ravb_reset(dev);
1fea9e25 MV	477	if (ret)
c4a8d9ca	478	return ret;
1fea9e25	479
8ae51b6f MV	480	ravb_base_desc_init(eth);
	481	ravb_tx_desc_init(eth);
	482	ravb_rx_desc_init(eth);
	483
	484	ret = ravb_config(dev);
	485	if (ret)
c4a8d9ca	486	return ret;
8ae51b6f MV	487
	488	/* Setting the control will start the AVB-DMAC process. */
	489	writel(CCC_OPC_OPERATION, eth->iobase + RAVB_REG_CCC);
	490
	491	return 0;
	492	}
	493
	494	static void ravb_stop(struct udevice *dev)
	495	{
1fea9e25 MV	496	struct ravb_priv *eth = dev_get_priv(dev);
1fea9e25 MV	497
d64c7894	498	phy_shutdown(eth->phydev);
8ae51b6f MV	499	ravb_reset(dev);
	500	}
	501
	502	static int ravb_probe(struct udevice *dev)
	503	{
c69cda25	504	struct eth_pdata *pdata = dev_get_plat(dev);
8ae51b6f	505	struct ravb_priv *eth = dev_get_priv(dev);
701db6e9	506	struct ofnode_phandle_args phandle_args;
8ae51b6f MV	507	struct mii_dev *mdiodev;
	508	void __iomem *iobase;
	509	int ret;
	510
	511	iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
	512	eth->iobase = iobase;
	513
182754f4	514	ret = clk_get_bulk(dev, &eth->clks);
1fea9e25 MV	515	if (ret < 0)
	516	goto err_mdio_alloc;
	517
701db6e9 MV	518	ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &phandle_args);
	519	if (!ret) {
	520	gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0,
	521	&eth->reset_gpio, GPIOD_IS_OUT);
	522	}
	523
	524	if (!dm_gpio_is_valid(&eth->reset_gpio)) {
	525	gpio_request_by_name(dev, "reset-gpios", 0, &eth->reset_gpio,
	526	GPIOD_IS_OUT);
	527	}
bddb44e9	528
8ae51b6f MV	529	mdiodev = mdio_alloc();
	530	if (!mdiodev) {
	531	ret = -ENOMEM;
	532	goto err_mdio_alloc;
	533	}
	534
	535	mdiodev->read = bb_miiphy_read;
	536	mdiodev->write = bb_miiphy_write;
	537	bb_miiphy_buses[0].priv = eth;
	538	snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);
	539
	540	ret = mdio_register(mdiodev);
	541	if (ret < 0)
	542	goto err_mdio_register;
	543
	544	eth->bus = miiphy_get_dev_by_name(dev->name);
	545
d64c7894	546	/* Bring up PHY */
182754f4	547	ret = clk_enable_bulk(&eth->clks);
d64c7894 MV	548	if (ret)
	549	goto err_mdio_register;
	550
	551	ret = ravb_reset(dev);
	552	if (ret)
	553	goto err_mdio_reset;
	554
	555	ret = ravb_phy_config(dev);
	556	if (ret)
	557	goto err_mdio_reset;
	558
8ae51b6f MV	559	return 0;
8ae51b6f MV	560
d64c7894	561	err_mdio_reset:
182754f4	562	clk_release_bulk(&eth->clks);
8ae51b6f MV	563	err_mdio_register:
	564	mdio_free(mdiodev);
	565	err_mdio_alloc:
	566	unmap_physmem(eth->iobase, MAP_NOCACHE);
	567	return ret;
	568	}
	569
	570	static int ravb_remove(struct udevice *dev)
	571	{
	572	struct ravb_priv *eth = dev_get_priv(dev);
	573
182754f4	574	clk_release_bulk(&eth->clks);
d64c7894	575
8ae51b6f MV	576	free(eth->phydev);
	577	mdio_unregister(eth->bus);
	578	mdio_free(eth->bus);
90997cda MV	579	if (dm_gpio_is_valid(&eth->reset_gpio))
90997cda MV	580	dm_gpio_free(dev, &eth->reset_gpio);
8ae51b6f MV	581	unmap_physmem(eth->iobase, MAP_NOCACHE);
	582
	583	return 0;
	584	}
	585
	586	int ravb_bb_init(struct bb_miiphy_bus *bus)
	587	{
	588	return 0;
	589	}
	590
	591	int ravb_bb_mdio_active(struct bb_miiphy_bus *bus)
	592	{
	593	struct ravb_priv *eth = bus->priv;
	594
	595	setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
	596
	597	return 0;
	598	}
	599
	600	int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus)
	601	{
	602	struct ravb_priv *eth = bus->priv;
	603
	604	clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
	605
	606	return 0;
	607	}
	608
	609	int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
	610	{
	611	struct ravb_priv *eth = bus->priv;
	612
	613	if (v)
	614	setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
	615	else
	616	clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
	617
	618	return 0;
	619	}
	620
	621	int ravb_bb_get_mdio(struct bb_miiphy_bus bus, int v)
	622	{
	623	struct ravb_priv *eth = bus->priv;
	624
	625	*v = (readl(eth->iobase + RAVB_REG_PIR) & PIR_MDI) >> 3;
	626
	627	return 0;
	628	}
	629
	630	int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
	631	{
	632	struct ravb_priv *eth = bus->priv;
	633
	634	if (v)
	635	setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
	636	else
	637	clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
	638
	639	return 0;
	640	}
	641
	642	int ravb_bb_delay(struct bb_miiphy_bus *bus)
	643	{
	644	udelay(10);
645
646	return 0;
647	}
648
649	struct bb_miiphy_bus bb_miiphy_buses[] = {
650	{
651	.name = "ravb",
652	.init = ravb_bb_init,
653	.mdio_active = ravb_bb_mdio_active,
654	.mdio_tristate = ravb_bb_mdio_tristate,
655	.set_mdio = ravb_bb_set_mdio,
656	.get_mdio = ravb_bb_get_mdio,
657	.set_mdc = ravb_bb_set_mdc,
658	.delay = ravb_bb_delay,
659	},
660	};
661	int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
662
663	static const struct eth_ops ravb_ops = {
664	.start = ravb_start,
665	.send = ravb_send,
666	.recv = ravb_recv,
667	.free_pkt = ravb_free_pkt,
668	.stop = ravb_stop,
669	.write_hwaddr = ravb_write_hwaddr,
670	};
671
d1998a9f	672	int ravb_of_to_plat(struct udevice *dev)
5ee8b4d7	673	{
c69cda25	674	struct eth_pdata *pdata = dev_get_plat(dev);
5ee8b4d7	675	const fdt32_t *cell;
5ee8b4d7	676
2548493a	677	pdata->iobase = dev_read_addr(dev);
123ca114 MB	678
123ca114 MB	679	pdata->phy_interface = dev_read_phy_mode(dev);
ffb0f6f4	680	if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
5ee8b4d7	681	return -EINVAL;
5ee8b4d7 MV	682
	683	pdata->max_speed = 1000;
	684	cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
	685	if (cell)
	686	pdata->max_speed = fdt32_to_cpu(*cell);
	687
	688	sprintf(bb_miiphy_buses[0].name, dev->name);
	689
123ca114	690	return 0;
5ee8b4d7 MV	691	}
	692
	693	static const struct udevice_id ravb_ids[] = {
5ee8b4d7 MV	694	{ .compatible = "renesas,etheravb-rcar-gen3" },
	695	{ }
	696	};
	697
8ae51b6f MV	698	U_BOOT_DRIVER(eth_ravb) = {
	699	.name = "ravb",
	700	.id = UCLASS_ETH,
5ee8b4d7	701	.of_match = ravb_ids,
d1998a9f	702	.of_to_plat = ravb_of_to_plat,
8ae51b6f MV	703	.probe = ravb_probe,
	704	.remove = ravb_remove,
	705	.ops = &ravb_ops,
41575d8e	706	.priv_auto = sizeof(struct ravb_priv),
caa4daa2	707	.plat_auto = sizeof(struct eth_pdata),
8ae51b6f MV	708	.flags = DM_FLAG_ALLOC_PRIV_DMA,
8ae51b6f MV	709	};