[people/ms/u-boot.git] / drivers / net / ravb.c

/*
 * drivers/net/ravb.c
 *     This file is driver for Renesas Ethernet AVB.
 *
 * Copyright (C) 2015-2017  Renesas Electronics Corporation
 *
 * Based on the SuperH Ethernet driver.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <errno.h>
#include <miiphy.h>
#include <malloc.h>
#include <linux/mii.h>
#include <wait_bit.h>
#include <asm/io.h>

/* Registers */
#define RAVB_REG_CCC		0x000
#define RAVB_REG_DBAT		0x004
#define RAVB_REG_CSR		0x00C
#define RAVB_REG_APSR		0x08C
#define RAVB_REG_RCR		0x090
#define RAVB_REG_TGC		0x300
#define RAVB_REG_TCCR		0x304
#define RAVB_REG_RIC0		0x360
#define RAVB_REG_RIC1		0x368
#define RAVB_REG_RIC2		0x370
#define RAVB_REG_TIC		0x378
#define RAVB_REG_ECMR		0x500
#define RAVB_REG_RFLR		0x508
#define RAVB_REG_ECSIPR		0x518
#define RAVB_REG_PIR		0x520
#define RAVB_REG_GECMR		0x5b0
#define RAVB_REG_MAHR		0x5c0
#define RAVB_REG_MALR		0x5c8

#define CCC_OPC_CONFIG		BIT(0)
#define CCC_OPC_OPERATION	BIT(1)
#define CCC_BOC			BIT(20)

#define CSR_OPS			0x0000000F
#define CSR_OPS_CONFIG		BIT(1)

#define TCCR_TSRQ0		BIT(0)

#define RFLR_RFL_MIN		0x05EE

#define PIR_MDI			BIT(3)
#define PIR_MDO			BIT(2)
#define PIR_MMD			BIT(1)
#define PIR_MDC			BIT(0)

#define ECMR_TRCCM		BIT(26)
#define ECMR_RZPF		BIT(20)
#define ECMR_PFR		BIT(18)
#define ECMR_RXF		BIT(17)
#define ECMR_RE			BIT(6)
#define ECMR_TE			BIT(5)
#define ECMR_DM			BIT(1)
#define ECMR_CHG_DM		(ECMR_TRCCM | ECMR_RZPF | ECMR_PFR | ECMR_RXF)

/* DMA Descriptors */
#define RAVB_NUM_BASE_DESC		16
#define RAVB_NUM_TX_DESC		8
#define RAVB_NUM_RX_DESC		8

#define RAVB_TX_QUEUE_OFFSET		0
#define RAVB_RX_QUEUE_OFFSET		4

#define RAVB_DESC_DT(n)			((n) << 28)
#define RAVB_DESC_DT_FSINGLE		RAVB_DESC_DT(0x7)
#define RAVB_DESC_DT_LINKFIX		RAVB_DESC_DT(0x9)
#define RAVB_DESC_DT_EOS		RAVB_DESC_DT(0xa)
#define RAVB_DESC_DT_FEMPTY		RAVB_DESC_DT(0xc)
#define RAVB_DESC_DT_EEMPTY		RAVB_DESC_DT(0x3)
#define RAVB_DESC_DT_MASK		RAVB_DESC_DT(0xf)

#define RAVB_DESC_DS(n)			(((n) & 0xfff) << 0)
#define RAVB_DESC_DS_MASK		0xfff

#define RAVB_RX_DESC_MSC_MC		BIT(23)
#define RAVB_RX_DESC_MSC_CEEF		BIT(22)
#define RAVB_RX_DESC_MSC_CRL		BIT(21)
#define RAVB_RX_DESC_MSC_FRE		BIT(20)
#define RAVB_RX_DESC_MSC_RTLF		BIT(19)
#define RAVB_RX_DESC_MSC_RTSF		BIT(18)
#define RAVB_RX_DESC_MSC_RFE		BIT(17)
#define RAVB_RX_DESC_MSC_CRC		BIT(16)
#define RAVB_RX_DESC_MSC_MASK		(0xff << 16)

#define RAVB_RX_DESC_MSC_RX_ERR_MASK \
	(RAVB_RX_DESC_MSC_CRC | RAVB_RX_DESC_MSC_RFE | RAVB_RX_DESC_MSC_RTLF | \
	 RAVB_RX_DESC_MSC_RTSF | RAVB_RX_DESC_MSC_CEEF)

#define RAVB_TX_TIMEOUT_MS		1000

struct ravb_desc {
	u32	ctrl;
	u32	dptr;
};

struct ravb_rxdesc {
	struct ravb_desc	data;
	struct ravb_desc	link;
	u8			__pad[48];
	u8			packet[PKTSIZE_ALIGN];
};

struct ravb_priv {
	struct ravb_desc	base_desc[RAVB_NUM_BASE_DESC];
	struct ravb_desc	tx_desc[RAVB_NUM_TX_DESC];
	struct ravb_rxdesc	rx_desc[RAVB_NUM_RX_DESC];
	u32			rx_desc_idx;
	u32			tx_desc_idx;

	struct phy_device	*phydev;
	struct mii_dev		*bus;
	void __iomem		*iobase;
};

static inline void ravb_flush_dcache(u32 addr, u32 len)
{
	flush_dcache_range(addr, addr + len);
}

static inline void ravb_invalidate_dcache(u32 addr, u32 len)
{
	u32 start = addr & ~((uintptr_t)ARCH_DMA_MINALIGN - 1);
	u32 end = roundup(addr + len, ARCH_DMA_MINALIGN);
	invalidate_dcache_range(start, end);
}

static int ravb_send(struct udevice *dev, void *packet, int len)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct ravb_desc *desc = &eth->tx_desc[eth->tx_desc_idx];
	unsigned int start;

	/* Update TX descriptor */
	ravb_flush_dcache((uintptr_t)packet, len);
	memset(desc, 0x0, sizeof(*desc));
	desc->ctrl = RAVB_DESC_DT_FSINGLE | RAVB_DESC_DS(len);
	desc->dptr = (uintptr_t)packet;
	ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));

	/* Restart the transmitter if disabled */
	if (!(readl(eth->iobase + RAVB_REG_TCCR) & TCCR_TSRQ0))
		setbits_le32(eth->iobase + RAVB_REG_TCCR, TCCR_TSRQ0);

	/* Wait until packet is transmitted */
	start = get_timer(0);
	while (get_timer(start) < RAVB_TX_TIMEOUT_MS) {
		ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
		if ((desc->ctrl & RAVB_DESC_DT_MASK) != RAVB_DESC_DT_FSINGLE)
			break;
		udelay(10);
	};

	if (get_timer(start) >= RAVB_TX_TIMEOUT_MS)
		return -ETIMEDOUT;

	eth->tx_desc_idx = (eth->tx_desc_idx + 1) % (RAVB_NUM_TX_DESC - 1);
	return 0;
}

static int ravb_recv(struct udevice *dev, int flags, uchar **packetp)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct ravb_rxdesc *desc = &eth->rx_desc[eth->rx_desc_idx];
	int len;
	u8 *packet;

	/* Check if the rx descriptor is ready */
	ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
	if ((desc->data.ctrl & RAVB_DESC_DT_MASK) == RAVB_DESC_DT_FEMPTY)
		return -EAGAIN;

	/* Check for errors */
	if (desc->data.ctrl & RAVB_RX_DESC_MSC_RX_ERR_MASK) {
		desc->data.ctrl &= ~RAVB_RX_DESC_MSC_MASK;
		return -EAGAIN;
	}

	len = desc->data.ctrl & RAVB_DESC_DS_MASK;
	packet = (u8 *)(uintptr_t)desc->data.dptr;
	ravb_invalidate_dcache((uintptr_t)packet, len);

	*packetp = packet;
	return len;
}

static int ravb_free_pkt(struct udevice *dev, uchar *packet, int length)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct ravb_rxdesc *desc = &eth->rx_desc[eth->rx_desc_idx];

	/* Make current descriptor available again */
	desc->data.ctrl = RAVB_DESC_DT_FEMPTY | RAVB_DESC_DS(PKTSIZE_ALIGN);
	ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));

	/* Point to the next descriptor */
	eth->rx_desc_idx = (eth->rx_desc_idx + 1) % RAVB_NUM_RX_DESC;
	desc = &eth->rx_desc[eth->rx_desc_idx];
	ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));

	return 0;
}

static int ravb_reset(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);

	/* Set config mode */
	writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC);

	/* Check the operating mode is changed to the config mode. */
	return wait_for_bit(dev->name, (void *)eth->iobase + RAVB_REG_CSR,
			    CSR_OPS_CONFIG, true, 100, true);
}

static void ravb_base_desc_init(struct ravb_priv *eth)
{
	const u32 desc_size = RAVB_NUM_BASE_DESC * sizeof(struct ravb_desc);
	int i;

	/* Initialize all descriptors */
	memset(eth->base_desc, 0x0, desc_size);

	for (i = 0; i < RAVB_NUM_BASE_DESC; i++)
		eth->base_desc[i].ctrl = RAVB_DESC_DT_EOS;

	ravb_flush_dcache((uintptr_t)eth->base_desc, desc_size);

	/* Register the descriptor base address table */
	writel((uintptr_t)eth->base_desc, eth->iobase + RAVB_REG_DBAT);
}

static void ravb_tx_desc_init(struct ravb_priv *eth)
{
	const u32 desc_size = RAVB_NUM_TX_DESC * sizeof(struct ravb_desc);
	int i;

	/* Initialize all descriptors */
	memset(eth->tx_desc, 0x0, desc_size);
	eth->tx_desc_idx = 0;

	for (i = 0; i < RAVB_NUM_TX_DESC; i++)
		eth->tx_desc[i].ctrl = RAVB_DESC_DT_EEMPTY;

	/* Mark the end of the descriptors */
	eth->tx_desc[RAVB_NUM_TX_DESC - 1].ctrl = RAVB_DESC_DT_LINKFIX;
	eth->tx_desc[RAVB_NUM_TX_DESC - 1].dptr = (uintptr_t)eth->tx_desc;
	ravb_flush_dcache((uintptr_t)eth->tx_desc, desc_size);

	/* Point the controller to the TX descriptor list. */
	eth->base_desc[RAVB_TX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
	eth->base_desc[RAVB_TX_QUEUE_OFFSET].dptr = (uintptr_t)eth->tx_desc;
	ravb_flush_dcache((uintptr_t)&eth->base_desc[RAVB_TX_QUEUE_OFFSET],
			  sizeof(struct ravb_desc));
}

static void ravb_rx_desc_init(struct ravb_priv *eth)
{
	const u32 desc_size = RAVB_NUM_RX_DESC * sizeof(struct ravb_rxdesc);
	int i;

	/* Initialize all descriptors */
	memset(eth->rx_desc, 0x0, desc_size);
	eth->rx_desc_idx = 0;

	for (i = 0; i < RAVB_NUM_RX_DESC; i++) {
		eth->rx_desc[i].data.ctrl = RAVB_DESC_DT_EEMPTY |
					    RAVB_DESC_DS(PKTSIZE_ALIGN);
		eth->rx_desc[i].data.dptr = (uintptr_t)eth->rx_desc[i].packet;

		eth->rx_desc[i].link.ctrl = RAVB_DESC_DT_LINKFIX;
		eth->rx_desc[i].link.dptr = (uintptr_t)&eth->rx_desc[i + 1];
	}

	/* Mark the end of the descriptors */
	eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.ctrl = RAVB_DESC_DT_LINKFIX;
	eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.dptr = (uintptr_t)eth->rx_desc;
	ravb_flush_dcache((uintptr_t)eth->rx_desc, desc_size);

	/* Point the controller to the rx descriptor list */
	eth->base_desc[RAVB_RX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
	eth->base_desc[RAVB_RX_QUEUE_OFFSET].dptr = (uintptr_t)eth->rx_desc;
	ravb_flush_dcache((uintptr_t)&eth->base_desc[RAVB_RX_QUEUE_OFFSET],
			  sizeof(struct ravb_desc));
}

static int ravb_phy_config(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_platdata(dev);
	struct phy_device *phydev;
	int mask = 0xffffffff, reg;

	phydev = phy_find_by_mask(eth->bus, mask, pdata->phy_interface);
	if (!phydev)
		return -ENODEV;

	phy_connect_dev(phydev, dev);

	eth->phydev = phydev;

	/* 10BASE is not supported for Ethernet AVB MAC */
	phydev->supported &= ~(SUPPORTED_10baseT_Full
			       | SUPPORTED_10baseT_Half);
	if (pdata->max_speed != 1000) {
		phydev->supported &= ~(SUPPORTED_1000baseT_Half
				       | SUPPORTED_1000baseT_Full);
		reg = phy_read(phydev, -1, MII_CTRL1000);
		reg &= ~(BIT(9) | BIT(8));
		phy_write(phydev, -1, MII_CTRL1000, reg);
	}

	phy_config(phydev);

	return 0;
}

/* Set Mac address */
static int ravb_write_hwaddr(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_platdata(dev);
	unsigned char *mac = pdata->enetaddr;

	writel((mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3],
	       eth->iobase + RAVB_REG_MAHR);

	writel((mac[4] << 8) | mac[5], eth->iobase + RAVB_REG_MALR);

	return 0;
}

/* E-MAC init function */
static int ravb_mac_init(struct ravb_priv *eth)
{
	/* Disable MAC Interrupt */
	writel(0, eth->iobase + RAVB_REG_ECSIPR);

	/* Recv frame limit set register */
	writel(RFLR_RFL_MIN, eth->iobase + RAVB_REG_RFLR);

	return 0;
}

/* AVB-DMAC init function */
static int ravb_dmac_init(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_platdata(dev);
	int ret = 0;

	/* Set CONFIG mode */
	ret = ravb_reset(dev);
	if (ret)
		return ret;

	/* Disable all interrupts */
	writel(0, eth->iobase + RAVB_REG_RIC0);
	writel(0, eth->iobase + RAVB_REG_RIC1);
	writel(0, eth->iobase + RAVB_REG_RIC2);
	writel(0, eth->iobase + RAVB_REG_TIC);

	/* Set little endian */
	clrbits_le32(eth->iobase + RAVB_REG_CCC, CCC_BOC);

	/* AVB rx set */
	writel(0x18000001, eth->iobase + RAVB_REG_RCR);

	/* FIFO size set */
	writel(0x00222210, eth->iobase + RAVB_REG_TGC);

	/* Delay CLK: 2ns */
	if (pdata->max_speed == 1000)
		writel(BIT(14), eth->iobase + RAVB_REG_APSR);

	return 0;
}

static int ravb_config(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct phy_device *phy;
	u32 mask = ECMR_CHG_DM | ECMR_RE | ECMR_TE;
	int ret;

	/* Configure AVB-DMAC register */
	ravb_dmac_init(dev);

	/* Configure E-MAC registers */
	ravb_mac_init(eth);
	ravb_write_hwaddr(dev);

	/* Configure phy */
	ret = ravb_phy_config(dev);
	if (ret)
		return ret;

	phy = eth->phydev;

	ret = phy_startup(phy);
	if (ret)
		return ret;

	/* Set the transfer speed */
	if (phy->speed == 100)
		writel(0, eth->iobase + RAVB_REG_GECMR);
	else if (phy->speed == 1000)
		writel(1, eth->iobase + RAVB_REG_GECMR);

	/* Check if full duplex mode is supported by the phy */
	if (phy->duplex)
		mask |= ECMR_DM;

	writel(mask, eth->iobase + RAVB_REG_ECMR);

	phy->drv->writeext(phy, -1, 0x02, 0x08, (0x0f << 5) | 0x19);

	return 0;
}

int ravb_start(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	int ret;

	ret = ravb_reset(dev);
	if (ret)
		return ret;

	ravb_base_desc_init(eth);
	ravb_tx_desc_init(eth);
	ravb_rx_desc_init(eth);

	ret = ravb_config(dev);
	if (ret)
		return ret;

	/* Setting the control will start the AVB-DMAC process. */
	writel(CCC_OPC_OPERATION, eth->iobase + RAVB_REG_CCC);

	return 0;
}

static void ravb_stop(struct udevice *dev)
{
	ravb_reset(dev);
}

static int ravb_probe(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_platdata(dev);
	struct ravb_priv *eth = dev_get_priv(dev);
	struct mii_dev *mdiodev;
	void __iomem *iobase;
	int ret;

	iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
	eth->iobase = iobase;

	mdiodev = mdio_alloc();
	if (!mdiodev) {
		ret = -ENOMEM;
		goto err_mdio_alloc;
	}

	mdiodev->read = bb_miiphy_read;
	mdiodev->write = bb_miiphy_write;
	bb_miiphy_buses[0].priv = eth;
	snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);

	ret = mdio_register(mdiodev);
	if (ret < 0)
		goto err_mdio_register;

	eth->bus = miiphy_get_dev_by_name(dev->name);

	return 0;

err_mdio_register:
	mdio_free(mdiodev);
err_mdio_alloc:
	unmap_physmem(eth->iobase, MAP_NOCACHE);
	return ret;
}

static int ravb_remove(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);

	free(eth->phydev);
	mdio_unregister(eth->bus);
	mdio_free(eth->bus);
	unmap_physmem(eth->iobase, MAP_NOCACHE);

	return 0;
}

int ravb_bb_init(struct bb_miiphy_bus *bus)
{
	return 0;
}

int ravb_bb_mdio_active(struct bb_miiphy_bus *bus)
{
	struct ravb_priv *eth = bus->priv;

	setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);

	return 0;
}

int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus)
{
	struct ravb_priv *eth = bus->priv;

	clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);

	return 0;
}

int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
{
	struct ravb_priv *eth = bus->priv;

	if (v)
		setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
	else
		clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);

	return 0;
}

int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
{
	struct ravb_priv *eth = bus->priv;

	*v = (readl(eth->iobase + RAVB_REG_PIR) & PIR_MDI) >> 3;

	return 0;
}

int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
{
	struct ravb_priv *eth = bus->priv;

	if (v)
		setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
	else
		clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);

	return 0;
}

int ravb_bb_delay(struct bb_miiphy_bus *bus)
{
	udelay(10);

	return 0;
}

struct bb_miiphy_bus bb_miiphy_buses[] = {
	{
		.name		= "ravb",
		.init		= ravb_bb_init,
		.mdio_active	= ravb_bb_mdio_active,
		.mdio_tristate	= ravb_bb_mdio_tristate,
		.set_mdio	= ravb_bb_set_mdio,
		.get_mdio	= ravb_bb_get_mdio,
		.set_mdc	= ravb_bb_set_mdc,
		.delay		= ravb_bb_delay,
	},
};
int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);

static const struct eth_ops ravb_ops = {
	.start			= ravb_start,
	.send			= ravb_send,
	.recv			= ravb_recv,
	.free_pkt		= ravb_free_pkt,
	.stop			= ravb_stop,
	.write_hwaddr		= ravb_write_hwaddr,
};

int ravb_ofdata_to_platdata(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_platdata(dev);
	const char *phy_mode;
	const fdt32_t *cell;
	int ret = 0;

	pdata->iobase = devfdt_get_addr(dev);
	pdata->phy_interface = -1;
	phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
			       NULL);
	if (phy_mode)
		pdata->phy_interface = phy_get_interface_by_name(phy_mode);
	if (pdata->phy_interface == -1) {
		debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
		return -EINVAL;
	}

	pdata->max_speed = 1000;
	cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
	if (cell)
		pdata->max_speed = fdt32_to_cpu(*cell);

	sprintf(bb_miiphy_buses[0].name, dev->name);

	return ret;
}

static const struct udevice_id ravb_ids[] = {
	{ .compatible = "renesas,etheravb-r8a7795" },
	{ .compatible = "renesas,etheravb-r8a7796" },
	{ .compatible = "renesas,etheravb-rcar-gen3" },
	{ }
};

U_BOOT_DRIVER(eth_ravb) = {
	.name		= "ravb",
	.id		= UCLASS_ETH,
	.of_match	= ravb_ids,
	.ofdata_to_platdata = ravb_ofdata_to_platdata,
	.probe		= ravb_probe,
	.remove		= ravb_remove,
	.ops		= &ravb_ops,
	.priv_auto_alloc_size = sizeof(struct ravb_priv),
	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
	.flags		= DM_FLAG_ALLOC_PRIV_DMA,
};
Commit	Line	Data
8ae51b6f MV	1	/*
	2	* drivers/net/ravb.c
	3	* This file is driver for Renesas Ethernet AVB.
	4	*
	5	* Copyright (C) 2015-2017 Renesas Electronics Corporation
	6	*
	7	* Based on the SuperH Ethernet driver.
	8	*
	9	* SPDX-License-Identifier: GPL-2.0+
	10	*/
	11
	12	#include <common.h>
	13	#include <dm.h>
	14	#include <errno.h>
	15	#include <miiphy.h>
	16	#include <malloc.h>
	17	#include <linux/mii.h>
	18	#include <wait_bit.h>
	19	#include <asm/io.h>
	20
	21	/* Registers */
	22	#define RAVB_REG_CCC 0x000
	23	#define RAVB_REG_DBAT 0x004
	24	#define RAVB_REG_CSR 0x00C
	25	#define RAVB_REG_APSR 0x08C
	26	#define RAVB_REG_RCR 0x090
	27	#define RAVB_REG_TGC 0x300
	28	#define RAVB_REG_TCCR 0x304
	29	#define RAVB_REG_RIC0 0x360
	30	#define RAVB_REG_RIC1 0x368
	31	#define RAVB_REG_RIC2 0x370
	32	#define RAVB_REG_TIC 0x378
	33	#define RAVB_REG_ECMR 0x500
	34	#define RAVB_REG_RFLR 0x508
	35	#define RAVB_REG_ECSIPR 0x518
	36	#define RAVB_REG_PIR 0x520
	37	#define RAVB_REG_GECMR 0x5b0
	38	#define RAVB_REG_MAHR 0x5c0
	39	#define RAVB_REG_MALR 0x5c8
	40
	41	#define CCC_OPC_CONFIG BIT(0)
	42	#define CCC_OPC_OPERATION BIT(1)
	43	#define CCC_BOC BIT(20)
	44
	45	#define CSR_OPS 0x0000000F
	46	#define CSR_OPS_CONFIG BIT(1)
	47
	48	#define TCCR_TSRQ0 BIT(0)
	49
	50	#define RFLR_RFL_MIN 0x05EE
	51
	52	#define PIR_MDI BIT(3)
	53	#define PIR_MDO BIT(2)
	54	#define PIR_MMD BIT(1)
	55	#define PIR_MDC BIT(0)
	56
	57	#define ECMR_TRCCM BIT(26)
	58	#define ECMR_RZPF BIT(20)
	59	#define ECMR_PFR BIT(18)
	60	#define ECMR_RXF BIT(17)
	61	#define ECMR_RE BIT(6)
	62	#define ECMR_TE BIT(5)
	63	#define ECMR_DM BIT(1)
	64	#define ECMR_CHG_DM (ECMR_TRCCM \| ECMR_RZPF \| ECMR_PFR \| ECMR_RXF)
65
66	/* DMA Descriptors */
67	#define RAVB_NUM_BASE_DESC 16
68	#define RAVB_NUM_TX_DESC 8
69	#define RAVB_NUM_RX_DESC 8
70
71	#define RAVB_TX_QUEUE_OFFSET 0
72	#define RAVB_RX_QUEUE_OFFSET 4
73
74	#define RAVB_DESC_DT(n) ((n) << 28)
75	#define RAVB_DESC_DT_FSINGLE RAVB_DESC_DT(0x7)
76	#define RAVB_DESC_DT_LINKFIX RAVB_DESC_DT(0x9)
77	#define RAVB_DESC_DT_EOS RAVB_DESC_DT(0xa)
78	#define RAVB_DESC_DT_FEMPTY RAVB_DESC_DT(0xc)
79	#define RAVB_DESC_DT_EEMPTY RAVB_DESC_DT(0x3)
80	#define RAVB_DESC_DT_MASK RAVB_DESC_DT(0xf)
81
82	#define RAVB_DESC_DS(n) (((n) & 0xfff) << 0)
83	#define RAVB_DESC_DS_MASK 0xfff
84
85	#define RAVB_RX_DESC_MSC_MC BIT(23)
86	#define RAVB_RX_DESC_MSC_CEEF BIT(22)
87	#define RAVB_RX_DESC_MSC_CRL BIT(21)
88	#define RAVB_RX_DESC_MSC_FRE BIT(20)
89	#define RAVB_RX_DESC_MSC_RTLF BIT(19)
90	#define RAVB_RX_DESC_MSC_RTSF BIT(18)
91	#define RAVB_RX_DESC_MSC_RFE BIT(17)
92	#define RAVB_RX_DESC_MSC_CRC BIT(16)
93	#define RAVB_RX_DESC_MSC_MASK (0xff << 16)
94
95	#define RAVB_RX_DESC_MSC_RX_ERR_MASK \
96	(RAVB_RX_DESC_MSC_CRC \| RAVB_RX_DESC_MSC_RFE \| RAVB_RX_DESC_MSC_RTLF \| \
97	RAVB_RX_DESC_MSC_RTSF \| RAVB_RX_DESC_MSC_CEEF)
98
99	#define RAVB_TX_TIMEOUT_MS 1000
100
101	struct ravb_desc {
102	u32 ctrl;
103	u32 dptr;
104	};
105
106	struct ravb_rxdesc {
107	struct ravb_desc data;
108	struct ravb_desc link;
109	u8 __pad[48];
110	u8 packet[PKTSIZE_ALIGN];
111	};
112
113	struct ravb_priv {
114	struct ravb_desc base_desc[RAVB_NUM_BASE_DESC];
115	struct ravb_desc tx_desc[RAVB_NUM_TX_DESC];
116	struct ravb_rxdesc rx_desc[RAVB_NUM_RX_DESC];
117	u32 rx_desc_idx;
118	u32 tx_desc_idx;
119
120	struct phy_device *phydev;
121	struct mii_dev *bus;
122	void __iomem *iobase;
123	};
124
125	static inline void ravb_flush_dcache(u32 addr, u32 len)
126	{
127	flush_dcache_range(addr, addr + len);
128	}
129
130	static inline void ravb_invalidate_dcache(u32 addr, u32 len)
131	{
132	u32 start = addr & ~((uintptr_t)ARCH_DMA_MINALIGN - 1);
133	u32 end = roundup(addr + len, ARCH_DMA_MINALIGN);
134	invalidate_dcache_range(start, end);
135	}
136
137	static int ravb_send(struct udevice dev, void packet, int len)
138	{
139	struct ravb_priv *eth = dev_get_priv(dev);
140	struct ravb_desc *desc = &eth->tx_desc[eth->tx_desc_idx];
141	unsigned int start;
142
143	/* Update TX descriptor */
144	ravb_flush_dcache((uintptr_t)packet, len);
145	memset(desc, 0x0, sizeof(*desc));
146	desc->ctrl = RAVB_DESC_DT_FSINGLE \| RAVB_DESC_DS(len);
147	desc->dptr = (uintptr_t)packet;
148	ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));
149
150	/* Restart the transmitter if disabled */
151	if (!(readl(eth->iobase + RAVB_REG_TCCR) & TCCR_TSRQ0))
152	setbits_le32(eth->iobase + RAVB_REG_TCCR, TCCR_TSRQ0);
153
154	/* Wait until packet is transmitted */
155	start = get_timer(0);
156	while (get_timer(start) < RAVB_TX_TIMEOUT_MS) {
157	ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
158	if ((desc->ctrl & RAVB_DESC_DT_MASK) != RAVB_DESC_DT_FSINGLE)
159	break;
160	udelay(10);
161	};
162
163	if (get_timer(start) >= RAVB_TX_TIMEOUT_MS)
164	return -ETIMEDOUT;
165
166	eth->tx_desc_idx = (eth->tx_desc_idx + 1) % (RAVB_NUM_TX_DESC - 1);
167	return 0;
168	}
169
170	static int ravb_recv(struct udevice dev, int flags, uchar *packetp)
171	{
172	struct ravb_priv *eth = dev_get_priv(dev);
173	struct ravb_rxdesc *desc = &eth->rx_desc[eth->rx_desc_idx];
174	int len;
175	u8 *packet;
176
177	/* Check if the rx descriptor is ready */
178	ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
179	if ((desc->data.ctrl & RAVB_DESC_DT_MASK) == RAVB_DESC_DT_FEMPTY)
180	return -EAGAIN;
181
182	/* Check for errors */
183	if (desc->data.ctrl & RAVB_RX_DESC_MSC_RX_ERR_MASK) {
184	desc->data.ctrl &= ~RAVB_RX_DESC_MSC_MASK;
185	return -EAGAIN;
186	}
187
188	len = desc->data.ctrl & RAVB_DESC_DS_MASK;
189	packet = (u8 *)(uintptr_t)desc->data.dptr;
190	ravb_invalidate_dcache((uintptr_t)packet, len);
191
192	*packetp = packet;
193	return len;
194	}
195
196	static int ravb_free_pkt(struct udevice dev, uchar packet, int length)
197	{
198	struct ravb_priv *eth = dev_get_priv(dev);
199	struct ravb_rxdesc *desc = &eth->rx_desc[eth->rx_desc_idx];
200
201	/* Make current descriptor available again */
202	desc->data.ctrl = RAVB_DESC_DT_FEMPTY \| RAVB_DESC_DS(PKTSIZE_ALIGN);
203	ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));
204
205	/* Point to the next descriptor */
206	eth->rx_desc_idx = (eth->rx_desc_idx + 1) % RAVB_NUM_RX_DESC;
207	desc = &eth->rx_desc[eth->rx_desc_idx];
208	ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
209
210	return 0;
211	}
212
213	static int ravb_reset(struct udevice *dev)
214	{
215	struct ravb_priv *eth = dev_get_priv(dev);
216
217	/* Set config mode */
218	writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC);
219
220	/* Check the operating mode is changed to the config mode. */
221	return wait_for_bit(dev->name, (void *)eth->iobase + RAVB_REG_CSR,
222	CSR_OPS_CONFIG, true, 100, true);
223	}
224
225	static void ravb_base_desc_init(struct ravb_priv *eth)
226	{
227	const u32 desc_size = RAVB_NUM_BASE_DESC * sizeof(struct ravb_desc);
228	int i;
229
230	/* Initialize all descriptors */
231	memset(eth->base_desc, 0x0, desc_size);
232
233	for (i = 0; i < RAVB_NUM_BASE_DESC; i++)
234	eth->base_desc[i].ctrl = RAVB_DESC_DT_EOS;
235
236	ravb_flush_dcache((uintptr_t)eth->base_desc, desc_size);
237
238	/* Register the descriptor base address table */
239	writel((uintptr_t)eth->base_desc, eth->iobase + RAVB_REG_DBAT);
240	}
241
242	static void ravb_tx_desc_init(struct ravb_priv *eth)
243	{
244	const u32 desc_size = RAVB_NUM_TX_DESC * sizeof(struct ravb_desc);
245	int i;
246
247	/* Initialize all descriptors */
248	memset(eth->tx_desc, 0x0, desc_size);
249	eth->tx_desc_idx = 0;
250
251	for (i = 0; i < RAVB_NUM_TX_DESC; i++)
252	eth->tx_desc[i].ctrl = RAVB_DESC_DT_EEMPTY;
253
254	/* Mark the end of the descriptors */
255	eth->tx_desc[RAVB_NUM_TX_DESC - 1].ctrl = RAVB_DESC_DT_LINKFIX;
256	eth->tx_desc[RAVB_NUM_TX_DESC - 1].dptr = (uintptr_t)eth->tx_desc;
257	ravb_flush_dcache((uintptr_t)eth->tx_desc, desc_size);
258
259	/* Point the controller to the TX descriptor list. */
260	eth->base_desc[RAVB_TX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
261	eth->base_desc[RAVB_TX_QUEUE_OFFSET].dptr = (uintptr_t)eth->tx_desc;
262	ravb_flush_dcache((uintptr_t)&eth->base_desc[RAVB_TX_QUEUE_OFFSET],
263	sizeof(struct ravb_desc));
264	}
265
266	static void ravb_rx_desc_init(struct ravb_priv *eth)
267	{
268	const u32 desc_size = RAVB_NUM_RX_DESC * sizeof(struct ravb_rxdesc);
269	int i;
270
271	/* Initialize all descriptors */
272	memset(eth->rx_desc, 0x0, desc_size);
273	eth->rx_desc_idx = 0;
274
275	for (i = 0; i < RAVB_NUM_RX_DESC; i++) {
276	eth->rx_desc[i].data.ctrl = RAVB_DESC_DT_EEMPTY \|
277	RAVB_DESC_DS(PKTSIZE_ALIGN);
278	eth->rx_desc[i].data.dptr = (uintptr_t)eth->rx_desc[i].packet;
279
280	eth->rx_desc[i].link.ctrl = RAVB_DESC_DT_LINKFIX;
281	eth->rx_desc[i].link.dptr = (uintptr_t)&eth->rx_desc[i + 1];
282	}
283
284	/* Mark the end of the descriptors */
285	eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.ctrl = RAVB_DESC_DT_LINKFIX;
286	eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.dptr = (uintptr_t)eth->rx_desc;
287	ravb_flush_dcache((uintptr_t)eth->rx_desc, desc_size);
288
289	/* Point the controller to the rx descriptor list */
290	eth->base_desc[RAVB_RX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
291	eth->base_desc[RAVB_RX_QUEUE_OFFSET].dptr = (uintptr_t)eth->rx_desc;
292	ravb_flush_dcache((uintptr_t)&eth->base_desc[RAVB_RX_QUEUE_OFFSET],
293	sizeof(struct ravb_desc));
294	}
295
296	static int ravb_phy_config(struct udevice *dev)
297	{
298	struct ravb_priv *eth = dev_get_priv(dev);
299	struct eth_pdata *pdata = dev_get_platdata(dev);
300	struct phy_device *phydev;
e821a7bd	301	int mask = 0xffffffff, reg;
8ae51b6f	302
e821a7bd	303	phydev = phy_find_by_mask(eth->bus, mask, pdata->phy_interface);
8ae51b6f MV	304	if (!phydev)
	305	return -ENODEV;
	306
e821a7bd MV	307	phy_connect_dev(phydev, dev);
e821a7bd MV	308
8ae51b6f MV	309	eth->phydev = phydev;
	310
	311	/* 10BASE is not supported for Ethernet AVB MAC */
	312	phydev->supported &= ~(SUPPORTED_10baseT_Full
	313	\| SUPPORTED_10baseT_Half);
	314	if (pdata->max_speed != 1000) {
	315	phydev->supported &= ~(SUPPORTED_1000baseT_Half
	316	\| SUPPORTED_1000baseT_Full);
	317	reg = phy_read(phydev, -1, MII_CTRL1000);
	318	reg &= ~(BIT(9) \| BIT(8));
	319	phy_write(phydev, -1, MII_CTRL1000, reg);
	320	}
	321
	322	phy_config(phydev);
	323
	324	return 0;
	325	}
	326
	327	/* Set Mac address */
	328	static int ravb_write_hwaddr(struct udevice *dev)
	329	{
	330	struct ravb_priv *eth = dev_get_priv(dev);
	331	struct eth_pdata *pdata = dev_get_platdata(dev);
	332	unsigned char *mac = pdata->enetaddr;
	333
	334	writel((mac[0] << 24) \| (mac[1] << 16) \| (mac[2] << 8) \| mac[3],
	335	eth->iobase + RAVB_REG_MAHR);
	336
	337	writel((mac[4] << 8) \| mac[5], eth->iobase + RAVB_REG_MALR);
	338
	339	return 0;
	340	}
	341
	342	/* E-MAC init function */
	343	static int ravb_mac_init(struct ravb_priv *eth)
	344	{
	345	/* Disable MAC Interrupt */
	346	writel(0, eth->iobase + RAVB_REG_ECSIPR);
	347
	348	/* Recv frame limit set register */
	349	writel(RFLR_RFL_MIN, eth->iobase + RAVB_REG_RFLR);
	350
	351	return 0;
	352	}
	353
	354	/* AVB-DMAC init function */
	355	static int ravb_dmac_init(struct udevice *dev)
	356	{
	357	struct ravb_priv *eth = dev_get_priv(dev);
	358	struct eth_pdata *pdata = dev_get_platdata(dev);
	359	int ret = 0;
	360
	361	/* Set CONFIG mode */
	362	ret = ravb_reset(dev);
	363	if (ret)
	364	return ret;
	365
	366	/* Disable all interrupts */
	367	writel(0, eth->iobase + RAVB_REG_RIC0);
	368	writel(0, eth->iobase + RAVB_REG_RIC1);
	369	writel(0, eth->iobase + RAVB_REG_RIC2);
	370	writel(0, eth->iobase + RAVB_REG_TIC);
	371
	372	/* Set little endian */
373	clrbits_le32(eth->iobase + RAVB_REG_CCC, CCC_BOC);
374
375	/* AVB rx set */
376	writel(0x18000001, eth->iobase + RAVB_REG_RCR);
377
378	/* FIFO size set */
379	writel(0x00222210, eth->iobase + RAVB_REG_TGC);
380
381	/* Delay CLK: 2ns */
382	if (pdata->max_speed == 1000)
383	writel(BIT(14), eth->iobase + RAVB_REG_APSR);
384
385	return 0;
386	}
387
388	static int ravb_config(struct udevice *dev)
389	{
390	struct ravb_priv *eth = dev_get_priv(dev);
391	struct phy_device *phy;
392	u32 mask = ECMR_CHG_DM \| ECMR_RE \| ECMR_TE;
393	int ret;
394
395	/* Configure AVB-DMAC register */
396	ravb_dmac_init(dev);
397
398	/* Configure E-MAC registers */
399	ravb_mac_init(eth);
400	ravb_write_hwaddr(dev);
401
402	/* Configure phy */
403	ret = ravb_phy_config(dev);
404	if (ret)
405	return ret;
406
407	phy = eth->phydev;
408
409	ret = phy_startup(phy);
410	if (ret)
411	return ret;
412
413	/* Set the transfer speed */
414	if (phy->speed == 100)
415	writel(0, eth->iobase + RAVB_REG_GECMR);
416	else if (phy->speed == 1000)
417	writel(1, eth->iobase + RAVB_REG_GECMR);
418
419	/* Check if full duplex mode is supported by the phy */
420	if (phy->duplex)
421	mask \|= ECMR_DM;
422
423	writel(mask, eth->iobase + RAVB_REG_ECMR);
424
425	phy->drv->writeext(phy, -1, 0x02, 0x08, (0x0f << 5) \| 0x19);
426
427	return 0;
428	}
429
430	int ravb_start(struct udevice *dev)
431	{
432	struct ravb_priv *eth = dev_get_priv(dev);
433	int ret;
434
435	ret = ravb_reset(dev);
436	if (ret)
437	return ret;
438
439	ravb_base_desc_init(eth);
440	ravb_tx_desc_init(eth);
441	ravb_rx_desc_init(eth);
442
443	ret = ravb_config(dev);
444	if (ret)
445	return ret;
446
447	/* Setting the control will start the AVB-DMAC process. */
448	writel(CCC_OPC_OPERATION, eth->iobase + RAVB_REG_CCC);
449
450	return 0;
451	}
452
453	static void ravb_stop(struct udevice *dev)
454	{
455	ravb_reset(dev);
456	}
457
458	static int ravb_probe(struct udevice *dev)
459	{
460	struct eth_pdata *pdata = dev_get_platdata(dev);
461	struct ravb_priv *eth = dev_get_priv(dev);
462	struct mii_dev *mdiodev;
463	void __iomem *iobase;
464	int ret;
465
466	iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
467	eth->iobase = iobase;
468
469	mdiodev = mdio_alloc();
470	if (!mdiodev) {
471	ret = -ENOMEM;
472	goto err_mdio_alloc;
473	}
474
475	mdiodev->read = bb_miiphy_read;
476	mdiodev->write = bb_miiphy_write;
477	bb_miiphy_buses[0].priv = eth;
478	snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);
479
480	ret = mdio_register(mdiodev);
481	if (ret < 0)
482	goto err_mdio_register;
483
484	eth->bus = miiphy_get_dev_by_name(dev->name);
485
486	return 0;
487
488	err_mdio_register:
489	mdio_free(mdiodev);
490	err_mdio_alloc:
491	unmap_physmem(eth->iobase, MAP_NOCACHE);
492	return ret;
493	}
494
495	static int ravb_remove(struct udevice *dev)
496	{
497	struct ravb_priv *eth = dev_get_priv(dev);
498
499	free(eth->phydev);
500	mdio_unregister(eth->bus);
501	mdio_free(eth->bus);
502	unmap_physmem(eth->iobase, MAP_NOCACHE);
503
504	return 0;
505	}
506
507	int ravb_bb_init(struct bb_miiphy_bus *bus)
508	{
509	return 0;
510	}
511
512	int ravb_bb_mdio_active(struct bb_miiphy_bus *bus)
513	{
514	struct ravb_priv *eth = bus->priv;
515
516	setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
517
518	return 0;
519	}
520
521	int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus)
522	{
523	struct ravb_priv *eth = bus->priv;
524
525	clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
526
527	return 0;
528	}
529
530	int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
531	{
532	struct ravb_priv *eth = bus->priv;
533
534	if (v)
535	setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
536	else
537	clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
538
539	return 0;
540	}
541
542	int ravb_bb_get_mdio(struct bb_miiphy_bus bus, int v)
543	{
544	struct ravb_priv *eth = bus->priv;
545
546	*v = (readl(eth->iobase + RAVB_REG_PIR) & PIR_MDI) >> 3;
547
548	return 0;
549	}
550
551	int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
552	{
553	struct ravb_priv *eth = bus->priv;
554
555	if (v)
556	setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
557	else
558	clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
559
560	return 0;
561	}
562
563	int ravb_bb_delay(struct bb_miiphy_bus *bus)
564	{
565	udelay(10);
566
567	return 0;
568	}
569
570	struct bb_miiphy_bus bb_miiphy_buses[] = {
571	{
572	.name = "ravb",
573	.init = ravb_bb_init,
574	.mdio_active = ravb_bb_mdio_active,
575	.mdio_tristate = ravb_bb_mdio_tristate,
576	.set_mdio = ravb_bb_set_mdio,
577	.get_mdio = ravb_bb_get_mdio,
578	.set_mdc = ravb_bb_set_mdc,
579	.delay = ravb_bb_delay,
580	},
581	};
582	int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
583
584	static const struct eth_ops ravb_ops = {
585	.start = ravb_start,
586	.send = ravb_send,
587	.recv = ravb_recv,
588	.free_pkt = ravb_free_pkt,
589	.stop = ravb_stop,
590	.write_hwaddr = ravb_write_hwaddr,
591	};
592
5ee8b4d7 MV	593	int ravb_ofdata_to_platdata(struct udevice *dev)
	594	{
	595	struct eth_pdata *pdata = dev_get_platdata(dev);
	596	const char *phy_mode;
	597	const fdt32_t *cell;
	598	int ret = 0;
	599
	600	pdata->iobase = devfdt_get_addr(dev);
	601	pdata->phy_interface = -1;
	602	phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
	603	NULL);
	604	if (phy_mode)
	605	pdata->phy_interface = phy_get_interface_by_name(phy_mode);
	606	if (pdata->phy_interface == -1) {
	607	debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
	608	return -EINVAL;
	609	}
	610
	611	pdata->max_speed = 1000;
	612	cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
	613	if (cell)
	614	pdata->max_speed = fdt32_to_cpu(*cell);
	615
	616	sprintf(bb_miiphy_buses[0].name, dev->name);
	617
	618	return ret;
	619	}
	620
	621	static const struct udevice_id ravb_ids[] = {
	622	{ .compatible = "renesas,etheravb-r8a7795" },
	623	{ .compatible = "renesas,etheravb-r8a7796" },
	624	{ .compatible = "renesas,etheravb-rcar-gen3" },
	625	{ }
	626	};
	627
8ae51b6f MV	628	U_BOOT_DRIVER(eth_ravb) = {
	629	.name = "ravb",
	630	.id = UCLASS_ETH,
5ee8b4d7 MV	631	.of_match = ravb_ids,
5ee8b4d7 MV	632	.ofdata_to_platdata = ravb_ofdata_to_platdata,
8ae51b6f MV	633	.probe = ravb_probe,
	634	.remove = ravb_remove,
	635	.ops = &ravb_ops,
	636	.priv_auto_alloc_size = sizeof(struct ravb_priv),
	637	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
	638	.flags = DM_FLAG_ALLOC_PRIV_DMA,
	639	};