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Commit | Line | Data |
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a8bd82de WD |
1 | /* |
2 | * rtl8169.c : U-Boot driver for the RealTek RTL8169 | |
3 | * | |
4 | * Masami Komiya (mkomiya@sonare.it) | |
5 | * | |
6 | * Most part is taken from r8169.c of etherboot | |
7 | * | |
8 | */ | |
9 | ||
10 | /************************************************************************** | |
11 | * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit | |
12 | * Written 2003 by Timothy Legge <tlegge@rogers.com> | |
13 | * | |
1a459660 | 14 | * SPDX-License-Identifier: GPL-2.0+ |
a8bd82de WD |
15 | * |
16 | * Portions of this code based on: | |
17 | * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver | |
18 | * for Linux kernel 2.4.x. | |
19 | * | |
20 | * Written 2002 ShuChen <shuchen@realtek.com.tw> | |
21 | * See Linux Driver for full information | |
22 | * | |
23 | * Linux Driver Version 1.27a, 10.02.2002 | |
24 | * | |
25 | * Thanks to: | |
26 | * Jean Chen of RealTek Semiconductor Corp. for | |
27 | * providing the evaluation NIC used to develop | |
28 | * this driver. RealTek's support for Etherboot | |
29 | * is appreciated. | |
30 | * | |
31 | * REVISION HISTORY: | |
32 | * ================ | |
33 | * | |
34 | * v1.0 11-26-2003 timlegge Initial port of Linux driver | |
35 | * v1.5 01-17-2004 timlegge Initial driver output cleanup | |
36 | * | |
37 | * Indent Options: indent -kr -i8 | |
38 | ***************************************************************************/ | |
6a5e1d75 GL |
39 | /* |
40 | * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk> | |
41 | * Modified to use le32_to_cpu and cpu_to_le32 properly | |
42 | */ | |
a8bd82de | 43 | #include <common.h> |
d0a5a0b2 | 44 | #include <dm.h> |
d58acdcb | 45 | #include <errno.h> |
a8bd82de | 46 | #include <malloc.h> |
cf92e05c | 47 | #include <memalign.h> |
a8bd82de | 48 | #include <net.h> |
d0a5a0b2 | 49 | #ifndef CONFIG_DM_ETH |
02d69891 | 50 | #include <netdev.h> |
d0a5a0b2 | 51 | #endif |
a8bd82de WD |
52 | #include <asm/io.h> |
53 | #include <pci.h> | |
54 | ||
a8bd82de WD |
55 | #undef DEBUG_RTL8169 |
56 | #undef DEBUG_RTL8169_TX | |
57 | #undef DEBUG_RTL8169_RX | |
58 | ||
59 | #define drv_version "v1.5" | |
60 | #define drv_date "01-17-2004" | |
61 | ||
744152f8 | 62 | static unsigned long ioaddr; |
a8bd82de WD |
63 | |
64 | /* Condensed operations for readability. */ | |
a8bd82de | 65 | #define currticks() get_timer(0) |
a8bd82de WD |
66 | |
67 | /* media options */ | |
68 | #define MAX_UNITS 8 | |
69 | static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; | |
70 | ||
71 | /* MAC address length*/ | |
72 | #define MAC_ADDR_LEN 6 | |
73 | ||
74 | /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/ | |
75 | #define MAX_ETH_FRAME_SIZE 1536 | |
76 | ||
77 | #define TX_FIFO_THRESH 256 /* In bytes */ | |
78 | ||
79 | #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ | |
80 | #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ | |
81 | #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ | |
82 | #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ | |
83 | #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */ | |
84 | #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ | |
85 | ||
86 | #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */ | |
c94bbfdf TR |
87 | #ifdef CONFIG_SYS_RX_ETH_BUFFER |
88 | #define NUM_RX_DESC CONFIG_SYS_RX_ETH_BUFFER | |
89 | #else | |
90 | #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */ | |
91 | #endif | |
a8bd82de WD |
92 | #define RX_BUF_SIZE 1536 /* Rx Buffer size */ |
93 | #define RX_BUF_LEN 8192 | |
94 | ||
95 | #define RTL_MIN_IO_SIZE 0x80 | |
96 | #define TX_TIMEOUT (6*HZ) | |
97 | ||
6a5e1d75 | 98 | /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */ |
744152f8 TR |
99 | #define RTL_W8(reg, val8) writeb((val8), ioaddr + (reg)) |
100 | #define RTL_W16(reg, val16) writew((val16), ioaddr + (reg)) | |
101 | #define RTL_W32(reg, val32) writel((val32), ioaddr + (reg)) | |
102 | #define RTL_R8(reg) readb(ioaddr + (reg)) | |
103 | #define RTL_R16(reg) readw(ioaddr + (reg)) | |
104 | #define RTL_R32(reg) readl(ioaddr + (reg)) | |
a8bd82de WD |
105 | |
106 | #define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE | |
107 | #define ETH_ALEN MAC_ADDR_LEN | |
108 | #define ETH_ZLEN 60 | |
109 | ||
744152f8 TR |
110 | #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)(unsigned long)dev->priv, \ |
111 | (pci_addr_t)(unsigned long)a) | |
112 | #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)(unsigned long)dev->priv, \ | |
113 | (phys_addr_t)a) | |
d65e34d1 | 114 | |
a8bd82de WD |
115 | enum RTL8169_registers { |
116 | MAC0 = 0, /* Ethernet hardware address. */ | |
117 | MAR0 = 8, /* Multicast filter. */ | |
db70b843 YS |
118 | TxDescStartAddrLow = 0x20, |
119 | TxDescStartAddrHigh = 0x24, | |
120 | TxHDescStartAddrLow = 0x28, | |
121 | TxHDescStartAddrHigh = 0x2c, | |
a8bd82de WD |
122 | FLASH = 0x30, |
123 | ERSR = 0x36, | |
124 | ChipCmd = 0x37, | |
125 | TxPoll = 0x38, | |
126 | IntrMask = 0x3C, | |
127 | IntrStatus = 0x3E, | |
128 | TxConfig = 0x40, | |
129 | RxConfig = 0x44, | |
130 | RxMissed = 0x4C, | |
131 | Cfg9346 = 0x50, | |
132 | Config0 = 0x51, | |
133 | Config1 = 0x52, | |
134 | Config2 = 0x53, | |
135 | Config3 = 0x54, | |
136 | Config4 = 0x55, | |
137 | Config5 = 0x56, | |
138 | MultiIntr = 0x5C, | |
139 | PHYAR = 0x60, | |
140 | TBICSR = 0x64, | |
141 | TBI_ANAR = 0x68, | |
142 | TBI_LPAR = 0x6A, | |
143 | PHYstatus = 0x6C, | |
144 | RxMaxSize = 0xDA, | |
145 | CPlusCmd = 0xE0, | |
db70b843 YS |
146 | RxDescStartAddrLow = 0xE4, |
147 | RxDescStartAddrHigh = 0xE8, | |
a8bd82de WD |
148 | EarlyTxThres = 0xEC, |
149 | FuncEvent = 0xF0, | |
150 | FuncEventMask = 0xF4, | |
151 | FuncPresetState = 0xF8, | |
152 | FuncForceEvent = 0xFC, | |
153 | }; | |
154 | ||
155 | enum RTL8169_register_content { | |
156 | /*InterruptStatusBits */ | |
157 | SYSErr = 0x8000, | |
158 | PCSTimeout = 0x4000, | |
159 | SWInt = 0x0100, | |
160 | TxDescUnavail = 0x80, | |
161 | RxFIFOOver = 0x40, | |
162 | RxUnderrun = 0x20, | |
163 | RxOverflow = 0x10, | |
164 | TxErr = 0x08, | |
165 | TxOK = 0x04, | |
166 | RxErr = 0x02, | |
167 | RxOK = 0x01, | |
168 | ||
169 | /*RxStatusDesc */ | |
170 | RxRES = 0x00200000, | |
171 | RxCRC = 0x00080000, | |
172 | RxRUNT = 0x00100000, | |
173 | RxRWT = 0x00400000, | |
174 | ||
175 | /*ChipCmdBits */ | |
176 | CmdReset = 0x10, | |
177 | CmdRxEnb = 0x08, | |
178 | CmdTxEnb = 0x04, | |
179 | RxBufEmpty = 0x01, | |
180 | ||
181 | /*Cfg9346Bits */ | |
182 | Cfg9346_Lock = 0x00, | |
183 | Cfg9346_Unlock = 0xC0, | |
184 | ||
185 | /*rx_mode_bits */ | |
186 | AcceptErr = 0x20, | |
187 | AcceptRunt = 0x10, | |
188 | AcceptBroadcast = 0x08, | |
189 | AcceptMulticast = 0x04, | |
190 | AcceptMyPhys = 0x02, | |
191 | AcceptAllPhys = 0x01, | |
192 | ||
193 | /*RxConfigBits */ | |
194 | RxCfgFIFOShift = 13, | |
195 | RxCfgDMAShift = 8, | |
196 | ||
197 | /*TxConfigBits */ | |
198 | TxInterFrameGapShift = 24, | |
199 | TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ | |
200 | ||
201 | /*rtl8169_PHYstatus */ | |
202 | TBI_Enable = 0x80, | |
203 | TxFlowCtrl = 0x40, | |
204 | RxFlowCtrl = 0x20, | |
205 | _1000bpsF = 0x10, | |
206 | _100bps = 0x08, | |
207 | _10bps = 0x04, | |
208 | LinkStatus = 0x02, | |
209 | FullDup = 0x01, | |
210 | ||
211 | /*GIGABIT_PHY_registers */ | |
212 | PHY_CTRL_REG = 0, | |
213 | PHY_STAT_REG = 1, | |
214 | PHY_AUTO_NEGO_REG = 4, | |
215 | PHY_1000_CTRL_REG = 9, | |
216 | ||
217 | /*GIGABIT_PHY_REG_BIT */ | |
218 | PHY_Restart_Auto_Nego = 0x0200, | |
219 | PHY_Enable_Auto_Nego = 0x1000, | |
220 | ||
221 | /* PHY_STAT_REG = 1; */ | |
6a5e1d75 | 222 | PHY_Auto_Nego_Comp = 0x0020, |
a8bd82de WD |
223 | |
224 | /* PHY_AUTO_NEGO_REG = 4; */ | |
225 | PHY_Cap_10_Half = 0x0020, | |
226 | PHY_Cap_10_Full = 0x0040, | |
227 | PHY_Cap_100_Half = 0x0080, | |
228 | PHY_Cap_100_Full = 0x0100, | |
229 | ||
230 | /* PHY_1000_CTRL_REG = 9; */ | |
231 | PHY_Cap_1000_Full = 0x0200, | |
232 | ||
233 | PHY_Cap_Null = 0x0, | |
234 | ||
235 | /*_MediaType*/ | |
236 | _10_Half = 0x01, | |
237 | _10_Full = 0x02, | |
238 | _100_Half = 0x04, | |
239 | _100_Full = 0x08, | |
240 | _1000_Full = 0x10, | |
241 | ||
242 | /*_TBICSRBit*/ | |
243 | TBILinkOK = 0x02000000, | |
244 | }; | |
245 | ||
246 | static struct { | |
247 | const char *name; | |
248 | u8 version; /* depend on RTL8169 docs */ | |
249 | u32 RxConfigMask; /* should clear the bits supported by this chip */ | |
250 | } rtl_chip_info[] = { | |
251 | {"RTL-8169", 0x00, 0xff7e1880,}, | |
252 | {"RTL-8169", 0x04, 0xff7e1880,}, | |
d75469d4 NI |
253 | {"RTL-8169", 0x00, 0xff7e1880,}, |
254 | {"RTL-8169s/8110s", 0x02, 0xff7e1880,}, | |
255 | {"RTL-8169s/8110s", 0x04, 0xff7e1880,}, | |
256 | {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,}, | |
257 | {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,}, | |
258 | {"RTL-8168b/8111sb", 0x30, 0xff7e1880,}, | |
259 | {"RTL-8168b/8111sb", 0x38, 0xff7e1880,}, | |
2287286b | 260 | {"RTL-8168d/8111d", 0x28, 0xff7e1880,}, |
65a6691e | 261 | {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,}, |
cc0856cd | 262 | {"RTL-8168/8111g", 0x4c, 0xff7e1880,}, |
d75469d4 NI |
263 | {"RTL-8101e", 0x34, 0xff7e1880,}, |
264 | {"RTL-8100e", 0x32, 0xff7e1880,}, | |
a8bd82de WD |
265 | }; |
266 | ||
267 | enum _DescStatusBit { | |
268 | OWNbit = 0x80000000, | |
269 | EORbit = 0x40000000, | |
270 | FSbit = 0x20000000, | |
271 | LSbit = 0x10000000, | |
272 | }; | |
273 | ||
274 | struct TxDesc { | |
275 | u32 status; | |
276 | u32 vlan_tag; | |
277 | u32 buf_addr; | |
278 | u32 buf_Haddr; | |
279 | }; | |
280 | ||
281 | struct RxDesc { | |
282 | u32 status; | |
283 | u32 vlan_tag; | |
284 | u32 buf_addr; | |
285 | u32 buf_Haddr; | |
286 | }; | |
287 | ||
d0a5a0b2 SG |
288 | static unsigned char rxdata[RX_BUF_LEN]; |
289 | ||
dad3ba0f | 290 | #define RTL8169_DESC_SIZE 16 |
a8bd82de | 291 | |
dad3ba0f TR |
292 | #if ARCH_DMA_MINALIGN > 256 |
293 | # define RTL8169_ALIGN ARCH_DMA_MINALIGN | |
294 | #else | |
295 | # define RTL8169_ALIGN 256 | |
296 | #endif | |
297 | ||
298 | /* | |
299 | * Warn if the cache-line size is larger than the descriptor size. In such | |
300 | * cases the driver will likely fail because the CPU needs to flush the cache | |
301 | * when requeuing RX buffers, therefore descriptors written by the hardware | |
302 | * may be discarded. | |
d58acdcb TR |
303 | * |
304 | * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause | |
305 | * the driver to allocate descriptors from a pool of non-cached memory. | |
dad3ba0f TR |
306 | */ |
307 | #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN | |
d0a5a0b2 SG |
308 | #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \ |
309 | !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86) | |
dad3ba0f TR |
310 | #warning cache-line size is larger than descriptor size |
311 | #endif | |
d58acdcb | 312 | #endif |
a8bd82de | 313 | |
dad3ba0f TR |
314 | /* |
315 | * Create a static buffer of size RX_BUF_SZ for each TX Descriptor. All | |
316 | * descriptors point to a part of this buffer. | |
317 | */ | |
318 | DEFINE_ALIGN_BUFFER(u8, txb, NUM_TX_DESC * RX_BUF_SIZE, RTL8169_ALIGN); | |
319 | ||
320 | /* | |
321 | * Create a static buffer of size RX_BUF_SZ for each RX Descriptor. All | |
322 | * descriptors point to a part of this buffer. | |
323 | */ | |
324 | DEFINE_ALIGN_BUFFER(u8, rxb, NUM_RX_DESC * RX_BUF_SIZE, RTL8169_ALIGN); | |
a8bd82de WD |
325 | |
326 | struct rtl8169_private { | |
d0a5a0b2 | 327 | ulong iobase; |
a8bd82de WD |
328 | void *mmio_addr; /* memory map physical address */ |
329 | int chipset; | |
330 | unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ | |
331 | unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ | |
332 | unsigned long dirty_tx; | |
a8bd82de WD |
333 | struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */ |
334 | struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */ | |
335 | unsigned char *RxBufferRings; /* Index of Rx Buffer */ | |
336 | unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */ | |
337 | unsigned char *Tx_skbuff[NUM_TX_DESC]; | |
338 | } tpx; | |
339 | ||
340 | static struct rtl8169_private *tpc; | |
341 | ||
342 | static const u16 rtl8169_intr_mask = | |
343 | SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr | | |
344 | TxOK | RxErr | RxOK; | |
345 | static const unsigned int rtl8169_rx_config = | |
346 | (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); | |
347 | ||
348 | static struct pci_device_id supported[] = { | |
d0a5a0b2 SG |
349 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167) }, |
350 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168) }, | |
351 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169) }, | |
a8bd82de WD |
352 | {} |
353 | }; | |
354 | ||
355 | void mdio_write(int RegAddr, int value) | |
356 | { | |
357 | int i; | |
358 | ||
359 | RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value); | |
360 | udelay(1000); | |
361 | ||
362 | for (i = 2000; i > 0; i--) { | |
363 | /* Check if the RTL8169 has completed writing to the specified MII register */ | |
364 | if (!(RTL_R32(PHYAR) & 0x80000000)) { | |
365 | break; | |
366 | } else { | |
367 | udelay(100); | |
368 | } | |
369 | } | |
370 | } | |
371 | ||
372 | int mdio_read(int RegAddr) | |
373 | { | |
374 | int i, value = -1; | |
375 | ||
376 | RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16); | |
377 | udelay(1000); | |
378 | ||
379 | for (i = 2000; i > 0; i--) { | |
380 | /* Check if the RTL8169 has completed retrieving data from the specified MII register */ | |
381 | if (RTL_R32(PHYAR) & 0x80000000) { | |
382 | value = (int) (RTL_R32(PHYAR) & 0xFFFF); | |
383 | break; | |
384 | } else { | |
385 | udelay(100); | |
386 | } | |
387 | } | |
388 | return value; | |
389 | } | |
390 | ||
d0a5a0b2 | 391 | static int rtl8169_init_board(unsigned long dev_iobase, const char *name) |
a8bd82de WD |
392 | { |
393 | int i; | |
394 | u32 tmp; | |
395 | ||
396 | #ifdef DEBUG_RTL8169 | |
397 | printf ("%s\n", __FUNCTION__); | |
398 | #endif | |
d0a5a0b2 | 399 | ioaddr = dev_iobase; |
a8bd82de WD |
400 | |
401 | /* Soft reset the chip. */ | |
402 | RTL_W8(ChipCmd, CmdReset); | |
403 | ||
404 | /* Check that the chip has finished the reset. */ | |
405 | for (i = 1000; i > 0; i--) | |
406 | if ((RTL_R8(ChipCmd) & CmdReset) == 0) | |
407 | break; | |
408 | else | |
409 | udelay(10); | |
410 | ||
411 | /* identify chip attached to board */ | |
412 | tmp = RTL_R32(TxConfig); | |
413 | tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24; | |
414 | ||
415 | for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){ | |
416 | if (tmp == rtl_chip_info[i].version) { | |
417 | tpc->chipset = i; | |
418 | goto match; | |
419 | } | |
420 | } | |
421 | ||
422 | /* if unknown chip, assume array element #0, original RTL-8169 in this case */ | |
d0a5a0b2 SG |
423 | printf("PCI device %s: unknown chip version, assuming RTL-8169\n", |
424 | name); | |
06c53bea | 425 | printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig)); |
a8bd82de WD |
426 | tpc->chipset = 0; |
427 | ||
428 | match: | |
429 | return 0; | |
430 | } | |
431 | ||
d58acdcb TR |
432 | /* |
433 | * TX and RX descriptors are 16 bytes. This causes problems with the cache | |
434 | * maintenance on CPUs where the cache-line size exceeds the size of these | |
435 | * descriptors. What will happen is that when the driver receives a packet | |
436 | * it will be immediately requeued for the hardware to reuse. The CPU will | |
437 | * therefore need to flush the cache-line containing the descriptor, which | |
438 | * will cause all other descriptors in the same cache-line to be flushed | |
439 | * along with it. If one of those descriptors had been written to by the | |
440 | * device those changes (and the associated packet) will be lost. | |
441 | * | |
442 | * To work around this, we make use of non-cached memory if available. If | |
443 | * descriptors are mapped uncached there's no need to manually flush them | |
444 | * or invalidate them. | |
445 | * | |
446 | * Note that this only applies to descriptors. The packet data buffers do | |
447 | * not have the same constraints since they are 1536 bytes large, so they | |
448 | * are unlikely to share cache-lines. | |
449 | */ | |
450 | static void *rtl_alloc_descs(unsigned int num) | |
451 | { | |
452 | size_t size = num * RTL8169_DESC_SIZE; | |
453 | ||
454 | #ifdef CONFIG_SYS_NONCACHED_MEMORY | |
455 | return (void *)noncached_alloc(size, RTL8169_ALIGN); | |
456 | #else | |
457 | return memalign(RTL8169_ALIGN, size); | |
458 | #endif | |
459 | } | |
460 | ||
22ece0e2 TR |
461 | /* |
462 | * Cache maintenance functions. These are simple wrappers around the more | |
463 | * general purpose flush_cache() and invalidate_dcache_range() functions. | |
464 | */ | |
465 | ||
466 | static void rtl_inval_rx_desc(struct RxDesc *desc) | |
467 | { | |
d58acdcb | 468 | #ifndef CONFIG_SYS_NONCACHED_MEMORY |
22ece0e2 TR |
469 | unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); |
470 | unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); | |
471 | ||
472 | invalidate_dcache_range(start, end); | |
d58acdcb | 473 | #endif |
22ece0e2 TR |
474 | } |
475 | ||
476 | static void rtl_flush_rx_desc(struct RxDesc *desc) | |
477 | { | |
d58acdcb | 478 | #ifndef CONFIG_SYS_NONCACHED_MEMORY |
22ece0e2 | 479 | flush_cache((unsigned long)desc, sizeof(*desc)); |
d58acdcb | 480 | #endif |
22ece0e2 TR |
481 | } |
482 | ||
483 | static void rtl_inval_tx_desc(struct TxDesc *desc) | |
484 | { | |
d58acdcb | 485 | #ifndef CONFIG_SYS_NONCACHED_MEMORY |
22ece0e2 TR |
486 | unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); |
487 | unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); | |
488 | ||
489 | invalidate_dcache_range(start, end); | |
d58acdcb | 490 | #endif |
22ece0e2 TR |
491 | } |
492 | ||
493 | static void rtl_flush_tx_desc(struct TxDesc *desc) | |
494 | { | |
d58acdcb | 495 | #ifndef CONFIG_SYS_NONCACHED_MEMORY |
22ece0e2 | 496 | flush_cache((unsigned long)desc, sizeof(*desc)); |
d58acdcb | 497 | #endif |
22ece0e2 TR |
498 | } |
499 | ||
500 | static void rtl_inval_buffer(void *buf, size_t size) | |
501 | { | |
502 | unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); | |
503 | unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN); | |
504 | ||
505 | invalidate_dcache_range(start, end); | |
506 | } | |
507 | ||
508 | static void rtl_flush_buffer(void *buf, size_t size) | |
509 | { | |
510 | flush_cache((unsigned long)buf, size); | |
511 | } | |
512 | ||
a8bd82de WD |
513 | /************************************************************************** |
514 | RECV - Receive a frame | |
515 | ***************************************************************************/ | |
d0a5a0b2 SG |
516 | static int rtl_recv_common(pci_dev_t bdf, unsigned long dev_iobase, |
517 | uchar **packetp) | |
a8bd82de WD |
518 | { |
519 | /* return true if there's an ethernet packet ready to read */ | |
520 | /* nic->packet should contain data on return */ | |
521 | /* nic->packetlen should contain length of data */ | |
522 | int cur_rx; | |
523 | int length = 0; | |
524 | ||
525 | #ifdef DEBUG_RTL8169_RX | |
526 | printf ("%s\n", __FUNCTION__); | |
527 | #endif | |
d0a5a0b2 | 528 | ioaddr = dev_iobase; |
a8bd82de WD |
529 | |
530 | cur_rx = tpc->cur_rx; | |
22ece0e2 TR |
531 | |
532 | rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]); | |
533 | ||
6a5e1d75 GL |
534 | if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) { |
535 | if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) { | |
6a5e1d75 GL |
536 | length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx]. |
537 | status) & 0x00001FFF) - 4; | |
a8bd82de | 538 | |
22ece0e2 | 539 | rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length); |
a8bd82de | 540 | memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); |
a8bd82de WD |
541 | |
542 | if (cur_rx == NUM_RX_DESC - 1) | |
543 | tpc->RxDescArray[cur_rx].status = | |
6a5e1d75 | 544 | cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); |
a8bd82de WD |
545 | else |
546 | tpc->RxDescArray[cur_rx].status = | |
6a5e1d75 | 547 | cpu_to_le32(OWNbit + RX_BUF_SIZE); |
d0a5a0b2 SG |
548 | tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32( |
549 | pci_mem_to_phys(bdf, (pci_addr_t)(unsigned long) | |
550 | tpc->RxBufferRing[cur_rx])); | |
22ece0e2 | 551 | rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]); |
d0a5a0b2 SG |
552 | #ifdef CONFIG_DM_ETH |
553 | *packetp = rxdata; | |
554 | #else | |
1fd92db8 | 555 | net_process_received_packet(rxdata, length); |
d0a5a0b2 | 556 | #endif |
a8bd82de WD |
557 | } else { |
558 | puts("Error Rx"); | |
d0a5a0b2 | 559 | length = -EIO; |
a8bd82de WD |
560 | } |
561 | cur_rx = (cur_rx + 1) % NUM_RX_DESC; | |
562 | tpc->cur_rx = cur_rx; | |
d0a5a0b2 | 563 | return length; |
a8bd82de | 564 | |
d75469d4 NI |
565 | } else { |
566 | ushort sts = RTL_R8(IntrStatus); | |
567 | RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr)); | |
568 | udelay(100); /* wait */ | |
a8bd82de WD |
569 | } |
570 | tpc->cur_rx = cur_rx; | |
571 | return (0); /* initially as this is called to flush the input */ | |
572 | } | |
573 | ||
d0a5a0b2 SG |
574 | #ifdef CONFIG_DM_ETH |
575 | int rtl8169_eth_recv(struct udevice *dev, int flags, uchar **packetp) | |
576 | { | |
577 | struct rtl8169_private *priv = dev_get_priv(dev); | |
578 | ||
579 | return rtl_recv_common(pci_get_bdf(dev), priv->iobase, packetp); | |
580 | } | |
581 | #else | |
582 | static int rtl_recv(struct eth_device *dev) | |
583 | { | |
f3ba5523 SW |
584 | return rtl_recv_common((pci_dev_t)(unsigned long)dev->priv, |
585 | dev->iobase, NULL); | |
d0a5a0b2 SG |
586 | } |
587 | #endif /* nCONFIG_DM_ETH */ | |
588 | ||
a8bd82de WD |
589 | #define HZ 1000 |
590 | /************************************************************************** | |
591 | SEND - Transmit a frame | |
592 | ***************************************************************************/ | |
d0a5a0b2 SG |
593 | static int rtl_send_common(pci_dev_t bdf, unsigned long dev_iobase, |
594 | void *packet, int length) | |
a8bd82de WD |
595 | { |
596 | /* send the packet to destination */ | |
597 | ||
598 | u32 to; | |
599 | u8 *ptxb; | |
600 | int entry = tpc->cur_tx % NUM_TX_DESC; | |
601 | u32 len = length; | |
6a5e1d75 | 602 | int ret; |
a8bd82de WD |
603 | |
604 | #ifdef DEBUG_RTL8169_TX | |
605 | int stime = currticks(); | |
606 | printf ("%s\n", __FUNCTION__); | |
607 | printf("sending %d bytes\n", len); | |
608 | #endif | |
609 | ||
d0a5a0b2 | 610 | ioaddr = dev_iobase; |
a8bd82de WD |
611 | |
612 | /* point to the current txb incase multiple tx_rings are used */ | |
613 | ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; | |
614 | memcpy(ptxb, (char *)packet, (int)length); | |
22ece0e2 | 615 | rtl_flush_buffer(ptxb, length); |
a8bd82de WD |
616 | |
617 | while (len < ETH_ZLEN) | |
618 | ptxb[len++] = '\0'; | |
619 | ||
db70b843 | 620 | tpc->TxDescArray[entry].buf_Haddr = 0; |
d0a5a0b2 SG |
621 | tpc->TxDescArray[entry].buf_addr = cpu_to_le32( |
622 | pci_mem_to_phys(bdf, (pci_addr_t)(unsigned long)ptxb)); | |
a8bd82de WD |
623 | if (entry != (NUM_TX_DESC - 1)) { |
624 | tpc->TxDescArray[entry].status = | |
6a5e1d75 GL |
625 | cpu_to_le32((OWNbit | FSbit | LSbit) | |
626 | ((len > ETH_ZLEN) ? len : ETH_ZLEN)); | |
a8bd82de WD |
627 | } else { |
628 | tpc->TxDescArray[entry].status = | |
6a5e1d75 GL |
629 | cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) | |
630 | ((len > ETH_ZLEN) ? len : ETH_ZLEN)); | |
a8bd82de | 631 | } |
22ece0e2 | 632 | rtl_flush_tx_desc(&tpc->TxDescArray[entry]); |
a8bd82de WD |
633 | RTL_W8(TxPoll, 0x40); /* set polling bit */ |
634 | ||
635 | tpc->cur_tx++; | |
636 | to = currticks() + TX_TIMEOUT; | |
d4c02e6f | 637 | do { |
22ece0e2 | 638 | rtl_inval_tx_desc(&tpc->TxDescArray[entry]); |
d4c02e6f | 639 | } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit) |
6a5e1d75 | 640 | && (currticks() < to)); /* wait */ |
a8bd82de WD |
641 | |
642 | if (currticks() >= to) { | |
643 | #ifdef DEBUG_RTL8169_TX | |
7a36b9c1 TR |
644 | puts("tx timeout/error\n"); |
645 | printf("%s elapsed time : %lu\n", __func__, currticks()-stime); | |
a8bd82de | 646 | #endif |
6a5e1d75 | 647 | ret = 0; |
a8bd82de WD |
648 | } else { |
649 | #ifdef DEBUG_RTL8169_TX | |
650 | puts("tx done\n"); | |
651 | #endif | |
6a5e1d75 | 652 | ret = length; |
a8bd82de | 653 | } |
6a5e1d75 GL |
654 | /* Delay to make net console (nc) work properly */ |
655 | udelay(20); | |
656 | return ret; | |
a8bd82de WD |
657 | } |
658 | ||
d0a5a0b2 SG |
659 | #ifdef CONFIG_DM_ETH |
660 | int rtl8169_eth_send(struct udevice *dev, void *packet, int length) | |
661 | { | |
662 | struct rtl8169_private *priv = dev_get_priv(dev); | |
663 | ||
664 | return rtl_send_common(pci_get_bdf(dev), priv->iobase, packet, length); | |
665 | } | |
666 | ||
667 | #else | |
668 | static int rtl_send(struct eth_device *dev, void *packet, int length) | |
669 | { | |
f3ba5523 SW |
670 | return rtl_send_common((pci_dev_t)(unsigned long)dev->priv, |
671 | dev->iobase, packet, length); | |
d0a5a0b2 SG |
672 | } |
673 | #endif | |
674 | ||
675 | static void rtl8169_set_rx_mode(void) | |
a8bd82de WD |
676 | { |
677 | u32 mc_filter[2]; /* Multicast hash filter */ | |
678 | int rx_mode; | |
679 | u32 tmp = 0; | |
680 | ||
681 | #ifdef DEBUG_RTL8169 | |
682 | printf ("%s\n", __FUNCTION__); | |
683 | #endif | |
684 | ||
685 | /* IFF_ALLMULTI */ | |
686 | /* Too many to filter perfectly -- accept all multicasts. */ | |
687 | rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; | |
688 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
689 | ||
690 | tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) & | |
691 | rtl_chip_info[tpc->chipset].RxConfigMask); | |
692 | ||
693 | RTL_W32(RxConfig, tmp); | |
694 | RTL_W32(MAR0 + 0, mc_filter[0]); | |
695 | RTL_W32(MAR0 + 4, mc_filter[1]); | |
696 | } | |
697 | ||
d0a5a0b2 | 698 | static void rtl8169_hw_start(pci_dev_t bdf) |
a8bd82de WD |
699 | { |
700 | u32 i; | |
701 | ||
702 | #ifdef DEBUG_RTL8169 | |
703 | int stime = currticks(); | |
704 | printf ("%s\n", __FUNCTION__); | |
705 | #endif | |
706 | ||
707 | #if 0 | |
708 | /* Soft reset the chip. */ | |
709 | RTL_W8(ChipCmd, CmdReset); | |
710 | ||
711 | /* Check that the chip has finished the reset. */ | |
712 | for (i = 1000; i > 0; i--) { | |
713 | if ((RTL_R8(ChipCmd) & CmdReset) == 0) | |
714 | break; | |
715 | else | |
716 | udelay(10); | |
717 | } | |
718 | #endif | |
719 | ||
720 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
db70b843 YS |
721 | |
722 | /* RTL-8169sb/8110sb or previous version */ | |
723 | if (tpc->chipset <= 5) | |
724 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); | |
725 | ||
a8bd82de WD |
726 | RTL_W8(EarlyTxThres, EarlyTxThld); |
727 | ||
728 | /* For gigabit rtl8169 */ | |
729 | RTL_W16(RxMaxSize, RxPacketMaxSize); | |
730 | ||
731 | /* Set Rx Config register */ | |
732 | i = rtl8169_rx_config | (RTL_R32(RxConfig) & | |
733 | rtl_chip_info[tpc->chipset].RxConfigMask); | |
734 | RTL_W32(RxConfig, i); | |
735 | ||
736 | /* Set DMA burst size and Interframe Gap Time */ | |
737 | RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | | |
738 | (InterFrameGap << TxInterFrameGapShift)); | |
739 | ||
740 | ||
741 | tpc->cur_rx = 0; | |
742 | ||
d0a5a0b2 SG |
743 | RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(bdf, |
744 | (pci_addr_t)(unsigned long)tpc->TxDescArray)); | |
db70b843 | 745 | RTL_W32(TxDescStartAddrHigh, (unsigned long)0); |
d0a5a0b2 SG |
746 | RTL_W32(RxDescStartAddrLow, pci_mem_to_phys( |
747 | bdf, (pci_addr_t)(unsigned long)tpc->RxDescArray)); | |
db70b843 YS |
748 | RTL_W32(RxDescStartAddrHigh, (unsigned long)0); |
749 | ||
750 | /* RTL-8169sc/8110sc or later version */ | |
751 | if (tpc->chipset > 5) | |
752 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); | |
753 | ||
a8bd82de WD |
754 | RTL_W8(Cfg9346, Cfg9346_Lock); |
755 | udelay(10); | |
756 | ||
757 | RTL_W32(RxMissed, 0); | |
758 | ||
d0a5a0b2 | 759 | rtl8169_set_rx_mode(); |
a8bd82de WD |
760 | |
761 | /* no early-rx interrupts */ | |
762 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); | |
763 | ||
764 | #ifdef DEBUG_RTL8169 | |
7a36b9c1 | 765 | printf("%s elapsed time : %lu\n", __func__, currticks()-stime); |
a8bd82de WD |
766 | #endif |
767 | } | |
768 | ||
d0a5a0b2 | 769 | static void rtl8169_init_ring(pci_dev_t bdf) |
a8bd82de WD |
770 | { |
771 | int i; | |
772 | ||
773 | #ifdef DEBUG_RTL8169 | |
774 | int stime = currticks(); | |
775 | printf ("%s\n", __FUNCTION__); | |
776 | #endif | |
777 | ||
778 | tpc->cur_rx = 0; | |
779 | tpc->cur_tx = 0; | |
780 | tpc->dirty_tx = 0; | |
781 | memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc)); | |
782 | memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc)); | |
783 | ||
784 | for (i = 0; i < NUM_TX_DESC; i++) { | |
785 | tpc->Tx_skbuff[i] = &txb[i]; | |
786 | } | |
787 | ||
788 | for (i = 0; i < NUM_RX_DESC; i++) { | |
789 | if (i == (NUM_RX_DESC - 1)) | |
790 | tpc->RxDescArray[i].status = | |
6a5e1d75 | 791 | cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); |
a8bd82de | 792 | else |
6a5e1d75 GL |
793 | tpc->RxDescArray[i].status = |
794 | cpu_to_le32(OWNbit + RX_BUF_SIZE); | |
a8bd82de WD |
795 | |
796 | tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; | |
d0a5a0b2 SG |
797 | tpc->RxDescArray[i].buf_addr = cpu_to_le32(pci_mem_to_phys( |
798 | bdf, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i])); | |
22ece0e2 | 799 | rtl_flush_rx_desc(&tpc->RxDescArray[i]); |
a8bd82de WD |
800 | } |
801 | ||
802 | #ifdef DEBUG_RTL8169 | |
7a36b9c1 | 803 | printf("%s elapsed time : %lu\n", __func__, currticks()-stime); |
a8bd82de WD |
804 | #endif |
805 | } | |
806 | ||
d0a5a0b2 | 807 | static void rtl8169_common_start(pci_dev_t bdf, unsigned char *enetaddr) |
a8bd82de WD |
808 | { |
809 | int i; | |
a8bd82de WD |
810 | |
811 | #ifdef DEBUG_RTL8169 | |
812 | int stime = currticks(); | |
813 | printf ("%s\n", __FUNCTION__); | |
814 | #endif | |
815 | ||
d0a5a0b2 SG |
816 | rtl8169_init_ring(bdf); |
817 | rtl8169_hw_start(bdf); | |
a8bd82de WD |
818 | /* Construct a perfect filter frame with the mac address as first match |
819 | * and broadcast for all others */ | |
820 | for (i = 0; i < 192; i++) | |
821 | txb[i] = 0xFF; | |
822 | ||
d0a5a0b2 SG |
823 | txb[0] = enetaddr[0]; |
824 | txb[1] = enetaddr[1]; | |
825 | txb[2] = enetaddr[2]; | |
826 | txb[3] = enetaddr[3]; | |
827 | txb[4] = enetaddr[4]; | |
828 | txb[5] = enetaddr[5]; | |
a8bd82de WD |
829 | |
830 | #ifdef DEBUG_RTL8169 | |
7a36b9c1 | 831 | printf("%s elapsed time : %lu\n", __func__, currticks()-stime); |
a8bd82de WD |
832 | #endif |
833 | } | |
834 | ||
d0a5a0b2 SG |
835 | #ifdef CONFIG_DM_ETH |
836 | static int rtl8169_eth_start(struct udevice *dev) | |
837 | { | |
838 | struct eth_pdata *plat = dev_get_platdata(dev); | |
839 | ||
840 | rtl8169_common_start(pci_get_bdf(dev), plat->enetaddr); | |
841 | ||
842 | return 0; | |
843 | } | |
844 | #else | |
a8bd82de | 845 | /************************************************************************** |
d0a5a0b2 | 846 | RESET - Finish setting up the ethernet interface |
a8bd82de | 847 | ***************************************************************************/ |
d0a5a0b2 SG |
848 | static int rtl_reset(struct eth_device *dev, bd_t *bis) |
849 | { | |
f3ba5523 SW |
850 | rtl8169_common_start((pci_dev_t)(unsigned long)dev->priv, |
851 | dev->enetaddr); | |
d0a5a0b2 SG |
852 | |
853 | return 0; | |
854 | } | |
855 | #endif /* nCONFIG_DM_ETH */ | |
856 | ||
857 | static void rtl_halt_common(unsigned long dev_iobase) | |
a8bd82de WD |
858 | { |
859 | int i; | |
860 | ||
861 | #ifdef DEBUG_RTL8169 | |
862 | printf ("%s\n", __FUNCTION__); | |
863 | #endif | |
864 | ||
d0a5a0b2 | 865 | ioaddr = dev_iobase; |
a8bd82de WD |
866 | |
867 | /* Stop the chip's Tx and Rx DMA processes. */ | |
868 | RTL_W8(ChipCmd, 0x00); | |
869 | ||
870 | /* Disable interrupts by clearing the interrupt mask. */ | |
871 | RTL_W16(IntrMask, 0x0000); | |
872 | ||
873 | RTL_W32(RxMissed, 0); | |
874 | ||
a8bd82de WD |
875 | for (i = 0; i < NUM_RX_DESC; i++) { |
876 | tpc->RxBufferRing[i] = NULL; | |
877 | } | |
878 | } | |
879 | ||
d0a5a0b2 SG |
880 | #ifdef CONFIG_DM_ETH |
881 | void rtl8169_eth_stop(struct udevice *dev) | |
882 | { | |
883 | struct rtl8169_private *priv = dev_get_priv(dev); | |
884 | ||
885 | rtl_halt_common(priv->iobase); | |
886 | } | |
887 | #else | |
888 | /************************************************************************** | |
889 | HALT - Turn off ethernet interface | |
890 | ***************************************************************************/ | |
891 | static void rtl_halt(struct eth_device *dev) | |
892 | { | |
893 | rtl_halt_common(dev->iobase); | |
894 | } | |
895 | #endif | |
896 | ||
a8bd82de WD |
897 | /************************************************************************** |
898 | INIT - Look for an adapter, this routine's visible to the outside | |
899 | ***************************************************************************/ | |
900 | ||
901 | #define board_found 1 | |
902 | #define valid_link 0 | |
d0a5a0b2 SG |
903 | static int rtl_init(unsigned long dev_ioaddr, const char *name, |
904 | unsigned char *enetaddr) | |
a8bd82de WD |
905 | { |
906 | static int board_idx = -1; | |
a8bd82de WD |
907 | int i, rc; |
908 | int option = -1, Cap10_100 = 0, Cap1000 = 0; | |
909 | ||
910 | #ifdef DEBUG_RTL8169 | |
911 | printf ("%s\n", __FUNCTION__); | |
912 | #endif | |
d0a5a0b2 | 913 | ioaddr = dev_ioaddr; |
a8bd82de WD |
914 | |
915 | board_idx++; | |
916 | ||
a8bd82de WD |
917 | /* point to private storage */ |
918 | tpc = &tpx; | |
919 | ||
d0a5a0b2 | 920 | rc = rtl8169_init_board(ioaddr, name); |
a8bd82de WD |
921 | if (rc) |
922 | return rc; | |
923 | ||
924 | /* Get MAC address. FIXME: read EEPROM */ | |
925 | for (i = 0; i < MAC_ADDR_LEN; i++) | |
d0a5a0b2 | 926 | enetaddr[i] = RTL_R8(MAC0 + i); |
a8bd82de WD |
927 | |
928 | #ifdef DEBUG_RTL8169 | |
db70b843 | 929 | printf("chipset = %d\n", tpc->chipset); |
a8bd82de WD |
930 | printf("MAC Address"); |
931 | for (i = 0; i < MAC_ADDR_LEN; i++) | |
d0a5a0b2 | 932 | printf(":%02x", enetaddr[i]); |
a8bd82de WD |
933 | putc('\n'); |
934 | #endif | |
935 | ||
936 | #ifdef DEBUG_RTL8169 | |
937 | /* Print out some hardware info */ | |
d0a5a0b2 | 938 | printf("%s: at ioaddr 0x%lx\n", name, ioaddr); |
a8bd82de WD |
939 | #endif |
940 | ||
941 | /* if TBI is not endbled */ | |
942 | if (!(RTL_R8(PHYstatus) & TBI_Enable)) { | |
943 | int val = mdio_read(PHY_AUTO_NEGO_REG); | |
944 | ||
945 | option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; | |
946 | /* Force RTL8169 in 10/100/1000 Full/Half mode. */ | |
947 | if (option > 0) { | |
948 | #ifdef DEBUG_RTL8169 | |
949 | printf("%s: Force-mode Enabled.\n", dev->name); | |
950 | #endif | |
951 | Cap10_100 = 0, Cap1000 = 0; | |
952 | switch (option) { | |
953 | case _10_Half: | |
954 | Cap10_100 = PHY_Cap_10_Half; | |
955 | Cap1000 = PHY_Cap_Null; | |
956 | break; | |
957 | case _10_Full: | |
958 | Cap10_100 = PHY_Cap_10_Full; | |
959 | Cap1000 = PHY_Cap_Null; | |
960 | break; | |
961 | case _100_Half: | |
962 | Cap10_100 = PHY_Cap_100_Half; | |
963 | Cap1000 = PHY_Cap_Null; | |
964 | break; | |
965 | case _100_Full: | |
966 | Cap10_100 = PHY_Cap_100_Full; | |
967 | Cap1000 = PHY_Cap_Null; | |
968 | break; | |
969 | case _1000_Full: | |
970 | Cap10_100 = PHY_Cap_Null; | |
971 | Cap1000 = PHY_Cap_1000_Full; | |
972 | break; | |
973 | default: | |
974 | break; | |
975 | } | |
976 | mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ | |
977 | mdio_write(PHY_1000_CTRL_REG, Cap1000); | |
978 | } else { | |
979 | #ifdef DEBUG_RTL8169 | |
980 | printf("%s: Auto-negotiation Enabled.\n", | |
981 | dev->name); | |
982 | #endif | |
983 | /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ | |
984 | mdio_write(PHY_AUTO_NEGO_REG, | |
985 | PHY_Cap_10_Half | PHY_Cap_10_Full | | |
986 | PHY_Cap_100_Half | PHY_Cap_100_Full | | |
987 | (val & 0x1F)); | |
988 | ||
989 | /* enable 1000 Full Mode */ | |
990 | mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full); | |
991 | ||
992 | } | |
993 | ||
994 | /* Enable auto-negotiation and restart auto-nigotiation */ | |
995 | mdio_write(PHY_CTRL_REG, | |
996 | PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego); | |
997 | udelay(100); | |
998 | ||
999 | /* wait for auto-negotiation process */ | |
1000 | for (i = 10000; i > 0; i--) { | |
1001 | /* check if auto-negotiation complete */ | |
6a5e1d75 | 1002 | if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) { |
a8bd82de WD |
1003 | udelay(100); |
1004 | option = RTL_R8(PHYstatus); | |
1005 | if (option & _1000bpsF) { | |
1006 | #ifdef DEBUG_RTL8169 | |
1007 | printf("%s: 1000Mbps Full-duplex operation.\n", | |
1008 | dev->name); | |
1009 | #endif | |
1010 | } else { | |
1011 | #ifdef DEBUG_RTL8169 | |
6a5e1d75 GL |
1012 | printf("%s: %sMbps %s-duplex operation.\n", |
1013 | dev->name, | |
1014 | (option & _100bps) ? "100" : | |
1015 | "10", | |
1016 | (option & FullDup) ? "Full" : | |
1017 | "Half"); | |
a8bd82de WD |
1018 | #endif |
1019 | } | |
1020 | break; | |
1021 | } else { | |
1022 | udelay(100); | |
1023 | } | |
1024 | } /* end for-loop to wait for auto-negotiation process */ | |
1025 | ||
1026 | } else { | |
1027 | udelay(100); | |
1028 | #ifdef DEBUG_RTL8169 | |
1029 | printf | |
1030 | ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n", | |
1031 | dev->name, | |
1032 | (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed"); | |
1033 | #endif | |
1034 | } | |
1035 | ||
dad3ba0f | 1036 | |
d58acdcb TR |
1037 | tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC); |
1038 | if (!tpc->RxDescArray) | |
1039 | return -ENOMEM; | |
1040 | ||
1041 | tpc->TxDescArray = rtl_alloc_descs(NUM_TX_DESC); | |
1042 | if (!tpc->TxDescArray) | |
1043 | return -ENOMEM; | |
1044 | ||
1045 | return 0; | |
a8bd82de WD |
1046 | } |
1047 | ||
d0a5a0b2 | 1048 | #ifndef CONFIG_DM_ETH |
a8bd82de WD |
1049 | int rtl8169_initialize(bd_t *bis) |
1050 | { | |
1051 | pci_dev_t devno; | |
1052 | int card_number = 0; | |
1053 | struct eth_device *dev; | |
1054 | u32 iobase; | |
1055 | int idx=0; | |
1056 | ||
1057 | while(1){ | |
2287286b TR |
1058 | unsigned int region; |
1059 | u16 device; | |
d58acdcb | 1060 | int err; |
2287286b | 1061 | |
a8bd82de WD |
1062 | /* Find RTL8169 */ |
1063 | if ((devno = pci_find_devices(supported, idx++)) < 0) | |
1064 | break; | |
1065 | ||
2287286b TR |
1066 | pci_read_config_word(devno, PCI_DEVICE_ID, &device); |
1067 | switch (device) { | |
1068 | case 0x8168: | |
1069 | region = 2; | |
1070 | break; | |
1071 | ||
1072 | default: | |
1073 | region = 1; | |
1074 | break; | |
1075 | } | |
1076 | ||
1077 | pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase); | |
a8bd82de WD |
1078 | iobase &= ~0xf; |
1079 | ||
1080 | debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); | |
1081 | ||
1082 | dev = (struct eth_device *)malloc(sizeof *dev); | |
f4eaef7b NI |
1083 | if (!dev) { |
1084 | printf("Can not allocate memory of rtl8169\n"); | |
1085 | break; | |
1086 | } | |
a8bd82de | 1087 | |
f4eaef7b | 1088 | memset(dev, 0, sizeof(*dev)); |
a8bd82de WD |
1089 | sprintf (dev->name, "RTL8169#%d", card_number); |
1090 | ||
744152f8 | 1091 | dev->priv = (void *)(unsigned long)devno; |
6a5e1d75 | 1092 | dev->iobase = (int)pci_mem_to_phys(devno, iobase); |
a8bd82de WD |
1093 | |
1094 | dev->init = rtl_reset; | |
1095 | dev->halt = rtl_halt; | |
1096 | dev->send = rtl_send; | |
1097 | dev->recv = rtl_recv; | |
1098 | ||
d0a5a0b2 | 1099 | err = rtl_init(dev->iobase, dev->name, dev->enetaddr); |
d58acdcb TR |
1100 | if (err < 0) { |
1101 | printf(pr_fmt("failed to initialize card: %d\n"), err); | |
1102 | free(dev); | |
1103 | continue; | |
1104 | } | |
a8bd82de | 1105 | |
d58acdcb | 1106 | eth_register (dev); |
a8bd82de WD |
1107 | |
1108 | card_number++; | |
1109 | } | |
1110 | return card_number; | |
1111 | } | |
d0a5a0b2 SG |
1112 | #endif |
1113 | ||
1114 | #ifdef CONFIG_DM_ETH | |
1115 | static int rtl8169_eth_probe(struct udevice *dev) | |
1116 | { | |
1117 | struct pci_child_platdata *pplat = dev_get_parent_platdata(dev); | |
1118 | struct rtl8169_private *priv = dev_get_priv(dev); | |
1119 | struct eth_pdata *plat = dev_get_platdata(dev); | |
1120 | u32 iobase; | |
1121 | int region; | |
1122 | int ret; | |
1123 | ||
1124 | debug("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); | |
1125 | switch (pplat->device) { | |
1126 | case 0x8168: | |
1127 | region = 2; | |
1128 | break; | |
1129 | default: | |
1130 | region = 1; | |
1131 | break; | |
1132 | } | |
1133 | pci_read_config32(pci_get_bdf(dev), PCI_BASE_ADDRESS_0 + region * 4, | |
1134 | &iobase); | |
1135 | iobase &= ~0xf; | |
1136 | priv->iobase = (int)pci_mem_to_phys(pci_get_bdf(dev), iobase); | |
1137 | ||
1138 | ret = rtl_init(priv->iobase, dev->name, plat->enetaddr); | |
1139 | if (ret < 0) { | |
1140 | printf(pr_fmt("failed to initialize card: %d\n"), ret); | |
1141 | return ret; | |
1142 | } | |
1143 | ||
1144 | return 0; | |
1145 | } | |
1146 | ||
1147 | static const struct eth_ops rtl8169_eth_ops = { | |
1148 | .start = rtl8169_eth_start, | |
1149 | .send = rtl8169_eth_send, | |
1150 | .recv = rtl8169_eth_recv, | |
1151 | .stop = rtl8169_eth_stop, | |
1152 | }; | |
1153 | ||
1154 | static const struct udevice_id rtl8169_eth_ids[] = { | |
1155 | { .compatible = "realtek,rtl8169" }, | |
1156 | { } | |
1157 | }; | |
1158 | ||
1159 | U_BOOT_DRIVER(eth_rtl8169) = { | |
1160 | .name = "eth_rtl8169", | |
1161 | .id = UCLASS_ETH, | |
1162 | .of_match = rtl8169_eth_ids, | |
1163 | .probe = rtl8169_eth_probe, | |
1164 | .ops = &rtl8169_eth_ops, | |
1165 | .priv_auto_alloc_size = sizeof(struct rtl8169_private), | |
1166 | .platdata_auto_alloc_size = sizeof(struct eth_pdata), | |
1167 | }; | |
1168 | ||
1169 | U_BOOT_PCI_DEVICE(eth_rtl8169, supported); | |
1170 | #endif |