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Commit | Line | Data |
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a8bd82de WD |
1 | /* |
2 | * rtl8169.c : U-Boot driver for the RealTek RTL8169 | |
3 | * | |
4 | * Masami Komiya (mkomiya@sonare.it) | |
5 | * | |
6 | * Most part is taken from r8169.c of etherboot | |
7 | * | |
8 | */ | |
9 | ||
10 | /************************************************************************** | |
11 | * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit | |
12 | * Written 2003 by Timothy Legge <tlegge@rogers.com> | |
13 | * | |
1a459660 | 14 | * SPDX-License-Identifier: GPL-2.0+ |
a8bd82de WD |
15 | * |
16 | * Portions of this code based on: | |
17 | * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver | |
18 | * for Linux kernel 2.4.x. | |
19 | * | |
20 | * Written 2002 ShuChen <shuchen@realtek.com.tw> | |
21 | * See Linux Driver for full information | |
22 | * | |
23 | * Linux Driver Version 1.27a, 10.02.2002 | |
24 | * | |
25 | * Thanks to: | |
26 | * Jean Chen of RealTek Semiconductor Corp. for | |
27 | * providing the evaluation NIC used to develop | |
28 | * this driver. RealTek's support for Etherboot | |
29 | * is appreciated. | |
30 | * | |
31 | * REVISION HISTORY: | |
32 | * ================ | |
33 | * | |
34 | * v1.0 11-26-2003 timlegge Initial port of Linux driver | |
35 | * v1.5 01-17-2004 timlegge Initial driver output cleanup | |
36 | * | |
37 | * Indent Options: indent -kr -i8 | |
38 | ***************************************************************************/ | |
6a5e1d75 GL |
39 | /* |
40 | * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk> | |
41 | * Modified to use le32_to_cpu and cpu_to_le32 properly | |
42 | */ | |
a8bd82de | 43 | #include <common.h> |
d0a5a0b2 | 44 | #include <dm.h> |
d58acdcb | 45 | #include <errno.h> |
a8bd82de | 46 | #include <malloc.h> |
cf92e05c | 47 | #include <memalign.h> |
a8bd82de | 48 | #include <net.h> |
d0a5a0b2 | 49 | #ifndef CONFIG_DM_ETH |
02d69891 | 50 | #include <netdev.h> |
d0a5a0b2 | 51 | #endif |
a8bd82de WD |
52 | #include <asm/io.h> |
53 | #include <pci.h> | |
54 | ||
a8bd82de WD |
55 | #undef DEBUG_RTL8169 |
56 | #undef DEBUG_RTL8169_TX | |
57 | #undef DEBUG_RTL8169_RX | |
58 | ||
59 | #define drv_version "v1.5" | |
60 | #define drv_date "01-17-2004" | |
61 | ||
744152f8 | 62 | static unsigned long ioaddr; |
a8bd82de WD |
63 | |
64 | /* Condensed operations for readability. */ | |
a8bd82de | 65 | #define currticks() get_timer(0) |
a8bd82de WD |
66 | |
67 | /* media options */ | |
68 | #define MAX_UNITS 8 | |
69 | static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; | |
70 | ||
71 | /* MAC address length*/ | |
72 | #define MAC_ADDR_LEN 6 | |
73 | ||
74 | /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/ | |
75 | #define MAX_ETH_FRAME_SIZE 1536 | |
76 | ||
77 | #define TX_FIFO_THRESH 256 /* In bytes */ | |
78 | ||
79 | #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ | |
80 | #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ | |
81 | #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ | |
82 | #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ | |
83 | #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */ | |
84 | #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ | |
85 | ||
86 | #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */ | |
c94bbfdf TR |
87 | #ifdef CONFIG_SYS_RX_ETH_BUFFER |
88 | #define NUM_RX_DESC CONFIG_SYS_RX_ETH_BUFFER | |
89 | #else | |
90 | #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */ | |
91 | #endif | |
a8bd82de WD |
92 | #define RX_BUF_SIZE 1536 /* Rx Buffer size */ |
93 | #define RX_BUF_LEN 8192 | |
94 | ||
95 | #define RTL_MIN_IO_SIZE 0x80 | |
96 | #define TX_TIMEOUT (6*HZ) | |
97 | ||
6a5e1d75 | 98 | /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */ |
744152f8 TR |
99 | #define RTL_W8(reg, val8) writeb((val8), ioaddr + (reg)) |
100 | #define RTL_W16(reg, val16) writew((val16), ioaddr + (reg)) | |
101 | #define RTL_W32(reg, val32) writel((val32), ioaddr + (reg)) | |
102 | #define RTL_R8(reg) readb(ioaddr + (reg)) | |
103 | #define RTL_R16(reg) readw(ioaddr + (reg)) | |
104 | #define RTL_R32(reg) readl(ioaddr + (reg)) | |
a8bd82de WD |
105 | |
106 | #define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE | |
107 | #define ETH_ALEN MAC_ADDR_LEN | |
108 | #define ETH_ZLEN 60 | |
109 | ||
744152f8 TR |
110 | #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)(unsigned long)dev->priv, \ |
111 | (pci_addr_t)(unsigned long)a) | |
112 | #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)(unsigned long)dev->priv, \ | |
113 | (phys_addr_t)a) | |
d65e34d1 | 114 | |
a8bd82de WD |
115 | enum RTL8169_registers { |
116 | MAC0 = 0, /* Ethernet hardware address. */ | |
117 | MAR0 = 8, /* Multicast filter. */ | |
db70b843 YS |
118 | TxDescStartAddrLow = 0x20, |
119 | TxDescStartAddrHigh = 0x24, | |
120 | TxHDescStartAddrLow = 0x28, | |
121 | TxHDescStartAddrHigh = 0x2c, | |
a8bd82de WD |
122 | FLASH = 0x30, |
123 | ERSR = 0x36, | |
124 | ChipCmd = 0x37, | |
125 | TxPoll = 0x38, | |
126 | IntrMask = 0x3C, | |
127 | IntrStatus = 0x3E, | |
128 | TxConfig = 0x40, | |
129 | RxConfig = 0x44, | |
130 | RxMissed = 0x4C, | |
131 | Cfg9346 = 0x50, | |
132 | Config0 = 0x51, | |
133 | Config1 = 0x52, | |
134 | Config2 = 0x53, | |
135 | Config3 = 0x54, | |
136 | Config4 = 0x55, | |
137 | Config5 = 0x56, | |
138 | MultiIntr = 0x5C, | |
139 | PHYAR = 0x60, | |
140 | TBICSR = 0x64, | |
141 | TBI_ANAR = 0x68, | |
142 | TBI_LPAR = 0x6A, | |
143 | PHYstatus = 0x6C, | |
144 | RxMaxSize = 0xDA, | |
145 | CPlusCmd = 0xE0, | |
db70b843 YS |
146 | RxDescStartAddrLow = 0xE4, |
147 | RxDescStartAddrHigh = 0xE8, | |
a8bd82de WD |
148 | EarlyTxThres = 0xEC, |
149 | FuncEvent = 0xF0, | |
150 | FuncEventMask = 0xF4, | |
151 | FuncPresetState = 0xF8, | |
152 | FuncForceEvent = 0xFC, | |
153 | }; | |
154 | ||
155 | enum RTL8169_register_content { | |
156 | /*InterruptStatusBits */ | |
157 | SYSErr = 0x8000, | |
158 | PCSTimeout = 0x4000, | |
159 | SWInt = 0x0100, | |
160 | TxDescUnavail = 0x80, | |
161 | RxFIFOOver = 0x40, | |
162 | RxUnderrun = 0x20, | |
163 | RxOverflow = 0x10, | |
164 | TxErr = 0x08, | |
165 | TxOK = 0x04, | |
166 | RxErr = 0x02, | |
167 | RxOK = 0x01, | |
168 | ||
169 | /*RxStatusDesc */ | |
170 | RxRES = 0x00200000, | |
171 | RxCRC = 0x00080000, | |
172 | RxRUNT = 0x00100000, | |
173 | RxRWT = 0x00400000, | |
174 | ||
175 | /*ChipCmdBits */ | |
176 | CmdReset = 0x10, | |
177 | CmdRxEnb = 0x08, | |
178 | CmdTxEnb = 0x04, | |
179 | RxBufEmpty = 0x01, | |
180 | ||
181 | /*Cfg9346Bits */ | |
182 | Cfg9346_Lock = 0x00, | |
183 | Cfg9346_Unlock = 0xC0, | |
184 | ||
185 | /*rx_mode_bits */ | |
186 | AcceptErr = 0x20, | |
187 | AcceptRunt = 0x10, | |
188 | AcceptBroadcast = 0x08, | |
189 | AcceptMulticast = 0x04, | |
190 | AcceptMyPhys = 0x02, | |
191 | AcceptAllPhys = 0x01, | |
192 | ||
193 | /*RxConfigBits */ | |
194 | RxCfgFIFOShift = 13, | |
195 | RxCfgDMAShift = 8, | |
196 | ||
197 | /*TxConfigBits */ | |
198 | TxInterFrameGapShift = 24, | |
199 | TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ | |
200 | ||
201 | /*rtl8169_PHYstatus */ | |
202 | TBI_Enable = 0x80, | |
203 | TxFlowCtrl = 0x40, | |
204 | RxFlowCtrl = 0x20, | |
205 | _1000bpsF = 0x10, | |
206 | _100bps = 0x08, | |
207 | _10bps = 0x04, | |
208 | LinkStatus = 0x02, | |
209 | FullDup = 0x01, | |
210 | ||
211 | /*GIGABIT_PHY_registers */ | |
212 | PHY_CTRL_REG = 0, | |
213 | PHY_STAT_REG = 1, | |
214 | PHY_AUTO_NEGO_REG = 4, | |
215 | PHY_1000_CTRL_REG = 9, | |
216 | ||
217 | /*GIGABIT_PHY_REG_BIT */ | |
218 | PHY_Restart_Auto_Nego = 0x0200, | |
219 | PHY_Enable_Auto_Nego = 0x1000, | |
220 | ||
221 | /* PHY_STAT_REG = 1; */ | |
6a5e1d75 | 222 | PHY_Auto_Nego_Comp = 0x0020, |
a8bd82de WD |
223 | |
224 | /* PHY_AUTO_NEGO_REG = 4; */ | |
225 | PHY_Cap_10_Half = 0x0020, | |
226 | PHY_Cap_10_Full = 0x0040, | |
227 | PHY_Cap_100_Half = 0x0080, | |
228 | PHY_Cap_100_Full = 0x0100, | |
229 | ||
230 | /* PHY_1000_CTRL_REG = 9; */ | |
231 | PHY_Cap_1000_Full = 0x0200, | |
232 | ||
233 | PHY_Cap_Null = 0x0, | |
234 | ||
235 | /*_MediaType*/ | |
236 | _10_Half = 0x01, | |
237 | _10_Full = 0x02, | |
238 | _100_Half = 0x04, | |
239 | _100_Full = 0x08, | |
240 | _1000_Full = 0x10, | |
241 | ||
242 | /*_TBICSRBit*/ | |
243 | TBILinkOK = 0x02000000, | |
244 | }; | |
245 | ||
246 | static struct { | |
247 | const char *name; | |
248 | u8 version; /* depend on RTL8169 docs */ | |
249 | u32 RxConfigMask; /* should clear the bits supported by this chip */ | |
250 | } rtl_chip_info[] = { | |
251 | {"RTL-8169", 0x00, 0xff7e1880,}, | |
252 | {"RTL-8169", 0x04, 0xff7e1880,}, | |
d75469d4 NI |
253 | {"RTL-8169", 0x00, 0xff7e1880,}, |
254 | {"RTL-8169s/8110s", 0x02, 0xff7e1880,}, | |
255 | {"RTL-8169s/8110s", 0x04, 0xff7e1880,}, | |
256 | {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,}, | |
257 | {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,}, | |
258 | {"RTL-8168b/8111sb", 0x30, 0xff7e1880,}, | |
259 | {"RTL-8168b/8111sb", 0x38, 0xff7e1880,}, | |
2287286b | 260 | {"RTL-8168d/8111d", 0x28, 0xff7e1880,}, |
65a6691e | 261 | {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,}, |
cc0856cd | 262 | {"RTL-8168/8111g", 0x4c, 0xff7e1880,}, |
d75469d4 NI |
263 | {"RTL-8101e", 0x34, 0xff7e1880,}, |
264 | {"RTL-8100e", 0x32, 0xff7e1880,}, | |
a8bd82de WD |
265 | }; |
266 | ||
267 | enum _DescStatusBit { | |
268 | OWNbit = 0x80000000, | |
269 | EORbit = 0x40000000, | |
270 | FSbit = 0x20000000, | |
271 | LSbit = 0x10000000, | |
272 | }; | |
273 | ||
274 | struct TxDesc { | |
275 | u32 status; | |
276 | u32 vlan_tag; | |
277 | u32 buf_addr; | |
278 | u32 buf_Haddr; | |
279 | }; | |
280 | ||
281 | struct RxDesc { | |
282 | u32 status; | |
283 | u32 vlan_tag; | |
284 | u32 buf_addr; | |
285 | u32 buf_Haddr; | |
286 | }; | |
287 | ||
d0a5a0b2 SG |
288 | static unsigned char rxdata[RX_BUF_LEN]; |
289 | ||
dad3ba0f | 290 | #define RTL8169_DESC_SIZE 16 |
a8bd82de | 291 | |
dad3ba0f TR |
292 | #if ARCH_DMA_MINALIGN > 256 |
293 | # define RTL8169_ALIGN ARCH_DMA_MINALIGN | |
294 | #else | |
295 | # define RTL8169_ALIGN 256 | |
296 | #endif | |
297 | ||
298 | /* | |
299 | * Warn if the cache-line size is larger than the descriptor size. In such | |
300 | * cases the driver will likely fail because the CPU needs to flush the cache | |
301 | * when requeuing RX buffers, therefore descriptors written by the hardware | |
302 | * may be discarded. | |
d58acdcb TR |
303 | * |
304 | * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause | |
305 | * the driver to allocate descriptors from a pool of non-cached memory. | |
dad3ba0f TR |
306 | */ |
307 | #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN | |
d0a5a0b2 SG |
308 | #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \ |
309 | !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86) | |
dad3ba0f TR |
310 | #warning cache-line size is larger than descriptor size |
311 | #endif | |
d58acdcb | 312 | #endif |
a8bd82de | 313 | |
dad3ba0f TR |
314 | /* |
315 | * Create a static buffer of size RX_BUF_SZ for each TX Descriptor. All | |
316 | * descriptors point to a part of this buffer. | |
317 | */ | |
318 | DEFINE_ALIGN_BUFFER(u8, txb, NUM_TX_DESC * RX_BUF_SIZE, RTL8169_ALIGN); | |
319 | ||
320 | /* | |
321 | * Create a static buffer of size RX_BUF_SZ for each RX Descriptor. All | |
322 | * descriptors point to a part of this buffer. | |
323 | */ | |
324 | DEFINE_ALIGN_BUFFER(u8, rxb, NUM_RX_DESC * RX_BUF_SIZE, RTL8169_ALIGN); | |
a8bd82de WD |
325 | |
326 | struct rtl8169_private { | |
d0a5a0b2 | 327 | ulong iobase; |
a8bd82de WD |
328 | void *mmio_addr; /* memory map physical address */ |
329 | int chipset; | |
330 | unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ | |
331 | unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ | |
332 | unsigned long dirty_tx; | |
a8bd82de WD |
333 | struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */ |
334 | struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */ | |
335 | unsigned char *RxBufferRings; /* Index of Rx Buffer */ | |
336 | unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */ | |
337 | unsigned char *Tx_skbuff[NUM_TX_DESC]; | |
338 | } tpx; | |
339 | ||
340 | static struct rtl8169_private *tpc; | |
341 | ||
342 | static const u16 rtl8169_intr_mask = | |
343 | SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr | | |
344 | TxOK | RxErr | RxOK; | |
345 | static const unsigned int rtl8169_rx_config = | |
346 | (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); | |
347 | ||
348 | static struct pci_device_id supported[] = { | |
d0a5a0b2 SG |
349 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167) }, |
350 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168) }, | |
351 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169) }, | |
a8bd82de WD |
352 | {} |
353 | }; | |
354 | ||
355 | void mdio_write(int RegAddr, int value) | |
356 | { | |
357 | int i; | |
358 | ||
359 | RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value); | |
360 | udelay(1000); | |
361 | ||
362 | for (i = 2000; i > 0; i--) { | |
363 | /* Check if the RTL8169 has completed writing to the specified MII register */ | |
364 | if (!(RTL_R32(PHYAR) & 0x80000000)) { | |
365 | break; | |
366 | } else { | |
367 | udelay(100); | |
368 | } | |
369 | } | |
370 | } | |
371 | ||
372 | int mdio_read(int RegAddr) | |
373 | { | |
374 | int i, value = -1; | |
375 | ||
376 | RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16); | |
377 | udelay(1000); | |
378 | ||
379 | for (i = 2000; i > 0; i--) { | |
380 | /* Check if the RTL8169 has completed retrieving data from the specified MII register */ | |
381 | if (RTL_R32(PHYAR) & 0x80000000) { | |
382 | value = (int) (RTL_R32(PHYAR) & 0xFFFF); | |
383 | break; | |
384 | } else { | |
385 | udelay(100); | |
386 | } | |
387 | } | |
388 | return value; | |
389 | } | |
390 | ||
d0a5a0b2 | 391 | static int rtl8169_init_board(unsigned long dev_iobase, const char *name) |
a8bd82de WD |
392 | { |
393 | int i; | |
394 | u32 tmp; | |
395 | ||
396 | #ifdef DEBUG_RTL8169 | |
397 | printf ("%s\n", __FUNCTION__); | |
398 | #endif | |
d0a5a0b2 | 399 | ioaddr = dev_iobase; |
a8bd82de WD |
400 | |
401 | /* Soft reset the chip. */ | |
402 | RTL_W8(ChipCmd, CmdReset); | |
403 | ||
404 | /* Check that the chip has finished the reset. */ | |
405 | for (i = 1000; i > 0; i--) | |
406 | if ((RTL_R8(ChipCmd) & CmdReset) == 0) | |
407 | break; | |
408 | else | |
409 | udelay(10); | |
410 | ||
411 | /* identify chip attached to board */ | |
412 | tmp = RTL_R32(TxConfig); | |
413 | tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24; | |
414 | ||
415 | for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){ | |
416 | if (tmp == rtl_chip_info[i].version) { | |
417 | tpc->chipset = i; | |
418 | goto match; | |
419 | } | |
420 | } | |
421 | ||
422 | /* if unknown chip, assume array element #0, original RTL-8169 in this case */ | |
d0a5a0b2 SG |
423 | printf("PCI device %s: unknown chip version, assuming RTL-8169\n", |
424 | name); | |
06c53bea | 425 | printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig)); |
a8bd82de WD |
426 | tpc->chipset = 0; |
427 | ||
428 | match: | |
429 | return 0; | |
430 | } | |
431 | ||
d58acdcb TR |
432 | /* |
433 | * TX and RX descriptors are 16 bytes. This causes problems with the cache | |
434 | * maintenance on CPUs where the cache-line size exceeds the size of these | |
435 | * descriptors. What will happen is that when the driver receives a packet | |
436 | * it will be immediately requeued for the hardware to reuse. The CPU will | |
437 | * therefore need to flush the cache-line containing the descriptor, which | |
438 | * will cause all other descriptors in the same cache-line to be flushed | |
439 | * along with it. If one of those descriptors had been written to by the | |
440 | * device those changes (and the associated packet) will be lost. | |
441 | * | |
442 | * To work around this, we make use of non-cached memory if available. If | |
443 | * descriptors are mapped uncached there's no need to manually flush them | |
444 | * or invalidate them. | |
445 | * | |
446 | * Note that this only applies to descriptors. The packet data buffers do | |
447 | * not have the same constraints since they are 1536 bytes large, so they | |
448 | * are unlikely to share cache-lines. | |
449 | */ | |
450 | static void *rtl_alloc_descs(unsigned int num) | |
451 | { | |
452 | size_t size = num * RTL8169_DESC_SIZE; | |
453 | ||
454 | #ifdef CONFIG_SYS_NONCACHED_MEMORY | |
455 | return (void *)noncached_alloc(size, RTL8169_ALIGN); | |
456 | #else | |
457 | return memalign(RTL8169_ALIGN, size); | |
458 | #endif | |
459 | } | |
460 | ||
22ece0e2 TR |
461 | /* |
462 | * Cache maintenance functions. These are simple wrappers around the more | |
463 | * general purpose flush_cache() and invalidate_dcache_range() functions. | |
464 | */ | |
465 | ||
466 | static void rtl_inval_rx_desc(struct RxDesc *desc) | |
467 | { | |
d58acdcb | 468 | #ifndef CONFIG_SYS_NONCACHED_MEMORY |
22ece0e2 TR |
469 | unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); |
470 | unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); | |
471 | ||
472 | invalidate_dcache_range(start, end); | |
d58acdcb | 473 | #endif |
22ece0e2 TR |
474 | } |
475 | ||
476 | static void rtl_flush_rx_desc(struct RxDesc *desc) | |
477 | { | |
d58acdcb | 478 | #ifndef CONFIG_SYS_NONCACHED_MEMORY |
22ece0e2 | 479 | flush_cache((unsigned long)desc, sizeof(*desc)); |
d58acdcb | 480 | #endif |
22ece0e2 TR |
481 | } |
482 | ||
483 | static void rtl_inval_tx_desc(struct TxDesc *desc) | |
484 | { | |
d58acdcb | 485 | #ifndef CONFIG_SYS_NONCACHED_MEMORY |
22ece0e2 TR |
486 | unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); |
487 | unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); | |
488 | ||
489 | invalidate_dcache_range(start, end); | |
d58acdcb | 490 | #endif |
22ece0e2 TR |
491 | } |
492 | ||
493 | static void rtl_flush_tx_desc(struct TxDesc *desc) | |
494 | { | |
d58acdcb | 495 | #ifndef CONFIG_SYS_NONCACHED_MEMORY |
22ece0e2 | 496 | flush_cache((unsigned long)desc, sizeof(*desc)); |
d58acdcb | 497 | #endif |
22ece0e2 TR |
498 | } |
499 | ||
500 | static void rtl_inval_buffer(void *buf, size_t size) | |
501 | { | |
502 | unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); | |
503 | unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN); | |
504 | ||
505 | invalidate_dcache_range(start, end); | |
506 | } | |
507 | ||
508 | static void rtl_flush_buffer(void *buf, size_t size) | |
509 | { | |
510 | flush_cache((unsigned long)buf, size); | |
511 | } | |
512 | ||
a8bd82de WD |
513 | /************************************************************************** |
514 | RECV - Receive a frame | |
515 | ***************************************************************************/ | |
552ddbe3 SG |
516 | #ifdef CONFIG_DM_ETH |
517 | static int rtl_recv_common(struct udevice *dev, unsigned long dev_iobase, | |
518 | uchar **packetp) | |
519 | #else | |
520 | static int rtl_recv_common(pci_dev_t dev, unsigned long dev_iobase, | |
d0a5a0b2 | 521 | uchar **packetp) |
552ddbe3 | 522 | #endif |
a8bd82de WD |
523 | { |
524 | /* return true if there's an ethernet packet ready to read */ | |
525 | /* nic->packet should contain data on return */ | |
526 | /* nic->packetlen should contain length of data */ | |
527 | int cur_rx; | |
528 | int length = 0; | |
529 | ||
530 | #ifdef DEBUG_RTL8169_RX | |
531 | printf ("%s\n", __FUNCTION__); | |
532 | #endif | |
d0a5a0b2 | 533 | ioaddr = dev_iobase; |
a8bd82de WD |
534 | |
535 | cur_rx = tpc->cur_rx; | |
22ece0e2 TR |
536 | |
537 | rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]); | |
538 | ||
6a5e1d75 GL |
539 | if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) { |
540 | if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) { | |
6a5e1d75 GL |
541 | length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx]. |
542 | status) & 0x00001FFF) - 4; | |
a8bd82de | 543 | |
22ece0e2 | 544 | rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length); |
a8bd82de | 545 | memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); |
a8bd82de WD |
546 | |
547 | if (cur_rx == NUM_RX_DESC - 1) | |
548 | tpc->RxDescArray[cur_rx].status = | |
6a5e1d75 | 549 | cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); |
a8bd82de WD |
550 | else |
551 | tpc->RxDescArray[cur_rx].status = | |
6a5e1d75 | 552 | cpu_to_le32(OWNbit + RX_BUF_SIZE); |
552ddbe3 | 553 | #ifdef CONFIG_DM_ETH |
d0a5a0b2 | 554 | tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32( |
552ddbe3 SG |
555 | dm_pci_mem_to_phys(dev, |
556 | (pci_addr_t)(unsigned long) | |
557 | tpc->RxBufferRing[cur_rx])); | |
558 | #else | |
559 | tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32( | |
560 | pci_mem_to_phys(dev, (pci_addr_t)(unsigned long) | |
d0a5a0b2 | 561 | tpc->RxBufferRing[cur_rx])); |
552ddbe3 | 562 | #endif |
22ece0e2 | 563 | rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]); |
d0a5a0b2 SG |
564 | #ifdef CONFIG_DM_ETH |
565 | *packetp = rxdata; | |
566 | #else | |
1fd92db8 | 567 | net_process_received_packet(rxdata, length); |
d0a5a0b2 | 568 | #endif |
a8bd82de WD |
569 | } else { |
570 | puts("Error Rx"); | |
d0a5a0b2 | 571 | length = -EIO; |
a8bd82de WD |
572 | } |
573 | cur_rx = (cur_rx + 1) % NUM_RX_DESC; | |
574 | tpc->cur_rx = cur_rx; | |
d0a5a0b2 | 575 | return length; |
a8bd82de | 576 | |
d75469d4 NI |
577 | } else { |
578 | ushort sts = RTL_R8(IntrStatus); | |
579 | RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr)); | |
580 | udelay(100); /* wait */ | |
a8bd82de WD |
581 | } |
582 | tpc->cur_rx = cur_rx; | |
583 | return (0); /* initially as this is called to flush the input */ | |
584 | } | |
585 | ||
d0a5a0b2 SG |
586 | #ifdef CONFIG_DM_ETH |
587 | int rtl8169_eth_recv(struct udevice *dev, int flags, uchar **packetp) | |
588 | { | |
589 | struct rtl8169_private *priv = dev_get_priv(dev); | |
590 | ||
552ddbe3 | 591 | return rtl_recv_common(dev, priv->iobase, packetp); |
d0a5a0b2 SG |
592 | } |
593 | #else | |
594 | static int rtl_recv(struct eth_device *dev) | |
595 | { | |
f3ba5523 SW |
596 | return rtl_recv_common((pci_dev_t)(unsigned long)dev->priv, |
597 | dev->iobase, NULL); | |
d0a5a0b2 SG |
598 | } |
599 | #endif /* nCONFIG_DM_ETH */ | |
600 | ||
a8bd82de WD |
601 | #define HZ 1000 |
602 | /************************************************************************** | |
603 | SEND - Transmit a frame | |
604 | ***************************************************************************/ | |
552ddbe3 SG |
605 | #ifdef CONFIG_DM_ETH |
606 | static int rtl_send_common(struct udevice *dev, unsigned long dev_iobase, | |
d0a5a0b2 | 607 | void *packet, int length) |
552ddbe3 SG |
608 | #else |
609 | static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase, | |
610 | void *packet, int length) | |
611 | #endif | |
a8bd82de WD |
612 | { |
613 | /* send the packet to destination */ | |
614 | ||
615 | u32 to; | |
616 | u8 *ptxb; | |
617 | int entry = tpc->cur_tx % NUM_TX_DESC; | |
618 | u32 len = length; | |
6a5e1d75 | 619 | int ret; |
a8bd82de WD |
620 | |
621 | #ifdef DEBUG_RTL8169_TX | |
622 | int stime = currticks(); | |
623 | printf ("%s\n", __FUNCTION__); | |
624 | printf("sending %d bytes\n", len); | |
625 | #endif | |
626 | ||
d0a5a0b2 | 627 | ioaddr = dev_iobase; |
a8bd82de WD |
628 | |
629 | /* point to the current txb incase multiple tx_rings are used */ | |
630 | ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; | |
631 | memcpy(ptxb, (char *)packet, (int)length); | |
632 | ||
633 | while (len < ETH_ZLEN) | |
634 | ptxb[len++] = '\0'; | |
635 | ||
7377647a PC |
636 | rtl_flush_buffer(ptxb, ALIGN(len, RTL8169_ALIGN)); |
637 | ||
db70b843 | 638 | tpc->TxDescArray[entry].buf_Haddr = 0; |
552ddbe3 | 639 | #ifdef CONFIG_DM_ETH |
d0a5a0b2 | 640 | tpc->TxDescArray[entry].buf_addr = cpu_to_le32( |
552ddbe3 SG |
641 | dm_pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb)); |
642 | #else | |
643 | tpc->TxDescArray[entry].buf_addr = cpu_to_le32( | |
644 | pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb)); | |
645 | #endif | |
a8bd82de WD |
646 | if (entry != (NUM_TX_DESC - 1)) { |
647 | tpc->TxDescArray[entry].status = | |
6a5e1d75 GL |
648 | cpu_to_le32((OWNbit | FSbit | LSbit) | |
649 | ((len > ETH_ZLEN) ? len : ETH_ZLEN)); | |
a8bd82de WD |
650 | } else { |
651 | tpc->TxDescArray[entry].status = | |
6a5e1d75 GL |
652 | cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) | |
653 | ((len > ETH_ZLEN) ? len : ETH_ZLEN)); | |
a8bd82de | 654 | } |
22ece0e2 | 655 | rtl_flush_tx_desc(&tpc->TxDescArray[entry]); |
a8bd82de WD |
656 | RTL_W8(TxPoll, 0x40); /* set polling bit */ |
657 | ||
658 | tpc->cur_tx++; | |
659 | to = currticks() + TX_TIMEOUT; | |
d4c02e6f | 660 | do { |
22ece0e2 | 661 | rtl_inval_tx_desc(&tpc->TxDescArray[entry]); |
d4c02e6f | 662 | } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit) |
6a5e1d75 | 663 | && (currticks() < to)); /* wait */ |
a8bd82de WD |
664 | |
665 | if (currticks() >= to) { | |
666 | #ifdef DEBUG_RTL8169_TX | |
7a36b9c1 TR |
667 | puts("tx timeout/error\n"); |
668 | printf("%s elapsed time : %lu\n", __func__, currticks()-stime); | |
a8bd82de | 669 | #endif |
4c64c4db | 670 | ret = -ETIMEDOUT; |
a8bd82de WD |
671 | } else { |
672 | #ifdef DEBUG_RTL8169_TX | |
673 | puts("tx done\n"); | |
674 | #endif | |
4c64c4db | 675 | ret = 0; |
a8bd82de | 676 | } |
6a5e1d75 GL |
677 | /* Delay to make net console (nc) work properly */ |
678 | udelay(20); | |
679 | return ret; | |
a8bd82de WD |
680 | } |
681 | ||
d0a5a0b2 SG |
682 | #ifdef CONFIG_DM_ETH |
683 | int rtl8169_eth_send(struct udevice *dev, void *packet, int length) | |
684 | { | |
685 | struct rtl8169_private *priv = dev_get_priv(dev); | |
686 | ||
552ddbe3 | 687 | return rtl_send_common(dev, priv->iobase, packet, length); |
d0a5a0b2 SG |
688 | } |
689 | ||
690 | #else | |
691 | static int rtl_send(struct eth_device *dev, void *packet, int length) | |
692 | { | |
f3ba5523 SW |
693 | return rtl_send_common((pci_dev_t)(unsigned long)dev->priv, |
694 | dev->iobase, packet, length); | |
d0a5a0b2 SG |
695 | } |
696 | #endif | |
697 | ||
698 | static void rtl8169_set_rx_mode(void) | |
a8bd82de WD |
699 | { |
700 | u32 mc_filter[2]; /* Multicast hash filter */ | |
701 | int rx_mode; | |
702 | u32 tmp = 0; | |
703 | ||
704 | #ifdef DEBUG_RTL8169 | |
705 | printf ("%s\n", __FUNCTION__); | |
706 | #endif | |
707 | ||
708 | /* IFF_ALLMULTI */ | |
709 | /* Too many to filter perfectly -- accept all multicasts. */ | |
710 | rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; | |
711 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
712 | ||
713 | tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) & | |
714 | rtl_chip_info[tpc->chipset].RxConfigMask); | |
715 | ||
716 | RTL_W32(RxConfig, tmp); | |
717 | RTL_W32(MAR0 + 0, mc_filter[0]); | |
718 | RTL_W32(MAR0 + 4, mc_filter[1]); | |
719 | } | |
720 | ||
552ddbe3 SG |
721 | #ifdef CONFIG_DM_ETH |
722 | static void rtl8169_hw_start(struct udevice *dev) | |
723 | #else | |
724 | static void rtl8169_hw_start(pci_dev_t dev) | |
725 | #endif | |
a8bd82de WD |
726 | { |
727 | u32 i; | |
728 | ||
729 | #ifdef DEBUG_RTL8169 | |
730 | int stime = currticks(); | |
731 | printf ("%s\n", __FUNCTION__); | |
732 | #endif | |
733 | ||
734 | #if 0 | |
735 | /* Soft reset the chip. */ | |
736 | RTL_W8(ChipCmd, CmdReset); | |
737 | ||
738 | /* Check that the chip has finished the reset. */ | |
739 | for (i = 1000; i > 0; i--) { | |
740 | if ((RTL_R8(ChipCmd) & CmdReset) == 0) | |
741 | break; | |
742 | else | |
743 | udelay(10); | |
744 | } | |
745 | #endif | |
746 | ||
747 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
db70b843 YS |
748 | |
749 | /* RTL-8169sb/8110sb or previous version */ | |
750 | if (tpc->chipset <= 5) | |
751 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); | |
752 | ||
a8bd82de WD |
753 | RTL_W8(EarlyTxThres, EarlyTxThld); |
754 | ||
755 | /* For gigabit rtl8169 */ | |
756 | RTL_W16(RxMaxSize, RxPacketMaxSize); | |
757 | ||
758 | /* Set Rx Config register */ | |
759 | i = rtl8169_rx_config | (RTL_R32(RxConfig) & | |
760 | rtl_chip_info[tpc->chipset].RxConfigMask); | |
761 | RTL_W32(RxConfig, i); | |
762 | ||
763 | /* Set DMA burst size and Interframe Gap Time */ | |
764 | RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | | |
765 | (InterFrameGap << TxInterFrameGapShift)); | |
766 | ||
767 | ||
768 | tpc->cur_rx = 0; | |
769 | ||
552ddbe3 SG |
770 | #ifdef CONFIG_DM_ETH |
771 | RTL_W32(TxDescStartAddrLow, dm_pci_mem_to_phys(dev, | |
d0a5a0b2 | 772 | (pci_addr_t)(unsigned long)tpc->TxDescArray)); |
552ddbe3 SG |
773 | #else |
774 | RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(dev, | |
775 | (pci_addr_t)(unsigned long)tpc->TxDescArray)); | |
776 | #endif | |
db70b843 | 777 | RTL_W32(TxDescStartAddrHigh, (unsigned long)0); |
552ddbe3 SG |
778 | #ifdef CONFIG_DM_ETH |
779 | RTL_W32(RxDescStartAddrLow, dm_pci_mem_to_phys( | |
780 | dev, (pci_addr_t)(unsigned long)tpc->RxDescArray)); | |
781 | #else | |
d0a5a0b2 | 782 | RTL_W32(RxDescStartAddrLow, pci_mem_to_phys( |
552ddbe3 SG |
783 | dev, (pci_addr_t)(unsigned long)tpc->RxDescArray)); |
784 | #endif | |
db70b843 YS |
785 | RTL_W32(RxDescStartAddrHigh, (unsigned long)0); |
786 | ||
787 | /* RTL-8169sc/8110sc or later version */ | |
788 | if (tpc->chipset > 5) | |
789 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); | |
790 | ||
a8bd82de WD |
791 | RTL_W8(Cfg9346, Cfg9346_Lock); |
792 | udelay(10); | |
793 | ||
794 | RTL_W32(RxMissed, 0); | |
795 | ||
d0a5a0b2 | 796 | rtl8169_set_rx_mode(); |
a8bd82de WD |
797 | |
798 | /* no early-rx interrupts */ | |
799 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); | |
800 | ||
801 | #ifdef DEBUG_RTL8169 | |
7a36b9c1 | 802 | printf("%s elapsed time : %lu\n", __func__, currticks()-stime); |
a8bd82de WD |
803 | #endif |
804 | } | |
805 | ||
552ddbe3 SG |
806 | #ifdef CONFIG_DM_ETH |
807 | static void rtl8169_init_ring(struct udevice *dev) | |
808 | #else | |
809 | static void rtl8169_init_ring(pci_dev_t dev) | |
810 | #endif | |
a8bd82de WD |
811 | { |
812 | int i; | |
813 | ||
814 | #ifdef DEBUG_RTL8169 | |
815 | int stime = currticks(); | |
816 | printf ("%s\n", __FUNCTION__); | |
817 | #endif | |
818 | ||
819 | tpc->cur_rx = 0; | |
820 | tpc->cur_tx = 0; | |
821 | tpc->dirty_tx = 0; | |
822 | memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc)); | |
823 | memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc)); | |
824 | ||
825 | for (i = 0; i < NUM_TX_DESC; i++) { | |
826 | tpc->Tx_skbuff[i] = &txb[i]; | |
827 | } | |
828 | ||
829 | for (i = 0; i < NUM_RX_DESC; i++) { | |
830 | if (i == (NUM_RX_DESC - 1)) | |
831 | tpc->RxDescArray[i].status = | |
6a5e1d75 | 832 | cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); |
a8bd82de | 833 | else |
6a5e1d75 GL |
834 | tpc->RxDescArray[i].status = |
835 | cpu_to_le32(OWNbit + RX_BUF_SIZE); | |
a8bd82de WD |
836 | |
837 | tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; | |
552ddbe3 SG |
838 | #ifdef CONFIG_DM_ETH |
839 | tpc->RxDescArray[i].buf_addr = cpu_to_le32(dm_pci_mem_to_phys( | |
840 | dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i])); | |
841 | #else | |
d0a5a0b2 | 842 | tpc->RxDescArray[i].buf_addr = cpu_to_le32(pci_mem_to_phys( |
552ddbe3 SG |
843 | dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i])); |
844 | #endif | |
22ece0e2 | 845 | rtl_flush_rx_desc(&tpc->RxDescArray[i]); |
a8bd82de WD |
846 | } |
847 | ||
848 | #ifdef DEBUG_RTL8169 | |
7a36b9c1 | 849 | printf("%s elapsed time : %lu\n", __func__, currticks()-stime); |
a8bd82de WD |
850 | #endif |
851 | } | |
852 | ||
552ddbe3 | 853 | #ifdef CONFIG_DM_ETH |
dad7b740 SW |
854 | static void rtl8169_common_start(struct udevice *dev, unsigned char *enetaddr, |
855 | unsigned long dev_iobase) | |
552ddbe3 | 856 | #else |
dad7b740 SW |
857 | static void rtl8169_common_start(pci_dev_t dev, unsigned char *enetaddr, |
858 | unsigned long dev_iobase) | |
552ddbe3 | 859 | #endif |
a8bd82de WD |
860 | { |
861 | int i; | |
a8bd82de WD |
862 | |
863 | #ifdef DEBUG_RTL8169 | |
864 | int stime = currticks(); | |
865 | printf ("%s\n", __FUNCTION__); | |
866 | #endif | |
867 | ||
dad7b740 SW |
868 | ioaddr = dev_iobase; |
869 | ||
552ddbe3 SG |
870 | rtl8169_init_ring(dev); |
871 | rtl8169_hw_start(dev); | |
a8bd82de WD |
872 | /* Construct a perfect filter frame with the mac address as first match |
873 | * and broadcast for all others */ | |
874 | for (i = 0; i < 192; i++) | |
875 | txb[i] = 0xFF; | |
876 | ||
d0a5a0b2 SG |
877 | txb[0] = enetaddr[0]; |
878 | txb[1] = enetaddr[1]; | |
879 | txb[2] = enetaddr[2]; | |
880 | txb[3] = enetaddr[3]; | |
881 | txb[4] = enetaddr[4]; | |
882 | txb[5] = enetaddr[5]; | |
a8bd82de WD |
883 | |
884 | #ifdef DEBUG_RTL8169 | |
7a36b9c1 | 885 | printf("%s elapsed time : %lu\n", __func__, currticks()-stime); |
a8bd82de WD |
886 | #endif |
887 | } | |
888 | ||
d0a5a0b2 SG |
889 | #ifdef CONFIG_DM_ETH |
890 | static int rtl8169_eth_start(struct udevice *dev) | |
891 | { | |
892 | struct eth_pdata *plat = dev_get_platdata(dev); | |
dad7b740 | 893 | struct rtl8169_private *priv = dev_get_priv(dev); |
d0a5a0b2 | 894 | |
dad7b740 | 895 | rtl8169_common_start(dev, plat->enetaddr, priv->iobase); |
d0a5a0b2 SG |
896 | |
897 | return 0; | |
898 | } | |
899 | #else | |
a8bd82de | 900 | /************************************************************************** |
d0a5a0b2 | 901 | RESET - Finish setting up the ethernet interface |
a8bd82de | 902 | ***************************************************************************/ |
d0a5a0b2 SG |
903 | static int rtl_reset(struct eth_device *dev, bd_t *bis) |
904 | { | |
f3ba5523 | 905 | rtl8169_common_start((pci_dev_t)(unsigned long)dev->priv, |
dad7b740 | 906 | dev->enetaddr, dev->iobase); |
d0a5a0b2 SG |
907 | |
908 | return 0; | |
909 | } | |
910 | #endif /* nCONFIG_DM_ETH */ | |
911 | ||
912 | static void rtl_halt_common(unsigned long dev_iobase) | |
a8bd82de WD |
913 | { |
914 | int i; | |
915 | ||
916 | #ifdef DEBUG_RTL8169 | |
917 | printf ("%s\n", __FUNCTION__); | |
918 | #endif | |
919 | ||
d0a5a0b2 | 920 | ioaddr = dev_iobase; |
a8bd82de WD |
921 | |
922 | /* Stop the chip's Tx and Rx DMA processes. */ | |
923 | RTL_W8(ChipCmd, 0x00); | |
924 | ||
925 | /* Disable interrupts by clearing the interrupt mask. */ | |
926 | RTL_W16(IntrMask, 0x0000); | |
927 | ||
928 | RTL_W32(RxMissed, 0); | |
929 | ||
a8bd82de WD |
930 | for (i = 0; i < NUM_RX_DESC; i++) { |
931 | tpc->RxBufferRing[i] = NULL; | |
932 | } | |
933 | } | |
934 | ||
d0a5a0b2 SG |
935 | #ifdef CONFIG_DM_ETH |
936 | void rtl8169_eth_stop(struct udevice *dev) | |
937 | { | |
938 | struct rtl8169_private *priv = dev_get_priv(dev); | |
939 | ||
940 | rtl_halt_common(priv->iobase); | |
941 | } | |
942 | #else | |
943 | /************************************************************************** | |
944 | HALT - Turn off ethernet interface | |
945 | ***************************************************************************/ | |
946 | static void rtl_halt(struct eth_device *dev) | |
947 | { | |
948 | rtl_halt_common(dev->iobase); | |
949 | } | |
950 | #endif | |
951 | ||
a8bd82de WD |
952 | /************************************************************************** |
953 | INIT - Look for an adapter, this routine's visible to the outside | |
954 | ***************************************************************************/ | |
955 | ||
956 | #define board_found 1 | |
957 | #define valid_link 0 | |
d0a5a0b2 SG |
958 | static int rtl_init(unsigned long dev_ioaddr, const char *name, |
959 | unsigned char *enetaddr) | |
a8bd82de WD |
960 | { |
961 | static int board_idx = -1; | |
a8bd82de WD |
962 | int i, rc; |
963 | int option = -1, Cap10_100 = 0, Cap1000 = 0; | |
964 | ||
965 | #ifdef DEBUG_RTL8169 | |
966 | printf ("%s\n", __FUNCTION__); | |
967 | #endif | |
d0a5a0b2 | 968 | ioaddr = dev_ioaddr; |
a8bd82de WD |
969 | |
970 | board_idx++; | |
971 | ||
a8bd82de WD |
972 | /* point to private storage */ |
973 | tpc = &tpx; | |
974 | ||
d0a5a0b2 | 975 | rc = rtl8169_init_board(ioaddr, name); |
a8bd82de WD |
976 | if (rc) |
977 | return rc; | |
978 | ||
979 | /* Get MAC address. FIXME: read EEPROM */ | |
980 | for (i = 0; i < MAC_ADDR_LEN; i++) | |
d0a5a0b2 | 981 | enetaddr[i] = RTL_R8(MAC0 + i); |
a8bd82de WD |
982 | |
983 | #ifdef DEBUG_RTL8169 | |
db70b843 | 984 | printf("chipset = %d\n", tpc->chipset); |
a8bd82de WD |
985 | printf("MAC Address"); |
986 | for (i = 0; i < MAC_ADDR_LEN; i++) | |
d0a5a0b2 | 987 | printf(":%02x", enetaddr[i]); |
a8bd82de WD |
988 | putc('\n'); |
989 | #endif | |
990 | ||
991 | #ifdef DEBUG_RTL8169 | |
992 | /* Print out some hardware info */ | |
d0a5a0b2 | 993 | printf("%s: at ioaddr 0x%lx\n", name, ioaddr); |
a8bd82de WD |
994 | #endif |
995 | ||
996 | /* if TBI is not endbled */ | |
997 | if (!(RTL_R8(PHYstatus) & TBI_Enable)) { | |
998 | int val = mdio_read(PHY_AUTO_NEGO_REG); | |
999 | ||
1000 | option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; | |
1001 | /* Force RTL8169 in 10/100/1000 Full/Half mode. */ | |
1002 | if (option > 0) { | |
1003 | #ifdef DEBUG_RTL8169 | |
dbe25386 | 1004 | printf("%s: Force-mode Enabled.\n", name); |
a8bd82de WD |
1005 | #endif |
1006 | Cap10_100 = 0, Cap1000 = 0; | |
1007 | switch (option) { | |
1008 | case _10_Half: | |
1009 | Cap10_100 = PHY_Cap_10_Half; | |
1010 | Cap1000 = PHY_Cap_Null; | |
1011 | break; | |
1012 | case _10_Full: | |
1013 | Cap10_100 = PHY_Cap_10_Full; | |
1014 | Cap1000 = PHY_Cap_Null; | |
1015 | break; | |
1016 | case _100_Half: | |
1017 | Cap10_100 = PHY_Cap_100_Half; | |
1018 | Cap1000 = PHY_Cap_Null; | |
1019 | break; | |
1020 | case _100_Full: | |
1021 | Cap10_100 = PHY_Cap_100_Full; | |
1022 | Cap1000 = PHY_Cap_Null; | |
1023 | break; | |
1024 | case _1000_Full: | |
1025 | Cap10_100 = PHY_Cap_Null; | |
1026 | Cap1000 = PHY_Cap_1000_Full; | |
1027 | break; | |
1028 | default: | |
1029 | break; | |
1030 | } | |
1031 | mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ | |
1032 | mdio_write(PHY_1000_CTRL_REG, Cap1000); | |
1033 | } else { | |
1034 | #ifdef DEBUG_RTL8169 | |
1035 | printf("%s: Auto-negotiation Enabled.\n", | |
dbe25386 | 1036 | name); |
a8bd82de WD |
1037 | #endif |
1038 | /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ | |
1039 | mdio_write(PHY_AUTO_NEGO_REG, | |
1040 | PHY_Cap_10_Half | PHY_Cap_10_Full | | |
1041 | PHY_Cap_100_Half | PHY_Cap_100_Full | | |
1042 | (val & 0x1F)); | |
1043 | ||
1044 | /* enable 1000 Full Mode */ | |
1045 | mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full); | |
1046 | ||
1047 | } | |
1048 | ||
1049 | /* Enable auto-negotiation and restart auto-nigotiation */ | |
1050 | mdio_write(PHY_CTRL_REG, | |
1051 | PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego); | |
1052 | udelay(100); | |
1053 | ||
1054 | /* wait for auto-negotiation process */ | |
1055 | for (i = 10000; i > 0; i--) { | |
1056 | /* check if auto-negotiation complete */ | |
6a5e1d75 | 1057 | if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) { |
a8bd82de WD |
1058 | udelay(100); |
1059 | option = RTL_R8(PHYstatus); | |
1060 | if (option & _1000bpsF) { | |
1061 | #ifdef DEBUG_RTL8169 | |
1062 | printf("%s: 1000Mbps Full-duplex operation.\n", | |
dbe25386 | 1063 | name); |
a8bd82de WD |
1064 | #endif |
1065 | } else { | |
1066 | #ifdef DEBUG_RTL8169 | |
6a5e1d75 | 1067 | printf("%s: %sMbps %s-duplex operation.\n", |
dbe25386 | 1068 | name, |
6a5e1d75 GL |
1069 | (option & _100bps) ? "100" : |
1070 | "10", | |
1071 | (option & FullDup) ? "Full" : | |
1072 | "Half"); | |
a8bd82de WD |
1073 | #endif |
1074 | } | |
1075 | break; | |
1076 | } else { | |
1077 | udelay(100); | |
1078 | } | |
1079 | } /* end for-loop to wait for auto-negotiation process */ | |
1080 | ||
1081 | } else { | |
1082 | udelay(100); | |
1083 | #ifdef DEBUG_RTL8169 | |
1084 | printf | |
1085 | ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n", | |
dbe25386 | 1086 | name, |
a8bd82de WD |
1087 | (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed"); |
1088 | #endif | |
1089 | } | |
1090 | ||
dad3ba0f | 1091 | |
d58acdcb TR |
1092 | tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC); |
1093 | if (!tpc->RxDescArray) | |
1094 | return -ENOMEM; | |
1095 | ||
1096 | tpc->TxDescArray = rtl_alloc_descs(NUM_TX_DESC); | |
1097 | if (!tpc->TxDescArray) | |
1098 | return -ENOMEM; | |
1099 | ||
1100 | return 0; | |
a8bd82de WD |
1101 | } |
1102 | ||
d0a5a0b2 | 1103 | #ifndef CONFIG_DM_ETH |
a8bd82de WD |
1104 | int rtl8169_initialize(bd_t *bis) |
1105 | { | |
1106 | pci_dev_t devno; | |
1107 | int card_number = 0; | |
1108 | struct eth_device *dev; | |
1109 | u32 iobase; | |
1110 | int idx=0; | |
1111 | ||
1112 | while(1){ | |
2287286b TR |
1113 | unsigned int region; |
1114 | u16 device; | |
d58acdcb | 1115 | int err; |
2287286b | 1116 | |
a8bd82de WD |
1117 | /* Find RTL8169 */ |
1118 | if ((devno = pci_find_devices(supported, idx++)) < 0) | |
1119 | break; | |
1120 | ||
2287286b TR |
1121 | pci_read_config_word(devno, PCI_DEVICE_ID, &device); |
1122 | switch (device) { | |
1123 | case 0x8168: | |
1124 | region = 2; | |
1125 | break; | |
1126 | ||
1127 | default: | |
1128 | region = 1; | |
1129 | break; | |
1130 | } | |
1131 | ||
1132 | pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase); | |
a8bd82de WD |
1133 | iobase &= ~0xf; |
1134 | ||
1135 | debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); | |
1136 | ||
1137 | dev = (struct eth_device *)malloc(sizeof *dev); | |
f4eaef7b NI |
1138 | if (!dev) { |
1139 | printf("Can not allocate memory of rtl8169\n"); | |
1140 | break; | |
1141 | } | |
a8bd82de | 1142 | |
f4eaef7b | 1143 | memset(dev, 0, sizeof(*dev)); |
a8bd82de WD |
1144 | sprintf (dev->name, "RTL8169#%d", card_number); |
1145 | ||
744152f8 | 1146 | dev->priv = (void *)(unsigned long)devno; |
6a5e1d75 | 1147 | dev->iobase = (int)pci_mem_to_phys(devno, iobase); |
a8bd82de WD |
1148 | |
1149 | dev->init = rtl_reset; | |
1150 | dev->halt = rtl_halt; | |
1151 | dev->send = rtl_send; | |
1152 | dev->recv = rtl_recv; | |
1153 | ||
d0a5a0b2 | 1154 | err = rtl_init(dev->iobase, dev->name, dev->enetaddr); |
d58acdcb TR |
1155 | if (err < 0) { |
1156 | printf(pr_fmt("failed to initialize card: %d\n"), err); | |
1157 | free(dev); | |
1158 | continue; | |
1159 | } | |
a8bd82de | 1160 | |
d58acdcb | 1161 | eth_register (dev); |
a8bd82de WD |
1162 | |
1163 | card_number++; | |
1164 | } | |
1165 | return card_number; | |
1166 | } | |
d0a5a0b2 SG |
1167 | #endif |
1168 | ||
1169 | #ifdef CONFIG_DM_ETH | |
1170 | static int rtl8169_eth_probe(struct udevice *dev) | |
1171 | { | |
1172 | struct pci_child_platdata *pplat = dev_get_parent_platdata(dev); | |
1173 | struct rtl8169_private *priv = dev_get_priv(dev); | |
1174 | struct eth_pdata *plat = dev_get_platdata(dev); | |
1175 | u32 iobase; | |
1176 | int region; | |
1177 | int ret; | |
1178 | ||
1179 | debug("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); | |
1180 | switch (pplat->device) { | |
1181 | case 0x8168: | |
1182 | region = 2; | |
1183 | break; | |
1184 | default: | |
1185 | region = 1; | |
1186 | break; | |
1187 | } | |
552ddbe3 | 1188 | dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0 + region * 4, &iobase); |
d0a5a0b2 | 1189 | iobase &= ~0xf; |
552ddbe3 | 1190 | priv->iobase = (int)dm_pci_mem_to_phys(dev, iobase); |
d0a5a0b2 SG |
1191 | |
1192 | ret = rtl_init(priv->iobase, dev->name, plat->enetaddr); | |
1193 | if (ret < 0) { | |
1194 | printf(pr_fmt("failed to initialize card: %d\n"), ret); | |
1195 | return ret; | |
1196 | } | |
1197 | ||
1198 | return 0; | |
1199 | } | |
1200 | ||
1201 | static const struct eth_ops rtl8169_eth_ops = { | |
1202 | .start = rtl8169_eth_start, | |
1203 | .send = rtl8169_eth_send, | |
1204 | .recv = rtl8169_eth_recv, | |
1205 | .stop = rtl8169_eth_stop, | |
1206 | }; | |
1207 | ||
1208 | static const struct udevice_id rtl8169_eth_ids[] = { | |
1209 | { .compatible = "realtek,rtl8169" }, | |
1210 | { } | |
1211 | }; | |
1212 | ||
1213 | U_BOOT_DRIVER(eth_rtl8169) = { | |
1214 | .name = "eth_rtl8169", | |
1215 | .id = UCLASS_ETH, | |
1216 | .of_match = rtl8169_eth_ids, | |
1217 | .probe = rtl8169_eth_probe, | |
1218 | .ops = &rtl8169_eth_ops, | |
1219 | .priv_auto_alloc_size = sizeof(struct rtl8169_private), | |
1220 | .platdata_auto_alloc_size = sizeof(struct eth_pdata), | |
1221 | }; | |
1222 | ||
1223 | U_BOOT_PCI_DEVICE(eth_rtl8169, supported); | |
1224 | #endif |