[people/ms/u-boot.git] / drivers / net / sh_eth.h

/*
 * sh_eth.h - Driver for Renesas SuperH ethernet controler.
 *
 * Copyright (C) 2008 - 2012 Renesas Solutions Corp.
 * Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu
 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
 *
 * This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <netdev.h>
#include <asm/types.h>

#define SHETHER_NAME "sh_eth"

#if defined(CONFIG_SH)
/* Malloc returns addresses in the P1 area (cacheable). However we need to
   use area P2 (non-cacheable) */
#define ADDR_TO_P2(addr)	((((int)(addr) & ~0xe0000000) | 0xa0000000))

/* The ethernet controller needs to use physical addresses */
#if defined(CONFIG_SH_32BIT)
#define ADDR_TO_PHY(addr)	((((int)(addr) & ~0xe0000000) | 0x40000000))
#else
#define ADDR_TO_PHY(addr)	((int)(addr) & ~0xe0000000)
#endif
#elif defined(CONFIG_ARM)
#define inl		readl
#define outl	writel
#define ADDR_TO_PHY(addr)	((int)(addr))
#define ADDR_TO_P2(addr)	(addr)
#endif /* defined(CONFIG_SH) */

/* Number of supported ports */
#define MAX_PORT_NUM	2

/* Buffers must be big enough to hold the largest ethernet frame. Also, rx
   buffers must be a multiple of 32 bytes */
#define MAX_BUF_SIZE	(48 * 32)

/* The number of tx descriptors must be large enough to point to 5 or more
   frames. If each frame uses 2 descriptors, at least 10 descriptors are needed.
   We use one descriptor per frame */
#define NUM_TX_DESC		8

/* The size of the tx descriptor is determined by how much padding is used.
   4, 20, or 52 bytes of padding can be used */
#define TX_DESC_PADDING		4
#define TX_DESC_SIZE		(12 + TX_DESC_PADDING)

/* Tx descriptor. We always use 3 bytes of padding */
struct tx_desc_s {
	volatile u32 td0;
	u32 td1;
	u32 td2;		/* Buffer start */
	u32 padding;
};

/* There is no limitation in the number of rx descriptors */
#define NUM_RX_DESC	8

/* The size of the rx descriptor is determined by how much padding is used.
   4, 20, or 52 bytes of padding can be used */
#define RX_DESC_PADDING		4
#define RX_DESC_SIZE		(12 + RX_DESC_PADDING)

/* Rx descriptor. We always use 4 bytes of padding */
struct rx_desc_s {
	volatile u32 rd0;
	volatile u32 rd1;
	u32 rd2;		/* Buffer start */
	u32 padding;
};

struct sh_eth_info {
	struct tx_desc_s *tx_desc_malloc;
	struct tx_desc_s *tx_desc_base;
	struct tx_desc_s *tx_desc_cur;
	struct rx_desc_s *rx_desc_malloc;
	struct rx_desc_s *rx_desc_base;
	struct rx_desc_s *rx_desc_cur;
	u8 *rx_buf_malloc;
	u8 *rx_buf_base;
	u8 mac_addr[6];
	u8 phy_addr;
	struct eth_device *dev;
	struct phy_device *phydev;
};

struct sh_eth_dev {
	int port;
	struct sh_eth_info port_info[MAX_PORT_NUM];
};

/* from linux/drivers/net/ethernet/renesas/sh_eth.h */
enum {
	/* E-DMAC registers */
	EDSR = 0,
	EDMR,
	EDTRR,
	EDRRR,
	EESR,
	EESIPR,
	TDLAR,
	TDFAR,
	TDFXR,
	TDFFR,
	RDLAR,
	RDFAR,
	RDFXR,
	RDFFR,
	TRSCER,
	RMFCR,
	TFTR,
	FDR,
	RMCR,
	EDOCR,
	TFUCR,
	RFOCR,
	FCFTR,
	RPADIR,
	TRIMD,
	RBWAR,
	TBRAR,

	/* Ether registers */
	ECMR,
	ECSR,
	ECSIPR,
	PIR,
	PSR,
	RDMLR,
	PIPR,
	RFLR,
	IPGR,
	APR,
	MPR,
	PFTCR,
	PFRCR,
	RFCR,
	RFCF,
	TPAUSER,
	TPAUSECR,
	BCFR,
	BCFRR,
	GECMR,
	BCULR,
	MAHR,
	MALR,
	TROCR,
	CDCR,
	LCCR,
	CNDCR,
	CEFCR,
	FRECR,
	TSFRCR,
	TLFRCR,
	CERCR,
	CEECR,
	MAFCR,
	RTRATE,
	CSMR,
	RMII_MII,

	/* This value must be written at last. */
	SH_ETH_MAX_REGISTER_OFFSET,
};

static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
	[EDSR]	= 0x0000,
	[EDMR]	= 0x0400,
	[EDTRR]	= 0x0408,
	[EDRRR]	= 0x0410,
	[EESR]	= 0x0428,
	[EESIPR]	= 0x0430,
	[TDLAR]	= 0x0010,
	[TDFAR]	= 0x0014,
	[TDFXR]	= 0x0018,
	[TDFFR]	= 0x001c,
	[RDLAR]	= 0x0030,
	[RDFAR]	= 0x0034,
	[RDFXR]	= 0x0038,
	[RDFFR]	= 0x003c,
	[TRSCER]	= 0x0438,
	[RMFCR]	= 0x0440,
	[TFTR]	= 0x0448,
	[FDR]	= 0x0450,
	[RMCR]	= 0x0458,
	[RPADIR]	= 0x0460,
	[FCFTR]	= 0x0468,
	[CSMR] = 0x04E4,

	[ECMR]	= 0x0500,
	[ECSR]	= 0x0510,
	[ECSIPR]	= 0x0518,
	[PIR]	= 0x0520,
	[PSR]	= 0x0528,
	[PIPR]	= 0x052c,
	[RFLR]	= 0x0508,
	[APR]	= 0x0554,
	[MPR]	= 0x0558,
	[PFTCR]	= 0x055c,
	[PFRCR]	= 0x0560,
	[TPAUSER]	= 0x0564,
	[GECMR]	= 0x05b0,
	[BCULR]	= 0x05b4,
	[MAHR]	= 0x05c0,
	[MALR]	= 0x05c8,
	[TROCR]	= 0x0700,
	[CDCR]	= 0x0708,
	[LCCR]	= 0x0710,
	[CEFCR]	= 0x0740,
	[FRECR]	= 0x0748,
	[TSFRCR]	= 0x0750,
	[TLFRCR]	= 0x0758,
	[RFCR]	= 0x0760,
	[CERCR]	= 0x0768,
	[CEECR]	= 0x0770,
	[MAFCR]	= 0x0778,
	[RMII_MII] =  0x0790,
};

static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
	[ECMR]	= 0x0100,
	[RFLR]	= 0x0108,
	[ECSR]	= 0x0110,
	[ECSIPR]	= 0x0118,
	[PIR]	= 0x0120,
	[PSR]	= 0x0128,
	[RDMLR]	= 0x0140,
	[IPGR]	= 0x0150,
	[APR]	= 0x0154,
	[MPR]	= 0x0158,
	[TPAUSER]	= 0x0164,
	[RFCF]	= 0x0160,
	[TPAUSECR]	= 0x0168,
	[BCFRR]	= 0x016c,
	[MAHR]	= 0x01c0,
	[MALR]	= 0x01c8,
	[TROCR]	= 0x01d0,
	[CDCR]	= 0x01d4,
	[LCCR]	= 0x01d8,
	[CNDCR]	= 0x01dc,
	[CEFCR]	= 0x01e4,
	[FRECR]	= 0x01e8,
	[TSFRCR]	= 0x01ec,
	[TLFRCR]	= 0x01f0,
	[RFCR]	= 0x01f4,
	[MAFCR]	= 0x01f8,
	[RTRATE]	= 0x01fc,

	[EDMR]	= 0x0000,
	[EDTRR]	= 0x0008,
	[EDRRR]	= 0x0010,
	[TDLAR]	= 0x0018,
	[RDLAR]	= 0x0020,
	[EESR]	= 0x0028,
	[EESIPR]	= 0x0030,
	[TRSCER]	= 0x0038,
	[RMFCR]	= 0x0040,
	[TFTR]	= 0x0048,
	[FDR]	= 0x0050,
	[RMCR]	= 0x0058,
	[TFUCR]	= 0x0064,
	[RFOCR]	= 0x0068,
	[FCFTR]	= 0x0070,
	[RPADIR]	= 0x0078,
	[TRIMD]	= 0x007c,
	[RBWAR]	= 0x00c8,
	[RDFAR]	= 0x00cc,
	[TBRAR]	= 0x00d4,
	[TDFAR]	= 0x00d8,
};

/* Register Address */
#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
#define SH_ETH_TYPE_GETHER
#define BASE_IO_ADDR	0xfee00000
#elif defined(CONFIG_CPU_SH7757)
#if defined(CONFIG_SH_ETHER_USE_GETHER)
#define SH_ETH_TYPE_GETHER
#define BASE_IO_ADDR	0xfee00000
#else
#define SH_ETH_TYPE_ETHER
#define BASE_IO_ADDR	0xfef00000
#endif
#elif defined(CONFIG_CPU_SH7724)
#define SH_ETH_TYPE_ETHER
#define BASE_IO_ADDR	0xA4600000
#elif defined(CONFIG_R8A7740)
#define SH_ETH_TYPE_GETHER
#define BASE_IO_ADDR	0xE9A00000
#endif

/*
 * Register's bits
 * Copy from Linux driver source code
 */
#if defined(SH_ETH_TYPE_GETHER)
/* EDSR */
enum EDSR_BIT {
	EDSR_ENT = 0x01, EDSR_ENR = 0x02,
};
#define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
#endif

/* EDMR */
enum DMAC_M_BIT {
	EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
#if defined(SH_ETH_TYPE_GETHER)
	EDMR_SRST	= 0x03, /* Receive/Send reset */
	EMDR_DESC_R	= 0x30, /* Descriptor reserve size */
	EDMR_EL		= 0x40, /* Litte endian */
#elif defined(SH_ETH_TYPE_ETHER)
	EDMR_SRST	= 0x01,
	EMDR_DESC_R	= 0x30, /* Descriptor reserve size */
	EDMR_EL		= 0x40, /* Litte endian */
#else
	EDMR_SRST = 0x01,
#endif
};

/* RFLR */
#define RFLR_RFL_MIN	0x05EE	/* Recv Frame length 1518 byte */

/* EDTRR */
enum DMAC_T_BIT {
#if defined(SH_ETH_TYPE_GETHER)
	EDTRR_TRNS = 0x03,
#else
	EDTRR_TRNS = 0x01,
#endif
};

/* GECMR */
enum GECMR_BIT {
#if defined(CONFIG_CPU_SH7757)
	GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00,
#else
	GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,
#endif
};

/* EDRRR*/
enum EDRRR_R_BIT {
	EDRRR_R = 0x01,
};

/* TPAUSER */
enum TPAUSER_BIT {
	TPAUSER_TPAUSE = 0x0000ffff,
	TPAUSER_UNLIMITED = 0,
};

/* BCFR */
enum BCFR_BIT {
	BCFR_RPAUSE = 0x0000ffff,
	BCFR_UNLIMITED = 0,
};

/* PIR */
enum PIR_BIT {
	PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
};

/* PSR */
enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };

/* EESR */
enum EESR_BIT {

#if defined(SH_ETH_TYPE_ETHER)
	EESR_TWB  = 0x40000000,
#else
	EESR_TWB  = 0xC0000000,
	EESR_TC1  = 0x20000000,
	EESR_TUC  = 0x10000000,
	EESR_ROC  = 0x80000000,
#endif
	EESR_TABT = 0x04000000,
	EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
#if defined(SH_ETH_TYPE_ETHER)
	EESR_ADE  = 0x00800000,
#endif
	EESR_ECI  = 0x00400000,
	EESR_FTC  = 0x00200000, EESR_TDE  = 0x00100000,
	EESR_TFE  = 0x00080000, EESR_FRC  = 0x00040000,
	EESR_RDE  = 0x00020000, EESR_RFE  = 0x00010000,
#if defined(SH_ETH_TYPE_ETHER)
	EESR_CND  = 0x00000800,
#endif
	EESR_DLC  = 0x00000400,
	EESR_CD   = 0x00000200, EESR_RTO  = 0x00000100,
	EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
	EESR_CELF = 0x00000020, EESR_RRF  = 0x00000010,
	rESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
	EESR_PRE  = 0x00000002, EESR_CERF = 0x00000001,
};


#if defined(SH_ETH_TYPE_GETHER)
# define TX_CHECK (EESR_TC1 | EESR_FTC)
# define EESR_ERR_CHECK	(EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
		| EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
# define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE)

#else
# define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO)
# define EESR_ERR_CHECK	(EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
		| EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
# define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE)
#endif

/* EESIPR */
enum DMAC_IM_BIT {
	DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
	DMAC_M_RABT = 0x02000000,
	DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
	DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
	DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
	DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
	DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
	DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
	DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
	DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
	DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
	DMAC_M_RINT1 = 0x00000001,
};

/* Receive descriptor bit */
enum RD_STS_BIT {
	RD_RACT = 0x80000000, RD_RDLE = 0x40000000,
	RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
	RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
	RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
	RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
	RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
	RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
	RD_RFS1 = 0x00000001,
};
#define RDF1ST	RD_RFP1
#define RDFEND	RD_RFP0
#define RD_RFP	(RD_RFP1|RD_RFP0)

/* RDFFR*/
enum RDFFR_BIT {
	RDFFR_RDLF = 0x01,
};

/* FCFTR */
enum FCFTR_BIT {
	FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
	FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
	FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
};
#define FIFO_F_D_RFF	(FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
#define FIFO_F_D_RFD	(FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)

/* Transfer descriptor bit */
enum TD_STS_BIT {
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER)
	TD_TACT = 0x80000000,
#else
	TD_TACT = 0x7fffffff,
#endif
	TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
	TD_TFP0 = 0x10000000,
};
#define TDF1ST	TD_TFP1
#define TDFEND	TD_TFP0
#define TD_TFP	(TD_TFP1|TD_TFP0)

/* RMCR */
enum RECV_RST_BIT { RMCR_RST = 0x01, };
/* ECMR */
enum FELIC_MODE_BIT {
#if defined(SH_ETH_TYPE_GETHER)
	ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000,
	ECMR_RZPF = 0x00100000,
#endif
	ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
	ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
	ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
	ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
	ECMR_PRM = 0x00000001,
#ifdef CONFIG_CPU_SH7724
	ECMR_RTM = 0x00000010,
#endif

};

#if defined(SH_ETH_TYPE_GETHER)
#define ECMR_CHG_DM	(ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \
						ECMR_TXF | ECMR_MCT)
#elif defined(SH_ETH_TYPE_ETHER)
#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
#else
#define ECMR_CHG_DM	(ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
#endif

/* ECSR */
enum ECSR_STATUS_BIT {
#if defined(SH_ETH_TYPE_ETHER)
	ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
#endif
	ECSR_LCHNG = 0x04,
	ECSR_MPD = 0x02, ECSR_ICD = 0x01,
};

#if defined(SH_ETH_TYPE_GETHER)
# define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
#else
# define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
			ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP)
#endif

/* ECSIPR */
enum ECSIPR_STATUS_MASK_BIT {
#if defined(SH_ETH_TYPE_ETHER)
	ECSIPR_BRCRXIP = 0x20,
	ECSIPR_PSRTOIP = 0x10,
#elif defined(SH_ETY_TYPE_GETHER)
	ECSIPR_PSRTOIP = 0x10,
	ECSIPR_PHYIP = 0x08,
#endif
	ECSIPR_LCHNGIP = 0x04,
	ECSIPR_MPDIP = 0x02,
	ECSIPR_ICDIP = 0x01,
};

#if defined(SH_ETH_TYPE_GETHER)
# define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
#else
# define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
				ECSIPR_ICDIP | ECSIPR_MPDIP)
#endif

/* APR */
enum APR_BIT {
	APR_AP = 0x00000004,
};

/* MPR */
enum MPR_BIT {
	MPR_MP = 0x00000006,
};

/* TRSCER */
enum DESC_I_BIT {
	DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
	DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
	DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
	DESC_I_RINT1 = 0x0001,
};

/* RPADIR */
enum RPADIR_BIT {
	RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
	RPADIR_PADR = 0x0003f,
};

#if defined(SH_ETH_TYPE_GETHER)
# define RPADIR_INIT (0x00)
#else
# define RPADIR_INIT (RPADIR_PADS1)
#endif

/* FDR */
enum FIFO_SIZE_BIT {
	FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
};

static inline unsigned long sh_eth_reg_addr(struct sh_eth_dev *eth,
					    int enum_index)
{
#if defined(SH_ETH_TYPE_GETHER)
	const u16 *reg_offset = sh_eth_offset_gigabit;
#elif defined(SH_ETH_TYPE_ETHER)
	const u16 *reg_offset = sh_eth_offset_fast_sh4;
#else
#error
#endif
	return BASE_IO_ADDR + reg_offset[enum_index] + 0x800 * eth->port;
}

static inline void sh_eth_write(struct sh_eth_dev *eth, unsigned long data,
				int enum_index)
{
	outl(data, sh_eth_reg_addr(eth, enum_index));
}

static inline unsigned long sh_eth_read(struct sh_eth_dev *eth,
					int enum_index)
{
	return inl(sh_eth_reg_addr(eth, enum_index));
}
Commit	Line	Data
9751ee09	1	/*
903de461	2	* sh_eth.h - Driver for Renesas SuperH ethernet controler.
9751ee09	3	*
dcd5a593 NI	4	* Copyright (C) 2008 - 2012 Renesas Solutions Corp.
dcd5a593 NI	5	* Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu
9751ee09 NI	6	* Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	21	*/
	22
bd3980cc	23	#include <netdev.h>
9751ee09 NI	24	#include <asm/types.h>
	25
	26	#define SHETHER_NAME "sh_eth"
	27
dcd5a593	28	#if defined(CONFIG_SH)
9751ee09 NI	29	/* Malloc returns addresses in the P1 area (cacheable). However we need to
	30	use area P2 (non-cacheable) */
	31	#define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) \| 0xa0000000))
	32
	33	/* The ethernet controller needs to use physical addresses */
903de461 YS	34	#if defined(CONFIG_SH_32BIT)
	35	#define ADDR_TO_PHY(addr) ((((int)(addr) & ~0xe0000000) \| 0x40000000))
	36	#else
9751ee09	37	#define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000)
903de461	38	#endif
dcd5a593 NI	39	#elif defined(CONFIG_ARM)
	40	#define inl readl
	41	#define outl writel
	42	#define ADDR_TO_PHY(addr) ((int)(addr))
	43	#define ADDR_TO_P2(addr) (addr)
	44	#endif /* defined(CONFIG_SH) */
9751ee09 NI	45
	46	/* Number of supported ports */
	47	#define MAX_PORT_NUM 2
	48
	49	/* Buffers must be big enough to hold the largest ethernet frame. Also, rx
	50	buffers must be a multiple of 32 bytes */
	51	#define MAX_BUF_SIZE (48 * 32)
	52
	53	/* The number of tx descriptors must be large enough to point to 5 or more
	54	frames. If each frame uses 2 descriptors, at least 10 descriptors are needed.
	55	We use one descriptor per frame */
	56	#define NUM_TX_DESC 8
	57
	58	/* The size of the tx descriptor is determined by how much padding is used.
	59	4, 20, or 52 bytes of padding can be used */
	60	#define TX_DESC_PADDING 4
	61	#define TX_DESC_SIZE (12 + TX_DESC_PADDING)
	62
bd3980cc	63	/* Tx descriptor. We always use 3 bytes of padding */
9751ee09 NI	64	struct tx_desc_s {
	65	volatile u32 td0;
	66	u32 td1;
	67	u32 td2; /* Buffer start */
	68	u32 padding;
	69	};
	70
	71	/* There is no limitation in the number of rx descriptors */
	72	#define NUM_RX_DESC 8
	73
	74	/* The size of the rx descriptor is determined by how much padding is used.
	75	4, 20, or 52 bytes of padding can be used */
	76	#define RX_DESC_PADDING 4
	77	#define RX_DESC_SIZE (12 + RX_DESC_PADDING)
	78
	79	/* Rx descriptor. We always use 4 bytes of padding */
	80	struct rx_desc_s {
	81	volatile u32 rd0;
	82	volatile u32 rd1;
	83	u32 rd2; /* Buffer start */
	84	u32 padding;
	85	};
	86
bd3980cc	87	struct sh_eth_info {
9751ee09 NI	88	struct tx_desc_s *tx_desc_malloc;
	89	struct tx_desc_s *tx_desc_base;
	90	struct tx_desc_s *tx_desc_cur;
	91	struct rx_desc_s *rx_desc_malloc;
	92	struct rx_desc_s *rx_desc_base;
	93	struct rx_desc_s *rx_desc_cur;
	94	u8 *rx_buf_malloc;
	95	u8 *rx_buf_base;
	96	u8 mac_addr[6];
	97	u8 phy_addr;
bd3980cc	98	struct eth_device *dev;
bd1024b0	99	struct phy_device *phydev;
9751ee09 NI	100	};
9751ee09 NI	101
bd3980cc	102	struct sh_eth_dev {
9751ee09	103	int port;
bd3980cc	104	struct sh_eth_info port_info[MAX_PORT_NUM];
9751ee09 NI	105	};
9751ee09 NI	106
49afb8ca YS	107	/* from linux/drivers/net/ethernet/renesas/sh_eth.h */
	108	enum {
	109	/* E-DMAC registers */
	110	EDSR = 0,
	111	EDMR,
	112	EDTRR,
	113	EDRRR,
	114	EESR,
	115	EESIPR,
	116	TDLAR,
	117	TDFAR,
	118	TDFXR,
	119	TDFFR,
	120	RDLAR,
	121	RDFAR,
	122	RDFXR,
	123	RDFFR,
	124	TRSCER,
	125	RMFCR,
	126	TFTR,
	127	FDR,
	128	RMCR,
	129	EDOCR,
	130	TFUCR,
	131	RFOCR,
	132	FCFTR,
	133	RPADIR,
	134	TRIMD,
	135	RBWAR,
	136	TBRAR,
	137
	138	/* Ether registers */
	139	ECMR,
	140	ECSR,
	141	ECSIPR,
	142	PIR,
	143	PSR,
	144	RDMLR,
	145	PIPR,
	146	RFLR,
	147	IPGR,
	148	APR,
	149	MPR,
	150	PFTCR,
	151	PFRCR,
	152	RFCR,
	153	RFCF,
	154	TPAUSER,
	155	TPAUSECR,
	156	BCFR,
	157	BCFRR,
	158	GECMR,
	159	BCULR,
	160	MAHR,
	161	MALR,
	162	TROCR,
	163	CDCR,
	164	LCCR,
	165	CNDCR,
	166	CEFCR,
	167	FRECR,
	168	TSFRCR,
	169	TLFRCR,
	170	CERCR,
171	CEECR,
172	MAFCR,
173	RTRATE,
174	CSMR,
175	RMII_MII,
176
177	/* This value must be written at last. */
178	SH_ETH_MAX_REGISTER_OFFSET,
179	};
180
181	static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
182	[EDSR] = 0x0000,
183	[EDMR] = 0x0400,
184	[EDTRR] = 0x0408,
185	[EDRRR] = 0x0410,
186	[EESR] = 0x0428,
187	[EESIPR] = 0x0430,
188	[TDLAR] = 0x0010,
189	[TDFAR] = 0x0014,
190	[TDFXR] = 0x0018,
191	[TDFFR] = 0x001c,
192	[RDLAR] = 0x0030,
193	[RDFAR] = 0x0034,
194	[RDFXR] = 0x0038,
195	[RDFFR] = 0x003c,
196	[TRSCER] = 0x0438,
197	[RMFCR] = 0x0440,
198	[TFTR] = 0x0448,
199	[FDR] = 0x0450,
200	[RMCR] = 0x0458,
201	[RPADIR] = 0x0460,
202	[FCFTR] = 0x0468,
203	[CSMR] = 0x04E4,
204
205	[ECMR] = 0x0500,
206	[ECSR] = 0x0510,
207	[ECSIPR] = 0x0518,
208	[PIR] = 0x0520,
209	[PSR] = 0x0528,
210	[PIPR] = 0x052c,
211	[RFLR] = 0x0508,
212	[APR] = 0x0554,
213	[MPR] = 0x0558,
214	[PFTCR] = 0x055c,
215	[PFRCR] = 0x0560,
216	[TPAUSER] = 0x0564,
217	[GECMR] = 0x05b0,
218	[BCULR] = 0x05b4,
219	[MAHR] = 0x05c0,
220	[MALR] = 0x05c8,
221	[TROCR] = 0x0700,
222	[CDCR] = 0x0708,
223	[LCCR] = 0x0710,
224	[CEFCR] = 0x0740,
225	[FRECR] = 0x0748,
226	[TSFRCR] = 0x0750,
227	[TLFRCR] = 0x0758,
228	[RFCR] = 0x0760,
229	[CERCR] = 0x0768,
230	[CEECR] = 0x0770,
231	[MAFCR] = 0x0778,
232	[RMII_MII] = 0x0790,
233	};
234
235	static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
236	[ECMR] = 0x0100,
237	[RFLR] = 0x0108,
238	[ECSR] = 0x0110,
239	[ECSIPR] = 0x0118,
240	[PIR] = 0x0120,
241	[PSR] = 0x0128,
242	[RDMLR] = 0x0140,
243	[IPGR] = 0x0150,
244	[APR] = 0x0154,
245	[MPR] = 0x0158,
246	[TPAUSER] = 0x0164,
247	[RFCF] = 0x0160,
248	[TPAUSECR] = 0x0168,
249	[BCFRR] = 0x016c,
250	[MAHR] = 0x01c0,
251	[MALR] = 0x01c8,
252	[TROCR] = 0x01d0,
253	[CDCR] = 0x01d4,
254	[LCCR] = 0x01d8,
255	[CNDCR] = 0x01dc,
256	[CEFCR] = 0x01e4,
257	[FRECR] = 0x01e8,
258	[TSFRCR] = 0x01ec,
259	[TLFRCR] = 0x01f0,
260	[RFCR] = 0x01f4,
261	[MAFCR] = 0x01f8,
262	[RTRATE] = 0x01fc,
263
264	[EDMR] = 0x0000,
265	[EDTRR] = 0x0008,
266	[EDRRR] = 0x0010,
267	[TDLAR] = 0x0018,
268	[RDLAR] = 0x0020,
269	[EESR] = 0x0028,
270	[EESIPR] = 0x0030,
271	[TRSCER] = 0x0038,
272	[RMFCR] = 0x0040,
273	[TFTR] = 0x0048,
274	[FDR] = 0x0050,
275	[RMCR] = 0x0058,
276	[TFUCR] = 0x0064,
277	[RFOCR] = 0x0068,
278	[FCFTR] = 0x0070,
279	[RPADIR] = 0x0078,
280	[TRIMD] = 0x007c,
281	[RBWAR] = 0x00c8,
282	[RDFAR] = 0x00cc,
283	[TBRAR] = 0x00d4,
284	[TDFAR] = 0x00d8,
285	};
286
9751ee09	287	/* Register Address */
49afb8ca	288	#if defined(CONFIG_CPU_SH7763) \|\| defined(CONFIG_CPU_SH7734)
26235093	289	#define SH_ETH_TYPE_GETHER
9751ee09	290	#define BASE_IO_ADDR 0xfee00000
903de461	291	#elif defined(CONFIG_CPU_SH7757)
631fea8f YS	292	#if defined(CONFIG_SH_ETHER_USE_GETHER)
	293	#define SH_ETH_TYPE_GETHER
	294	#define BASE_IO_ADDR 0xfee00000
	295	#else
26235093	296	#define SH_ETH_TYPE_ETHER
903de461	297	#define BASE_IO_ADDR 0xfef00000
631fea8f	298	#endif
3bb4cc31	299	#elif defined(CONFIG_CPU_SH7724)
26235093	300	#define SH_ETH_TYPE_ETHER
3bb4cc31	301	#define BASE_IO_ADDR 0xA4600000
dcd5a593 NI	302	#elif defined(CONFIG_R8A7740)
	303	#define SH_ETH_TYPE_GETHER
	304	#define BASE_IO_ADDR 0xE9A00000
903de461 YS	305	#endif
903de461 YS	306
9751ee09 NI	307	/*
	308	* Register's bits
	309	* Copy from Linux driver source code
	310	*/
26235093	311	#if defined(SH_ETH_TYPE_GETHER)
9751ee09 NI	312	/* EDSR */
	313	enum EDSR_BIT {
	314	EDSR_ENT = 0x01, EDSR_ENR = 0x02,
	315	};
	316	#define EDSR_ENALL (EDSR_ENT\|EDSR_ENR)
	317	#endif
	318
	319	/* EDMR */
	320	enum DMAC_M_BIT {
	321	EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
26235093	322	#if defined(SH_ETH_TYPE_GETHER)
ee6ec5d4	323	EDMR_SRST = 0x03, /* Receive/Send reset */
9751ee09 NI	324	EMDR_DESC_R = 0x30, /* Descriptor reserve size */
9751ee09 NI	325	EDMR_EL = 0x40, /* Litte endian */
26235093	326	#elif defined(SH_ETH_TYPE_ETHER)
903de461 YS	327	EDMR_SRST = 0x01,
	328	EMDR_DESC_R = 0x30, /* Descriptor reserve size */
	329	EDMR_EL = 0x40, /* Litte endian */
26235093	330	#else
9751ee09 NI	331	EDMR_SRST = 0x01,
	332	#endif
	333	};
	334
	335	/* RFLR */
	336	#define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */
	337
	338	/* EDTRR */
	339	enum DMAC_T_BIT {
26235093	340	#if defined(SH_ETH_TYPE_GETHER)
9751ee09 NI	341	EDTRR_TRNS = 0x03,
	342	#else
	343	EDTRR_TRNS = 0x01,
	344	#endif
	345	};
	346
	347	/* GECMR */
	348	enum GECMR_BIT {
631fea8f YS	349	#if defined(CONFIG_CPU_SH7757)
	350	GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00,
	351	#else
09fcc8b5	352	GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,
631fea8f	353	#endif
9751ee09 NI	354	};
	355
	356	/* EDRRR*/
	357	enum EDRRR_R_BIT {
	358	EDRRR_R = 0x01,
	359	};
	360
	361	/* TPAUSER */
	362	enum TPAUSER_BIT {
	363	TPAUSER_TPAUSE = 0x0000ffff,
	364	TPAUSER_UNLIMITED = 0,
	365	};
	366
	367	/* BCFR */
	368	enum BCFR_BIT {
	369	BCFR_RPAUSE = 0x0000ffff,
	370	BCFR_UNLIMITED = 0,
	371	};
	372
	373	/* PIR */
	374	enum PIR_BIT {
	375	PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
	376	};
	377
	378	/* PSR */
	379	enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
	380
	381	/* EESR */
	382	enum EESR_BIT {
ee6ec5d4	383
26235093	384	#if defined(SH_ETH_TYPE_ETHER)
9751ee09 NI	385	EESR_TWB = 0x40000000,
	386	#else
	387	EESR_TWB = 0xC0000000,
	388	EESR_TC1 = 0x20000000,
	389	EESR_TUC = 0x10000000,
	390	EESR_ROC = 0x80000000,
	391	#endif
	392	EESR_TABT = 0x04000000,
	393	EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
26235093	394	#if defined(SH_ETH_TYPE_ETHER)
9751ee09 NI	395	EESR_ADE = 0x00800000,
	396	#endif
	397	EESR_ECI = 0x00400000,
	398	EESR_FTC = 0x00200000, EESR_TDE = 0x00100000,
	399	EESR_TFE = 0x00080000, EESR_FRC = 0x00040000,
	400	EESR_RDE = 0x00020000, EESR_RFE = 0x00010000,
26235093	401	#if defined(SH_ETH_TYPE_ETHER)
9751ee09 NI	402	EESR_CND = 0x00000800,
	403	#endif
	404	EESR_DLC = 0x00000400,
	405	EESR_CD = 0x00000200, EESR_RTO = 0x00000100,
	406	EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
	407	EESR_CELF = 0x00000020, EESR_RRF = 0x00000010,
	408	rESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
	409	EESR_PRE = 0x00000002, EESR_CERF = 0x00000001,
	410	};
	411
	412
26235093	413	#if defined(SH_ETH_TYPE_GETHER)
9751ee09 NI	414	# define TX_CHECK (EESR_TC1 \| EESR_FTC)
	415	# define EESR_ERR_CHECK (EESR_TWB \| EESR_TABT \| EESR_RABT \| EESR_RDE \
	416	\| EESR_RFRMER \| EESR_TFE \| EESR_TDE \| EESR_ECI)
	417	# define TX_ERROR_CEHCK (EESR_TWB \| EESR_TABT \| EESR_TDE \| EESR_TFE)
	418
	419	#else
	420	# define TX_CHECK (EESR_FTC \| EESR_CND \| EESR_DLC \| EESR_CD \| EESR_RTO)
	421	# define EESR_ERR_CHECK (EESR_TWB \| EESR_TABT \| EESR_RABT \| EESR_RDE \
	422	\| EESR_RFRMER \| EESR_ADE \| EESR_TFE \| EESR_TDE \| EESR_ECI)
	423	# define TX_ERROR_CEHCK (EESR_TWB \| EESR_TABT \| EESR_ADE \| EESR_TDE \| EESR_TFE)
	424	#endif
	425
	426	/* EESIPR */
	427	enum DMAC_IM_BIT {
	428	DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
	429	DMAC_M_RABT = 0x02000000,
	430	DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
	431	DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
	432	DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
	433	DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
	434	DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
	435	DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
	436	DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
	437	DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
	438	DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
	439	DMAC_M_RINT1 = 0x00000001,
	440	};
	441
	442	/* Receive descriptor bit */
	443	enum RD_STS_BIT {
	444	RD_RACT = 0x80000000, RD_RDLE = 0x40000000,
	445	RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
	446	RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
	447	RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
	448	RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
	449	RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
	450	RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
	451	RD_RFS1 = 0x00000001,
	452	};
	453	#define RDF1ST RD_RFP1
	454	#define RDFEND RD_RFP0
	455	#define RD_RFP (RD_RFP1\|RD_RFP0)
	456
	457	/* RDFFR*/
	458	enum RDFFR_BIT {
	459	RDFFR_RDLF = 0x01,
	460	};
	461
	462	/* FCFTR */
	463	enum FCFTR_BIT {
	464	FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
	465	FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
	466	FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
	467	};
	468	#define FIFO_F_D_RFF (FCFTR_RFF2\|FCFTR_RFF1\|FCFTR_RFF0)
	469	#define FIFO_F_D_RFD (FCFTR_RFD2\|FCFTR_RFD1\|FCFTR_RFD0)
	470
	471	/* Transfer descriptor bit */
	472	enum TD_STS_BIT {
26235093	473	#if defined(SH_ETH_TYPE_GETHER) \|\| defined(SH_ETH_TYPE_ETHER)
9751ee09 NI	474	TD_TACT = 0x80000000,
	475	#else
	476	TD_TACT = 0x7fffffff,
	477	#endif
	478	TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
	479	TD_TFP0 = 0x10000000,
	480	};
	481	#define TDF1ST TD_TFP1
	482	#define TDFEND TD_TFP0
	483	#define TD_TFP (TD_TFP1\|TD_TFP0)
	484
	485	/* RMCR */
	486	enum RECV_RST_BIT { RMCR_RST = 0x01, };
	487	/* ECMR */
	488	enum FELIC_MODE_BIT {
26235093	489	#if defined(SH_ETH_TYPE_GETHER)
9751ee09 NI	490	ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000,
	491	ECMR_RZPF = 0x00100000,
	492	#endif
	493	ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
	494	ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
	495	ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
	496	ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
	497	ECMR_PRM = 0x00000001,
3bb4cc31 NI	498	#ifdef CONFIG_CPU_SH7724
	499	ECMR_RTM = 0x00000010,
	500	#endif
	501
9751ee09 NI	502	};
9751ee09 NI	503
26235093	504	#if defined(SH_ETH_TYPE_GETHER)
9751ee09 NI	505	#define ECMR_CHG_DM (ECMR_TRCCM \| ECMR_RZPF \| ECMR_ZPF \| ECMR_PFR \| ECMR_RXF \| \
9751ee09 NI	506	ECMR_TXF \| ECMR_MCT)
26235093	507	#elif defined(SH_ETH_TYPE_ETHER)
3bb4cc31	508	#define ECMR_CHG_DM (ECMR_ZPF \| ECMR_PFR \| ECMR_RXF \| ECMR_TXF)
9751ee09	509	#else
903de461	510	#define ECMR_CHG_DM (ECMR_ZPF \| ECMR_PFR \| ECMR_RXF \| ECMR_TXF \| ECMR_MCT)
9751ee09 NI	511	#endif
	512
	513	/* ECSR */
	514	enum ECSR_STATUS_BIT {
26235093	515	#if defined(SH_ETH_TYPE_ETHER)
9751ee09 NI	516	ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
	517	#endif
	518	ECSR_LCHNG = 0x04,
	519	ECSR_MPD = 0x02, ECSR_ICD = 0x01,
	520	};
	521
26235093	522	#if defined(SH_ETH_TYPE_GETHER)
9751ee09 NI	523	# define ECSR_INIT (ECSR_ICD \| ECSIPR_MPDIP)
	524	#else
	525	# define ECSR_INIT (ECSR_BRCRX \| ECSR_PSRTO \| \
	526	ECSR_LCHNG \| ECSR_ICD \| ECSIPR_MPDIP)
	527	#endif
	528
	529	/* ECSIPR */
	530	enum ECSIPR_STATUS_MASK_BIT {
26235093	531	#if defined(SH_ETH_TYPE_ETHER)
a6616efb	532	ECSIPR_BRCRXIP = 0x20,
ee6ec5d4	533	ECSIPR_PSRTOIP = 0x10,
26235093	534	#elif defined(SH_ETY_TYPE_GETHER)
ee6ec5d4 NI	535	ECSIPR_PSRTOIP = 0x10,
ee6ec5d4 NI	536	ECSIPR_PHYIP = 0x08,
a6616efb	537	#endif
9751ee09	538	ECSIPR_LCHNGIP = 0x04,
ee6ec5d4 NI	539	ECSIPR_MPDIP = 0x02,
ee6ec5d4 NI	540	ECSIPR_ICDIP = 0x01,
9751ee09 NI	541	};
9751ee09 NI	542
26235093	543	#if defined(SH_ETH_TYPE_GETHER)
9751ee09 NI	544	# define ECSIPR_INIT (ECSIPR_LCHNGIP \| ECSIPR_ICDIP \| ECSIPR_MPDIP)
	545	#else
	546	# define ECSIPR_INIT (ECSIPR_BRCRXIP \| ECSIPR_PSRTOIP \| ECSIPR_LCHNGIP \| \
	547	ECSIPR_ICDIP \| ECSIPR_MPDIP)
	548	#endif
	549
	550	/* APR */
	551	enum APR_BIT {
	552	APR_AP = 0x00000004,
	553	};
	554
	555	/* MPR */
	556	enum MPR_BIT {
	557	MPR_MP = 0x00000006,
	558	};
	559
	560	/* TRSCER */
	561	enum DESC_I_BIT {
	562	DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
	563	DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
	564	DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
	565	DESC_I_RINT1 = 0x0001,
	566	};
	567
	568	/* RPADIR */
	569	enum RPADIR_BIT {
	570	RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
	571	RPADIR_PADR = 0x0003f,
	572	};
	573
26235093	574	#if defined(SH_ETH_TYPE_GETHER)
9751ee09 NI	575	# define RPADIR_INIT (0x00)
	576	#else
	577	# define RPADIR_INIT (RPADIR_PADS1)
	578	#endif
	579
	580	/* FDR */
	581	enum FIFO_SIZE_BIT {
	582	FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
	583	};
49afb8ca YS	584
	585	static inline unsigned long sh_eth_reg_addr(struct sh_eth_dev *eth,
	586	int enum_index)
	587	{
	588	#if defined(SH_ETH_TYPE_GETHER)
	589	const u16 *reg_offset = sh_eth_offset_gigabit;
	590	#elif defined(SH_ETH_TYPE_ETHER)
	591	const u16 *reg_offset = sh_eth_offset_fast_sh4;
	592	#else
	593	#error
	594	#endif
	595	return BASE_IO_ADDR + reg_offset[enum_index] + 0x800 * eth->port;
	596	}
	597
	598	static inline void sh_eth_write(struct sh_eth_dev *eth, unsigned long data,
	599	int enum_index)
	600	{
	601	outl(data, sh_eth_reg_addr(eth, enum_index));
	602	}
	603
	604	static inline unsigned long sh_eth_read(struct sh_eth_dev *eth,
	605	int enum_index)
	606	{
	607	return inl(sh_eth_reg_addr(eth, enum_index));
	608	}