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fe8c2806 WD |
1 | /*------------------------------------------------------------------------ |
2 | . smc91111.c | |
3 | . This is a driver for SMSC's 91C111 single-chip Ethernet device. | |
4 | . | |
5 | . (C) Copyright 2002 | |
6 | . Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
7 | . Rolf Offermanns <rof@sysgo.de> | |
8 | . | |
9 | . Copyright (C) 2001 Standard Microsystems Corporation (SMSC) | |
42dfe7a1 | 10 | . Developed by Simple Network Magic Corporation (SNMC) |
fe8c2806 WD |
11 | . Copyright (C) 1996 by Erik Stahlman (ES) |
12 | . | |
13 | . This program is free software; you can redistribute it and/or modify | |
14 | . it under the terms of the GNU General Public License as published by | |
15 | . the Free Software Foundation; either version 2 of the License, or | |
16 | . (at your option) any later version. | |
17 | . | |
18 | . This program is distributed in the hope that it will be useful, | |
19 | . but WITHOUT ANY WARRANTY; without even the implied warranty of | |
42dfe7a1 | 20 | . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
fe8c2806 WD |
21 | . GNU General Public License for more details. |
22 | . | |
23 | . You should have received a copy of the GNU General Public License | |
24 | . along with this program; if not, write to the Free Software | |
42dfe7a1 | 25 | . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
fe8c2806 WD |
26 | . |
27 | . Information contained in this file was obtained from the LAN91C111 | |
28 | . manual from SMC. To get a copy, if you really want one, you can find | |
29 | . information under www.smsc.com. | |
30 | . | |
31 | . | |
32 | . "Features" of the SMC chip: | |
33 | . Integrated PHY/MAC for 10/100BaseT Operation | |
34 | . Supports internal and external MII | |
35 | . Integrated 8K packet memory | |
36 | . EEPROM interface for configuration | |
37 | . | |
38 | . Arguments: | |
42dfe7a1 | 39 | . io = for the base address |
fe8c2806 WD |
40 | . irq = for the IRQ |
41 | . | |
42 | . author: | |
42dfe7a1 WD |
43 | . Erik Stahlman ( erik@vt.edu ) |
44 | . Daris A Nevil ( dnevil@snmc.com ) | |
fe8c2806 WD |
45 | . |
46 | . | |
47 | . Hardware multicast code from Peter Cammaert ( pc@denkart.be ) | |
48 | . | |
49 | . Sources: | |
42dfe7a1 WD |
50 | . o SMSC LAN91C111 databook (www.smsc.com) |
51 | . o smc9194.c by Erik Stahlman | |
52 | . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov ) | |
fe8c2806 WD |
53 | . |
54 | . History: | |
42dfe7a1 | 55 | . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks. |
fe8c2806 | 56 | . 10/17/01 Marco Hasewinkel Modify for DNP/1110 |
42dfe7a1 WD |
57 | . 07/25/01 Woojung Huh Modify for ADS Bitsy |
58 | . 04/25/01 Daris A Nevil Initial public release through SMSC | |
59 | . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111 | |
fe8c2806 WD |
60 | ----------------------------------------------------------------------------*/ |
61 | ||
62 | #include <common.h> | |
63 | #include <command.h> | |
f39748ae | 64 | #include <config.h> |
7194ab80 | 65 | #include <malloc.h> |
fe8c2806 WD |
66 | #include "smc91111.h" |
67 | #include <net.h> | |
68 | ||
fe8c2806 WD |
69 | /* Use power-down feature of the chip */ |
70 | #define POWER_DOWN 0 | |
71 | ||
72 | #define NO_AUTOPROBE | |
73 | ||
0be248fa | 74 | #define SMC_DEBUG 0 |
8bf3b005 WD |
75 | |
76 | #if SMC_DEBUG > 1 | |
fe8c2806 WD |
77 | static const char version[] = |
78 | "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n"; | |
8bf3b005 | 79 | #endif |
fe8c2806 | 80 | |
f39748ae WD |
81 | /* Autonegotiation timeout in seconds */ |
82 | #ifndef CONFIG_SMC_AUTONEG_TIMEOUT | |
83 | #define CONFIG_SMC_AUTONEG_TIMEOUT 10 | |
84 | #endif | |
85 | ||
fe8c2806 WD |
86 | /*------------------------------------------------------------------------ |
87 | . | |
88 | . Configuration options, for the experienced user to change. | |
89 | . | |
90 | -------------------------------------------------------------------------*/ | |
91 | ||
92 | /* | |
93 | . Wait time for memory to be free. This probably shouldn't be | |
94 | . tuned that much, as waiting for this means nothing else happens | |
95 | . in the system | |
96 | */ | |
97 | #define MEMORY_WAIT_TIME 16 | |
98 | ||
99 | ||
100 | #if (SMC_DEBUG > 2 ) | |
101 | #define PRINTK3(args...) printf(args) | |
102 | #else | |
103 | #define PRINTK3(args...) | |
104 | #endif | |
105 | ||
106 | #if SMC_DEBUG > 1 | |
107 | #define PRINTK2(args...) printf(args) | |
108 | #else | |
109 | #define PRINTK2(args...) | |
110 | #endif | |
111 | ||
112 | #ifdef SMC_DEBUG | |
113 | #define PRINTK(args...) printf(args) | |
114 | #else | |
115 | #define PRINTK(args...) | |
116 | #endif | |
117 | ||
118 | ||
119 | /*------------------------------------------------------------------------ | |
120 | . | |
42dfe7a1 | 121 | . The internal workings of the driver. If you are changing anything |
fe8c2806 WD |
122 | . here with the SMC stuff, you should have the datasheet and know |
123 | . what you are doing. | |
124 | . | |
125 | -------------------------------------------------------------------------*/ | |
fe8c2806 WD |
126 | |
127 | /* Memory sizing constant */ | |
128 | #define LAN91C111_MEMORY_MULTIPLIER (1024*2) | |
129 | ||
130 | #ifndef CONFIG_SMC91111_BASE | |
7194ab80 BW |
131 | #error "SMC91111 Base address must be passed to initialization funciton" |
132 | /* #define CONFIG_SMC91111_BASE 0x20000300 */ | |
fe8c2806 WD |
133 | #endif |
134 | ||
fe8c2806 WD |
135 | #define SMC_DEV_NAME "SMC91111" |
136 | #define SMC_PHY_ADDR 0x0000 | |
137 | #define SMC_ALLOC_MAX_TRY 5 | |
138 | #define SMC_TX_TIMEOUT 30 | |
139 | ||
140 | #define SMC_PHY_CLOCK_DELAY 1000 | |
141 | ||
142 | #define ETH_ZLEN 60 | |
143 | ||
42dfe7a1 | 144 | #ifdef CONFIG_SMC_USE_32_BIT |
fe8c2806 WD |
145 | #define USE_32_BIT 1 |
146 | #else | |
147 | #undef USE_32_BIT | |
148 | #endif | |
fe8c2806 | 149 | |
0afe519a | 150 | #ifdef SHARED_RESOURCES |
7194ab80 BW |
151 | extern void swap_to(int device_id); |
152 | #else | |
153 | # define swap_to(x) | |
0afe519a | 154 | #endif |
fe8c2806 | 155 | |
fe8c2806 | 156 | #ifndef CONFIG_SMC91111_EXT_PHY |
7194ab80 | 157 | static void smc_phy_configure(struct eth_device *dev); |
fe8c2806 WD |
158 | #endif /* !CONFIG_SMC91111_EXT_PHY */ |
159 | ||
fe8c2806 WD |
160 | /* |
161 | ------------------------------------------------------------ | |
162 | . | |
163 | . Internal routines | |
164 | . | |
165 | ------------------------------------------------------------ | |
166 | */ | |
167 | ||
c3c7f861 WD |
168 | #ifdef CONFIG_SMC_USE_IOFUNCS |
169 | /* | |
170 | * input and output functions | |
171 | * | |
172 | * Implemented due to inx,outx macros accessing the device improperly | |
173 | * and putting the device into an unkown state. | |
174 | * | |
175 | * For instance, on Sharp LPD7A400 SDK, affects were chip memory | |
176 | * could not be free'd (hence the alloc failures), duplicate packets, | |
177 | * packets being corrupt (shifted) on the wire, etc. Switching to the | |
178 | * inx,outx functions fixed this problem. | |
179 | */ | |
c3c7f861 WD |
180 | |
181 | #define barrier() __asm__ __volatile__("": : :"memory") | |
182 | ||
7194ab80 | 183 | static inline word SMC_inw(struct eth_device *dev, dword offset) |
c3c7f861 WD |
184 | { |
185 | word v; | |
7194ab80 | 186 | v = *((volatile word*)(dev->iobase + offset)); |
c3c7f861 WD |
187 | barrier(); *(volatile u32*)(0xc0000000); |
188 | return v; | |
189 | } | |
190 | ||
7194ab80 | 191 | static inline void SMC_outw(struct eth_device *dev, word value, dword offset) |
c3c7f861 | 192 | { |
7194ab80 | 193 | *((volatile word*)(dev->iobase + offset)) = value; |
c3c7f861 WD |
194 | barrier(); *(volatile u32*)(0xc0000000); |
195 | } | |
196 | ||
7194ab80 | 197 | static inline byte SMC_inb(struct eth_device *dev, dword offset) |
c3c7f861 WD |
198 | { |
199 | word _w; | |
200 | ||
7194ab80 | 201 | _w = SMC_inw(dev, offset & ~((dword)1)); |
c3c7f861 WD |
202 | return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w); |
203 | } | |
204 | ||
7194ab80 | 205 | static inline void SMC_outb(struct eth_device *dev, byte value, dword offset) |
c3c7f861 WD |
206 | { |
207 | word _w; | |
208 | ||
7194ab80 | 209 | _w = SMC_inw(dev, offset & ~((dword)1)); |
c3c7f861 | 210 | if (offset & 1) |
7194ab80 BW |
211 | *((volatile word*)(dev->iobase + (offset & ~((dword)1)))) = |
212 | (value<<8) | (_w & 0x00ff); | |
c3c7f861 | 213 | else |
7194ab80 BW |
214 | *((volatile word*)(dev->iobase + offset)) = |
215 | value | (_w & 0xff00); | |
c3c7f861 WD |
216 | } |
217 | ||
7194ab80 BW |
218 | static inline void SMC_insw(struct eth_device *dev, dword offset, |
219 | volatile uchar* buf, dword len) | |
c3c7f861 | 220 | { |
d52fb7e3 WD |
221 | volatile word *p = (volatile word *)buf; |
222 | ||
c3c7f861 | 223 | while (len-- > 0) { |
7194ab80 | 224 | *p++ = SMC_inw(dev, offset); |
d52fb7e3 WD |
225 | barrier(); |
226 | *((volatile u32*)(0xc0000000)); | |
c3c7f861 WD |
227 | } |
228 | } | |
229 | ||
7194ab80 BW |
230 | static inline void SMC_outsw(struct eth_device *dev, dword offset, |
231 | uchar* buf, dword len) | |
c3c7f861 | 232 | { |
d52fb7e3 WD |
233 | volatile word *p = (volatile word *)buf; |
234 | ||
c3c7f861 | 235 | while (len-- > 0) { |
7194ab80 | 236 | SMC_outw(dev, *p++, offset); |
d52fb7e3 WD |
237 | barrier(); |
238 | *(volatile u32*)(0xc0000000); | |
c3c7f861 WD |
239 | } |
240 | } | |
241 | #endif /* CONFIG_SMC_USE_IOFUNCS */ | |
242 | ||
fe8c2806 WD |
243 | /* |
244 | . A rather simple routine to print out a packet for debugging purposes. | |
245 | */ | |
246 | #if SMC_DEBUG > 2 | |
247 | static void print_packet( byte *, int ); | |
248 | #endif | |
249 | ||
250 | #define tx_done(dev) 1 | |
251 | ||
7194ab80 | 252 | static int poll4int (struct eth_device *dev, byte mask, int timeout) |
b56ddc63 | 253 | { |
6d0f6bcf | 254 | int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ; |
b56ddc63 | 255 | int is_timeout = 0; |
7194ab80 | 256 | word old_bank = SMC_inw (dev, BSR_REG); |
b56ddc63 WD |
257 | |
258 | PRINTK2 ("Polling...\n"); | |
7194ab80 BW |
259 | SMC_SELECT_BANK (dev, 2); |
260 | while ((SMC_inw (dev, SMC91111_INT_REG) & mask) == 0) { | |
b56ddc63 WD |
261 | if (get_timer (0) >= tmo) { |
262 | is_timeout = 1; | |
263 | break; | |
264 | } | |
fe8c2806 | 265 | } |
fe8c2806 | 266 | |
b56ddc63 | 267 | /* restore old bank selection */ |
7194ab80 | 268 | SMC_SELECT_BANK (dev, old_bank); |
fe8c2806 | 269 | |
b56ddc63 WD |
270 | if (is_timeout) |
271 | return 1; | |
272 | else | |
273 | return 0; | |
fe8c2806 WD |
274 | } |
275 | ||
487778b7 | 276 | /* Only one release command at a time, please */ |
7194ab80 | 277 | static inline void smc_wait_mmu_release_complete (struct eth_device *dev) |
487778b7 WD |
278 | { |
279 | int count = 0; | |
b56ddc63 | 280 | |
487778b7 | 281 | /* assume bank 2 selected */ |
7194ab80 | 282 | while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { |
b56ddc63 WD |
283 | udelay (1); /* Wait until not busy */ |
284 | if (++count > 200) | |
285 | break; | |
487778b7 WD |
286 | } |
287 | } | |
288 | ||
fe8c2806 WD |
289 | /* |
290 | . Function: smc_reset( void ) | |
291 | . Purpose: | |
42dfe7a1 WD |
292 | . This sets the SMC91111 chip to its normal state, hopefully from whatever |
293 | . mess that any other DOS driver has put it in. | |
fe8c2806 WD |
294 | . |
295 | . Maybe I should reset more registers to defaults in here? SOFTRST should | |
296 | . do that for me. | |
297 | . | |
298 | . Method: | |
299 | . 1. send a SOFT RESET | |
300 | . 2. wait for it to finish | |
301 | . 3. enable autorelease mode | |
302 | . 4. reset the memory management unit | |
303 | . 5. clear all interrupts | |
304 | . | |
305 | */ | |
7194ab80 | 306 | static void smc_reset (struct eth_device *dev) |
fe8c2806 | 307 | { |
f39748ae | 308 | PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME); |
fe8c2806 WD |
309 | |
310 | /* This resets the registers mostly to defaults, but doesn't | |
311 | affect EEPROM. That seems unnecessary */ | |
7194ab80 BW |
312 | SMC_SELECT_BANK (dev, 0); |
313 | SMC_outw (dev, RCR_SOFTRST, RCR_REG); | |
fe8c2806 WD |
314 | |
315 | /* Setup the Configuration Register */ | |
316 | /* This is necessary because the CONFIG_REG is not affected */ | |
317 | /* by a soft reset */ | |
318 | ||
7194ab80 | 319 | SMC_SELECT_BANK (dev, 1); |
fe8c2806 | 320 | #if defined(CONFIG_SMC91111_EXT_PHY) |
7194ab80 | 321 | SMC_outw (dev, CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG); |
fe8c2806 | 322 | #else |
7194ab80 | 323 | SMC_outw (dev, CONFIG_DEFAULT, CONFIG_REG); |
fe8c2806 WD |
324 | #endif |
325 | ||
326 | ||
327 | /* Release from possible power-down state */ | |
328 | /* Configuration register is not affected by Soft Reset */ | |
7194ab80 BW |
329 | SMC_outw (dev, SMC_inw (dev, CONFIG_REG) | CONFIG_EPH_POWER_EN, |
330 | CONFIG_REG); | |
fe8c2806 | 331 | |
7194ab80 | 332 | SMC_SELECT_BANK (dev, 0); |
fe8c2806 WD |
333 | |
334 | /* this should pause enough for the chip to be happy */ | |
b56ddc63 | 335 | udelay (10); |
fe8c2806 WD |
336 | |
337 | /* Disable transmit and receive functionality */ | |
7194ab80 BW |
338 | SMC_outw (dev, RCR_CLEAR, RCR_REG); |
339 | SMC_outw (dev, TCR_CLEAR, TCR_REG); | |
fe8c2806 WD |
340 | |
341 | /* set the control register */ | |
7194ab80 BW |
342 | SMC_SELECT_BANK (dev, 1); |
343 | SMC_outw (dev, CTL_DEFAULT, CTL_REG); | |
fe8c2806 WD |
344 | |
345 | /* Reset the MMU */ | |
7194ab80 BW |
346 | SMC_SELECT_BANK (dev, 2); |
347 | smc_wait_mmu_release_complete (dev); | |
348 | SMC_outw (dev, MC_RESET, MMU_CMD_REG); | |
349 | while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) | |
b56ddc63 | 350 | udelay (1); /* Wait until not busy */ |
fe8c2806 WD |
351 | |
352 | /* Note: It doesn't seem that waiting for the MMU busy is needed here, | |
353 | but this is a place where future chipsets _COULD_ break. Be wary | |
8bde7f77 | 354 | of issuing another MMU command right after this */ |
fe8c2806 WD |
355 | |
356 | /* Disable all interrupts */ | |
7194ab80 | 357 | SMC_outb (dev, 0, IM_REG); |
fe8c2806 WD |
358 | } |
359 | ||
360 | /* | |
361 | . Function: smc_enable | |
362 | . Purpose: let the chip talk to the outside work | |
363 | . Method: | |
364 | . 1. Enable the transmitter | |
365 | . 2. Enable the receiver | |
366 | . 3. Enable interrupts | |
367 | */ | |
7194ab80 | 368 | static void smc_enable(struct eth_device *dev) |
fe8c2806 | 369 | { |
f39748ae | 370 | PRINTK2("%s: smc_enable\n", SMC_DEV_NAME); |
7194ab80 | 371 | SMC_SELECT_BANK( dev, 0 ); |
fe8c2806 | 372 | /* see the header file for options in TCR/RCR DEFAULT*/ |
7194ab80 BW |
373 | SMC_outw( dev, TCR_DEFAULT, TCR_REG ); |
374 | SMC_outw( dev, RCR_DEFAULT, RCR_REG ); | |
fe8c2806 WD |
375 | |
376 | /* clear MII_DIS */ | |
377 | /* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */ | |
378 | } | |
379 | ||
380 | /* | |
7194ab80 | 381 | . Function: smc_halt |
fe8c2806 WD |
382 | . Purpose: closes down the SMC91xxx chip. |
383 | . Method: | |
384 | . 1. zero the interrupt mask | |
385 | . 2. clear the enable receive flag | |
386 | . 3. clear the enable xmit flags | |
387 | . | |
388 | . TODO: | |
389 | . (1) maybe utilize power down mode. | |
390 | . Why not yet? Because while the chip will go into power down mode, | |
391 | . the manual says that it will wake up in response to any I/O requests | |
42dfe7a1 | 392 | . in the register space. Empirical results do not show this working. |
fe8c2806 | 393 | */ |
7194ab80 | 394 | static void smc_halt(struct eth_device *dev) |
fe8c2806 | 395 | { |
7194ab80 | 396 | PRINTK2("%s: smc_halt\n", SMC_DEV_NAME); |
fe8c2806 WD |
397 | |
398 | /* no more interrupts for me */ | |
7194ab80 BW |
399 | SMC_SELECT_BANK( dev, 2 ); |
400 | SMC_outb( dev, 0, IM_REG ); | |
fe8c2806 WD |
401 | |
402 | /* and tell the card to stay away from that nasty outside world */ | |
7194ab80 BW |
403 | SMC_SELECT_BANK( dev, 0 ); |
404 | SMC_outb( dev, RCR_CLEAR, RCR_REG ); | |
405 | SMC_outb( dev, TCR_CLEAR, TCR_REG ); | |
406 | ||
0afe519a | 407 | swap_to(FLASH); |
fe8c2806 WD |
408 | } |
409 | ||
410 | ||
411 | /* | |
7194ab80 | 412 | . Function: smc_send(struct net_device * ) |
fe8c2806 WD |
413 | . Purpose: |
414 | . This sends the actual packet to the SMC9xxx chip. | |
415 | . | |
416 | . Algorithm: | |
42dfe7a1 | 417 | . First, see if a saved_skb is available. |
fe8c2806 WD |
418 | . ( this should NOT be called if there is no 'saved_skb' |
419 | . Now, find the packet number that the chip allocated | |
420 | . Point the data pointers at it in memory | |
421 | . Set the length word in the chip's memory | |
422 | . Dump the packet to chip memory | |
423 | . Check if a last byte is needed ( odd length packet ) | |
424 | . if so, set the control flag right | |
42dfe7a1 | 425 | . Tell the card to send it |
fe8c2806 | 426 | . Enable the transmit interrupt, so I know if it failed |
42dfe7a1 | 427 | . Free the kernel data if I actually sent it. |
fe8c2806 | 428 | */ |
7194ab80 BW |
429 | static int smc_send(struct eth_device *dev, volatile void *packet, |
430 | int packet_length) | |
fe8c2806 | 431 | { |
b56ddc63 | 432 | byte packet_no; |
b56ddc63 WD |
433 | byte *buf; |
434 | int length; | |
435 | int numPages; | |
436 | int try = 0; | |
437 | int time_out; | |
438 | byte status; | |
518e2e1a WD |
439 | byte saved_pnr; |
440 | word saved_ptr; | |
fe8c2806 | 441 | |
518e2e1a | 442 | /* save PTR and PNR registers before manipulation */ |
7194ab80 BW |
443 | SMC_SELECT_BANK (dev, 2); |
444 | saved_pnr = SMC_inb( dev, PN_REG ); | |
445 | saved_ptr = SMC_inw( dev, PTR_REG ); | |
fe8c2806 | 446 | |
f39748ae | 447 | PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME); |
fe8c2806 WD |
448 | |
449 | length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN; | |
450 | ||
451 | /* allocate memory | |
b56ddc63 WD |
452 | ** The MMU wants the number of pages to be the number of 256 bytes |
453 | ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) ) | |
454 | ** | |
455 | ** The 91C111 ignores the size bits, but the code is left intact | |
456 | ** for backwards and future compatibility. | |
457 | ** | |
458 | ** Pkt size for allocating is data length +6 (for additional status | |
459 | ** words, length and ctl!) | |
460 | ** | |
461 | ** If odd size then last byte is included in this header. | |
462 | */ | |
463 | numPages = ((length & 0xfffe) + 6); | |
464 | numPages >>= 8; /* Divide by 256 */ | |
465 | ||
466 | if (numPages > 7) { | |
467 | printf ("%s: Far too big packet error. \n", SMC_DEV_NAME); | |
fe8c2806 WD |
468 | return 0; |
469 | } | |
470 | ||
471 | /* now, try to allocate the memory */ | |
7194ab80 BW |
472 | SMC_SELECT_BANK (dev, 2); |
473 | SMC_outw (dev, MC_ALLOC | numPages, MMU_CMD_REG); | |
fe8c2806 | 474 | |
dc7c9a1a | 475 | /* FIXME: the ALLOC_INT bit never gets set * |
42dfe7a1 WD |
476 | * so the following will always give a * |
477 | * memory allocation error. * | |
478 | * same code works in armboot though * | |
dc7c9a1a WD |
479 | * -ro |
480 | */ | |
481 | ||
fe8c2806 WD |
482 | again: |
483 | try++; | |
484 | time_out = MEMORY_WAIT_TIME; | |
485 | do { | |
7194ab80 | 486 | status = SMC_inb (dev, SMC91111_INT_REG); |
b56ddc63 | 487 | if (status & IM_ALLOC_INT) { |
fe8c2806 | 488 | /* acknowledge the interrupt */ |
7194ab80 | 489 | SMC_outb (dev, IM_ALLOC_INT, SMC91111_INT_REG); |
8bde7f77 | 490 | break; |
fe8c2806 | 491 | } |
b56ddc63 WD |
492 | } while (--time_out); |
493 | ||
494 | if (!time_out) { | |
495 | PRINTK2 ("%s: memory allocation, try %d failed ...\n", | |
496 | SMC_DEV_NAME, try); | |
497 | if (try < SMC_ALLOC_MAX_TRY) | |
498 | goto again; | |
499 | else | |
500 | return 0; | |
fe8c2806 WD |
501 | } |
502 | ||
b56ddc63 WD |
503 | PRINTK2 ("%s: memory allocation, try %d succeeded ...\n", |
504 | SMC_DEV_NAME, try); | |
fe8c2806 | 505 | |
b56ddc63 | 506 | buf = (byte *) packet; |
fe8c2806 WD |
507 | |
508 | /* If I get here, I _know_ there is a packet slot waiting for me */ | |
7194ab80 | 509 | packet_no = SMC_inb (dev, AR_REG); |
b56ddc63 | 510 | if (packet_no & AR_FAILED) { |
fe8c2806 | 511 | /* or isn't there? BAD CHIP! */ |
b56ddc63 | 512 | printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME); |
fe8c2806 WD |
513 | return 0; |
514 | } | |
515 | ||
516 | /* we have a packet address, so tell the card to use it */ | |
1f6d4258 | 517 | #ifndef CONFIG_XAENIAX |
7194ab80 | 518 | SMC_outb (dev, packet_no, PN_REG); |
1f6d4258 WD |
519 | #else |
520 | /* On Xaeniax board, we can't use SMC_outb here because that way | |
521 | * the Allocate MMU command will end up written to the command register | |
522 | * as well, which will lead to a problem. | |
523 | */ | |
7194ab80 | 524 | SMC_outl (dev, packet_no << 16, 0); |
1f6d4258 | 525 | #endif |
b79a11cc WD |
526 | /* do not write new ptr value if Write data fifo not empty */ |
527 | while ( saved_ptr & PTR_NOTEMPTY ) | |
518e2e1a WD |
528 | printf ("Write data fifo not empty!\n"); |
529 | ||
fe8c2806 | 530 | /* point to the beginning of the packet */ |
7194ab80 | 531 | SMC_outw (dev, PTR_AUTOINC, PTR_REG); |
fe8c2806 | 532 | |
b56ddc63 WD |
533 | PRINTK3 ("%s: Trying to xmit packet of length %x\n", |
534 | SMC_DEV_NAME, length); | |
fe8c2806 WD |
535 | |
536 | #if SMC_DEBUG > 2 | |
b56ddc63 WD |
537 | printf ("Transmitting Packet\n"); |
538 | print_packet (buf, length); | |
fe8c2806 WD |
539 | #endif |
540 | ||
541 | /* send the packet length ( +6 for status, length and ctl byte ) | |
8bde7f77 | 542 | and the status word ( set to zeros ) */ |
fe8c2806 | 543 | #ifdef USE_32_BIT |
7194ab80 | 544 | SMC_outl (dev, (length + 6) << 16, SMC91111_DATA_REG); |
fe8c2806 | 545 | #else |
7194ab80 | 546 | SMC_outw (dev, 0, SMC91111_DATA_REG); |
b56ddc63 | 547 | /* send the packet length ( +6 for status words, length, and ctl */ |
7194ab80 | 548 | SMC_outw (dev, (length + 6), SMC91111_DATA_REG); |
fe8c2806 WD |
549 | #endif |
550 | ||
551 | /* send the actual data | |
b56ddc63 WD |
552 | . I _think_ it's faster to send the longs first, and then |
553 | . mop up by sending the last word. It depends heavily | |
42dfe7a1 | 554 | . on alignment, at least on the 486. Maybe it would be |
b56ddc63 WD |
555 | . a good idea to check which is optimal? But that could take |
556 | . almost as much time as is saved? | |
557 | */ | |
fe8c2806 | 558 | #ifdef USE_32_BIT |
7194ab80 | 559 | SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2); |
bb310d46 | 560 | #ifndef CONFIG_XAENIAX |
b56ddc63 | 561 | if (length & 0x2) |
7194ab80 | 562 | SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))), |
b56ddc63 | 563 | SMC91111_DATA_REG); |
bb310d46 WD |
564 | #else |
565 | /* On XANEIAX, we can only use 32-bit writes, so we need to handle | |
566 | * unaligned tail part specially. The standard code doesn't work. | |
567 | */ | |
568 | if ((length & 3) == 3) { | |
569 | u16 * ptr = (u16*) &buf[length-3]; | |
7194ab80 | 570 | SMC_outl(dev, (*ptr) | ((0x2000 | buf[length-1]) << 16), |
bb310d46 WD |
571 | SMC91111_DATA_REG); |
572 | } else if ((length & 2) == 2) { | |
573 | u16 * ptr = (u16*) &buf[length-2]; | |
7194ab80 | 574 | SMC_outl(dev, *ptr, SMC91111_DATA_REG); |
bb310d46 | 575 | } else if (length & 1) { |
7194ab80 | 576 | SMC_outl(dev, (0x2000 | buf[length-1]), SMC91111_DATA_REG); |
bb310d46 | 577 | } else { |
7194ab80 | 578 | SMC_outl(dev, 0, SMC91111_DATA_REG); |
bb310d46 WD |
579 | } |
580 | #endif | |
fe8c2806 | 581 | #else |
7194ab80 | 582 | SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1); |
fe8c2806 WD |
583 | #endif /* USE_32_BIT */ |
584 | ||
bb310d46 | 585 | #ifndef CONFIG_XAENIAX |
42dfe7a1 | 586 | /* Send the last byte, if there is one. */ |
b56ddc63 | 587 | if ((length & 1) == 0) { |
7194ab80 | 588 | SMC_outw (dev, 0, SMC91111_DATA_REG); |
fe8c2806 | 589 | } else { |
7194ab80 | 590 | SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG); |
fe8c2806 | 591 | } |
bb310d46 | 592 | #endif |
fe8c2806 WD |
593 | |
594 | /* and let the chipset deal with it */ | |
7194ab80 | 595 | SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG); |
fe8c2806 WD |
596 | |
597 | /* poll for TX INT */ | |
7194ab80 | 598 | /* if (poll4int (dev, IM_TX_INT, SMC_TX_TIMEOUT)) { */ |
518e2e1a | 599 | /* poll for TX_EMPTY INT - autorelease enabled */ |
7194ab80 | 600 | if (poll4int(dev, IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) { |
fe8c2806 | 601 | /* sending failed */ |
b56ddc63 | 602 | PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME); |
fe8c2806 WD |
603 | |
604 | /* release packet */ | |
518e2e1a | 605 | /* no need to release, MMU does that now */ |
1f6d4258 | 606 | #ifdef CONFIG_XAENIAX |
7194ab80 | 607 | SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG); |
1f6d4258 | 608 | #endif |
fe8c2806 | 609 | |
8bde7f77 | 610 | /* wait for MMU getting ready (low) */ |
7194ab80 | 611 | while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { |
b56ddc63 | 612 | udelay (10); |
8bde7f77 | 613 | } |
fe8c2806 | 614 | |
b56ddc63 | 615 | PRINTK2 ("MMU ready\n"); |
fe8c2806 WD |
616 | |
617 | ||
618 | return 0; | |
619 | } else { | |
620 | /* ack. int */ | |
7194ab80 | 621 | SMC_outb (dev, IM_TX_EMPTY_INT, SMC91111_INT_REG); |
518e2e1a | 622 | /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */ |
b56ddc63 WD |
623 | PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME, |
624 | length); | |
fe8c2806 WD |
625 | |
626 | /* release packet */ | |
518e2e1a | 627 | /* no need to release, MMU does that now */ |
1f6d4258 | 628 | #ifdef CONFIG_XAENIAX |
7194ab80 | 629 | SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG); |
1f6d4258 | 630 | #endif |
fe8c2806 | 631 | |
8bde7f77 | 632 | /* wait for MMU getting ready (low) */ |
7194ab80 | 633 | while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { |
b56ddc63 | 634 | udelay (10); |
8bde7f77 | 635 | } |
fe8c2806 | 636 | |
b56ddc63 | 637 | PRINTK2 ("MMU ready\n"); |
fe8c2806 WD |
638 | |
639 | ||
640 | } | |
641 | ||
518e2e1a | 642 | /* restore previously saved registers */ |
1f6d4258 | 643 | #ifndef CONFIG_XAENIAX |
7194ab80 | 644 | SMC_outb( dev, saved_pnr, PN_REG ); |
1f6d4258 WD |
645 | #else |
646 | /* On Xaeniax board, we can't use SMC_outb here because that way | |
647 | * the Allocate MMU command will end up written to the command register | |
648 | * as well, which will lead to a problem. | |
649 | */ | |
7194ab80 | 650 | SMC_outl(dev, saved_pnr << 16, 0); |
1f6d4258 | 651 | #endif |
7194ab80 | 652 | SMC_outw( dev, saved_ptr, PTR_REG ); |
518e2e1a | 653 | |
fe8c2806 WD |
654 | return length; |
655 | } | |
656 | ||
fe8c2806 WD |
657 | /* |
658 | * Open and Initialize the board | |
659 | * | |
660 | * Set up everything, reset the card, etc .. | |
661 | * | |
662 | */ | |
7194ab80 | 663 | static int smc_init(struct eth_device *dev, bd_t *bd) |
fe8c2806 | 664 | { |
7194ab80 | 665 | int i; |
fe8c2806 | 666 | |
7194ab80 BW |
667 | swap_to(ETHERNET); |
668 | ||
669 | PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME); | |
fe8c2806 WD |
670 | |
671 | /* reset the hardware */ | |
7194ab80 BW |
672 | smc_reset (dev); |
673 | smc_enable (dev); | |
fe8c2806 WD |
674 | |
675 | /* Configure the PHY */ | |
676 | #ifndef CONFIG_SMC91111_EXT_PHY | |
7194ab80 | 677 | smc_phy_configure (dev); |
fe8c2806 WD |
678 | #endif |
679 | ||
fe8c2806 | 680 | /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */ |
7194ab80 BW |
681 | /* SMC_SELECT_BANK(dev, 0); */ |
682 | /* SMC_outw(dev, 0, RPC_REG); */ | |
683 | SMC_SELECT_BANK (dev, 1); | |
487778b7 | 684 | |
fe8c2806 | 685 | #ifdef USE_32_BIT |
b56ddc63 | 686 | for (i = 0; i < 6; i += 2) { |
fe8c2806 WD |
687 | word address; |
688 | ||
7194ab80 BW |
689 | address = dev->enetaddr[i + 1] << 8; |
690 | address |= dev->enetaddr[i]; | |
691 | SMC_outw(dev, address, (ADDR0_REG + i)); | |
fe8c2806 WD |
692 | } |
693 | #else | |
b56ddc63 | 694 | for (i = 0; i < 6; i++) |
7194ab80 | 695 | SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i)); |
fe8c2806 WD |
696 | #endif |
697 | ||
7194ab80 BW |
698 | printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr); |
699 | ||
fe8c2806 WD |
700 | return 0; |
701 | } | |
702 | ||
fe8c2806 WD |
703 | /*------------------------------------------------------------- |
704 | . | |
705 | . smc_rcv - receive a packet from the card | |
706 | . | |
707 | . There is ( at least ) a packet waiting to be read from | |
708 | . chip-memory. | |
709 | . | |
710 | . o Read the status | |
711 | . o If an error, record it | |
712 | . o otherwise, read in the packet | |
713 | -------------------------------------------------------------- | |
714 | */ | |
7194ab80 | 715 | static int smc_rcv(struct eth_device *dev) |
fe8c2806 | 716 | { |
42dfe7a1 | 717 | int packet_number; |
fe8c2806 WD |
718 | word status; |
719 | word packet_length; | |
42dfe7a1 | 720 | int is_error = 0; |
fe8c2806 WD |
721 | #ifdef USE_32_BIT |
722 | dword stat_len; | |
723 | #endif | |
518e2e1a WD |
724 | byte saved_pnr; |
725 | word saved_ptr; | |
fe8c2806 | 726 | |
7194ab80 | 727 | SMC_SELECT_BANK(dev, 2); |
518e2e1a | 728 | /* save PTR and PTR registers */ |
7194ab80 BW |
729 | saved_pnr = SMC_inb( dev, PN_REG ); |
730 | saved_ptr = SMC_inw( dev, PTR_REG ); | |
518e2e1a | 731 | |
7194ab80 | 732 | packet_number = SMC_inw( dev, RXFIFO_REG ); |
fe8c2806 WD |
733 | |
734 | if ( packet_number & RXFIFO_REMPTY ) { | |
735 | ||
736 | return 0; | |
737 | } | |
738 | ||
f39748ae | 739 | PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME); |
fe8c2806 | 740 | /* start reading from the start of the packet */ |
7194ab80 | 741 | SMC_outw( dev, PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG ); |
fe8c2806 WD |
742 | |
743 | /* First two words are status and packet_length */ | |
744 | #ifdef USE_32_BIT | |
7194ab80 | 745 | stat_len = SMC_inl(dev, SMC91111_DATA_REG); |
fe8c2806 WD |
746 | status = stat_len & 0xffff; |
747 | packet_length = stat_len >> 16; | |
748 | #else | |
7194ab80 BW |
749 | status = SMC_inw( dev, SMC91111_DATA_REG ); |
750 | packet_length = SMC_inw( dev, SMC91111_DATA_REG ); | |
fe8c2806 WD |
751 | #endif |
752 | ||
753 | packet_length &= 0x07ff; /* mask off top bits */ | |
754 | ||
755 | PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length ); | |
756 | ||
757 | if ( !(status & RS_ERRORS ) ){ | |
758 | /* Adjust for having already read the first two words */ | |
759 | packet_length -= 4; /*4; */ | |
760 | ||
761 | ||
fe8c2806 WD |
762 | /* set odd length for bug in LAN91C111, */ |
763 | /* which never sets RS_ODDFRAME */ | |
764 | /* TODO ? */ | |
765 | ||
766 | ||
767 | #ifdef USE_32_BIT | |
768 | PRINTK3(" Reading %d dwords (and %d bytes) \n", | |
769 | packet_length >> 2, packet_length & 3 ); | |
770 | /* QUESTION: Like in the TX routine, do I want | |
771 | to send the DWORDs or the bytes first, or some | |
772 | mixture. A mixture might improve already slow PIO | |
42dfe7a1 | 773 | performance */ |
7194ab80 BW |
774 | SMC_insl( dev, SMC91111_DATA_REG, NetRxPackets[0], |
775 | packet_length >> 2 ); | |
fe8c2806 WD |
776 | /* read the left over bytes */ |
777 | if (packet_length & 3) { | |
778 | int i; | |
779 | ||
7194ab80 BW |
780 | byte *tail = (byte *)(NetRxPackets[0] + |
781 | (packet_length & ~3)); | |
782 | dword leftover = SMC_inl(dev, SMC91111_DATA_REG); | |
fe8c2806 WD |
783 | for (i=0; i<(packet_length & 3); i++) |
784 | *tail++ = (byte) (leftover >> (8*i)) & 0xff; | |
785 | } | |
786 | #else | |
787 | PRINTK3(" Reading %d words and %d byte(s) \n", | |
788 | (packet_length >> 1 ), packet_length & 1 ); | |
7194ab80 BW |
789 | SMC_insw(dev, SMC91111_DATA_REG , NetRxPackets[0], |
790 | packet_length >> 1); | |
fe8c2806 WD |
791 | |
792 | #endif /* USE_32_BIT */ | |
793 | ||
794 | #if SMC_DEBUG > 2 | |
795 | printf("Receiving Packet\n"); | |
796 | print_packet( NetRxPackets[0], packet_length ); | |
797 | #endif | |
798 | } else { | |
799 | /* error ... */ | |
800 | /* TODO ? */ | |
801 | is_error = 1; | |
802 | } | |
803 | ||
7194ab80 | 804 | while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY ) |
fe8c2806 WD |
805 | udelay(1); /* Wait until not busy */ |
806 | ||
807 | /* error or good, tell the card to get rid of this packet */ | |
7194ab80 | 808 | SMC_outw( dev, MC_RELEASE, MMU_CMD_REG ); |
fe8c2806 | 809 | |
7194ab80 | 810 | while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY ) |
fe8c2806 WD |
811 | udelay(1); /* Wait until not busy */ |
812 | ||
518e2e1a | 813 | /* restore saved registers */ |
1f6d4258 | 814 | #ifndef CONFIG_XAENIAX |
7194ab80 | 815 | SMC_outb( dev, saved_pnr, PN_REG ); |
1f6d4258 WD |
816 | #else |
817 | /* On Xaeniax board, we can't use SMC_outb here because that way | |
818 | * the Allocate MMU command will end up written to the command register | |
819 | * as well, which will lead to a problem. | |
820 | */ | |
7194ab80 | 821 | SMC_outl( dev, saved_pnr << 16, 0); |
1f6d4258 | 822 | #endif |
7194ab80 | 823 | SMC_outw( dev, saved_ptr, PTR_REG ); |
518e2e1a | 824 | |
fe8c2806 WD |
825 | if (!is_error) { |
826 | /* Pass the packet up to the protocol layers. */ | |
827 | NetReceive(NetRxPackets[0], packet_length); | |
828 | return packet_length; | |
829 | } else { | |
830 | return 0; | |
831 | } | |
832 | ||
833 | } | |
834 | ||
835 | ||
fe8c2806 WD |
836 | #if 0 |
837 | /*------------------------------------------------------------ | |
838 | . Modify a bit in the LAN91C111 register set | |
839 | .-------------------------------------------------------------*/ | |
7194ab80 | 840 | static word smc_modify_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, |
fe8c2806 WD |
841 | unsigned int bit, int val) |
842 | { | |
843 | word regval; | |
844 | ||
7194ab80 | 845 | SMC_SELECT_BANK( dev, bank ); |
fe8c2806 | 846 | |
7194ab80 | 847 | regval = SMC_inw( dev, reg ); |
fe8c2806 WD |
848 | if (val) |
849 | regval |= bit; | |
850 | else | |
851 | regval &= ~bit; | |
852 | ||
7194ab80 | 853 | SMC_outw( dev, regval, 0 ); |
fe8c2806 WD |
854 | return(regval); |
855 | } | |
856 | ||
857 | ||
858 | /*------------------------------------------------------------ | |
859 | . Retrieve a bit in the LAN91C111 register set | |
860 | .-------------------------------------------------------------*/ | |
7194ab80 | 861 | static int smc_get_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, unsigned int bit) |
fe8c2806 | 862 | { |
7194ab80 BW |
863 | SMC_SELECT_BANK( dev, bank ); |
864 | if ( SMC_inw( dev, reg ) & bit) | |
fe8c2806 WD |
865 | return(1); |
866 | else | |
867 | return(0); | |
868 | } | |
869 | ||
870 | ||
871 | /*------------------------------------------------------------ | |
872 | . Modify a LAN91C111 register (word access only) | |
873 | .-------------------------------------------------------------*/ | |
7194ab80 | 874 | static void smc_modify_reg(struct eth_device *dev, int bank, int ioaddr, int reg, word val) |
fe8c2806 | 875 | { |
7194ab80 BW |
876 | SMC_SELECT_BANK( dev, bank ); |
877 | SMC_outw( dev, val, reg ); | |
fe8c2806 WD |
878 | } |
879 | ||
880 | ||
881 | /*------------------------------------------------------------ | |
882 | . Retrieve a LAN91C111 register (word access only) | |
883 | .-------------------------------------------------------------*/ | |
7194ab80 | 884 | static int smc_get_reg(struct eth_device *dev, int bank, int ioaddr, int reg) |
fe8c2806 | 885 | { |
7194ab80 BW |
886 | SMC_SELECT_BANK( dev, bank ); |
887 | return(SMC_inw( dev, reg )); | |
fe8c2806 WD |
888 | } |
889 | ||
890 | #endif /* 0 */ | |
891 | ||
892 | /*---PHY CONTROL AND CONFIGURATION----------------------------------------- */ | |
893 | ||
894 | #if (SMC_DEBUG > 2 ) | |
895 | ||
896 | /*------------------------------------------------------------ | |
897 | . Debugging function for viewing MII Management serial bitstream | |
898 | .-------------------------------------------------------------*/ | |
b56ddc63 | 899 | static void smc_dump_mii_stream (byte * bits, int size) |
fe8c2806 WD |
900 | { |
901 | int i; | |
902 | ||
b56ddc63 WD |
903 | printf ("BIT#:"); |
904 | for (i = 0; i < size; ++i) { | |
905 | printf ("%d", i % 10); | |
906 | } | |
fe8c2806 | 907 | |
b56ddc63 WD |
908 | printf ("\nMDOE:"); |
909 | for (i = 0; i < size; ++i) { | |
fe8c2806 | 910 | if (bits[i] & MII_MDOE) |
b56ddc63 | 911 | printf ("1"); |
fe8c2806 | 912 | else |
b56ddc63 WD |
913 | printf ("0"); |
914 | } | |
fe8c2806 | 915 | |
b56ddc63 WD |
916 | printf ("\nMDO :"); |
917 | for (i = 0; i < size; ++i) { | |
fe8c2806 | 918 | if (bits[i] & MII_MDO) |
b56ddc63 | 919 | printf ("1"); |
fe8c2806 | 920 | else |
b56ddc63 WD |
921 | printf ("0"); |
922 | } | |
fe8c2806 | 923 | |
b56ddc63 WD |
924 | printf ("\nMDI :"); |
925 | for (i = 0; i < size; ++i) { | |
fe8c2806 | 926 | if (bits[i] & MII_MDI) |
b56ddc63 | 927 | printf ("1"); |
fe8c2806 | 928 | else |
b56ddc63 WD |
929 | printf ("0"); |
930 | } | |
fe8c2806 | 931 | |
b56ddc63 | 932 | printf ("\n"); |
fe8c2806 WD |
933 | } |
934 | #endif | |
935 | ||
936 | /*------------------------------------------------------------ | |
937 | . Reads a register from the MII Management serial interface | |
938 | .-------------------------------------------------------------*/ | |
939 | #ifndef CONFIG_SMC91111_EXT_PHY | |
7194ab80 | 940 | static word smc_read_phy_register (struct eth_device *dev, byte phyreg) |
fe8c2806 WD |
941 | { |
942 | int oldBank; | |
943 | int i; | |
944 | byte mask; | |
945 | word mii_reg; | |
946 | byte bits[64]; | |
947 | int clk_idx = 0; | |
948 | int input_idx; | |
949 | word phydata; | |
950 | byte phyaddr = SMC_PHY_ADDR; | |
951 | ||
952 | /* 32 consecutive ones on MDO to establish sync */ | |
953 | for (i = 0; i < 32; ++i) | |
954 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
955 | ||
956 | /* Start code <01> */ | |
957 | bits[clk_idx++] = MII_MDOE; | |
958 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
959 | ||
960 | /* Read command <10> */ | |
961 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
962 | bits[clk_idx++] = MII_MDOE; | |
963 | ||
964 | /* Output the PHY address, msb first */ | |
b56ddc63 WD |
965 | mask = (byte) 0x10; |
966 | for (i = 0; i < 5; ++i) { | |
fe8c2806 WD |
967 | if (phyaddr & mask) |
968 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
969 | else | |
970 | bits[clk_idx++] = MII_MDOE; | |
971 | ||
972 | /* Shift to next lowest bit */ | |
973 | mask >>= 1; | |
b56ddc63 | 974 | } |
fe8c2806 WD |
975 | |
976 | /* Output the phy register number, msb first */ | |
b56ddc63 WD |
977 | mask = (byte) 0x10; |
978 | for (i = 0; i < 5; ++i) { | |
fe8c2806 WD |
979 | if (phyreg & mask) |
980 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
981 | else | |
982 | bits[clk_idx++] = MII_MDOE; | |
983 | ||
984 | /* Shift to next lowest bit */ | |
985 | mask >>= 1; | |
b56ddc63 | 986 | } |
fe8c2806 WD |
987 | |
988 | /* Tristate and turnaround (2 bit times) */ | |
989 | bits[clk_idx++] = 0; | |
990 | /*bits[clk_idx++] = 0; */ | |
991 | ||
992 | /* Input starts at this bit time */ | |
993 | input_idx = clk_idx; | |
994 | ||
995 | /* Will input 16 bits */ | |
996 | for (i = 0; i < 16; ++i) | |
997 | bits[clk_idx++] = 0; | |
998 | ||
999 | /* Final clock bit */ | |
1000 | bits[clk_idx++] = 0; | |
1001 | ||
1002 | /* Save the current bank */ | |
7194ab80 | 1003 | oldBank = SMC_inw (dev, BANK_SELECT); |
fe8c2806 WD |
1004 | |
1005 | /* Select bank 3 */ | |
7194ab80 | 1006 | SMC_SELECT_BANK (dev, 3); |
fe8c2806 WD |
1007 | |
1008 | /* Get the current MII register value */ | |
7194ab80 | 1009 | mii_reg = SMC_inw (dev, MII_REG); |
fe8c2806 WD |
1010 | |
1011 | /* Turn off all MII Interface bits */ | |
b56ddc63 | 1012 | mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO); |
fe8c2806 WD |
1013 | |
1014 | /* Clock all 64 cycles */ | |
b56ddc63 | 1015 | for (i = 0; i < sizeof bits; ++i) { |
fe8c2806 | 1016 | /* Clock Low - output data */ |
7194ab80 | 1017 | SMC_outw (dev, mii_reg | bits[i], MII_REG); |
b56ddc63 | 1018 | udelay (SMC_PHY_CLOCK_DELAY); |
fe8c2806 WD |
1019 | |
1020 | ||
1021 | /* Clock Hi - input data */ | |
7194ab80 | 1022 | SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG); |
b56ddc63 | 1023 | udelay (SMC_PHY_CLOCK_DELAY); |
7194ab80 | 1024 | bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI; |
b56ddc63 | 1025 | } |
fe8c2806 WD |
1026 | |
1027 | /* Return to idle state */ | |
1028 | /* Set clock to low, data to low, and output tristated */ | |
7194ab80 | 1029 | SMC_outw (dev, mii_reg, MII_REG); |
b56ddc63 | 1030 | udelay (SMC_PHY_CLOCK_DELAY); |
fe8c2806 WD |
1031 | |
1032 | /* Restore original bank select */ | |
7194ab80 | 1033 | SMC_SELECT_BANK (dev, oldBank); |
fe8c2806 WD |
1034 | |
1035 | /* Recover input data */ | |
1036 | phydata = 0; | |
b56ddc63 | 1037 | for (i = 0; i < 16; ++i) { |
fe8c2806 WD |
1038 | phydata <<= 1; |
1039 | ||
1040 | if (bits[input_idx++] & MII_MDI) | |
1041 | phydata |= 0x0001; | |
b56ddc63 | 1042 | } |
fe8c2806 WD |
1043 | |
1044 | #if (SMC_DEBUG > 2 ) | |
b56ddc63 | 1045 | printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n", |
fe8c2806 | 1046 | phyaddr, phyreg, phydata); |
b56ddc63 | 1047 | smc_dump_mii_stream (bits, sizeof bits); |
fe8c2806 WD |
1048 | #endif |
1049 | ||
b56ddc63 | 1050 | return (phydata); |
fe8c2806 WD |
1051 | } |
1052 | ||
1053 | ||
1054 | /*------------------------------------------------------------ | |
1055 | . Writes a register to the MII Management serial interface | |
1056 | .-------------------------------------------------------------*/ | |
7194ab80 BW |
1057 | static void smc_write_phy_register (struct eth_device *dev, byte phyreg, |
1058 | word phydata) | |
fe8c2806 WD |
1059 | { |
1060 | int oldBank; | |
1061 | int i; | |
1062 | word mask; | |
1063 | word mii_reg; | |
1064 | byte bits[65]; | |
1065 | int clk_idx = 0; | |
1066 | byte phyaddr = SMC_PHY_ADDR; | |
1067 | ||
1068 | /* 32 consecutive ones on MDO to establish sync */ | |
1069 | for (i = 0; i < 32; ++i) | |
1070 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1071 | ||
1072 | /* Start code <01> */ | |
1073 | bits[clk_idx++] = MII_MDOE; | |
1074 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1075 | ||
1076 | /* Write command <01> */ | |
1077 | bits[clk_idx++] = MII_MDOE; | |
1078 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1079 | ||
1080 | /* Output the PHY address, msb first */ | |
b56ddc63 WD |
1081 | mask = (byte) 0x10; |
1082 | for (i = 0; i < 5; ++i) { | |
fe8c2806 WD |
1083 | if (phyaddr & mask) |
1084 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1085 | else | |
1086 | bits[clk_idx++] = MII_MDOE; | |
1087 | ||
1088 | /* Shift to next lowest bit */ | |
1089 | mask >>= 1; | |
b56ddc63 | 1090 | } |
fe8c2806 WD |
1091 | |
1092 | /* Output the phy register number, msb first */ | |
b56ddc63 WD |
1093 | mask = (byte) 0x10; |
1094 | for (i = 0; i < 5; ++i) { | |
fe8c2806 WD |
1095 | if (phyreg & mask) |
1096 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1097 | else | |
1098 | bits[clk_idx++] = MII_MDOE; | |
1099 | ||
1100 | /* Shift to next lowest bit */ | |
1101 | mask >>= 1; | |
b56ddc63 | 1102 | } |
fe8c2806 WD |
1103 | |
1104 | /* Tristate and turnaround (2 bit times) */ | |
1105 | bits[clk_idx++] = 0; | |
1106 | bits[clk_idx++] = 0; | |
1107 | ||
1108 | /* Write out 16 bits of data, msb first */ | |
1109 | mask = 0x8000; | |
b56ddc63 | 1110 | for (i = 0; i < 16; ++i) { |
fe8c2806 WD |
1111 | if (phydata & mask) |
1112 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1113 | else | |
1114 | bits[clk_idx++] = MII_MDOE; | |
1115 | ||
1116 | /* Shift to next lowest bit */ | |
1117 | mask >>= 1; | |
b56ddc63 | 1118 | } |
fe8c2806 WD |
1119 | |
1120 | /* Final clock bit (tristate) */ | |
1121 | bits[clk_idx++] = 0; | |
1122 | ||
1123 | /* Save the current bank */ | |
7194ab80 | 1124 | oldBank = SMC_inw (dev, BANK_SELECT); |
fe8c2806 WD |
1125 | |
1126 | /* Select bank 3 */ | |
7194ab80 | 1127 | SMC_SELECT_BANK (dev, 3); |
fe8c2806 WD |
1128 | |
1129 | /* Get the current MII register value */ | |
7194ab80 | 1130 | mii_reg = SMC_inw (dev, MII_REG); |
fe8c2806 WD |
1131 | |
1132 | /* Turn off all MII Interface bits */ | |
b56ddc63 | 1133 | mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO); |
fe8c2806 WD |
1134 | |
1135 | /* Clock all cycles */ | |
b56ddc63 | 1136 | for (i = 0; i < sizeof bits; ++i) { |
fe8c2806 | 1137 | /* Clock Low - output data */ |
7194ab80 | 1138 | SMC_outw (dev, mii_reg | bits[i], MII_REG); |
b56ddc63 | 1139 | udelay (SMC_PHY_CLOCK_DELAY); |
fe8c2806 WD |
1140 | |
1141 | ||
1142 | /* Clock Hi - input data */ | |
7194ab80 | 1143 | SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG); |
b56ddc63 | 1144 | udelay (SMC_PHY_CLOCK_DELAY); |
7194ab80 | 1145 | bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI; |
b56ddc63 | 1146 | } |
fe8c2806 WD |
1147 | |
1148 | /* Return to idle state */ | |
1149 | /* Set clock to low, data to low, and output tristated */ | |
7194ab80 | 1150 | SMC_outw (dev, mii_reg, MII_REG); |
b56ddc63 | 1151 | udelay (SMC_PHY_CLOCK_DELAY); |
fe8c2806 WD |
1152 | |
1153 | /* Restore original bank select */ | |
7194ab80 | 1154 | SMC_SELECT_BANK (dev, oldBank); |
fe8c2806 WD |
1155 | |
1156 | #if (SMC_DEBUG > 2 ) | |
b56ddc63 | 1157 | printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n", |
fe8c2806 | 1158 | phyaddr, phyreg, phydata); |
b56ddc63 | 1159 | smc_dump_mii_stream (bits, sizeof bits); |
fe8c2806 WD |
1160 | #endif |
1161 | } | |
1162 | #endif /* !CONFIG_SMC91111_EXT_PHY */ | |
1163 | ||
1164 | ||
fe8c2806 WD |
1165 | /*------------------------------------------------------------ |
1166 | . Waits the specified number of milliseconds - kernel friendly | |
1167 | .-------------------------------------------------------------*/ | |
1168 | #ifndef CONFIG_SMC91111_EXT_PHY | |
1169 | static void smc_wait_ms(unsigned int ms) | |
1170 | { | |
1171 | udelay(ms*1000); | |
1172 | } | |
1173 | #endif /* !CONFIG_SMC91111_EXT_PHY */ | |
1174 | ||
1175 | ||
fe8c2806 WD |
1176 | /*------------------------------------------------------------ |
1177 | . Configures the specified PHY using Autonegotiation. Calls | |
1178 | . smc_phy_fixed() if the user has requested a certain config. | |
1179 | .-------------------------------------------------------------*/ | |
1180 | #ifndef CONFIG_SMC91111_EXT_PHY | |
7194ab80 | 1181 | static void smc_phy_configure (struct eth_device *dev) |
fe8c2806 WD |
1182 | { |
1183 | int timeout; | |
1184 | byte phyaddr; | |
b56ddc63 WD |
1185 | word my_phy_caps; /* My PHY capabilities */ |
1186 | word my_ad_caps; /* My Advertised capabilities */ | |
1187 | word status = 0; /*;my status = 0 */ | |
fe8c2806 WD |
1188 | int failed = 0; |
1189 | ||
f39748ae | 1190 | PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME); |
fe8c2806 WD |
1191 | |
1192 | ||
fe8c2806 WD |
1193 | /* Get the detected phy address */ |
1194 | phyaddr = SMC_PHY_ADDR; | |
1195 | ||
1196 | /* Reset the PHY, setting all other bits to zero */ | |
7194ab80 | 1197 | smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_RST); |
fe8c2806 WD |
1198 | |
1199 | /* Wait for the reset to complete, or time out */ | |
b56ddc63 WD |
1200 | timeout = 6; /* Wait up to 3 seconds */ |
1201 | while (timeout--) { | |
7194ab80 | 1202 | if (!(smc_read_phy_register (dev, PHY_CNTL_REG) |
b56ddc63 | 1203 | & PHY_CNTL_RST)) { |
fe8c2806 WD |
1204 | /* reset complete */ |
1205 | break; | |
fe8c2806 WD |
1206 | } |
1207 | ||
b56ddc63 WD |
1208 | smc_wait_ms (500); /* wait 500 millisecs */ |
1209 | } | |
1210 | ||
1211 | if (timeout < 1) { | |
1212 | printf ("%s:PHY reset timed out\n", SMC_DEV_NAME); | |
fe8c2806 | 1213 | goto smc_phy_configure_exit; |
b56ddc63 | 1214 | } |
fe8c2806 WD |
1215 | |
1216 | /* Read PHY Register 18, Status Output */ | |
1217 | /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */ | |
1218 | ||
1219 | /* Enable PHY Interrupts (for register 18) */ | |
1220 | /* Interrupts listed here are disabled */ | |
7194ab80 | 1221 | smc_write_phy_register (dev, PHY_MASK_REG, 0xffff); |
fe8c2806 WD |
1222 | |
1223 | /* Configure the Receive/Phy Control register */ | |
7194ab80 BW |
1224 | SMC_SELECT_BANK (dev, 0); |
1225 | SMC_outw (dev, RPC_DEFAULT, RPC_REG); | |
fe8c2806 WD |
1226 | |
1227 | /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */ | |
7194ab80 | 1228 | my_phy_caps = smc_read_phy_register (dev, PHY_STAT_REG); |
b56ddc63 | 1229 | my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */ |
fe8c2806 WD |
1230 | |
1231 | if (my_phy_caps & PHY_STAT_CAP_T4) | |
1232 | my_ad_caps |= PHY_AD_T4; | |
1233 | ||
1234 | if (my_phy_caps & PHY_STAT_CAP_TXF) | |
1235 | my_ad_caps |= PHY_AD_TX_FDX; | |
1236 | ||
1237 | if (my_phy_caps & PHY_STAT_CAP_TXH) | |
1238 | my_ad_caps |= PHY_AD_TX_HDX; | |
1239 | ||
1240 | if (my_phy_caps & PHY_STAT_CAP_TF) | |
1241 | my_ad_caps |= PHY_AD_10_FDX; | |
1242 | ||
1243 | if (my_phy_caps & PHY_STAT_CAP_TH) | |
1244 | my_ad_caps |= PHY_AD_10_HDX; | |
1245 | ||
1246 | /* Update our Auto-Neg Advertisement Register */ | |
7194ab80 | 1247 | smc_write_phy_register (dev, PHY_AD_REG, my_ad_caps); |
fe8c2806 | 1248 | |
518e2e1a WD |
1249 | /* Read the register back. Without this, it appears that when */ |
1250 | /* auto-negotiation is restarted, sometimes it isn't ready and */ | |
1251 | /* the link does not come up. */ | |
7194ab80 | 1252 | smc_read_phy_register(dev, PHY_AD_REG); |
518e2e1a | 1253 | |
f39748ae WD |
1254 | PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps); |
1255 | PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps); | |
fe8c2806 WD |
1256 | |
1257 | /* Restart auto-negotiation process in order to advertise my caps */ | |
7194ab80 | 1258 | smc_write_phy_register (dev, PHY_CNTL_REG, |
b56ddc63 | 1259 | PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST); |
fe8c2806 WD |
1260 | |
1261 | /* Wait for the auto-negotiation to complete. This may take from */ | |
1262 | /* 2 to 3 seconds. */ | |
1263 | /* Wait for the reset to complete, or time out */ | |
f39748ae | 1264 | timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2; |
b56ddc63 | 1265 | while (timeout--) { |
f39748ae | 1266 | |
7194ab80 | 1267 | status = smc_read_phy_register (dev, PHY_STAT_REG); |
b56ddc63 | 1268 | if (status & PHY_STAT_ANEG_ACK) { |
fe8c2806 WD |
1269 | /* auto-negotiate complete */ |
1270 | break; | |
b56ddc63 | 1271 | } |
fe8c2806 | 1272 | |
b56ddc63 | 1273 | smc_wait_ms (500); /* wait 500 millisecs */ |
fe8c2806 WD |
1274 | |
1275 | /* Restart auto-negotiation if remote fault */ | |
b56ddc63 | 1276 | if (status & PHY_STAT_REM_FLT) { |
f39748ae | 1277 | printf ("%s: PHY remote fault detected\n", |
b56ddc63 | 1278 | SMC_DEV_NAME); |
fe8c2806 WD |
1279 | |
1280 | /* Restart auto-negotiation */ | |
f39748ae | 1281 | printf ("%s: PHY restarting auto-negotiation\n", |
fe8c2806 | 1282 | SMC_DEV_NAME); |
7194ab80 | 1283 | smc_write_phy_register (dev, PHY_CNTL_REG, |
b56ddc63 WD |
1284 | PHY_CNTL_ANEG_EN | |
1285 | PHY_CNTL_ANEG_RST | | |
1286 | PHY_CNTL_SPEED | | |
1287 | PHY_CNTL_DPLX); | |
fe8c2806 | 1288 | } |
b56ddc63 | 1289 | } |
fe8c2806 | 1290 | |
b56ddc63 | 1291 | if (timeout < 1) { |
f39748ae | 1292 | printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME); |
fe8c2806 | 1293 | failed = 1; |
b56ddc63 | 1294 | } |
fe8c2806 WD |
1295 | |
1296 | /* Fail if we detected an auto-negotiate remote fault */ | |
b56ddc63 | 1297 | if (status & PHY_STAT_REM_FLT) { |
f39748ae | 1298 | printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME); |
fe8c2806 | 1299 | failed = 1; |
b56ddc63 | 1300 | } |
fe8c2806 WD |
1301 | |
1302 | /* Re-Configure the Receive/Phy Control register */ | |
7194ab80 | 1303 | SMC_outw (dev, RPC_DEFAULT, RPC_REG); |
fe8c2806 | 1304 | |
26238132 | 1305 | smc_phy_configure_exit: ; |
fe8c2806 WD |
1306 | |
1307 | } | |
1308 | #endif /* !CONFIG_SMC91111_EXT_PHY */ | |
1309 | ||
1310 | ||
1311 | #if SMC_DEBUG > 2 | |
1312 | static void print_packet( byte * buf, int length ) | |
1313 | { | |
8bde7f77 WD |
1314 | int i; |
1315 | int remainder; | |
1316 | int lines; | |
fe8c2806 | 1317 | |
8bde7f77 | 1318 | printf("Packet of length %d \n", length ); |
fe8c2806 WD |
1319 | |
1320 | #if SMC_DEBUG > 3 | |
8bde7f77 WD |
1321 | lines = length / 16; |
1322 | remainder = length % 16; | |
1323 | ||
1324 | for ( i = 0; i < lines ; i ++ ) { | |
1325 | int cur; | |
1326 | ||
1327 | for ( cur = 0; cur < 8; cur ++ ) { | |
1328 | byte a, b; | |
1329 | ||
1330 | a = *(buf ++ ); | |
1331 | b = *(buf ++ ); | |
1332 | printf("%02x%02x ", a, b ); | |
1333 | } | |
1334 | printf("\n"); | |
1335 | } | |
1336 | for ( i = 0; i < remainder/2 ; i++ ) { | |
1337 | byte a, b; | |
1338 | ||
1339 | a = *(buf ++ ); | |
1340 | b = *(buf ++ ); | |
1341 | printf("%02x%02x ", a, b ); | |
1342 | } | |
1343 | printf("\n"); | |
fe8c2806 | 1344 | #endif |
fe8c2806 WD |
1345 | } |
1346 | #endif | |
1347 | ||
7194ab80 | 1348 | int smc91111_initialize(u8 dev_num, int base_addr) |
0b97ab14 | 1349 | { |
7194ab80 BW |
1350 | struct smc91111_priv *priv; |
1351 | struct eth_device *dev; | |
1352 | int i; | |
b56ddc63 | 1353 | |
7194ab80 BW |
1354 | priv = malloc(sizeof(*priv)); |
1355 | if (!priv) | |
1356 | return 0; | |
1357 | dev = malloc(sizeof(*dev)); | |
1358 | if (!dev) { | |
1359 | free(priv); | |
1360 | return 0; | |
b56ddc63 WD |
1361 | } |
1362 | ||
7194ab80 BW |
1363 | priv->dev_num = dev_num; |
1364 | dev->priv = priv; | |
1365 | dev->iobase = base_addr; | |
0b97ab14 | 1366 | |
7194ab80 BW |
1367 | swap_to(ETHERNET); |
1368 | SMC_SELECT_BANK(dev, 1); | |
1369 | for (i = 0; i < 6; ++i) | |
1370 | dev->enetaddr[i] = SMC_inb(dev, (ADDR0_REG + i)); | |
1371 | swap_to(FLASH); | |
f39748ae | 1372 | |
7194ab80 BW |
1373 | dev->init = smc_init; |
1374 | dev->halt = smc_halt; | |
1375 | dev->send = smc_send; | |
1376 | dev->recv = smc_rcv; | |
1377 | sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num); | |
f39748ae | 1378 | |
7194ab80 BW |
1379 | eth_register(dev); |
1380 | return 0; | |
0b97ab14 | 1381 | } |