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Commit | Line | Data |
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fe8c2806 WD |
1 | /*------------------------------------------------------------------------ |
2 | . smc91111.c | |
3 | . This is a driver for SMSC's 91C111 single-chip Ethernet device. | |
4 | . | |
5 | . (C) Copyright 2002 | |
6 | . Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
7 | . Rolf Offermanns <rof@sysgo.de> | |
8 | . | |
9 | . Copyright (C) 2001 Standard Microsystems Corporation (SMSC) | |
42dfe7a1 | 10 | . Developed by Simple Network Magic Corporation (SNMC) |
fe8c2806 WD |
11 | . Copyright (C) 1996 by Erik Stahlman (ES) |
12 | . | |
1a459660 | 13 | * SPDX-License-Identifier: GPL-2.0+ |
fe8c2806 WD |
14 | . |
15 | . Information contained in this file was obtained from the LAN91C111 | |
16 | . manual from SMC. To get a copy, if you really want one, you can find | |
17 | . information under www.smsc.com. | |
18 | . | |
19 | . | |
20 | . "Features" of the SMC chip: | |
21 | . Integrated PHY/MAC for 10/100BaseT Operation | |
22 | . Supports internal and external MII | |
23 | . Integrated 8K packet memory | |
24 | . EEPROM interface for configuration | |
25 | . | |
26 | . Arguments: | |
42dfe7a1 | 27 | . io = for the base address |
fe8c2806 WD |
28 | . irq = for the IRQ |
29 | . | |
30 | . author: | |
42dfe7a1 WD |
31 | . Erik Stahlman ( erik@vt.edu ) |
32 | . Daris A Nevil ( dnevil@snmc.com ) | |
fe8c2806 WD |
33 | . |
34 | . | |
35 | . Hardware multicast code from Peter Cammaert ( pc@denkart.be ) | |
36 | . | |
37 | . Sources: | |
42dfe7a1 WD |
38 | . o SMSC LAN91C111 databook (www.smsc.com) |
39 | . o smc9194.c by Erik Stahlman | |
40 | . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov ) | |
fe8c2806 WD |
41 | . |
42 | . History: | |
42dfe7a1 | 43 | . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks. |
fe8c2806 | 44 | . 10/17/01 Marco Hasewinkel Modify for DNP/1110 |
42dfe7a1 WD |
45 | . 07/25/01 Woojung Huh Modify for ADS Bitsy |
46 | . 04/25/01 Daris A Nevil Initial public release through SMSC | |
47 | . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111 | |
fe8c2806 WD |
48 | ----------------------------------------------------------------------------*/ |
49 | ||
50 | #include <common.h> | |
51 | #include <command.h> | |
f39748ae | 52 | #include <config.h> |
7194ab80 | 53 | #include <malloc.h> |
fe8c2806 WD |
54 | #include "smc91111.h" |
55 | #include <net.h> | |
56 | ||
fe8c2806 WD |
57 | /* Use power-down feature of the chip */ |
58 | #define POWER_DOWN 0 | |
59 | ||
60 | #define NO_AUTOPROBE | |
61 | ||
0be248fa | 62 | #define SMC_DEBUG 0 |
8bf3b005 WD |
63 | |
64 | #if SMC_DEBUG > 1 | |
fe8c2806 WD |
65 | static const char version[] = |
66 | "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n"; | |
8bf3b005 | 67 | #endif |
fe8c2806 | 68 | |
f39748ae WD |
69 | /* Autonegotiation timeout in seconds */ |
70 | #ifndef CONFIG_SMC_AUTONEG_TIMEOUT | |
71 | #define CONFIG_SMC_AUTONEG_TIMEOUT 10 | |
72 | #endif | |
73 | ||
fe8c2806 WD |
74 | /*------------------------------------------------------------------------ |
75 | . | |
76 | . Configuration options, for the experienced user to change. | |
77 | . | |
78 | -------------------------------------------------------------------------*/ | |
79 | ||
80 | /* | |
81 | . Wait time for memory to be free. This probably shouldn't be | |
82 | . tuned that much, as waiting for this means nothing else happens | |
83 | . in the system | |
84 | */ | |
85 | #define MEMORY_WAIT_TIME 16 | |
86 | ||
87 | ||
88 | #if (SMC_DEBUG > 2 ) | |
89 | #define PRINTK3(args...) printf(args) | |
90 | #else | |
91 | #define PRINTK3(args...) | |
92 | #endif | |
93 | ||
94 | #if SMC_DEBUG > 1 | |
95 | #define PRINTK2(args...) printf(args) | |
96 | #else | |
97 | #define PRINTK2(args...) | |
98 | #endif | |
99 | ||
100 | #ifdef SMC_DEBUG | |
101 | #define PRINTK(args...) printf(args) | |
102 | #else | |
103 | #define PRINTK(args...) | |
104 | #endif | |
105 | ||
106 | ||
107 | /*------------------------------------------------------------------------ | |
108 | . | |
42dfe7a1 | 109 | . The internal workings of the driver. If you are changing anything |
fe8c2806 WD |
110 | . here with the SMC stuff, you should have the datasheet and know |
111 | . what you are doing. | |
112 | . | |
113 | -------------------------------------------------------------------------*/ | |
fe8c2806 WD |
114 | |
115 | /* Memory sizing constant */ | |
116 | #define LAN91C111_MEMORY_MULTIPLIER (1024*2) | |
117 | ||
118 | #ifndef CONFIG_SMC91111_BASE | |
7194ab80 BW |
119 | #error "SMC91111 Base address must be passed to initialization funciton" |
120 | /* #define CONFIG_SMC91111_BASE 0x20000300 */ | |
fe8c2806 WD |
121 | #endif |
122 | ||
fe8c2806 WD |
123 | #define SMC_DEV_NAME "SMC91111" |
124 | #define SMC_PHY_ADDR 0x0000 | |
125 | #define SMC_ALLOC_MAX_TRY 5 | |
126 | #define SMC_TX_TIMEOUT 30 | |
127 | ||
128 | #define SMC_PHY_CLOCK_DELAY 1000 | |
129 | ||
130 | #define ETH_ZLEN 60 | |
131 | ||
42dfe7a1 | 132 | #ifdef CONFIG_SMC_USE_32_BIT |
fe8c2806 WD |
133 | #define USE_32_BIT 1 |
134 | #else | |
135 | #undef USE_32_BIT | |
136 | #endif | |
fe8c2806 | 137 | |
0afe519a | 138 | #ifdef SHARED_RESOURCES |
7194ab80 BW |
139 | extern void swap_to(int device_id); |
140 | #else | |
141 | # define swap_to(x) | |
0afe519a | 142 | #endif |
fe8c2806 | 143 | |
fe8c2806 | 144 | #ifndef CONFIG_SMC91111_EXT_PHY |
7194ab80 | 145 | static void smc_phy_configure(struct eth_device *dev); |
fe8c2806 WD |
146 | #endif /* !CONFIG_SMC91111_EXT_PHY */ |
147 | ||
fe8c2806 WD |
148 | /* |
149 | ------------------------------------------------------------ | |
150 | . | |
151 | . Internal routines | |
152 | . | |
153 | ------------------------------------------------------------ | |
154 | */ | |
155 | ||
c3c7f861 WD |
156 | #ifdef CONFIG_SMC_USE_IOFUNCS |
157 | /* | |
158 | * input and output functions | |
159 | * | |
160 | * Implemented due to inx,outx macros accessing the device improperly | |
161 | * and putting the device into an unkown state. | |
162 | * | |
163 | * For instance, on Sharp LPD7A400 SDK, affects were chip memory | |
164 | * could not be free'd (hence the alloc failures), duplicate packets, | |
165 | * packets being corrupt (shifted) on the wire, etc. Switching to the | |
166 | * inx,outx functions fixed this problem. | |
167 | */ | |
c3c7f861 | 168 | |
7194ab80 | 169 | static inline word SMC_inw(struct eth_device *dev, dword offset) |
c3c7f861 WD |
170 | { |
171 | word v; | |
7194ab80 | 172 | v = *((volatile word*)(dev->iobase + offset)); |
c3c7f861 WD |
173 | barrier(); *(volatile u32*)(0xc0000000); |
174 | return v; | |
175 | } | |
176 | ||
7194ab80 | 177 | static inline void SMC_outw(struct eth_device *dev, word value, dword offset) |
c3c7f861 | 178 | { |
7194ab80 | 179 | *((volatile word*)(dev->iobase + offset)) = value; |
c3c7f861 WD |
180 | barrier(); *(volatile u32*)(0xc0000000); |
181 | } | |
182 | ||
7194ab80 | 183 | static inline byte SMC_inb(struct eth_device *dev, dword offset) |
c3c7f861 WD |
184 | { |
185 | word _w; | |
186 | ||
7194ab80 | 187 | _w = SMC_inw(dev, offset & ~((dword)1)); |
c3c7f861 WD |
188 | return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w); |
189 | } | |
190 | ||
7194ab80 | 191 | static inline void SMC_outb(struct eth_device *dev, byte value, dword offset) |
c3c7f861 WD |
192 | { |
193 | word _w; | |
194 | ||
7194ab80 | 195 | _w = SMC_inw(dev, offset & ~((dword)1)); |
c3c7f861 | 196 | if (offset & 1) |
7194ab80 BW |
197 | *((volatile word*)(dev->iobase + (offset & ~((dword)1)))) = |
198 | (value<<8) | (_w & 0x00ff); | |
c3c7f861 | 199 | else |
7194ab80 BW |
200 | *((volatile word*)(dev->iobase + offset)) = |
201 | value | (_w & 0xff00); | |
c3c7f861 WD |
202 | } |
203 | ||
7194ab80 BW |
204 | static inline void SMC_insw(struct eth_device *dev, dword offset, |
205 | volatile uchar* buf, dword len) | |
c3c7f861 | 206 | { |
d52fb7e3 WD |
207 | volatile word *p = (volatile word *)buf; |
208 | ||
c3c7f861 | 209 | while (len-- > 0) { |
7194ab80 | 210 | *p++ = SMC_inw(dev, offset); |
d52fb7e3 WD |
211 | barrier(); |
212 | *((volatile u32*)(0xc0000000)); | |
c3c7f861 WD |
213 | } |
214 | } | |
215 | ||
7194ab80 BW |
216 | static inline void SMC_outsw(struct eth_device *dev, dword offset, |
217 | uchar* buf, dword len) | |
c3c7f861 | 218 | { |
d52fb7e3 WD |
219 | volatile word *p = (volatile word *)buf; |
220 | ||
c3c7f861 | 221 | while (len-- > 0) { |
7194ab80 | 222 | SMC_outw(dev, *p++, offset); |
d52fb7e3 WD |
223 | barrier(); |
224 | *(volatile u32*)(0xc0000000); | |
c3c7f861 WD |
225 | } |
226 | } | |
227 | #endif /* CONFIG_SMC_USE_IOFUNCS */ | |
228 | ||
fe8c2806 WD |
229 | /* |
230 | . A rather simple routine to print out a packet for debugging purposes. | |
231 | */ | |
232 | #if SMC_DEBUG > 2 | |
233 | static void print_packet( byte *, int ); | |
234 | #endif | |
235 | ||
236 | #define tx_done(dev) 1 | |
237 | ||
7194ab80 | 238 | static int poll4int (struct eth_device *dev, byte mask, int timeout) |
b56ddc63 | 239 | { |
6d0f6bcf | 240 | int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ; |
b56ddc63 | 241 | int is_timeout = 0; |
7194ab80 | 242 | word old_bank = SMC_inw (dev, BSR_REG); |
b56ddc63 WD |
243 | |
244 | PRINTK2 ("Polling...\n"); | |
7194ab80 BW |
245 | SMC_SELECT_BANK (dev, 2); |
246 | while ((SMC_inw (dev, SMC91111_INT_REG) & mask) == 0) { | |
b56ddc63 WD |
247 | if (get_timer (0) >= tmo) { |
248 | is_timeout = 1; | |
249 | break; | |
250 | } | |
fe8c2806 | 251 | } |
fe8c2806 | 252 | |
b56ddc63 | 253 | /* restore old bank selection */ |
7194ab80 | 254 | SMC_SELECT_BANK (dev, old_bank); |
fe8c2806 | 255 | |
b56ddc63 WD |
256 | if (is_timeout) |
257 | return 1; | |
258 | else | |
259 | return 0; | |
fe8c2806 WD |
260 | } |
261 | ||
487778b7 | 262 | /* Only one release command at a time, please */ |
7194ab80 | 263 | static inline void smc_wait_mmu_release_complete (struct eth_device *dev) |
487778b7 WD |
264 | { |
265 | int count = 0; | |
b56ddc63 | 266 | |
487778b7 | 267 | /* assume bank 2 selected */ |
7194ab80 | 268 | while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { |
b56ddc63 WD |
269 | udelay (1); /* Wait until not busy */ |
270 | if (++count > 200) | |
271 | break; | |
487778b7 WD |
272 | } |
273 | } | |
274 | ||
fe8c2806 WD |
275 | /* |
276 | . Function: smc_reset( void ) | |
277 | . Purpose: | |
42dfe7a1 WD |
278 | . This sets the SMC91111 chip to its normal state, hopefully from whatever |
279 | . mess that any other DOS driver has put it in. | |
fe8c2806 WD |
280 | . |
281 | . Maybe I should reset more registers to defaults in here? SOFTRST should | |
282 | . do that for me. | |
283 | . | |
284 | . Method: | |
285 | . 1. send a SOFT RESET | |
286 | . 2. wait for it to finish | |
287 | . 3. enable autorelease mode | |
288 | . 4. reset the memory management unit | |
289 | . 5. clear all interrupts | |
290 | . | |
291 | */ | |
7194ab80 | 292 | static void smc_reset (struct eth_device *dev) |
fe8c2806 | 293 | { |
f39748ae | 294 | PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME); |
fe8c2806 WD |
295 | |
296 | /* This resets the registers mostly to defaults, but doesn't | |
297 | affect EEPROM. That seems unnecessary */ | |
7194ab80 BW |
298 | SMC_SELECT_BANK (dev, 0); |
299 | SMC_outw (dev, RCR_SOFTRST, RCR_REG); | |
fe8c2806 WD |
300 | |
301 | /* Setup the Configuration Register */ | |
302 | /* This is necessary because the CONFIG_REG is not affected */ | |
303 | /* by a soft reset */ | |
304 | ||
7194ab80 | 305 | SMC_SELECT_BANK (dev, 1); |
fe8c2806 | 306 | #if defined(CONFIG_SMC91111_EXT_PHY) |
7194ab80 | 307 | SMC_outw (dev, CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG); |
fe8c2806 | 308 | #else |
7194ab80 | 309 | SMC_outw (dev, CONFIG_DEFAULT, CONFIG_REG); |
fe8c2806 WD |
310 | #endif |
311 | ||
312 | ||
313 | /* Release from possible power-down state */ | |
314 | /* Configuration register is not affected by Soft Reset */ | |
7194ab80 BW |
315 | SMC_outw (dev, SMC_inw (dev, CONFIG_REG) | CONFIG_EPH_POWER_EN, |
316 | CONFIG_REG); | |
fe8c2806 | 317 | |
7194ab80 | 318 | SMC_SELECT_BANK (dev, 0); |
fe8c2806 WD |
319 | |
320 | /* this should pause enough for the chip to be happy */ | |
b56ddc63 | 321 | udelay (10); |
fe8c2806 WD |
322 | |
323 | /* Disable transmit and receive functionality */ | |
7194ab80 BW |
324 | SMC_outw (dev, RCR_CLEAR, RCR_REG); |
325 | SMC_outw (dev, TCR_CLEAR, TCR_REG); | |
fe8c2806 WD |
326 | |
327 | /* set the control register */ | |
7194ab80 BW |
328 | SMC_SELECT_BANK (dev, 1); |
329 | SMC_outw (dev, CTL_DEFAULT, CTL_REG); | |
fe8c2806 WD |
330 | |
331 | /* Reset the MMU */ | |
7194ab80 BW |
332 | SMC_SELECT_BANK (dev, 2); |
333 | smc_wait_mmu_release_complete (dev); | |
334 | SMC_outw (dev, MC_RESET, MMU_CMD_REG); | |
335 | while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) | |
b56ddc63 | 336 | udelay (1); /* Wait until not busy */ |
fe8c2806 WD |
337 | |
338 | /* Note: It doesn't seem that waiting for the MMU busy is needed here, | |
339 | but this is a place where future chipsets _COULD_ break. Be wary | |
8bde7f77 | 340 | of issuing another MMU command right after this */ |
fe8c2806 WD |
341 | |
342 | /* Disable all interrupts */ | |
7194ab80 | 343 | SMC_outb (dev, 0, IM_REG); |
fe8c2806 WD |
344 | } |
345 | ||
346 | /* | |
347 | . Function: smc_enable | |
348 | . Purpose: let the chip talk to the outside work | |
349 | . Method: | |
350 | . 1. Enable the transmitter | |
351 | . 2. Enable the receiver | |
352 | . 3. Enable interrupts | |
353 | */ | |
7194ab80 | 354 | static void smc_enable(struct eth_device *dev) |
fe8c2806 | 355 | { |
f39748ae | 356 | PRINTK2("%s: smc_enable\n", SMC_DEV_NAME); |
7194ab80 | 357 | SMC_SELECT_BANK( dev, 0 ); |
fe8c2806 | 358 | /* see the header file for options in TCR/RCR DEFAULT*/ |
7194ab80 BW |
359 | SMC_outw( dev, TCR_DEFAULT, TCR_REG ); |
360 | SMC_outw( dev, RCR_DEFAULT, RCR_REG ); | |
fe8c2806 WD |
361 | |
362 | /* clear MII_DIS */ | |
363 | /* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */ | |
364 | } | |
365 | ||
366 | /* | |
7194ab80 | 367 | . Function: smc_halt |
fe8c2806 WD |
368 | . Purpose: closes down the SMC91xxx chip. |
369 | . Method: | |
370 | . 1. zero the interrupt mask | |
371 | . 2. clear the enable receive flag | |
372 | . 3. clear the enable xmit flags | |
373 | . | |
374 | . TODO: | |
375 | . (1) maybe utilize power down mode. | |
376 | . Why not yet? Because while the chip will go into power down mode, | |
377 | . the manual says that it will wake up in response to any I/O requests | |
42dfe7a1 | 378 | . in the register space. Empirical results do not show this working. |
fe8c2806 | 379 | */ |
7194ab80 | 380 | static void smc_halt(struct eth_device *dev) |
fe8c2806 | 381 | { |
7194ab80 | 382 | PRINTK2("%s: smc_halt\n", SMC_DEV_NAME); |
fe8c2806 WD |
383 | |
384 | /* no more interrupts for me */ | |
7194ab80 BW |
385 | SMC_SELECT_BANK( dev, 2 ); |
386 | SMC_outb( dev, 0, IM_REG ); | |
fe8c2806 WD |
387 | |
388 | /* and tell the card to stay away from that nasty outside world */ | |
7194ab80 BW |
389 | SMC_SELECT_BANK( dev, 0 ); |
390 | SMC_outb( dev, RCR_CLEAR, RCR_REG ); | |
391 | SMC_outb( dev, TCR_CLEAR, TCR_REG ); | |
392 | ||
0afe519a | 393 | swap_to(FLASH); |
fe8c2806 WD |
394 | } |
395 | ||
396 | ||
397 | /* | |
7194ab80 | 398 | . Function: smc_send(struct net_device * ) |
fe8c2806 WD |
399 | . Purpose: |
400 | . This sends the actual packet to the SMC9xxx chip. | |
401 | . | |
402 | . Algorithm: | |
42dfe7a1 | 403 | . First, see if a saved_skb is available. |
fe8c2806 WD |
404 | . ( this should NOT be called if there is no 'saved_skb' |
405 | . Now, find the packet number that the chip allocated | |
406 | . Point the data pointers at it in memory | |
407 | . Set the length word in the chip's memory | |
408 | . Dump the packet to chip memory | |
409 | . Check if a last byte is needed ( odd length packet ) | |
410 | . if so, set the control flag right | |
42dfe7a1 | 411 | . Tell the card to send it |
fe8c2806 | 412 | . Enable the transmit interrupt, so I know if it failed |
42dfe7a1 | 413 | . Free the kernel data if I actually sent it. |
fe8c2806 | 414 | */ |
9f098640 | 415 | static int smc_send(struct eth_device *dev, void *packet, int packet_length) |
fe8c2806 | 416 | { |
b56ddc63 | 417 | byte packet_no; |
b56ddc63 WD |
418 | byte *buf; |
419 | int length; | |
420 | int numPages; | |
421 | int try = 0; | |
422 | int time_out; | |
423 | byte status; | |
518e2e1a WD |
424 | byte saved_pnr; |
425 | word saved_ptr; | |
fe8c2806 | 426 | |
518e2e1a | 427 | /* save PTR and PNR registers before manipulation */ |
7194ab80 BW |
428 | SMC_SELECT_BANK (dev, 2); |
429 | saved_pnr = SMC_inb( dev, PN_REG ); | |
430 | saved_ptr = SMC_inw( dev, PTR_REG ); | |
fe8c2806 | 431 | |
f39748ae | 432 | PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME); |
fe8c2806 WD |
433 | |
434 | length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN; | |
435 | ||
436 | /* allocate memory | |
b56ddc63 WD |
437 | ** The MMU wants the number of pages to be the number of 256 bytes |
438 | ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) ) | |
439 | ** | |
440 | ** The 91C111 ignores the size bits, but the code is left intact | |
441 | ** for backwards and future compatibility. | |
442 | ** | |
443 | ** Pkt size for allocating is data length +6 (for additional status | |
444 | ** words, length and ctl!) | |
445 | ** | |
446 | ** If odd size then last byte is included in this header. | |
447 | */ | |
448 | numPages = ((length & 0xfffe) + 6); | |
449 | numPages >>= 8; /* Divide by 256 */ | |
450 | ||
451 | if (numPages > 7) { | |
452 | printf ("%s: Far too big packet error. \n", SMC_DEV_NAME); | |
fe8c2806 WD |
453 | return 0; |
454 | } | |
455 | ||
456 | /* now, try to allocate the memory */ | |
7194ab80 BW |
457 | SMC_SELECT_BANK (dev, 2); |
458 | SMC_outw (dev, MC_ALLOC | numPages, MMU_CMD_REG); | |
fe8c2806 | 459 | |
dc7c9a1a | 460 | /* FIXME: the ALLOC_INT bit never gets set * |
42dfe7a1 WD |
461 | * so the following will always give a * |
462 | * memory allocation error. * | |
463 | * same code works in armboot though * | |
dc7c9a1a WD |
464 | * -ro |
465 | */ | |
466 | ||
fe8c2806 WD |
467 | again: |
468 | try++; | |
469 | time_out = MEMORY_WAIT_TIME; | |
470 | do { | |
7194ab80 | 471 | status = SMC_inb (dev, SMC91111_INT_REG); |
b56ddc63 | 472 | if (status & IM_ALLOC_INT) { |
fe8c2806 | 473 | /* acknowledge the interrupt */ |
7194ab80 | 474 | SMC_outb (dev, IM_ALLOC_INT, SMC91111_INT_REG); |
8bde7f77 | 475 | break; |
fe8c2806 | 476 | } |
b56ddc63 WD |
477 | } while (--time_out); |
478 | ||
479 | if (!time_out) { | |
480 | PRINTK2 ("%s: memory allocation, try %d failed ...\n", | |
481 | SMC_DEV_NAME, try); | |
482 | if (try < SMC_ALLOC_MAX_TRY) | |
483 | goto again; | |
484 | else | |
485 | return 0; | |
fe8c2806 WD |
486 | } |
487 | ||
b56ddc63 WD |
488 | PRINTK2 ("%s: memory allocation, try %d succeeded ...\n", |
489 | SMC_DEV_NAME, try); | |
fe8c2806 | 490 | |
b56ddc63 | 491 | buf = (byte *) packet; |
fe8c2806 WD |
492 | |
493 | /* If I get here, I _know_ there is a packet slot waiting for me */ | |
7194ab80 | 494 | packet_no = SMC_inb (dev, AR_REG); |
b56ddc63 | 495 | if (packet_no & AR_FAILED) { |
fe8c2806 | 496 | /* or isn't there? BAD CHIP! */ |
b56ddc63 | 497 | printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME); |
fe8c2806 WD |
498 | return 0; |
499 | } | |
500 | ||
501 | /* we have a packet address, so tell the card to use it */ | |
1f6d4258 | 502 | #ifndef CONFIG_XAENIAX |
7194ab80 | 503 | SMC_outb (dev, packet_no, PN_REG); |
1f6d4258 WD |
504 | #else |
505 | /* On Xaeniax board, we can't use SMC_outb here because that way | |
506 | * the Allocate MMU command will end up written to the command register | |
507 | * as well, which will lead to a problem. | |
508 | */ | |
7194ab80 | 509 | SMC_outl (dev, packet_no << 16, 0); |
1f6d4258 | 510 | #endif |
b79a11cc WD |
511 | /* do not write new ptr value if Write data fifo not empty */ |
512 | while ( saved_ptr & PTR_NOTEMPTY ) | |
518e2e1a WD |
513 | printf ("Write data fifo not empty!\n"); |
514 | ||
fe8c2806 | 515 | /* point to the beginning of the packet */ |
7194ab80 | 516 | SMC_outw (dev, PTR_AUTOINC, PTR_REG); |
fe8c2806 | 517 | |
b56ddc63 WD |
518 | PRINTK3 ("%s: Trying to xmit packet of length %x\n", |
519 | SMC_DEV_NAME, length); | |
fe8c2806 WD |
520 | |
521 | #if SMC_DEBUG > 2 | |
b56ddc63 WD |
522 | printf ("Transmitting Packet\n"); |
523 | print_packet (buf, length); | |
fe8c2806 WD |
524 | #endif |
525 | ||
526 | /* send the packet length ( +6 for status, length and ctl byte ) | |
8bde7f77 | 527 | and the status word ( set to zeros ) */ |
fe8c2806 | 528 | #ifdef USE_32_BIT |
7194ab80 | 529 | SMC_outl (dev, (length + 6) << 16, SMC91111_DATA_REG); |
fe8c2806 | 530 | #else |
7194ab80 | 531 | SMC_outw (dev, 0, SMC91111_DATA_REG); |
b56ddc63 | 532 | /* send the packet length ( +6 for status words, length, and ctl */ |
7194ab80 | 533 | SMC_outw (dev, (length + 6), SMC91111_DATA_REG); |
fe8c2806 WD |
534 | #endif |
535 | ||
536 | /* send the actual data | |
b56ddc63 WD |
537 | . I _think_ it's faster to send the longs first, and then |
538 | . mop up by sending the last word. It depends heavily | |
42dfe7a1 | 539 | . on alignment, at least on the 486. Maybe it would be |
b56ddc63 WD |
540 | . a good idea to check which is optimal? But that could take |
541 | . almost as much time as is saved? | |
542 | */ | |
fe8c2806 | 543 | #ifdef USE_32_BIT |
7194ab80 | 544 | SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2); |
bb310d46 | 545 | #ifndef CONFIG_XAENIAX |
b56ddc63 | 546 | if (length & 0x2) |
7194ab80 | 547 | SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))), |
b56ddc63 | 548 | SMC91111_DATA_REG); |
bb310d46 WD |
549 | #else |
550 | /* On XANEIAX, we can only use 32-bit writes, so we need to handle | |
551 | * unaligned tail part specially. The standard code doesn't work. | |
552 | */ | |
553 | if ((length & 3) == 3) { | |
554 | u16 * ptr = (u16*) &buf[length-3]; | |
7194ab80 | 555 | SMC_outl(dev, (*ptr) | ((0x2000 | buf[length-1]) << 16), |
bb310d46 WD |
556 | SMC91111_DATA_REG); |
557 | } else if ((length & 2) == 2) { | |
558 | u16 * ptr = (u16*) &buf[length-2]; | |
7194ab80 | 559 | SMC_outl(dev, *ptr, SMC91111_DATA_REG); |
bb310d46 | 560 | } else if (length & 1) { |
7194ab80 | 561 | SMC_outl(dev, (0x2000 | buf[length-1]), SMC91111_DATA_REG); |
bb310d46 | 562 | } else { |
7194ab80 | 563 | SMC_outl(dev, 0, SMC91111_DATA_REG); |
bb310d46 WD |
564 | } |
565 | #endif | |
fe8c2806 | 566 | #else |
7194ab80 | 567 | SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1); |
fe8c2806 WD |
568 | #endif /* USE_32_BIT */ |
569 | ||
bb310d46 | 570 | #ifndef CONFIG_XAENIAX |
42dfe7a1 | 571 | /* Send the last byte, if there is one. */ |
b56ddc63 | 572 | if ((length & 1) == 0) { |
7194ab80 | 573 | SMC_outw (dev, 0, SMC91111_DATA_REG); |
fe8c2806 | 574 | } else { |
7194ab80 | 575 | SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG); |
fe8c2806 | 576 | } |
bb310d46 | 577 | #endif |
fe8c2806 WD |
578 | |
579 | /* and let the chipset deal with it */ | |
7194ab80 | 580 | SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG); |
fe8c2806 WD |
581 | |
582 | /* poll for TX INT */ | |
7194ab80 | 583 | /* if (poll4int (dev, IM_TX_INT, SMC_TX_TIMEOUT)) { */ |
518e2e1a | 584 | /* poll for TX_EMPTY INT - autorelease enabled */ |
7194ab80 | 585 | if (poll4int(dev, IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) { |
fe8c2806 | 586 | /* sending failed */ |
b56ddc63 | 587 | PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME); |
fe8c2806 WD |
588 | |
589 | /* release packet */ | |
518e2e1a | 590 | /* no need to release, MMU does that now */ |
1f6d4258 | 591 | #ifdef CONFIG_XAENIAX |
7194ab80 | 592 | SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG); |
1f6d4258 | 593 | #endif |
fe8c2806 | 594 | |
8bde7f77 | 595 | /* wait for MMU getting ready (low) */ |
7194ab80 | 596 | while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { |
b56ddc63 | 597 | udelay (10); |
8bde7f77 | 598 | } |
fe8c2806 | 599 | |
b56ddc63 | 600 | PRINTK2 ("MMU ready\n"); |
fe8c2806 WD |
601 | |
602 | ||
603 | return 0; | |
604 | } else { | |
605 | /* ack. int */ | |
7194ab80 | 606 | SMC_outb (dev, IM_TX_EMPTY_INT, SMC91111_INT_REG); |
518e2e1a | 607 | /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */ |
b56ddc63 WD |
608 | PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME, |
609 | length); | |
fe8c2806 WD |
610 | |
611 | /* release packet */ | |
518e2e1a | 612 | /* no need to release, MMU does that now */ |
1f6d4258 | 613 | #ifdef CONFIG_XAENIAX |
7194ab80 | 614 | SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG); |
1f6d4258 | 615 | #endif |
fe8c2806 | 616 | |
8bde7f77 | 617 | /* wait for MMU getting ready (low) */ |
7194ab80 | 618 | while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { |
b56ddc63 | 619 | udelay (10); |
8bde7f77 | 620 | } |
fe8c2806 | 621 | |
b56ddc63 | 622 | PRINTK2 ("MMU ready\n"); |
fe8c2806 WD |
623 | |
624 | ||
625 | } | |
626 | ||
518e2e1a | 627 | /* restore previously saved registers */ |
1f6d4258 | 628 | #ifndef CONFIG_XAENIAX |
7194ab80 | 629 | SMC_outb( dev, saved_pnr, PN_REG ); |
1f6d4258 WD |
630 | #else |
631 | /* On Xaeniax board, we can't use SMC_outb here because that way | |
632 | * the Allocate MMU command will end up written to the command register | |
633 | * as well, which will lead to a problem. | |
634 | */ | |
7194ab80 | 635 | SMC_outl(dev, saved_pnr << 16, 0); |
1f6d4258 | 636 | #endif |
7194ab80 | 637 | SMC_outw( dev, saved_ptr, PTR_REG ); |
518e2e1a | 638 | |
fe8c2806 WD |
639 | return length; |
640 | } | |
641 | ||
1ca6d0df TC |
642 | static int smc_write_hwaddr(struct eth_device *dev) |
643 | { | |
644 | int i; | |
645 | ||
646 | swap_to(ETHERNET); | |
647 | SMC_SELECT_BANK (dev, 1); | |
648 | #ifdef USE_32_BIT | |
649 | for (i = 0; i < 6; i += 2) { | |
650 | word address; | |
651 | ||
652 | address = dev->enetaddr[i + 1] << 8; | |
653 | address |= dev->enetaddr[i]; | |
654 | SMC_outw(dev, address, (ADDR0_REG + i)); | |
655 | } | |
656 | #else | |
657 | for (i = 0; i < 6; i++) | |
658 | SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i)); | |
659 | #endif | |
660 | swap_to(FLASH); | |
661 | return 0; | |
662 | } | |
663 | ||
fe8c2806 WD |
664 | /* |
665 | * Open and Initialize the board | |
666 | * | |
667 | * Set up everything, reset the card, etc .. | |
668 | * | |
669 | */ | |
7194ab80 | 670 | static int smc_init(struct eth_device *dev, bd_t *bd) |
fe8c2806 | 671 | { |
7194ab80 BW |
672 | swap_to(ETHERNET); |
673 | ||
674 | PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME); | |
fe8c2806 WD |
675 | |
676 | /* reset the hardware */ | |
7194ab80 BW |
677 | smc_reset (dev); |
678 | smc_enable (dev); | |
fe8c2806 WD |
679 | |
680 | /* Configure the PHY */ | |
681 | #ifndef CONFIG_SMC91111_EXT_PHY | |
7194ab80 | 682 | smc_phy_configure (dev); |
fe8c2806 WD |
683 | #endif |
684 | ||
fe8c2806 | 685 | /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */ |
7194ab80 BW |
686 | /* SMC_SELECT_BANK(dev, 0); */ |
687 | /* SMC_outw(dev, 0, RPC_REG); */ | |
fe8c2806 | 688 | |
7194ab80 BW |
689 | printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr); |
690 | ||
fe8c2806 WD |
691 | return 0; |
692 | } | |
693 | ||
fe8c2806 WD |
694 | /*------------------------------------------------------------- |
695 | . | |
696 | . smc_rcv - receive a packet from the card | |
697 | . | |
698 | . There is ( at least ) a packet waiting to be read from | |
699 | . chip-memory. | |
700 | . | |
701 | . o Read the status | |
702 | . o If an error, record it | |
703 | . o otherwise, read in the packet | |
704 | -------------------------------------------------------------- | |
705 | */ | |
7194ab80 | 706 | static int smc_rcv(struct eth_device *dev) |
fe8c2806 | 707 | { |
42dfe7a1 | 708 | int packet_number; |
fe8c2806 WD |
709 | word status; |
710 | word packet_length; | |
42dfe7a1 | 711 | int is_error = 0; |
fe8c2806 WD |
712 | #ifdef USE_32_BIT |
713 | dword stat_len; | |
714 | #endif | |
518e2e1a WD |
715 | byte saved_pnr; |
716 | word saved_ptr; | |
fe8c2806 | 717 | |
7194ab80 | 718 | SMC_SELECT_BANK(dev, 2); |
518e2e1a | 719 | /* save PTR and PTR registers */ |
7194ab80 BW |
720 | saved_pnr = SMC_inb( dev, PN_REG ); |
721 | saved_ptr = SMC_inw( dev, PTR_REG ); | |
518e2e1a | 722 | |
7194ab80 | 723 | packet_number = SMC_inw( dev, RXFIFO_REG ); |
fe8c2806 WD |
724 | |
725 | if ( packet_number & RXFIFO_REMPTY ) { | |
726 | ||
727 | return 0; | |
728 | } | |
729 | ||
f39748ae | 730 | PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME); |
fe8c2806 | 731 | /* start reading from the start of the packet */ |
7194ab80 | 732 | SMC_outw( dev, PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG ); |
fe8c2806 WD |
733 | |
734 | /* First two words are status and packet_length */ | |
735 | #ifdef USE_32_BIT | |
7194ab80 | 736 | stat_len = SMC_inl(dev, SMC91111_DATA_REG); |
fe8c2806 WD |
737 | status = stat_len & 0xffff; |
738 | packet_length = stat_len >> 16; | |
739 | #else | |
7194ab80 BW |
740 | status = SMC_inw( dev, SMC91111_DATA_REG ); |
741 | packet_length = SMC_inw( dev, SMC91111_DATA_REG ); | |
fe8c2806 WD |
742 | #endif |
743 | ||
744 | packet_length &= 0x07ff; /* mask off top bits */ | |
745 | ||
746 | PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length ); | |
747 | ||
748 | if ( !(status & RS_ERRORS ) ){ | |
749 | /* Adjust for having already read the first two words */ | |
750 | packet_length -= 4; /*4; */ | |
751 | ||
752 | ||
fe8c2806 WD |
753 | /* set odd length for bug in LAN91C111, */ |
754 | /* which never sets RS_ODDFRAME */ | |
755 | /* TODO ? */ | |
756 | ||
757 | ||
758 | #ifdef USE_32_BIT | |
759 | PRINTK3(" Reading %d dwords (and %d bytes) \n", | |
760 | packet_length >> 2, packet_length & 3 ); | |
761 | /* QUESTION: Like in the TX routine, do I want | |
762 | to send the DWORDs or the bytes first, or some | |
763 | mixture. A mixture might improve already slow PIO | |
42dfe7a1 | 764 | performance */ |
7194ab80 BW |
765 | SMC_insl( dev, SMC91111_DATA_REG, NetRxPackets[0], |
766 | packet_length >> 2 ); | |
fe8c2806 WD |
767 | /* read the left over bytes */ |
768 | if (packet_length & 3) { | |
769 | int i; | |
770 | ||
7194ab80 BW |
771 | byte *tail = (byte *)(NetRxPackets[0] + |
772 | (packet_length & ~3)); | |
773 | dword leftover = SMC_inl(dev, SMC91111_DATA_REG); | |
fe8c2806 WD |
774 | for (i=0; i<(packet_length & 3); i++) |
775 | *tail++ = (byte) (leftover >> (8*i)) & 0xff; | |
776 | } | |
777 | #else | |
778 | PRINTK3(" Reading %d words and %d byte(s) \n", | |
779 | (packet_length >> 1 ), packet_length & 1 ); | |
7194ab80 BW |
780 | SMC_insw(dev, SMC91111_DATA_REG , NetRxPackets[0], |
781 | packet_length >> 1); | |
fe8c2806 WD |
782 | |
783 | #endif /* USE_32_BIT */ | |
784 | ||
785 | #if SMC_DEBUG > 2 | |
786 | printf("Receiving Packet\n"); | |
787 | print_packet( NetRxPackets[0], packet_length ); | |
788 | #endif | |
789 | } else { | |
790 | /* error ... */ | |
791 | /* TODO ? */ | |
792 | is_error = 1; | |
793 | } | |
794 | ||
7194ab80 | 795 | while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY ) |
fe8c2806 WD |
796 | udelay(1); /* Wait until not busy */ |
797 | ||
798 | /* error or good, tell the card to get rid of this packet */ | |
7194ab80 | 799 | SMC_outw( dev, MC_RELEASE, MMU_CMD_REG ); |
fe8c2806 | 800 | |
7194ab80 | 801 | while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY ) |
fe8c2806 WD |
802 | udelay(1); /* Wait until not busy */ |
803 | ||
518e2e1a | 804 | /* restore saved registers */ |
1f6d4258 | 805 | #ifndef CONFIG_XAENIAX |
7194ab80 | 806 | SMC_outb( dev, saved_pnr, PN_REG ); |
1f6d4258 WD |
807 | #else |
808 | /* On Xaeniax board, we can't use SMC_outb here because that way | |
809 | * the Allocate MMU command will end up written to the command register | |
810 | * as well, which will lead to a problem. | |
811 | */ | |
7194ab80 | 812 | SMC_outl( dev, saved_pnr << 16, 0); |
1f6d4258 | 813 | #endif |
7194ab80 | 814 | SMC_outw( dev, saved_ptr, PTR_REG ); |
518e2e1a | 815 | |
fe8c2806 WD |
816 | if (!is_error) { |
817 | /* Pass the packet up to the protocol layers. */ | |
818 | NetReceive(NetRxPackets[0], packet_length); | |
819 | return packet_length; | |
820 | } else { | |
821 | return 0; | |
822 | } | |
823 | ||
824 | } | |
825 | ||
826 | ||
fe8c2806 WD |
827 | #if 0 |
828 | /*------------------------------------------------------------ | |
829 | . Modify a bit in the LAN91C111 register set | |
830 | .-------------------------------------------------------------*/ | |
7194ab80 | 831 | static word smc_modify_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, |
fe8c2806 WD |
832 | unsigned int bit, int val) |
833 | { | |
834 | word regval; | |
835 | ||
7194ab80 | 836 | SMC_SELECT_BANK( dev, bank ); |
fe8c2806 | 837 | |
7194ab80 | 838 | regval = SMC_inw( dev, reg ); |
fe8c2806 WD |
839 | if (val) |
840 | regval |= bit; | |
841 | else | |
842 | regval &= ~bit; | |
843 | ||
7194ab80 | 844 | SMC_outw( dev, regval, 0 ); |
fe8c2806 WD |
845 | return(regval); |
846 | } | |
847 | ||
848 | ||
849 | /*------------------------------------------------------------ | |
850 | . Retrieve a bit in the LAN91C111 register set | |
851 | .-------------------------------------------------------------*/ | |
7194ab80 | 852 | static int smc_get_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, unsigned int bit) |
fe8c2806 | 853 | { |
7194ab80 BW |
854 | SMC_SELECT_BANK( dev, bank ); |
855 | if ( SMC_inw( dev, reg ) & bit) | |
fe8c2806 WD |
856 | return(1); |
857 | else | |
858 | return(0); | |
859 | } | |
860 | ||
861 | ||
862 | /*------------------------------------------------------------ | |
863 | . Modify a LAN91C111 register (word access only) | |
864 | .-------------------------------------------------------------*/ | |
7194ab80 | 865 | static void smc_modify_reg(struct eth_device *dev, int bank, int ioaddr, int reg, word val) |
fe8c2806 | 866 | { |
7194ab80 BW |
867 | SMC_SELECT_BANK( dev, bank ); |
868 | SMC_outw( dev, val, reg ); | |
fe8c2806 WD |
869 | } |
870 | ||
871 | ||
872 | /*------------------------------------------------------------ | |
873 | . Retrieve a LAN91C111 register (word access only) | |
874 | .-------------------------------------------------------------*/ | |
7194ab80 | 875 | static int smc_get_reg(struct eth_device *dev, int bank, int ioaddr, int reg) |
fe8c2806 | 876 | { |
7194ab80 BW |
877 | SMC_SELECT_BANK( dev, bank ); |
878 | return(SMC_inw( dev, reg )); | |
fe8c2806 WD |
879 | } |
880 | ||
881 | #endif /* 0 */ | |
882 | ||
883 | /*---PHY CONTROL AND CONFIGURATION----------------------------------------- */ | |
884 | ||
885 | #if (SMC_DEBUG > 2 ) | |
886 | ||
887 | /*------------------------------------------------------------ | |
888 | . Debugging function for viewing MII Management serial bitstream | |
889 | .-------------------------------------------------------------*/ | |
b56ddc63 | 890 | static void smc_dump_mii_stream (byte * bits, int size) |
fe8c2806 WD |
891 | { |
892 | int i; | |
893 | ||
b56ddc63 WD |
894 | printf ("BIT#:"); |
895 | for (i = 0; i < size; ++i) { | |
896 | printf ("%d", i % 10); | |
897 | } | |
fe8c2806 | 898 | |
b56ddc63 WD |
899 | printf ("\nMDOE:"); |
900 | for (i = 0; i < size; ++i) { | |
fe8c2806 | 901 | if (bits[i] & MII_MDOE) |
b56ddc63 | 902 | printf ("1"); |
fe8c2806 | 903 | else |
b56ddc63 WD |
904 | printf ("0"); |
905 | } | |
fe8c2806 | 906 | |
b56ddc63 WD |
907 | printf ("\nMDO :"); |
908 | for (i = 0; i < size; ++i) { | |
fe8c2806 | 909 | if (bits[i] & MII_MDO) |
b56ddc63 | 910 | printf ("1"); |
fe8c2806 | 911 | else |
b56ddc63 WD |
912 | printf ("0"); |
913 | } | |
fe8c2806 | 914 | |
b56ddc63 WD |
915 | printf ("\nMDI :"); |
916 | for (i = 0; i < size; ++i) { | |
fe8c2806 | 917 | if (bits[i] & MII_MDI) |
b56ddc63 | 918 | printf ("1"); |
fe8c2806 | 919 | else |
b56ddc63 WD |
920 | printf ("0"); |
921 | } | |
fe8c2806 | 922 | |
b56ddc63 | 923 | printf ("\n"); |
fe8c2806 WD |
924 | } |
925 | #endif | |
926 | ||
927 | /*------------------------------------------------------------ | |
928 | . Reads a register from the MII Management serial interface | |
929 | .-------------------------------------------------------------*/ | |
930 | #ifndef CONFIG_SMC91111_EXT_PHY | |
7194ab80 | 931 | static word smc_read_phy_register (struct eth_device *dev, byte phyreg) |
fe8c2806 WD |
932 | { |
933 | int oldBank; | |
934 | int i; | |
935 | byte mask; | |
936 | word mii_reg; | |
937 | byte bits[64]; | |
938 | int clk_idx = 0; | |
939 | int input_idx; | |
940 | word phydata; | |
941 | byte phyaddr = SMC_PHY_ADDR; | |
942 | ||
943 | /* 32 consecutive ones on MDO to establish sync */ | |
944 | for (i = 0; i < 32; ++i) | |
945 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
946 | ||
947 | /* Start code <01> */ | |
948 | bits[clk_idx++] = MII_MDOE; | |
949 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
950 | ||
951 | /* Read command <10> */ | |
952 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
953 | bits[clk_idx++] = MII_MDOE; | |
954 | ||
955 | /* Output the PHY address, msb first */ | |
b56ddc63 WD |
956 | mask = (byte) 0x10; |
957 | for (i = 0; i < 5; ++i) { | |
fe8c2806 WD |
958 | if (phyaddr & mask) |
959 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
960 | else | |
961 | bits[clk_idx++] = MII_MDOE; | |
962 | ||
963 | /* Shift to next lowest bit */ | |
964 | mask >>= 1; | |
b56ddc63 | 965 | } |
fe8c2806 WD |
966 | |
967 | /* Output the phy register number, msb first */ | |
b56ddc63 WD |
968 | mask = (byte) 0x10; |
969 | for (i = 0; i < 5; ++i) { | |
fe8c2806 WD |
970 | if (phyreg & mask) |
971 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
972 | else | |
973 | bits[clk_idx++] = MII_MDOE; | |
974 | ||
975 | /* Shift to next lowest bit */ | |
976 | mask >>= 1; | |
b56ddc63 | 977 | } |
fe8c2806 WD |
978 | |
979 | /* Tristate and turnaround (2 bit times) */ | |
980 | bits[clk_idx++] = 0; | |
981 | /*bits[clk_idx++] = 0; */ | |
982 | ||
983 | /* Input starts at this bit time */ | |
984 | input_idx = clk_idx; | |
985 | ||
986 | /* Will input 16 bits */ | |
987 | for (i = 0; i < 16; ++i) | |
988 | bits[clk_idx++] = 0; | |
989 | ||
990 | /* Final clock bit */ | |
991 | bits[clk_idx++] = 0; | |
992 | ||
993 | /* Save the current bank */ | |
7194ab80 | 994 | oldBank = SMC_inw (dev, BANK_SELECT); |
fe8c2806 WD |
995 | |
996 | /* Select bank 3 */ | |
7194ab80 | 997 | SMC_SELECT_BANK (dev, 3); |
fe8c2806 WD |
998 | |
999 | /* Get the current MII register value */ | |
7194ab80 | 1000 | mii_reg = SMC_inw (dev, MII_REG); |
fe8c2806 WD |
1001 | |
1002 | /* Turn off all MII Interface bits */ | |
b56ddc63 | 1003 | mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO); |
fe8c2806 WD |
1004 | |
1005 | /* Clock all 64 cycles */ | |
b56ddc63 | 1006 | for (i = 0; i < sizeof bits; ++i) { |
fe8c2806 | 1007 | /* Clock Low - output data */ |
7194ab80 | 1008 | SMC_outw (dev, mii_reg | bits[i], MII_REG); |
b56ddc63 | 1009 | udelay (SMC_PHY_CLOCK_DELAY); |
fe8c2806 WD |
1010 | |
1011 | ||
1012 | /* Clock Hi - input data */ | |
7194ab80 | 1013 | SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG); |
b56ddc63 | 1014 | udelay (SMC_PHY_CLOCK_DELAY); |
7194ab80 | 1015 | bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI; |
b56ddc63 | 1016 | } |
fe8c2806 WD |
1017 | |
1018 | /* Return to idle state */ | |
1019 | /* Set clock to low, data to low, and output tristated */ | |
7194ab80 | 1020 | SMC_outw (dev, mii_reg, MII_REG); |
b56ddc63 | 1021 | udelay (SMC_PHY_CLOCK_DELAY); |
fe8c2806 WD |
1022 | |
1023 | /* Restore original bank select */ | |
7194ab80 | 1024 | SMC_SELECT_BANK (dev, oldBank); |
fe8c2806 WD |
1025 | |
1026 | /* Recover input data */ | |
1027 | phydata = 0; | |
b56ddc63 | 1028 | for (i = 0; i < 16; ++i) { |
fe8c2806 WD |
1029 | phydata <<= 1; |
1030 | ||
1031 | if (bits[input_idx++] & MII_MDI) | |
1032 | phydata |= 0x0001; | |
b56ddc63 | 1033 | } |
fe8c2806 WD |
1034 | |
1035 | #if (SMC_DEBUG > 2 ) | |
b56ddc63 | 1036 | printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n", |
fe8c2806 | 1037 | phyaddr, phyreg, phydata); |
b56ddc63 | 1038 | smc_dump_mii_stream (bits, sizeof bits); |
fe8c2806 WD |
1039 | #endif |
1040 | ||
b56ddc63 | 1041 | return (phydata); |
fe8c2806 WD |
1042 | } |
1043 | ||
1044 | ||
1045 | /*------------------------------------------------------------ | |
1046 | . Writes a register to the MII Management serial interface | |
1047 | .-------------------------------------------------------------*/ | |
7194ab80 BW |
1048 | static void smc_write_phy_register (struct eth_device *dev, byte phyreg, |
1049 | word phydata) | |
fe8c2806 WD |
1050 | { |
1051 | int oldBank; | |
1052 | int i; | |
1053 | word mask; | |
1054 | word mii_reg; | |
1055 | byte bits[65]; | |
1056 | int clk_idx = 0; | |
1057 | byte phyaddr = SMC_PHY_ADDR; | |
1058 | ||
1059 | /* 32 consecutive ones on MDO to establish sync */ | |
1060 | for (i = 0; i < 32; ++i) | |
1061 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1062 | ||
1063 | /* Start code <01> */ | |
1064 | bits[clk_idx++] = MII_MDOE; | |
1065 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1066 | ||
1067 | /* Write command <01> */ | |
1068 | bits[clk_idx++] = MII_MDOE; | |
1069 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1070 | ||
1071 | /* Output the PHY address, msb first */ | |
b56ddc63 WD |
1072 | mask = (byte) 0x10; |
1073 | for (i = 0; i < 5; ++i) { | |
fe8c2806 WD |
1074 | if (phyaddr & mask) |
1075 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1076 | else | |
1077 | bits[clk_idx++] = MII_MDOE; | |
1078 | ||
1079 | /* Shift to next lowest bit */ | |
1080 | mask >>= 1; | |
b56ddc63 | 1081 | } |
fe8c2806 WD |
1082 | |
1083 | /* Output the phy register number, msb first */ | |
b56ddc63 WD |
1084 | mask = (byte) 0x10; |
1085 | for (i = 0; i < 5; ++i) { | |
fe8c2806 WD |
1086 | if (phyreg & mask) |
1087 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1088 | else | |
1089 | bits[clk_idx++] = MII_MDOE; | |
1090 | ||
1091 | /* Shift to next lowest bit */ | |
1092 | mask >>= 1; | |
b56ddc63 | 1093 | } |
fe8c2806 WD |
1094 | |
1095 | /* Tristate and turnaround (2 bit times) */ | |
1096 | bits[clk_idx++] = 0; | |
1097 | bits[clk_idx++] = 0; | |
1098 | ||
1099 | /* Write out 16 bits of data, msb first */ | |
1100 | mask = 0x8000; | |
b56ddc63 | 1101 | for (i = 0; i < 16; ++i) { |
fe8c2806 WD |
1102 | if (phydata & mask) |
1103 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1104 | else | |
1105 | bits[clk_idx++] = MII_MDOE; | |
1106 | ||
1107 | /* Shift to next lowest bit */ | |
1108 | mask >>= 1; | |
b56ddc63 | 1109 | } |
fe8c2806 WD |
1110 | |
1111 | /* Final clock bit (tristate) */ | |
1112 | bits[clk_idx++] = 0; | |
1113 | ||
1114 | /* Save the current bank */ | |
7194ab80 | 1115 | oldBank = SMC_inw (dev, BANK_SELECT); |
fe8c2806 WD |
1116 | |
1117 | /* Select bank 3 */ | |
7194ab80 | 1118 | SMC_SELECT_BANK (dev, 3); |
fe8c2806 WD |
1119 | |
1120 | /* Get the current MII register value */ | |
7194ab80 | 1121 | mii_reg = SMC_inw (dev, MII_REG); |
fe8c2806 WD |
1122 | |
1123 | /* Turn off all MII Interface bits */ | |
b56ddc63 | 1124 | mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO); |
fe8c2806 WD |
1125 | |
1126 | /* Clock all cycles */ | |
b56ddc63 | 1127 | for (i = 0; i < sizeof bits; ++i) { |
fe8c2806 | 1128 | /* Clock Low - output data */ |
7194ab80 | 1129 | SMC_outw (dev, mii_reg | bits[i], MII_REG); |
b56ddc63 | 1130 | udelay (SMC_PHY_CLOCK_DELAY); |
fe8c2806 WD |
1131 | |
1132 | ||
1133 | /* Clock Hi - input data */ | |
7194ab80 | 1134 | SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG); |
b56ddc63 | 1135 | udelay (SMC_PHY_CLOCK_DELAY); |
7194ab80 | 1136 | bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI; |
b56ddc63 | 1137 | } |
fe8c2806 WD |
1138 | |
1139 | /* Return to idle state */ | |
1140 | /* Set clock to low, data to low, and output tristated */ | |
7194ab80 | 1141 | SMC_outw (dev, mii_reg, MII_REG); |
b56ddc63 | 1142 | udelay (SMC_PHY_CLOCK_DELAY); |
fe8c2806 WD |
1143 | |
1144 | /* Restore original bank select */ | |
7194ab80 | 1145 | SMC_SELECT_BANK (dev, oldBank); |
fe8c2806 WD |
1146 | |
1147 | #if (SMC_DEBUG > 2 ) | |
b56ddc63 | 1148 | printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n", |
fe8c2806 | 1149 | phyaddr, phyreg, phydata); |
b56ddc63 | 1150 | smc_dump_mii_stream (bits, sizeof bits); |
fe8c2806 WD |
1151 | #endif |
1152 | } | |
1153 | #endif /* !CONFIG_SMC91111_EXT_PHY */ | |
1154 | ||
1155 | ||
fe8c2806 WD |
1156 | /*------------------------------------------------------------ |
1157 | . Configures the specified PHY using Autonegotiation. Calls | |
1158 | . smc_phy_fixed() if the user has requested a certain config. | |
1159 | .-------------------------------------------------------------*/ | |
1160 | #ifndef CONFIG_SMC91111_EXT_PHY | |
7194ab80 | 1161 | static void smc_phy_configure (struct eth_device *dev) |
fe8c2806 WD |
1162 | { |
1163 | int timeout; | |
b56ddc63 WD |
1164 | word my_phy_caps; /* My PHY capabilities */ |
1165 | word my_ad_caps; /* My Advertised capabilities */ | |
1166 | word status = 0; /*;my status = 0 */ | |
fe8c2806 | 1167 | |
f39748ae | 1168 | PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME); |
fe8c2806 | 1169 | |
fe8c2806 | 1170 | /* Reset the PHY, setting all other bits to zero */ |
7194ab80 | 1171 | smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_RST); |
fe8c2806 WD |
1172 | |
1173 | /* Wait for the reset to complete, or time out */ | |
b56ddc63 WD |
1174 | timeout = 6; /* Wait up to 3 seconds */ |
1175 | while (timeout--) { | |
7194ab80 | 1176 | if (!(smc_read_phy_register (dev, PHY_CNTL_REG) |
b56ddc63 | 1177 | & PHY_CNTL_RST)) { |
fe8c2806 WD |
1178 | /* reset complete */ |
1179 | break; | |
fe8c2806 WD |
1180 | } |
1181 | ||
65029492 | 1182 | mdelay(500); /* wait 500 millisecs */ |
b56ddc63 WD |
1183 | } |
1184 | ||
1185 | if (timeout < 1) { | |
1186 | printf ("%s:PHY reset timed out\n", SMC_DEV_NAME); | |
fe8c2806 | 1187 | goto smc_phy_configure_exit; |
b56ddc63 | 1188 | } |
fe8c2806 WD |
1189 | |
1190 | /* Read PHY Register 18, Status Output */ | |
1191 | /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */ | |
1192 | ||
1193 | /* Enable PHY Interrupts (for register 18) */ | |
1194 | /* Interrupts listed here are disabled */ | |
7194ab80 | 1195 | smc_write_phy_register (dev, PHY_MASK_REG, 0xffff); |
fe8c2806 WD |
1196 | |
1197 | /* Configure the Receive/Phy Control register */ | |
7194ab80 BW |
1198 | SMC_SELECT_BANK (dev, 0); |
1199 | SMC_outw (dev, RPC_DEFAULT, RPC_REG); | |
fe8c2806 WD |
1200 | |
1201 | /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */ | |
7194ab80 | 1202 | my_phy_caps = smc_read_phy_register (dev, PHY_STAT_REG); |
b56ddc63 | 1203 | my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */ |
fe8c2806 WD |
1204 | |
1205 | if (my_phy_caps & PHY_STAT_CAP_T4) | |
1206 | my_ad_caps |= PHY_AD_T4; | |
1207 | ||
1208 | if (my_phy_caps & PHY_STAT_CAP_TXF) | |
1209 | my_ad_caps |= PHY_AD_TX_FDX; | |
1210 | ||
1211 | if (my_phy_caps & PHY_STAT_CAP_TXH) | |
1212 | my_ad_caps |= PHY_AD_TX_HDX; | |
1213 | ||
1214 | if (my_phy_caps & PHY_STAT_CAP_TF) | |
1215 | my_ad_caps |= PHY_AD_10_FDX; | |
1216 | ||
1217 | if (my_phy_caps & PHY_STAT_CAP_TH) | |
1218 | my_ad_caps |= PHY_AD_10_HDX; | |
1219 | ||
1220 | /* Update our Auto-Neg Advertisement Register */ | |
7194ab80 | 1221 | smc_write_phy_register (dev, PHY_AD_REG, my_ad_caps); |
fe8c2806 | 1222 | |
518e2e1a WD |
1223 | /* Read the register back. Without this, it appears that when */ |
1224 | /* auto-negotiation is restarted, sometimes it isn't ready and */ | |
1225 | /* the link does not come up. */ | |
7194ab80 | 1226 | smc_read_phy_register(dev, PHY_AD_REG); |
518e2e1a | 1227 | |
f39748ae WD |
1228 | PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps); |
1229 | PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps); | |
fe8c2806 WD |
1230 | |
1231 | /* Restart auto-negotiation process in order to advertise my caps */ | |
7194ab80 | 1232 | smc_write_phy_register (dev, PHY_CNTL_REG, |
b56ddc63 | 1233 | PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST); |
fe8c2806 WD |
1234 | |
1235 | /* Wait for the auto-negotiation to complete. This may take from */ | |
1236 | /* 2 to 3 seconds. */ | |
1237 | /* Wait for the reset to complete, or time out */ | |
f39748ae | 1238 | timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2; |
b56ddc63 | 1239 | while (timeout--) { |
f39748ae | 1240 | |
7194ab80 | 1241 | status = smc_read_phy_register (dev, PHY_STAT_REG); |
b56ddc63 | 1242 | if (status & PHY_STAT_ANEG_ACK) { |
fe8c2806 WD |
1243 | /* auto-negotiate complete */ |
1244 | break; | |
b56ddc63 | 1245 | } |
fe8c2806 | 1246 | |
65029492 | 1247 | mdelay(500); /* wait 500 millisecs */ |
fe8c2806 WD |
1248 | |
1249 | /* Restart auto-negotiation if remote fault */ | |
b56ddc63 | 1250 | if (status & PHY_STAT_REM_FLT) { |
f39748ae | 1251 | printf ("%s: PHY remote fault detected\n", |
b56ddc63 | 1252 | SMC_DEV_NAME); |
fe8c2806 WD |
1253 | |
1254 | /* Restart auto-negotiation */ | |
f39748ae | 1255 | printf ("%s: PHY restarting auto-negotiation\n", |
fe8c2806 | 1256 | SMC_DEV_NAME); |
7194ab80 | 1257 | smc_write_phy_register (dev, PHY_CNTL_REG, |
b56ddc63 WD |
1258 | PHY_CNTL_ANEG_EN | |
1259 | PHY_CNTL_ANEG_RST | | |
1260 | PHY_CNTL_SPEED | | |
1261 | PHY_CNTL_DPLX); | |
fe8c2806 | 1262 | } |
b56ddc63 | 1263 | } |
fe8c2806 | 1264 | |
b56ddc63 | 1265 | if (timeout < 1) { |
f39748ae | 1266 | printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME); |
b56ddc63 | 1267 | } |
fe8c2806 WD |
1268 | |
1269 | /* Fail if we detected an auto-negotiate remote fault */ | |
b56ddc63 | 1270 | if (status & PHY_STAT_REM_FLT) { |
f39748ae | 1271 | printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME); |
b56ddc63 | 1272 | } |
fe8c2806 WD |
1273 | |
1274 | /* Re-Configure the Receive/Phy Control register */ | |
7194ab80 | 1275 | SMC_outw (dev, RPC_DEFAULT, RPC_REG); |
fe8c2806 | 1276 | |
26238132 | 1277 | smc_phy_configure_exit: ; |
fe8c2806 WD |
1278 | |
1279 | } | |
1280 | #endif /* !CONFIG_SMC91111_EXT_PHY */ | |
1281 | ||
1282 | ||
1283 | #if SMC_DEBUG > 2 | |
1284 | static void print_packet( byte * buf, int length ) | |
1285 | { | |
8bde7f77 WD |
1286 | int i; |
1287 | int remainder; | |
1288 | int lines; | |
fe8c2806 | 1289 | |
8bde7f77 | 1290 | printf("Packet of length %d \n", length ); |
fe8c2806 WD |
1291 | |
1292 | #if SMC_DEBUG > 3 | |
8bde7f77 WD |
1293 | lines = length / 16; |
1294 | remainder = length % 16; | |
1295 | ||
1296 | for ( i = 0; i < lines ; i ++ ) { | |
1297 | int cur; | |
1298 | ||
1299 | for ( cur = 0; cur < 8; cur ++ ) { | |
1300 | byte a, b; | |
1301 | ||
1302 | a = *(buf ++ ); | |
1303 | b = *(buf ++ ); | |
1304 | printf("%02x%02x ", a, b ); | |
1305 | } | |
1306 | printf("\n"); | |
1307 | } | |
1308 | for ( i = 0; i < remainder/2 ; i++ ) { | |
1309 | byte a, b; | |
1310 | ||
1311 | a = *(buf ++ ); | |
1312 | b = *(buf ++ ); | |
1313 | printf("%02x%02x ", a, b ); | |
1314 | } | |
1315 | printf("\n"); | |
fe8c2806 | 1316 | #endif |
fe8c2806 WD |
1317 | } |
1318 | #endif | |
1319 | ||
7194ab80 | 1320 | int smc91111_initialize(u8 dev_num, int base_addr) |
0b97ab14 | 1321 | { |
7194ab80 BW |
1322 | struct smc91111_priv *priv; |
1323 | struct eth_device *dev; | |
1324 | int i; | |
b56ddc63 | 1325 | |
7194ab80 BW |
1326 | priv = malloc(sizeof(*priv)); |
1327 | if (!priv) | |
1328 | return 0; | |
1329 | dev = malloc(sizeof(*dev)); | |
1330 | if (!dev) { | |
1331 | free(priv); | |
1332 | return 0; | |
b56ddc63 WD |
1333 | } |
1334 | ||
1ca6d0df | 1335 | memset(dev, 0, sizeof(*dev)); |
7194ab80 BW |
1336 | priv->dev_num = dev_num; |
1337 | dev->priv = priv; | |
1338 | dev->iobase = base_addr; | |
0b97ab14 | 1339 | |
7194ab80 BW |
1340 | swap_to(ETHERNET); |
1341 | SMC_SELECT_BANK(dev, 1); | |
1342 | for (i = 0; i < 6; ++i) | |
1343 | dev->enetaddr[i] = SMC_inb(dev, (ADDR0_REG + i)); | |
1344 | swap_to(FLASH); | |
f39748ae | 1345 | |
7194ab80 BW |
1346 | dev->init = smc_init; |
1347 | dev->halt = smc_halt; | |
1348 | dev->send = smc_send; | |
1349 | dev->recv = smc_rcv; | |
1ca6d0df | 1350 | dev->write_hwaddr = smc_write_hwaddr; |
7194ab80 | 1351 | sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num); |
f39748ae | 1352 | |
7194ab80 BW |
1353 | eth_register(dev); |
1354 | return 0; | |
0b97ab14 | 1355 | } |