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fe8c2806 WD |
1 | /*------------------------------------------------------------------------ |
2 | . smc91111.h - macros for the LAN91C111 Ethernet Driver | |
3 | . | |
4 | . (C) Copyright 2002 | |
5 | . Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
6 | . Rolf Offermanns <rof@sysgo.de> | |
7 | . Copyright (C) 2001 Standard Microsystems Corporation (SMSC) | |
8 | . Developed by Simple Network Magic Corporation (SNMC) | |
9 | . Copyright (C) 1996 by Erik Stahlman (ES) | |
10 | . | |
1a459660 | 11 | * SPDX-License-Identifier: GPL-2.0+ |
fe8c2806 WD |
12 | . |
13 | . This file contains register information and access macros for | |
14 | . the LAN91C111 single chip ethernet controller. It is a modified | |
15 | . version of the smc9194.h file. | |
16 | . | |
17 | . Information contained in this file was obtained from the LAN91C111 | |
18 | . manual from SMC. To get a copy, if you really want one, you can find | |
19 | . information under www.smsc.com. | |
20 | . | |
21 | . Authors | |
53677ef1 | 22 | . Erik Stahlman ( erik@vt.edu ) |
fe8c2806 WD |
23 | . Daris A Nevil ( dnevil@snmc.com ) |
24 | . | |
25 | . History | |
26 | . 03/16/01 Daris A Nevil Modified for use with LAN91C111 device | |
27 | . | |
28 | ---------------------------------------------------------------------------*/ | |
29 | #ifndef _SMC91111_H_ | |
30 | #define _SMC91111_H_ | |
31 | ||
32 | #include <asm/types.h> | |
33 | #include <config.h> | |
34 | ||
35 | /* | |
36 | * This function may be called by the board specific initialisation code | |
37 | * in order to override the default mac address. | |
38 | */ | |
39 | ||
d52fb7e3 | 40 | void smc_set_mac_addr (const unsigned char *addr); |
fe8c2806 WD |
41 | |
42 | ||
43 | /* I want some simple types */ | |
44 | ||
45 | typedef unsigned char byte; | |
46 | typedef unsigned short word; | |
53677ef1 | 47 | typedef unsigned long int dword; |
fe8c2806 | 48 | |
7194ab80 BW |
49 | struct smc91111_priv{ |
50 | u8 dev_num; | |
51 | }; | |
52 | ||
fe8c2806 WD |
53 | /* |
54 | . DEBUGGING LEVELS | |
55 | . | |
56 | . 0 for normal operation | |
57 | . 1 for slightly more details | |
58 | . >2 for various levels of increasingly useless information | |
59 | . 2 for interrupt tracking, status flags | |
60 | . 3 for packet info | |
61 | . 4 for complete packet dumps | |
62 | */ | |
63 | /*#define SMC_DEBUG 0 */ | |
64 | ||
65 | /* Because of bank switching, the LAN91xxx uses only 16 I/O ports */ | |
66 | ||
67 | #define SMC_IO_EXTENT 16 | |
68 | ||
abc20aba | 69 | #ifdef CONFIG_CPU_PXA25X |
fe8c2806 | 70 | |
ca0e7748 | 71 | #ifdef CONFIG_XSENGINE |
1031ae96 BW |
72 | #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+((r)<<1)))) |
73 | #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1)))) | |
7194ab80 | 74 | #define SMC_inb(a,p) ({ \ |
1031ae96 | 75 | unsigned int __p = (unsigned int)((a)->iobase + ((p)<<1)); \ |
ca0e7748 WD |
76 | unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \ |
77 | if (__p & 2) __v >>= 8; \ | |
78 | else __v &= 0xff; \ | |
79 | __v; }) | |
1f6d4258 | 80 | #elif defined(CONFIG_XAENIAX) |
7194ab80 BW |
81 | #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r)))) |
82 | #define SMC_inw(a,z) ({ \ | |
83 | unsigned int __p = (unsigned int)((a)->iobase + (z)); \ | |
1f6d4258 WD |
84 | unsigned int __v = *(volatile unsigned int *)((__p) & ~3); \ |
85 | if (__p & 3) __v >>= 16; \ | |
86 | else __v &= 0xffff; \ | |
87 | __v; }) | |
7194ab80 BW |
88 | #define SMC_inb(a,p) ({ \ |
89 | unsigned int ___v = SMC_inw((a),(p) & ~1); \ | |
1031ae96 | 90 | if ((p) & 1) ___v >>= 8; \ |
1f6d4258 WD |
91 | else ___v &= 0xff; \ |
92 | ___v; }) | |
ca0e7748 | 93 | #else |
7194ab80 BW |
94 | #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r)))) |
95 | #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r)))) | |
96 | #define SMC_inb(a,p) ({ \ | |
97 | unsigned int __p = (unsigned int)((a)->iobase + (p)); \ | |
487778b7 | 98 | unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \ |
fe8c2806 WD |
99 | if (__p & 1) __v >>= 8; \ |
100 | else __v &= 0xff; \ | |
101 | __v; }) | |
ca0e7748 | 102 | #endif |
fe8c2806 | 103 | |
ca0e7748 | 104 | #ifdef CONFIG_XSENGINE |
7194ab80 BW |
105 | #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d) |
106 | #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r<<1))) = d) | |
1f6d4258 | 107 | #elif defined (CONFIG_XAENIAX) |
7194ab80 BW |
108 | #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d) |
109 | #define SMC_outw(a,d,p) ({ \ | |
110 | dword __dwo = SMC_inl((a),(p) & ~3); \ | |
1f6d4258 WD |
111 | dword __dwn = (word)(d); \ |
112 | __dwo &= ((p) & 3) ? 0x0000ffff : 0xffff0000; \ | |
113 | __dwo |= ((p) & 3) ? __dwn << 16 : __dwn; \ | |
7194ab80 | 114 | SMC_outl((a), __dwo, (p) & ~3); \ |
1f6d4258 | 115 | }) |
ca0e7748 | 116 | #else |
7194ab80 BW |
117 | #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d) |
118 | #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r))) = d) | |
ca0e7748 WD |
119 | #endif |
120 | ||
7194ab80 BW |
121 | #define SMC_outb(a,d,r) ({ word __d = (byte)(d); \ |
122 | word __w = SMC_inw((a),(r)&~1); \ | |
fe8c2806 WD |
123 | __w &= ((r)&1) ? 0x00FF : 0xFF00; \ |
124 | __w |= ((r)&1) ? __d<<8 : __d; \ | |
7194ab80 | 125 | SMC_outw((a),__w,(r)&~1); \ |
fe8c2806 WD |
126 | }) |
127 | ||
7194ab80 | 128 | #define SMC_outsl(a,r,b,l) ({ int __i; \ |
fe8c2806 WD |
129 | dword *__b2; \ |
130 | __b2 = (dword *) b; \ | |
131 | for (__i = 0; __i < l; __i++) { \ | |
7194ab80 | 132 | SMC_outl((a), *(__b2 + __i), r); \ |
fe8c2806 WD |
133 | } \ |
134 | }) | |
135 | ||
7194ab80 | 136 | #define SMC_outsw(a,r,b,l) ({ int __i; \ |
fe8c2806 WD |
137 | word *__b2; \ |
138 | __b2 = (word *) b; \ | |
139 | for (__i = 0; __i < l; __i++) { \ | |
7194ab80 | 140 | SMC_outw((a), *(__b2 + __i), r); \ |
fe8c2806 WD |
141 | } \ |
142 | }) | |
143 | ||
7194ab80 | 144 | #define SMC_insl(a,r,b,l) ({ int __i ; \ |
fe8c2806 | 145 | dword *__b2; \ |
53677ef1 WD |
146 | __b2 = (dword *) b; \ |
147 | for (__i = 0; __i < l; __i++) { \ | |
7194ab80 BW |
148 | *(__b2 + __i) = SMC_inl((a),(r)); \ |
149 | SMC_inl((a),0); \ | |
fe8c2806 WD |
150 | }; \ |
151 | }) | |
152 | ||
7194ab80 | 153 | #define SMC_insw(a,r,b,l) ({ int __i ; \ |
fe8c2806 | 154 | word *__b2; \ |
53677ef1 WD |
155 | __b2 = (word *) b; \ |
156 | for (__i = 0; __i < l; __i++) { \ | |
7194ab80 BW |
157 | *(__b2 + __i) = SMC_inw((a),(r)); \ |
158 | SMC_inw((a),0); \ | |
fe8c2806 WD |
159 | }; \ |
160 | }) | |
161 | ||
7194ab80 | 162 | #define SMC_insb(a,r,b,l) ({ int __i ; \ |
fe8c2806 | 163 | byte *__b2; \ |
53677ef1 WD |
164 | __b2 = (byte *) b; \ |
165 | for (__i = 0; __i < l; __i++) { \ | |
7194ab80 BW |
166 | *(__b2 + __i) = SMC_inb((a),(r)); \ |
167 | SMC_inb((a),0); \ | |
fe8c2806 WD |
168 | }; \ |
169 | }) | |
170 | ||
abc20aba | 171 | #elif defined(CONFIG_LEON) /* if not CONFIG_CPU_PXA25X */ |
3eac6402 DH |
172 | |
173 | #define SMC_LEON_SWAP16(_x_) ({ word _x = (_x_); ((_x << 8) | (_x >> 8)); }) | |
174 | ||
175 | #define SMC_LEON_SWAP32(_x_) \ | |
176 | ({ dword _x = (_x_); \ | |
177 | ((_x << 24) | \ | |
178 | ((0x0000FF00UL & _x) << 8) | \ | |
179 | ((0x00FF0000UL & _x) >> 8) | \ | |
180 | (_x >> 24)); }) | |
181 | ||
7194ab80 BW |
182 | #define SMC_inl(a,r) (SMC_LEON_SWAP32((*(volatile dword *)((a)->iobase+((r)<<0))))) |
183 | #define SMC_inl_nosw(a,r) ((*(volatile dword *)((a)->iobase+((r)<<0)))) | |
184 | #define SMC_inw(a,r) (SMC_LEON_SWAP16((*(volatile word *)((a)->iobase+((r)<<0))))) | |
185 | #define SMC_inw_nosw(a,r) ((*(volatile word *)((a)->iobase+((r)<<0)))) | |
186 | #define SMC_inb(a,p) ({ \ | |
187 | word ___v = SMC_inw((a),(p) & ~1); \ | |
3eac6402 DH |
188 | if ((p) & 1) ___v >>= 8; \ |
189 | else ___v &= 0xff; \ | |
190 | ___v; }) | |
191 | ||
7194ab80 BW |
192 | #define SMC_outl(a,d,r) (*(volatile dword *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP32(d)) |
193 | #define SMC_outl_nosw(a,d,r) (*(volatile dword *)((a)->iobase+((r)<<0))=(d)) | |
194 | #define SMC_outw(a,d,r) (*(volatile word *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP16(d)) | |
195 | #define SMC_outw_nosw(a,d,r) (*(volatile word *)((a)->iobase+((r)<<0))=(d)) | |
196 | #define SMC_outb(a,d,r) do{ word __d = (byte)(d); \ | |
197 | word __w = SMC_inw((a),(r)&~1); \ | |
3eac6402 DH |
198 | __w &= ((r)&1) ? 0x00FF : 0xFF00; \ |
199 | __w |= ((r)&1) ? __d<<8 : __d; \ | |
7194ab80 | 200 | SMC_outw((a),__w,(r)&~1); \ |
3eac6402 | 201 | }while(0) |
7194ab80 | 202 | #define SMC_outsl(a,r,b,l) do{ int __i; \ |
3eac6402 DH |
203 | dword *__b2; \ |
204 | __b2 = (dword *) b; \ | |
205 | for (__i = 0; __i < l; __i++) { \ | |
7194ab80 | 206 | SMC_outl_nosw((a), *(__b2 + __i), r); \ |
3eac6402 DH |
207 | } \ |
208 | }while(0) | |
7194ab80 | 209 | #define SMC_outsw(a,r,b,l) do{ int __i; \ |
3eac6402 DH |
210 | word *__b2; \ |
211 | __b2 = (word *) b; \ | |
212 | for (__i = 0; __i < l; __i++) { \ | |
7194ab80 | 213 | SMC_outw_nosw((a), *(__b2 + __i), r); \ |
3eac6402 DH |
214 | } \ |
215 | }while(0) | |
7194ab80 | 216 | #define SMC_insl(a,r,b,l) do{ int __i ; \ |
3eac6402 DH |
217 | dword *__b2; \ |
218 | __b2 = (dword *) b; \ | |
219 | for (__i = 0; __i < l; __i++) { \ | |
7194ab80 | 220 | *(__b2 + __i) = SMC_inl_nosw((a),(r)); \ |
3eac6402 DH |
221 | }; \ |
222 | }while(0) | |
223 | ||
7194ab80 | 224 | #define SMC_insw(a,r,b,l) do{ int __i ; \ |
3eac6402 DH |
225 | word *__b2; \ |
226 | __b2 = (word *) b; \ | |
227 | for (__i = 0; __i < l; __i++) { \ | |
7194ab80 | 228 | *(__b2 + __i) = SMC_inw_nosw((a),(r)); \ |
3eac6402 DH |
229 | }; \ |
230 | }while(0) | |
231 | ||
7194ab80 | 232 | #define SMC_insb(a,r,b,l) do{ int __i ; \ |
3eac6402 DH |
233 | byte *__b2; \ |
234 | __b2 = (byte *) b; \ | |
235 | for (__i = 0; __i < l; __i++) { \ | |
7194ab80 | 236 | *(__b2 + __i) = SMC_inb((a),(r)); \ |
3eac6402 DH |
237 | }; \ |
238 | }while(0) | |
239 | ||
abc20aba | 240 | #else /* if not CONFIG_CPU_PXA25X and not CONFIG_LEON */ |
fe8c2806 | 241 | |
c3c7f861 | 242 | #ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */ |
fe8c2806 WD |
243 | /* |
244 | * We have only 16 Bit PCMCIA access on Socket 0 | |
245 | */ | |
246 | ||
aaf224ab | 247 | #ifdef CONFIG_ADNPESC1 |
7194ab80 | 248 | #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1)))) |
0afe519a | 249 | #elif CONFIG_BLACKFIN |
7194ab80 | 250 | #define SMC_inw(a,r) ({ word __v = (*((volatile word *)((a)->iobase+(r)))); SSYNC(); __v;}) |
aaf224ab | 251 | #else |
7194ab80 | 252 | #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r)))) |
aaf224ab | 253 | #endif |
7194ab80 | 254 | #define SMC_inb(a,r) (((r)&1) ? SMC_inw((a),(r)&~1)>>8 : SMC_inw((a),(r)&0xFF)) |
fe8c2806 | 255 | |
aaf224ab | 256 | #ifdef CONFIG_ADNPESC1 |
7194ab80 | 257 | #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+((r)<<1))) = d) |
0afe519a | 258 | #elif CONFIG_BLACKFIN |
7194ab80 | 259 | #define SMC_outw(a,d,r) {(*((volatile word *)((a)->iobase+(r))) = d); SSYNC();} |
aaf224ab | 260 | #else |
7194ab80 | 261 | #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r))) = d) |
aaf224ab | 262 | #endif |
7194ab80 BW |
263 | #define SMC_outb(a,d,r) ({ word __d = (byte)(d); \ |
264 | word __w = SMC_inw((a),(r)&~1); \ | |
fe8c2806 WD |
265 | __w &= ((r)&1) ? 0x00FF : 0xFF00; \ |
266 | __w |= ((r)&1) ? __d<<8 : __d; \ | |
7194ab80 | 267 | SMC_outw((a),__w,(r)&~1); \ |
fe8c2806 WD |
268 | }) |
269 | #if 0 | |
7194ab80 | 270 | #define SMC_outsw(a,r,b,l) outsw((a)->iobase+(r), (b), (l)) |
fe8c2806 | 271 | #else |
7194ab80 | 272 | #define SMC_outsw(a,r,b,l) ({ int __i; \ |
fe8c2806 WD |
273 | word *__b2; \ |
274 | __b2 = (word *) b; \ | |
275 | for (__i = 0; __i < l; __i++) { \ | |
7194ab80 | 276 | SMC_outw((a), *(__b2 + __i), r); \ |
fe8c2806 WD |
277 | } \ |
278 | }) | |
279 | #endif | |
280 | ||
281 | #if 0 | |
7194ab80 | 282 | #define SMC_insw(a,r,b,l) insw((a)->iobase+(r), (b), (l)) |
fe8c2806 | 283 | #else |
7194ab80 | 284 | #define SMC_insw(a,r,b,l) ({ int __i ; \ |
fe8c2806 | 285 | word *__b2; \ |
53677ef1 WD |
286 | __b2 = (word *) b; \ |
287 | for (__i = 0; __i < l; __i++) { \ | |
7194ab80 BW |
288 | *(__b2 + __i) = SMC_inw((a),(r)); \ |
289 | SMC_inw((a),0); \ | |
fe8c2806 WD |
290 | }; \ |
291 | }) | |
292 | #endif | |
293 | ||
c3c7f861 WD |
294 | #endif /* CONFIG_SMC_USE_IOFUNCS */ |
295 | ||
a3ad8e26 WD |
296 | #if defined(CONFIG_SMC_USE_32_BIT) |
297 | ||
ca0e7748 | 298 | #ifdef CONFIG_XSENGINE |
7194ab80 | 299 | #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r<<1)))) |
ca0e7748 | 300 | #else |
7194ab80 | 301 | #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r)))) |
ca0e7748 | 302 | #endif |
a3ad8e26 | 303 | |
7194ab80 | 304 | #define SMC_insl(a,r,b,l) ({ int __i ; \ |
a3ad8e26 | 305 | dword *__b2; \ |
53677ef1 WD |
306 | __b2 = (dword *) b; \ |
307 | for (__i = 0; __i < l; __i++) { \ | |
7194ab80 BW |
308 | *(__b2 + __i) = SMC_inl((a),(r)); \ |
309 | SMC_inl((a),0); \ | |
a3ad8e26 WD |
310 | }; \ |
311 | }) | |
312 | ||
ca0e7748 | 313 | #ifdef CONFIG_XSENGINE |
7194ab80 | 314 | #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d) |
ca0e7748 | 315 | #else |
7194ab80 | 316 | #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d) |
ca0e7748 | 317 | #endif |
7194ab80 | 318 | #define SMC_outsl(a,r,b,l) ({ int __i; \ |
a3ad8e26 WD |
319 | dword *__b2; \ |
320 | __b2 = (dword *) b; \ | |
321 | for (__i = 0; __i < l; __i++) { \ | |
7194ab80 | 322 | SMC_outl((a), *(__b2 + __i), r); \ |
a3ad8e26 WD |
323 | } \ |
324 | }) | |
325 | ||
326 | #endif /* CONFIG_SMC_USE_32_BIT */ | |
327 | ||
fe8c2806 WD |
328 | #endif |
329 | ||
330 | /*--------------------------------------------------------------- | |
331 | . | |
332 | . A description of the SMSC registers is probably in order here, | |
333 | . although for details, the SMC datasheet is invaluable. | |
334 | . | |
335 | . Basically, the chip has 4 banks of registers ( 0 to 3 ), which | |
336 | . are accessed by writing a number into the BANK_SELECT register | |
337 | . ( I also use a SMC_SELECT_BANK macro for this ). | |
338 | . | |
339 | . The banks are configured so that for most purposes, bank 2 is all | |
340 | . that is needed for simple run time tasks. | |
341 | -----------------------------------------------------------------------*/ | |
342 | ||
343 | /* | |
344 | . Bank Select Register: | |
345 | . | |
346 | . yyyy yyyy 0000 00xx | |
53677ef1 | 347 | . xx = bank number |
fe8c2806 WD |
348 | . yyyy yyyy = 0x33, for identification purposes. |
349 | */ | |
350 | #define BANK_SELECT 14 | |
351 | ||
352 | /* Transmit Control Register */ | |
353 | /* BANK 0 */ | |
53677ef1 | 354 | #define TCR_REG 0x0000 /* transmit control register */ |
fe8c2806 WD |
355 | #define TCR_ENABLE 0x0001 /* When 1 we can transmit */ |
356 | #define TCR_LOOP 0x0002 /* Controls output pin LBK */ | |
357 | #define TCR_FORCOL 0x0004 /* When 1 will force a collision */ | |
358 | #define TCR_PAD_EN 0x0080 /* When 1 will pad tx frames < 64 bytes w/0 */ | |
359 | #define TCR_NOCRC 0x0100 /* When 1 will not append CRC to tx frames */ | |
360 | #define TCR_MON_CSN 0x0400 /* When 1 tx monitors carrier */ | |
53677ef1 | 361 | #define TCR_FDUPLX 0x0800 /* When 1 enables full duplex operation */ |
fe8c2806 WD |
362 | #define TCR_STP_SQET 0x1000 /* When 1 stops tx if Signal Quality Error */ |
363 | #define TCR_EPH_LOOP 0x2000 /* When 1 enables EPH block loopback */ | |
364 | #define TCR_SWFDUP 0x8000 /* When 1 enables Switched Full Duplex mode */ | |
365 | ||
366 | #define TCR_CLEAR 0 /* do NOTHING */ | |
367 | /* the default settings for the TCR register : */ | |
368 | /* QUESTION: do I want to enable padding of short packets ? */ | |
53677ef1 | 369 | #define TCR_DEFAULT TCR_ENABLE |
fe8c2806 WD |
370 | |
371 | ||
372 | /* EPH Status Register */ | |
373 | /* BANK 0 */ | |
374 | #define EPH_STATUS_REG 0x0002 | |
375 | #define ES_TX_SUC 0x0001 /* Last TX was successful */ | |
376 | #define ES_SNGL_COL 0x0002 /* Single collision detected for last tx */ | |
377 | #define ES_MUL_COL 0x0004 /* Multiple collisions detected for last tx */ | |
378 | #define ES_LTX_MULT 0x0008 /* Last tx was a multicast */ | |
379 | #define ES_16COL 0x0010 /* 16 Collisions Reached */ | |
380 | #define ES_SQET 0x0020 /* Signal Quality Error Test */ | |
381 | #define ES_LTXBRD 0x0040 /* Last tx was a broadcast */ | |
382 | #define ES_TXDEFR 0x0080 /* Transmit Deferred */ | |
383 | #define ES_LATCOL 0x0200 /* Late collision detected on last tx */ | |
384 | #define ES_LOSTCARR 0x0400 /* Lost Carrier Sense */ | |
385 | #define ES_EXC_DEF 0x0800 /* Excessive Deferral */ | |
386 | #define ES_CTR_ROL 0x1000 /* Counter Roll Over indication */ | |
387 | #define ES_LINK_OK 0x4000 /* Driven by inverted value of nLNK pin */ | |
388 | #define ES_TXUNRN 0x8000 /* Tx Underrun */ | |
389 | ||
390 | ||
391 | /* Receive Control Register */ | |
392 | /* BANK 0 */ | |
393 | #define RCR_REG 0x0004 | |
394 | #define RCR_RX_ABORT 0x0001 /* Set if a rx frame was aborted */ | |
395 | #define RCR_PRMS 0x0002 /* Enable promiscuous mode */ | |
396 | #define RCR_ALMUL 0x0004 /* When set accepts all multicast frames */ | |
397 | #define RCR_RXEN 0x0100 /* IFF this is set, we can receive packets */ | |
398 | #define RCR_STRIP_CRC 0x0200 /* When set strips CRC from rx packets */ | |
399 | #define RCR_ABORT_ENB 0x0200 /* When set will abort rx on collision */ | |
400 | #define RCR_FILT_CAR 0x0400 /* When set filters leading 12 bit s of carrier */ | |
53677ef1 | 401 | #define RCR_SOFTRST 0x8000 /* resets the chip */ |
fe8c2806 WD |
402 | |
403 | /* the normal settings for the RCR register : */ | |
404 | #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) | |
405 | #define RCR_CLEAR 0x0 /* set it to a base state */ | |
406 | ||
407 | /* Counter Register */ | |
408 | /* BANK 0 */ | |
409 | #define COUNTER_REG 0x0006 | |
410 | ||
411 | /* Memory Information Register */ | |
412 | /* BANK 0 */ | |
413 | #define MIR_REG 0x0008 | |
414 | ||
415 | /* Receive/Phy Control Register */ | |
416 | /* BANK 0 */ | |
417 | #define RPC_REG 0x000A | |
418 | #define RPC_SPEED 0x2000 /* When 1 PHY is in 100Mbps mode. */ | |
419 | #define RPC_DPLX 0x1000 /* When 1 PHY is in Full-Duplex Mode */ | |
420 | #define RPC_ANEG 0x0800 /* When 1 PHY is in Auto-Negotiate Mode */ | |
421 | #define RPC_LSXA_SHFT 5 /* Bits to shift LS2A,LS1A,LS0A to lsb */ | |
422 | #define RPC_LSXB_SHFT 2 /* Bits to get LS2B,LS1B,LS0B to lsb */ | |
423 | #define RPC_LED_100_10 (0x00) /* LED = 100Mbps OR's with 10Mbps link detect */ | |
424 | #define RPC_LED_RES (0x01) /* LED = Reserved */ | |
425 | #define RPC_LED_10 (0x02) /* LED = 10Mbps link detect */ | |
426 | #define RPC_LED_FD (0x03) /* LED = Full Duplex Mode */ | |
427 | #define RPC_LED_TX_RX (0x04) /* LED = TX or RX packet occurred */ | |
428 | #define RPC_LED_100 (0x05) /* LED = 100Mbps link dectect */ | |
429 | #define RPC_LED_TX (0x06) /* LED = TX packet occurred */ | |
430 | #define RPC_LED_RX (0x07) /* LED = RX packet occurred */ | |
c935d3bd | 431 | #if defined(CONFIG_DK1C20) || defined(CONFIG_DK1S10) |
8bf3b005 | 432 | /* buggy schematic: LEDa -> yellow, LEDb --> green */ |
aaf224ab WD |
433 | #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ |
434 | | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \ | |
435 | | (RPC_LED_100_10 << RPC_LSXB_SHFT) ) | |
436 | #elif defined(CONFIG_ADNPESC1) | |
437 | /* SSV ADNP/ESC1 has only one LED: LEDa -> Rx/Tx indicator */ | |
8bf3b005 WD |
438 | #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ |
439 | | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \ | |
440 | | (RPC_LED_100_10 << RPC_LSXB_SHFT) ) | |
441 | #else | |
442 | /* SMSC reference design: LEDa --> green, LEDb --> yellow */ | |
443 | #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ | |
444 | | (RPC_LED_100_10 << RPC_LSXA_SHFT) \ | |
445 | | (RPC_LED_TX_RX << RPC_LSXB_SHFT) ) | |
446 | #endif | |
fe8c2806 WD |
447 | |
448 | /* Bank 0 0x000C is reserved */ | |
449 | ||
450 | /* Bank Select Register */ | |
451 | /* All Banks */ | |
452 | #define BSR_REG 0x000E | |
453 | ||
454 | ||
455 | /* Configuration Reg */ | |
456 | /* BANK 1 */ | |
457 | #define CONFIG_REG 0x0000 | |
458 | #define CONFIG_EXT_PHY 0x0200 /* 1=external MII, 0=internal Phy */ | |
459 | #define CONFIG_GPCNTRL 0x0400 /* Inverse value drives pin nCNTRL */ | |
460 | #define CONFIG_NO_WAIT 0x1000 /* When 1 no extra wait states on ISA bus */ | |
461 | #define CONFIG_EPH_POWER_EN 0x8000 /* When 0 EPH is placed into low power mode. */ | |
462 | ||
463 | /* Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low */ | |
464 | #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN) | |
465 | ||
466 | ||
467 | /* Base Address Register */ | |
468 | /* BANK 1 */ | |
469 | #define BASE_REG 0x0002 | |
470 | ||
471 | ||
472 | /* Individual Address Registers */ | |
473 | /* BANK 1 */ | |
474 | #define ADDR0_REG 0x0004 | |
475 | #define ADDR1_REG 0x0006 | |
476 | #define ADDR2_REG 0x0008 | |
477 | ||
478 | ||
479 | /* General Purpose Register */ | |
480 | /* BANK 1 */ | |
481 | #define GP_REG 0x000A | |
482 | ||
483 | ||
484 | /* Control Register */ | |
485 | /* BANK 1 */ | |
486 | #define CTL_REG 0x000C | |
487 | #define CTL_RCV_BAD 0x4000 /* When 1 bad CRC packets are received */ | |
488 | #define CTL_AUTO_RELEASE 0x0800 /* When 1 tx pages are released automatically */ | |
489 | #define CTL_LE_ENABLE 0x0080 /* When 1 enables Link Error interrupt */ | |
490 | #define CTL_CR_ENABLE 0x0040 /* When 1 enables Counter Rollover interrupt */ | |
491 | #define CTL_TE_ENABLE 0x0020 /* When 1 enables Transmit Error interrupt */ | |
492 | #define CTL_EEPROM_SELECT 0x0004 /* Controls EEPROM reload & store */ | |
493 | #define CTL_RELOAD 0x0002 /* When set reads EEPROM into registers */ | |
494 | #define CTL_STORE 0x0001 /* When set stores registers into EEPROM */ | |
518e2e1a | 495 | #define CTL_DEFAULT (0x1A10) /* Autorelease enabled*/ |
fe8c2806 WD |
496 | |
497 | /* MMU Command Register */ | |
498 | /* BANK 2 */ | |
499 | #define MMU_CMD_REG 0x0000 | |
500 | #define MC_BUSY 1 /* When 1 the last release has not completed */ | |
501 | #define MC_NOP (0<<5) /* No Op */ | |
53677ef1 | 502 | #define MC_ALLOC (1<<5) /* OR with number of 256 byte packets */ |
fe8c2806 | 503 | #define MC_RESET (2<<5) /* Reset MMU to initial state */ |
53677ef1 WD |
504 | #define MC_REMOVE (3<<5) /* Remove the current rx packet */ |
505 | #define MC_RELEASE (4<<5) /* Remove and release the current rx packet */ | |
506 | #define MC_FREEPKT (5<<5) /* Release packet in PNR register */ | |
fe8c2806 WD |
507 | #define MC_ENQUEUE (6<<5) /* Enqueue the packet for transmit */ |
508 | #define MC_RSTTXFIFO (7<<5) /* Reset the TX FIFOs */ | |
509 | ||
510 | ||
511 | /* Packet Number Register */ | |
512 | /* BANK 2 */ | |
513 | #define PN_REG 0x0002 | |
514 | ||
515 | ||
516 | /* Allocation Result Register */ | |
517 | /* BANK 2 */ | |
518 | #define AR_REG 0x0003 | |
519 | #define AR_FAILED 0x80 /* Alocation Failed */ | |
520 | ||
521 | ||
522 | /* RX FIFO Ports Register */ | |
523 | /* BANK 2 */ | |
524 | #define RXFIFO_REG 0x0004 /* Must be read as a word */ | |
525 | #define RXFIFO_REMPTY 0x8000 /* RX FIFO Empty */ | |
526 | ||
527 | ||
528 | /* TX FIFO Ports Register */ | |
529 | /* BANK 2 */ | |
530 | #define TXFIFO_REG RXFIFO_REG /* Must be read as a word */ | |
531 | #define TXFIFO_TEMPTY 0x80 /* TX FIFO Empty */ | |
532 | ||
533 | ||
534 | /* Pointer Register */ | |
535 | /* BANK 2 */ | |
536 | #define PTR_REG 0x0006 | |
537 | #define PTR_RCV 0x8000 /* 1=Receive area, 0=Transmit area */ | |
53677ef1 | 538 | #define PTR_AUTOINC 0x4000 /* Auto increment the pointer on each access */ |
fe8c2806 | 539 | #define PTR_READ 0x2000 /* When 1 the operation is a read */ |
518e2e1a | 540 | #define PTR_NOTEMPTY 0x0800 /* When 1 _do not_ write fifo DATA REG */ |
fe8c2806 WD |
541 | |
542 | ||
543 | /* Data Register */ | |
544 | /* BANK 2 */ | |
545 | #define SMC91111_DATA_REG 0x0008 | |
546 | ||
547 | ||
548 | /* Interrupt Status/Acknowledge Register */ | |
549 | /* BANK 2 */ | |
550 | #define SMC91111_INT_REG 0x000C | |
551 | ||
552 | ||
553 | /* Interrupt Mask Register */ | |
554 | /* BANK 2 */ | |
555 | #define IM_REG 0x000D | |
556 | #define IM_MDINT 0x80 /* PHY MI Register 18 Interrupt */ | |
557 | #define IM_ERCV_INT 0x40 /* Early Receive Interrupt */ | |
558 | #define IM_EPH_INT 0x20 /* Set by Etheret Protocol Handler section */ | |
559 | #define IM_RX_OVRN_INT 0x10 /* Set by Receiver Overruns */ | |
560 | #define IM_ALLOC_INT 0x08 /* Set when allocation request is completed */ | |
561 | #define IM_TX_EMPTY_INT 0x04 /* Set if the TX FIFO goes empty */ | |
562 | #define IM_TX_INT 0x02 /* Transmit Interrrupt */ | |
563 | #define IM_RCV_INT 0x01 /* Receive Interrupt */ | |
564 | ||
565 | ||
566 | /* Multicast Table Registers */ | |
567 | /* BANK 3 */ | |
568 | #define MCAST_REG1 0x0000 | |
569 | #define MCAST_REG2 0x0002 | |
570 | #define MCAST_REG3 0x0004 | |
571 | #define MCAST_REG4 0x0006 | |
572 | ||
573 | ||
574 | /* Management Interface Register (MII) */ | |
575 | /* BANK 3 */ | |
576 | #define MII_REG 0x0008 | |
577 | #define MII_MSK_CRS100 0x4000 /* Disables CRS100 detection during tx half dup */ | |
578 | #define MII_MDOE 0x0008 /* MII Output Enable */ | |
579 | #define MII_MCLK 0x0004 /* MII Clock, pin MDCLK */ | |
580 | #define MII_MDI 0x0002 /* MII Input, pin MDI */ | |
581 | #define MII_MDO 0x0001 /* MII Output, pin MDO */ | |
582 | ||
583 | ||
584 | /* Revision Register */ | |
585 | /* BANK 3 */ | |
586 | #define REV_REG 0x000A /* ( hi: chip id low: rev # ) */ | |
587 | ||
588 | ||
589 | /* Early RCV Register */ | |
590 | /* BANK 3 */ | |
591 | /* this is NOT on SMC9192 */ | |
592 | #define ERCV_REG 0x000C | |
593 | #define ERCV_RCV_DISCRD 0x0080 /* When 1 discards a packet being received */ | |
594 | #define ERCV_THRESHOLD 0x001F /* ERCV Threshold Mask */ | |
595 | ||
596 | /* External Register */ | |
597 | /* BANK 7 */ | |
598 | #define EXT_REG 0x0000 | |
599 | ||
600 | ||
601 | #define CHIP_9192 3 | |
602 | #define CHIP_9194 4 | |
603 | #define CHIP_9195 5 | |
604 | #define CHIP_9196 6 | |
605 | #define CHIP_91100 7 | |
606 | #define CHIP_91100FD 8 | |
607 | #define CHIP_91111FD 9 | |
608 | ||
609 | #if 0 | |
610 | static const char * chip_ids[ 15 ] = { | |
611 | NULL, NULL, NULL, | |
612 | /* 3 */ "SMC91C90/91C92", | |
613 | /* 4 */ "SMC91C94", | |
614 | /* 5 */ "SMC91C95", | |
615 | /* 6 */ "SMC91C96", | |
616 | /* 7 */ "SMC91C100", | |
617 | /* 8 */ "SMC91C100FD", | |
618 | /* 9 */ "SMC91C111", | |
619 | NULL, NULL, | |
620 | NULL, NULL, NULL}; | |
621 | #endif | |
622 | ||
623 | /* | |
624 | . Transmit status bits | |
625 | */ | |
626 | #define TS_SUCCESS 0x0001 | |
627 | #define TS_LOSTCAR 0x0400 | |
628 | #define TS_LATCOL 0x0200 | |
629 | #define TS_16COL 0x0010 | |
630 | ||
631 | /* | |
632 | . Receive status bits | |
633 | */ | |
634 | #define RS_ALGNERR 0x8000 | |
635 | #define RS_BRODCAST 0x4000 | |
636 | #define RS_BADCRC 0x2000 | |
637 | #define RS_ODDFRAME 0x1000 /* bug: the LAN91C111 never sets this on receive */ | |
638 | #define RS_TOOLONG 0x0800 | |
639 | #define RS_TOOSHORT 0x0400 | |
640 | #define RS_MULTICAST 0x0001 | |
641 | #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) | |
642 | ||
643 | ||
644 | /* PHY Types */ | |
645 | enum { | |
646 | PHY_LAN83C183 = 1, /* LAN91C111 Internal PHY */ | |
647 | PHY_LAN83C180 | |
648 | }; | |
649 | ||
650 | ||
651 | /* PHY Register Addresses (LAN91C111 Internal PHY) */ | |
652 | ||
653 | /* PHY Control Register */ | |
654 | #define PHY_CNTL_REG 0x00 | |
655 | #define PHY_CNTL_RST 0x8000 /* 1=PHY Reset */ | |
656 | #define PHY_CNTL_LPBK 0x4000 /* 1=PHY Loopback */ | |
657 | #define PHY_CNTL_SPEED 0x2000 /* 1=100Mbps, 0=10Mpbs */ | |
658 | #define PHY_CNTL_ANEG_EN 0x1000 /* 1=Enable Auto negotiation */ | |
659 | #define PHY_CNTL_PDN 0x0800 /* 1=PHY Power Down mode */ | |
660 | #define PHY_CNTL_MII_DIS 0x0400 /* 1=MII 4 bit interface disabled */ | |
661 | #define PHY_CNTL_ANEG_RST 0x0200 /* 1=Reset Auto negotiate */ | |
662 | #define PHY_CNTL_DPLX 0x0100 /* 1=Full Duplex, 0=Half Duplex */ | |
663 | #define PHY_CNTL_COLTST 0x0080 /* 1= MII Colision Test */ | |
664 | ||
665 | /* PHY Status Register */ | |
666 | #define PHY_STAT_REG 0x01 | |
667 | #define PHY_STAT_CAP_T4 0x8000 /* 1=100Base-T4 capable */ | |
668 | #define PHY_STAT_CAP_TXF 0x4000 /* 1=100Base-X full duplex capable */ | |
669 | #define PHY_STAT_CAP_TXH 0x2000 /* 1=100Base-X half duplex capable */ | |
670 | #define PHY_STAT_CAP_TF 0x1000 /* 1=10Mbps full duplex capable */ | |
671 | #define PHY_STAT_CAP_TH 0x0800 /* 1=10Mbps half duplex capable */ | |
672 | #define PHY_STAT_CAP_SUPR 0x0040 /* 1=recv mgmt frames with not preamble */ | |
673 | #define PHY_STAT_ANEG_ACK 0x0020 /* 1=ANEG has completed */ | |
674 | #define PHY_STAT_REM_FLT 0x0010 /* 1=Remote Fault detected */ | |
675 | #define PHY_STAT_CAP_ANEG 0x0008 /* 1=Auto negotiate capable */ | |
676 | #define PHY_STAT_LINK 0x0004 /* 1=valid link */ | |
677 | #define PHY_STAT_JAB 0x0002 /* 1=10Mbps jabber condition */ | |
678 | #define PHY_STAT_EXREG 0x0001 /* 1=extended registers implemented */ | |
679 | ||
680 | /* PHY Identifier Registers */ | |
681 | #define PHY_ID1_REG 0x02 /* PHY Identifier 1 */ | |
682 | #define PHY_ID2_REG 0x03 /* PHY Identifier 2 */ | |
683 | ||
684 | /* PHY Auto-Negotiation Advertisement Register */ | |
685 | #define PHY_AD_REG 0x04 | |
686 | #define PHY_AD_NP 0x8000 /* 1=PHY requests exchange of Next Page */ | |
687 | #define PHY_AD_ACK 0x4000 /* 1=got link code word from remote */ | |
688 | #define PHY_AD_RF 0x2000 /* 1=advertise remote fault */ | |
689 | #define PHY_AD_T4 0x0200 /* 1=PHY is capable of 100Base-T4 */ | |
690 | #define PHY_AD_TX_FDX 0x0100 /* 1=PHY is capable of 100Base-TX FDPLX */ | |
691 | #define PHY_AD_TX_HDX 0x0080 /* 1=PHY is capable of 100Base-TX HDPLX */ | |
692 | #define PHY_AD_10_FDX 0x0040 /* 1=PHY is capable of 10Base-T FDPLX */ | |
693 | #define PHY_AD_10_HDX 0x0020 /* 1=PHY is capable of 10Base-T HDPLX */ | |
694 | #define PHY_AD_CSMA 0x0001 /* 1=PHY is capable of 802.3 CMSA */ | |
695 | ||
696 | /* PHY Auto-negotiation Remote End Capability Register */ | |
697 | #define PHY_RMT_REG 0x05 | |
698 | /* Uses same bit definitions as PHY_AD_REG */ | |
699 | ||
700 | /* PHY Configuration Register 1 */ | |
701 | #define PHY_CFG1_REG 0x10 | |
702 | #define PHY_CFG1_LNKDIS 0x8000 /* 1=Rx Link Detect Function disabled */ | |
703 | #define PHY_CFG1_XMTDIS 0x4000 /* 1=TP Transmitter Disabled */ | |
704 | #define PHY_CFG1_XMTPDN 0x2000 /* 1=TP Transmitter Powered Down */ | |
705 | #define PHY_CFG1_BYPSCR 0x0400 /* 1=Bypass scrambler/descrambler */ | |
706 | #define PHY_CFG1_UNSCDS 0x0200 /* 1=Unscramble Idle Reception Disable */ | |
707 | #define PHY_CFG1_EQLZR 0x0100 /* 1=Rx Equalizer Disabled */ | |
708 | #define PHY_CFG1_CABLE 0x0080 /* 1=STP(150ohm), 0=UTP(100ohm) */ | |
709 | #define PHY_CFG1_RLVL0 0x0040 /* 1=Rx Squelch level reduced by 4.5db */ | |
710 | #define PHY_CFG1_TLVL_SHIFT 2 /* Transmit Output Level Adjust */ | |
711 | #define PHY_CFG1_TLVL_MASK 0x003C | |
712 | #define PHY_CFG1_TRF_MASK 0x0003 /* Transmitter Rise/Fall time */ | |
713 | ||
714 | ||
715 | /* PHY Configuration Register 2 */ | |
716 | #define PHY_CFG2_REG 0x11 | |
717 | #define PHY_CFG2_APOLDIS 0x0020 /* 1=Auto Polarity Correction disabled */ | |
718 | #define PHY_CFG2_JABDIS 0x0010 /* 1=Jabber disabled */ | |
719 | #define PHY_CFG2_MREG 0x0008 /* 1=Multiple register access (MII mgt) */ | |
720 | #define PHY_CFG2_INTMDIO 0x0004 /* 1=Interrupt signaled with MDIO pulseo */ | |
721 | ||
722 | /* PHY Status Output (and Interrupt status) Register */ | |
723 | #define PHY_INT_REG 0x12 /* Status Output (Interrupt Status) */ | |
724 | #define PHY_INT_INT 0x8000 /* 1=bits have changed since last read */ | |
725 | #define PHY_INT_LNKFAIL 0x4000 /* 1=Link Not detected */ | |
726 | #define PHY_INT_LOSSSYNC 0x2000 /* 1=Descrambler has lost sync */ | |
727 | #define PHY_INT_CWRD 0x1000 /* 1=Invalid 4B5B code detected on rx */ | |
728 | #define PHY_INT_SSD 0x0800 /* 1=No Start Of Stream detected on rx */ | |
729 | #define PHY_INT_ESD 0x0400 /* 1=No End Of Stream detected on rx */ | |
730 | #define PHY_INT_RPOL 0x0200 /* 1=Reverse Polarity detected */ | |
731 | #define PHY_INT_JAB 0x0100 /* 1=Jabber detected */ | |
732 | #define PHY_INT_SPDDET 0x0080 /* 1=100Base-TX mode, 0=10Base-T mode */ | |
733 | #define PHY_INT_DPLXDET 0x0040 /* 1=Device in Full Duplex */ | |
734 | ||
735 | /* PHY Interrupt/Status Mask Register */ | |
736 | #define PHY_MASK_REG 0x13 /* Interrupt Mask */ | |
737 | /* Uses the same bit definitions as PHY_INT_REG */ | |
738 | ||
739 | ||
fe8c2806 WD |
740 | /*------------------------------------------------------------------------- |
741 | . I define some macros to make it easier to do somewhat common | |
742 | . or slightly complicated, repeated tasks. | |
743 | --------------------------------------------------------------------------*/ | |
744 | ||
745 | /* select a register bank, 0 to 3 */ | |
746 | ||
7194ab80 | 747 | #define SMC_SELECT_BANK(a,x) { SMC_outw((a), (x), BANK_SELECT ); } |
fe8c2806 WD |
748 | |
749 | /* this enables an interrupt in the interrupt mask register */ | |
7194ab80 | 750 | #define SMC_ENABLE_INT(a,x) {\ |
fe8c2806 | 751 | unsigned char mask;\ |
7194ab80 BW |
752 | SMC_SELECT_BANK((a),2);\ |
753 | mask = SMC_inb((a), IM_REG );\ | |
fe8c2806 | 754 | mask |= (x);\ |
7194ab80 | 755 | SMC_outb( (a), mask, IM_REG ); \ |
fe8c2806 WD |
756 | } |
757 | ||
758 | /* this disables an interrupt from the interrupt mask register */ | |
759 | ||
7194ab80 | 760 | #define SMC_DISABLE_INT(a,x) {\ |
fe8c2806 WD |
761 | unsigned char mask;\ |
762 | SMC_SELECT_BANK(2);\ | |
7194ab80 | 763 | mask = SMC_inb( (a), IM_REG );\ |
fe8c2806 | 764 | mask &= ~(x);\ |
7194ab80 | 765 | SMC_outb( (a), mask, IM_REG ); \ |
fe8c2806 WD |
766 | } |
767 | ||
768 | /*---------------------------------------------------------------------- | |
769 | . Define the interrupts that I want to receive from the card | |
770 | . | |
771 | . I want: | |
772 | . IM_EPH_INT, for nasty errors | |
773 | . IM_RCV_INT, for happy received packets | |
774 | . IM_RX_OVRN_INT, because I have to kick the receiver | |
775 | . IM_MDINT, for PHY Register 18 Status Changes | |
776 | --------------------------------------------------------------------------*/ | |
777 | #define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | \ | |
778 | IM_MDINT) | |
779 | ||
780 | #endif /* _SMC_91111_H_ */ |