]>
Commit | Line | Data |
---|---|---|
de1b686b SH |
1 | /* |
2 | * SMSC LAN9[12]1[567] Network driver | |
3 | * | |
cce9cfda | 4 | * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> |
de1b686b | 5 | * |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
de1b686b SH |
7 | */ |
8 | ||
9 | #include <common.h> | |
de1b686b | 10 | #include <command.h> |
736fead8 | 11 | #include <malloc.h> |
de1b686b SH |
12 | #include <net.h> |
13 | #include <miiphy.h> | |
14 | ||
75ba6d69 | 15 | #include "smc911x.h" |
de1b686b | 16 | |
736fead8 | 17 | u32 pkt_data_pull(struct eth_device *dev, u32 addr) \ |
890a02e8 | 18 | __attribute__ ((weak, alias ("smc911x_reg_read"))); |
736fead8 | 19 | void pkt_data_push(struct eth_device *dev, u32 addr, u32 val) \ |
890a02e8 | 20 | __attribute__ ((weak, alias ("smc911x_reg_write"))); |
33314470 | 21 | |
45b6b65c | 22 | static void smc911x_handle_mac_address(struct eth_device *dev) |
de1b686b SH |
23 | { |
24 | unsigned long addrh, addrl; | |
736fead8 | 25 | uchar *m = dev->enetaddr; |
de1b686b | 26 | |
736fead8 BW |
27 | addrl = m[0] | (m[1] << 8) | (m[2] << 16) | (m[3] << 24); |
28 | addrh = m[4] | (m[5] << 8); | |
29 | smc911x_set_mac_csr(dev, ADDRL, addrl); | |
30 | smc911x_set_mac_csr(dev, ADDRH, addrh); | |
de1b686b | 31 | |
736fead8 | 32 | printf(DRIVERNAME ": MAC %pM\n", m); |
de1b686b SH |
33 | } |
34 | ||
6af1d41a | 35 | static int smc911x_eth_phy_read(struct eth_device *dev, |
736fead8 | 36 | u8 phy, u8 reg, u16 *val) |
de1b686b | 37 | { |
736fead8 | 38 | while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY) |
3e0f331c | 39 | ; |
de1b686b | 40 | |
736fead8 BW |
41 | smc911x_set_mac_csr(dev, MII_ACC, phy << 11 | reg << 6 | |
42 | MII_ACC_MII_BUSY); | |
de1b686b | 43 | |
736fead8 | 44 | while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY) |
3e0f331c | 45 | ; |
de1b686b | 46 | |
736fead8 | 47 | *val = smc911x_get_mac_csr(dev, MII_DATA); |
de1b686b SH |
48 | |
49 | return 0; | |
50 | } | |
51 | ||
6af1d41a | 52 | static int smc911x_eth_phy_write(struct eth_device *dev, |
736fead8 | 53 | u8 phy, u8 reg, u16 val) |
de1b686b | 54 | { |
736fead8 | 55 | while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY) |
3e0f331c | 56 | ; |
de1b686b | 57 | |
736fead8 BW |
58 | smc911x_set_mac_csr(dev, MII_DATA, val); |
59 | smc911x_set_mac_csr(dev, MII_ACC, | |
de1b686b SH |
60 | phy << 11 | reg << 6 | MII_ACC_MII_BUSY | MII_ACC_MII_WRITE); |
61 | ||
736fead8 | 62 | while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY) |
3e0f331c | 63 | ; |
de1b686b SH |
64 | return 0; |
65 | } | |
66 | ||
736fead8 | 67 | static int smc911x_phy_reset(struct eth_device *dev) |
de1b686b SH |
68 | { |
69 | u32 reg; | |
70 | ||
736fead8 | 71 | reg = smc911x_reg_read(dev, PMT_CTRL); |
de1b686b SH |
72 | reg &= ~0xfffff030; |
73 | reg |= PMT_CTRL_PHY_RST; | |
736fead8 | 74 | smc911x_reg_write(dev, PMT_CTRL, reg); |
de1b686b SH |
75 | |
76 | mdelay(100); | |
77 | ||
78 | return 0; | |
79 | } | |
80 | ||
736fead8 | 81 | static void smc911x_phy_configure(struct eth_device *dev) |
de1b686b SH |
82 | { |
83 | int timeout; | |
84 | u16 status; | |
85 | ||
736fead8 | 86 | smc911x_phy_reset(dev); |
de1b686b | 87 | |
6af1d41a | 88 | smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_RESET); |
de1b686b | 89 | mdelay(1); |
6af1d41a HR |
90 | smc911x_eth_phy_write(dev, 1, MII_ADVERTISE, 0x01e1); |
91 | smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_ANENABLE | | |
8ef583a0 | 92 | BMCR_ANRESTART); |
de1b686b SH |
93 | |
94 | timeout = 5000; | |
95 | do { | |
96 | mdelay(1); | |
97 | if ((timeout--) == 0) | |
98 | goto err_out; | |
99 | ||
6af1d41a | 100 | if (smc911x_eth_phy_read(dev, 1, MII_BMSR, &status) != 0) |
de1b686b | 101 | goto err_out; |
8ef583a0 | 102 | } while (!(status & BMSR_LSTATUS)); |
de1b686b SH |
103 | |
104 | printf(DRIVERNAME ": phy initialized\n"); | |
105 | ||
106 | return; | |
107 | ||
108 | err_out: | |
109 | printf(DRIVERNAME ": autonegotiation timed out\n"); | |
110 | } | |
111 | ||
736fead8 | 112 | static void smc911x_enable(struct eth_device *dev) |
de1b686b SH |
113 | { |
114 | /* Enable TX */ | |
736fead8 | 115 | smc911x_reg_write(dev, HW_CFG, 8 << 16 | HW_CFG_SF); |
de1b686b | 116 | |
736fead8 | 117 | smc911x_reg_write(dev, GPT_CFG, GPT_CFG_TIMER_EN | 10000); |
de1b686b | 118 | |
736fead8 | 119 | smc911x_reg_write(dev, TX_CFG, TX_CFG_TX_ON); |
de1b686b SH |
120 | |
121 | /* no padding to start of packets */ | |
736fead8 | 122 | smc911x_reg_write(dev, RX_CFG, 0); |
de1b686b | 123 | |
736fead8 BW |
124 | smc911x_set_mac_csr(dev, MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN | |
125 | MAC_CR_HBDIS); | |
de1b686b SH |
126 | |
127 | } | |
128 | ||
736fead8 | 129 | static int smc911x_init(struct eth_device *dev, bd_t * bd) |
de1b686b | 130 | { |
2a6cc97b | 131 | struct chip_id *id = dev->priv; |
de1b686b | 132 | |
4946775c | 133 | printf(DRIVERNAME ": detected %s controller\n", id->name); |
de1b686b | 134 | |
736fead8 | 135 | smc911x_reset(dev); |
de1b686b SH |
136 | |
137 | /* Configure the PHY, initialize the link state */ | |
736fead8 | 138 | smc911x_phy_configure(dev); |
de1b686b | 139 | |
45b6b65c | 140 | smc911x_handle_mac_address(dev); |
de1b686b SH |
141 | |
142 | /* Turn on Tx + Rx */ | |
736fead8 | 143 | smc911x_enable(dev); |
de1b686b SH |
144 | |
145 | return 0; | |
de1b686b SH |
146 | } |
147 | ||
fd89b61b | 148 | static int smc911x_send(struct eth_device *dev, void *packet, int length) |
de1b686b SH |
149 | { |
150 | u32 *data = (u32*)packet; | |
151 | u32 tmplen; | |
152 | u32 status; | |
153 | ||
736fead8 BW |
154 | smc911x_reg_write(dev, TX_DATA_FIFO, TX_CMD_A_INT_FIRST_SEG | |
155 | TX_CMD_A_INT_LAST_SEG | length); | |
156 | smc911x_reg_write(dev, TX_DATA_FIFO, length); | |
de1b686b SH |
157 | |
158 | tmplen = (length + 3) / 4; | |
159 | ||
3e0f331c | 160 | while (tmplen--) |
736fead8 | 161 | pkt_data_push(dev, TX_DATA_FIFO, *data++); |
de1b686b SH |
162 | |
163 | /* wait for transmission */ | |
736fead8 BW |
164 | while (!((smc911x_reg_read(dev, TX_FIFO_INF) & |
165 | TX_FIFO_INF_TSUSED) >> 16)); | |
de1b686b SH |
166 | |
167 | /* get status. Ignore 'no carrier' error, it has no meaning for | |
168 | * full duplex operation | |
169 | */ | |
736fead8 BW |
170 | status = smc911x_reg_read(dev, TX_STATUS_FIFO) & |
171 | (TX_STS_LOC | TX_STS_LATE_COLL | TX_STS_MANY_COLL | | |
172 | TX_STS_MANY_DEFER | TX_STS_UNDERRUN); | |
de1b686b | 173 | |
3e0f331c | 174 | if (!status) |
de1b686b SH |
175 | return 0; |
176 | ||
177 | printf(DRIVERNAME ": failed to send packet: %s%s%s%s%s\n", | |
178 | status & TX_STS_LOC ? "TX_STS_LOC " : "", | |
179 | status & TX_STS_LATE_COLL ? "TX_STS_LATE_COLL " : "", | |
180 | status & TX_STS_MANY_COLL ? "TX_STS_MANY_COLL " : "", | |
181 | status & TX_STS_MANY_DEFER ? "TX_STS_MANY_DEFER " : "", | |
182 | status & TX_STS_UNDERRUN ? "TX_STS_UNDERRUN" : ""); | |
183 | ||
184 | return -1; | |
185 | } | |
186 | ||
736fead8 | 187 | static void smc911x_halt(struct eth_device *dev) |
de1b686b | 188 | { |
736fead8 | 189 | smc911x_reset(dev); |
99dd6ab4 | 190 | smc911x_handle_mac_address(dev); |
de1b686b SH |
191 | } |
192 | ||
736fead8 | 193 | static int smc911x_rx(struct eth_device *dev) |
de1b686b | 194 | { |
1fd92db8 | 195 | u32 *data = (u32 *)net_rx_packets[0]; |
de1b686b SH |
196 | u32 pktlen, tmplen; |
197 | u32 status; | |
198 | ||
736fead8 BW |
199 | if ((smc911x_reg_read(dev, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED) >> 16) { |
200 | status = smc911x_reg_read(dev, RX_STATUS_FIFO); | |
de1b686b SH |
201 | pktlen = (status & RX_STS_PKT_LEN) >> 16; |
202 | ||
736fead8 | 203 | smc911x_reg_write(dev, RX_CFG, 0); |
de1b686b | 204 | |
bd75db3f | 205 | tmplen = (pktlen + 3) / 4; |
3e0f331c | 206 | while (tmplen--) |
736fead8 | 207 | *data++ = pkt_data_pull(dev, RX_DATA_FIFO); |
de1b686b | 208 | |
3e0f331c | 209 | if (status & RX_STS_ES) |
de1b686b SH |
210 | printf(DRIVERNAME |
211 | ": dropped bad packet. Status: 0x%08x\n", | |
212 | status); | |
213 | else | |
1fd92db8 | 214 | net_process_received_packet(net_rx_packets[0], pktlen); |
de1b686b SH |
215 | } |
216 | ||
217 | return 0; | |
218 | } | |
736fead8 | 219 | |
6af1d41a HR |
220 | #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
221 | /* wrapper for smc911x_eth_phy_read */ | |
5a49f174 JH |
222 | static int smc911x_miiphy_read(struct mii_dev *bus, int phy, int devad, |
223 | int reg) | |
6af1d41a | 224 | { |
5a49f174 JH |
225 | u16 val = 0; |
226 | struct eth_device *dev = eth_get_dev_by_name(bus->name); | |
227 | if (dev) { | |
228 | int retval = smc911x_eth_phy_read(dev, phy, reg, &val); | |
229 | if (retval < 0) | |
230 | return retval; | |
231 | return val; | |
232 | } | |
875e0bc6 | 233 | return -ENODEV; |
6af1d41a HR |
234 | } |
235 | /* wrapper for smc911x_eth_phy_write */ | |
5a49f174 JH |
236 | static int smc911x_miiphy_write(struct mii_dev *bus, int phy, int devad, |
237 | int reg, u16 val) | |
6af1d41a | 238 | { |
5a49f174 | 239 | struct eth_device *dev = eth_get_dev_by_name(bus->name); |
6af1d41a HR |
240 | if (dev) |
241 | return smc911x_eth_phy_write(dev, phy, reg, val); | |
875e0bc6 | 242 | return -ENODEV; |
6af1d41a HR |
243 | } |
244 | #endif | |
245 | ||
736fead8 BW |
246 | int smc911x_initialize(u8 dev_num, int base_addr) |
247 | { | |
248 | unsigned long addrl, addrh; | |
249 | struct eth_device *dev; | |
250 | ||
251 | dev = malloc(sizeof(*dev)); | |
252 | if (!dev) { | |
fbd47b67 | 253 | return -1; |
736fead8 BW |
254 | } |
255 | memset(dev, 0, sizeof(*dev)); | |
256 | ||
257 | dev->iobase = base_addr; | |
258 | ||
4bc3d2af SS |
259 | /* Try to detect chip. Will fail if not present. */ |
260 | if (smc911x_detect_chip(dev)) { | |
261 | free(dev); | |
262 | return 0; | |
263 | } | |
264 | ||
736fead8 BW |
265 | addrh = smc911x_get_mac_csr(dev, ADDRH); |
266 | addrl = smc911x_get_mac_csr(dev, ADDRL); | |
76771e59 SR |
267 | if (!(addrl == 0xffffffff && addrh == 0x0000ffff)) { |
268 | /* address is obtained from optional eeprom */ | |
269 | dev->enetaddr[0] = addrl; | |
270 | dev->enetaddr[1] = addrl >> 8; | |
271 | dev->enetaddr[2] = addrl >> 16; | |
272 | dev->enetaddr[3] = addrl >> 24; | |
273 | dev->enetaddr[4] = addrh; | |
274 | dev->enetaddr[5] = addrh >> 8; | |
275 | } | |
736fead8 BW |
276 | |
277 | dev->init = smc911x_init; | |
278 | dev->halt = smc911x_halt; | |
279 | dev->send = smc911x_send; | |
280 | dev->recv = smc911x_rx; | |
281 | sprintf(dev->name, "%s-%hu", DRIVERNAME, dev_num); | |
282 | ||
283 | eth_register(dev); | |
6af1d41a HR |
284 | |
285 | #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) | |
5a49f174 JH |
286 | int retval; |
287 | struct mii_dev *mdiodev = mdio_alloc(); | |
288 | if (!mdiodev) | |
289 | return -ENOMEM; | |
290 | strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); | |
291 | mdiodev->read = smc911x_miiphy_read; | |
292 | mdiodev->write = smc911x_miiphy_write; | |
293 | ||
294 | retval = mdio_register(mdiodev); | |
295 | if (retval < 0) | |
296 | return retval; | |
6af1d41a HR |
297 | #endif |
298 | ||
fbd47b67 | 299 | return 1; |
736fead8 | 300 | } |