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Commit | Line | Data |
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518ce472 | 1 | /* |
b70ed300 | 2 | * sunxi_emac.c -- Allwinner A10 ethernet driver |
518ce472 HN |
3 | * |
4 | * (C) Copyright 2012, Stefan Roese <sr@denx.de> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
518ce472 HN |
7 | */ |
8 | ||
9 | #include <common.h> | |
939ed1cb | 10 | #include <dm.h> |
b70ed300 | 11 | #include <linux/err.h> |
518ce472 | 12 | #include <malloc.h> |
518ce472 | 13 | #include <miiphy.h> |
b70ed300 | 14 | #include <net.h> |
518ce472 HN |
15 | #include <asm/io.h> |
16 | #include <asm/arch/clock.h> | |
17 | #include <asm/arch/gpio.h> | |
18 | ||
19 | /* EMAC register */ | |
b70ed300 | 20 | struct emac_regs { |
518ce472 HN |
21 | u32 ctl; /* 0x00 */ |
22 | u32 tx_mode; /* 0x04 */ | |
23 | u32 tx_flow; /* 0x08 */ | |
24 | u32 tx_ctl0; /* 0x0c */ | |
25 | u32 tx_ctl1; /* 0x10 */ | |
26 | u32 tx_ins; /* 0x14 */ | |
27 | u32 tx_pl0; /* 0x18 */ | |
28 | u32 tx_pl1; /* 0x1c */ | |
29 | u32 tx_sta; /* 0x20 */ | |
30 | u32 tx_io_data; /* 0x24 */ | |
b70ed300 | 31 | u32 tx_io_data1;/* 0x28 */ |
518ce472 HN |
32 | u32 tx_tsvl0; /* 0x2c */ |
33 | u32 tx_tsvh0; /* 0x30 */ | |
34 | u32 tx_tsvl1; /* 0x34 */ | |
35 | u32 tx_tsvh1; /* 0x38 */ | |
36 | u32 rx_ctl; /* 0x3c */ | |
37 | u32 rx_hash0; /* 0x40 */ | |
38 | u32 rx_hash1; /* 0x44 */ | |
39 | u32 rx_sta; /* 0x48 */ | |
40 | u32 rx_io_data; /* 0x4c */ | |
41 | u32 rx_fbc; /* 0x50 */ | |
42 | u32 int_ctl; /* 0x54 */ | |
43 | u32 int_sta; /* 0x58 */ | |
44 | u32 mac_ctl0; /* 0x5c */ | |
45 | u32 mac_ctl1; /* 0x60 */ | |
46 | u32 mac_ipgt; /* 0x64 */ | |
47 | u32 mac_ipgr; /* 0x68 */ | |
48 | u32 mac_clrt; /* 0x6c */ | |
49 | u32 mac_maxf; /* 0x70 */ | |
50 | u32 mac_supp; /* 0x74 */ | |
51 | u32 mac_test; /* 0x78 */ | |
52 | u32 mac_mcfg; /* 0x7c */ | |
53 | u32 mac_mcmd; /* 0x80 */ | |
54 | u32 mac_madr; /* 0x84 */ | |
55 | u32 mac_mwtd; /* 0x88 */ | |
56 | u32 mac_mrdd; /* 0x8c */ | |
57 | u32 mac_mind; /* 0x90 */ | |
58 | u32 mac_ssrr; /* 0x94 */ | |
59 | u32 mac_a0; /* 0x98 */ | |
60 | u32 mac_a1; /* 0x9c */ | |
61 | }; | |
62 | ||
63 | /* SRAMC register */ | |
64 | struct sunxi_sramc_regs { | |
65 | u32 ctrl0; | |
66 | u32 ctrl1; | |
67 | }; | |
68 | ||
69 | /* 0: Disable 1: Aborted frame enable(default) */ | |
70 | #define EMAC_TX_AB_M (0x1 << 0) | |
71 | /* 0: CPU 1: DMA(default) */ | |
72 | #define EMAC_TX_TM (0x1 << 1) | |
73 | ||
74 | #define EMAC_TX_SETUP (0) | |
75 | ||
76 | /* 0: DRQ asserted 1: DRQ automatically(default) */ | |
77 | #define EMAC_RX_DRQ_MODE (0x1 << 1) | |
78 | /* 0: CPU 1: DMA(default) */ | |
79 | #define EMAC_RX_TM (0x1 << 2) | |
80 | /* 0: Normal(default) 1: Pass all Frames */ | |
81 | #define EMAC_RX_PA (0x1 << 4) | |
82 | /* 0: Normal(default) 1: Pass Control Frames */ | |
83 | #define EMAC_RX_PCF (0x1 << 5) | |
84 | /* 0: Normal(default) 1: Pass Frames with CRC Error */ | |
85 | #define EMAC_RX_PCRCE (0x1 << 6) | |
86 | /* 0: Normal(default) 1: Pass Frames with Length Error */ | |
87 | #define EMAC_RX_PLE (0x1 << 7) | |
88 | /* 0: Normal 1: Pass Frames length out of range(default) */ | |
89 | #define EMAC_RX_POR (0x1 << 8) | |
90 | /* 0: Not accept 1: Accept unicast Packets(default) */ | |
91 | #define EMAC_RX_UCAD (0x1 << 16) | |
92 | /* 0: Normal(default) 1: DA Filtering */ | |
93 | #define EMAC_RX_DAF (0x1 << 17) | |
94 | /* 0: Not accept 1: Accept multicast Packets(default) */ | |
95 | #define EMAC_RX_MCO (0x1 << 20) | |
96 | /* 0: Disable(default) 1: Enable Hash filter */ | |
97 | #define EMAC_RX_MHF (0x1 << 21) | |
98 | /* 0: Not accept 1: Accept Broadcast Packets(default) */ | |
99 | #define EMAC_RX_BCO (0x1 << 22) | |
100 | /* 0: Disable(default) 1: Enable SA Filtering */ | |
101 | #define EMAC_RX_SAF (0x1 << 24) | |
102 | /* 0: Normal(default) 1: Inverse Filtering */ | |
103 | #define EMAC_RX_SAIF (0x1 << 25) | |
104 | ||
105 | #define EMAC_RX_SETUP (EMAC_RX_POR | EMAC_RX_UCAD | EMAC_RX_DAF | \ | |
106 | EMAC_RX_MCO | EMAC_RX_BCO) | |
107 | ||
108 | /* 0: Disable 1: Enable Receive Flow Control(default) */ | |
109 | #define EMAC_MAC_CTL0_RFC (0x1 << 2) | |
110 | /* 0: Disable 1: Enable Transmit Flow Control(default) */ | |
111 | #define EMAC_MAC_CTL0_TFC (0x1 << 3) | |
112 | ||
113 | #define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC) | |
114 | ||
115 | /* 0: Disable 1: Enable MAC Frame Length Checking(default) */ | |
116 | #define EMAC_MAC_CTL1_FLC (0x1 << 1) | |
117 | /* 0: Disable(default) 1: Enable Huge Frame */ | |
118 | #define EMAC_MAC_CTL1_HF (0x1 << 2) | |
119 | /* 0: Disable(default) 1: Enable MAC Delayed CRC */ | |
120 | #define EMAC_MAC_CTL1_DCRC (0x1 << 3) | |
121 | /* 0: Disable 1: Enable MAC CRC(default) */ | |
122 | #define EMAC_MAC_CTL1_CRC (0x1 << 4) | |
123 | /* 0: Disable 1: Enable MAC PAD Short frames(default) */ | |
124 | #define EMAC_MAC_CTL1_PC (0x1 << 5) | |
125 | /* 0: Disable(default) 1: Enable MAC PAD Short frames and append CRC */ | |
126 | #define EMAC_MAC_CTL1_VC (0x1 << 6) | |
127 | /* 0: Disable(default) 1: Enable MAC auto detect Short frames */ | |
128 | #define EMAC_MAC_CTL1_ADP (0x1 << 7) | |
129 | /* 0: Disable(default) 1: Enable */ | |
130 | #define EMAC_MAC_CTL1_PRE (0x1 << 8) | |
131 | /* 0: Disable(default) 1: Enable */ | |
132 | #define EMAC_MAC_CTL1_LPE (0x1 << 9) | |
133 | /* 0: Disable(default) 1: Enable no back off */ | |
134 | #define EMAC_MAC_CTL1_NB (0x1 << 12) | |
135 | /* 0: Disable(default) 1: Enable */ | |
136 | #define EMAC_MAC_CTL1_BNB (0x1 << 13) | |
137 | /* 0: Disable(default) 1: Enable */ | |
138 | #define EMAC_MAC_CTL1_ED (0x1 << 14) | |
139 | ||
140 | #define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \ | |
141 | EMAC_MAC_CTL1_PC) | |
142 | ||
143 | #define EMAC_MAC_IPGT 0x15 | |
144 | ||
b70ed300 | 145 | #define EMAC_MAC_NBTB_IPG1 0xc |
518ce472 HN |
146 | #define EMAC_MAC_NBTB_IPG2 0x12 |
147 | ||
148 | #define EMAC_MAC_CW 0x37 | |
b70ed300 | 149 | #define EMAC_MAC_RM 0xf |
518ce472 HN |
150 | |
151 | #define EMAC_MAC_MFL 0x0600 | |
152 | ||
153 | /* Receive status */ | |
b70ed300 SR |
154 | #define EMAC_CRCERR (0x1 << 4) |
155 | #define EMAC_LENERR (0x3 << 5) | |
518ce472 | 156 | |
d88c2f11 | 157 | #define EMAC_RX_BUFSIZE 2000 |
518ce472 | 158 | |
b70ed300 | 159 | struct emac_eth_dev { |
8145dea4 HG |
160 | struct emac_regs *regs; |
161 | struct mii_dev *bus; | |
162 | struct phy_device *phydev; | |
518ce472 | 163 | int link_printed; |
939ed1cb HG |
164 | #ifdef CONFIG_DM_ETH |
165 | uchar rx_buf[EMAC_RX_BUFSIZE]; | |
166 | #endif | |
518ce472 HN |
167 | }; |
168 | ||
b70ed300 | 169 | struct emac_rxhdr { |
518ce472 HN |
170 | s16 rx_len; |
171 | u16 rx_status; | |
172 | }; | |
173 | ||
b70ed300 | 174 | static void emac_inblk_32bit(void *reg, void *data, int count) |
518ce472 HN |
175 | { |
176 | int cnt = (count + 3) >> 2; | |
177 | ||
178 | if (cnt) { | |
179 | u32 *buf = data; | |
180 | ||
181 | do { | |
182 | u32 x = readl(reg); | |
183 | *buf++ = x; | |
184 | } while (--cnt); | |
185 | } | |
186 | } | |
187 | ||
b70ed300 | 188 | static void emac_outblk_32bit(void *reg, void *data, int count) |
518ce472 HN |
189 | { |
190 | int cnt = (count + 3) >> 2; | |
191 | ||
192 | if (cnt) { | |
193 | const u32 *buf = data; | |
194 | ||
195 | do { | |
196 | writel(*buf++, reg); | |
197 | } while (--cnt); | |
198 | } | |
199 | } | |
200 | ||
b70ed300 | 201 | /* Read a word from phyxcer */ |
8145dea4 | 202 | static int emac_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) |
518ce472 | 203 | { |
8145dea4 HG |
204 | struct emac_eth_dev *priv = bus->priv; |
205 | struct emac_regs *regs = priv->regs; | |
518ce472 HN |
206 | |
207 | /* issue the phy address and reg */ | |
208 | writel(addr << 8 | reg, ®s->mac_madr); | |
209 | ||
210 | /* pull up the phy io line */ | |
211 | writel(0x1, ®s->mac_mcmd); | |
212 | ||
213 | /* Wait read complete */ | |
214 | mdelay(1); | |
215 | ||
216 | /* push down the phy io line */ | |
217 | writel(0x0, ®s->mac_mcmd); | |
218 | ||
8145dea4 HG |
219 | /* And read data */ |
220 | return readl(®s->mac_mrdd); | |
518ce472 HN |
221 | } |
222 | ||
b70ed300 | 223 | /* Write a word to phyxcer */ |
8145dea4 HG |
224 | static int emac_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, |
225 | u16 value) | |
518ce472 | 226 | { |
8145dea4 HG |
227 | struct emac_eth_dev *priv = bus->priv; |
228 | struct emac_regs *regs = priv->regs; | |
518ce472 HN |
229 | |
230 | /* issue the phy address and reg */ | |
231 | writel(addr << 8 | reg, ®s->mac_madr); | |
232 | ||
233 | /* pull up the phy io line */ | |
234 | writel(0x1, ®s->mac_mcmd); | |
235 | ||
236 | /* Wait write complete */ | |
237 | mdelay(1); | |
238 | ||
239 | /* push down the phy io line */ | |
240 | writel(0x0, ®s->mac_mcmd); | |
241 | ||
242 | /* and write data */ | |
243 | writel(value, ®s->mac_mwtd); | |
244 | ||
245 | return 0; | |
246 | } | |
247 | ||
8145dea4 | 248 | static int sunxi_emac_init_phy(struct emac_eth_dev *priv, void *dev) |
518ce472 | 249 | { |
8145dea4 HG |
250 | int ret, mask = 0xffffffff; |
251 | ||
252 | #ifdef CONFIG_PHY_ADDR | |
253 | mask = 1 << CONFIG_PHY_ADDR; | |
254 | #endif | |
255 | ||
256 | priv->bus = mdio_alloc(); | |
257 | if (!priv->bus) { | |
258 | printf("Failed to allocate MDIO bus\n"); | |
259 | return -ENOMEM; | |
260 | } | |
261 | ||
262 | priv->bus->read = emac_mdio_read; | |
263 | priv->bus->write = emac_mdio_write; | |
264 | priv->bus->priv = priv; | |
265 | strcpy(priv->bus->name, "emac"); | |
266 | ||
267 | ret = mdio_register(priv->bus); | |
268 | if (ret) | |
269 | return ret; | |
270 | ||
271 | priv->phydev = phy_find_by_mask(priv->bus, mask, | |
272 | PHY_INTERFACE_MODE_MII); | |
273 | if (!priv->phydev) | |
274 | return -ENODEV; | |
275 | ||
276 | phy_connect_dev(priv->phydev, dev); | |
277 | phy_config(priv->phydev); | |
278 | ||
279 | return 0; | |
280 | } | |
281 | ||
282 | static void emac_setup(struct emac_eth_dev *priv) | |
283 | { | |
284 | struct emac_regs *regs = priv->regs; | |
518ce472 | 285 | u32 reg_val; |
518ce472 HN |
286 | |
287 | /* Set up TX */ | |
288 | writel(EMAC_TX_SETUP, ®s->tx_mode); | |
289 | ||
290 | /* Set up RX */ | |
291 | writel(EMAC_RX_SETUP, ®s->rx_ctl); | |
292 | ||
293 | /* Set MAC */ | |
294 | /* Set MAC CTL0 */ | |
295 | writel(EMAC_MAC_CTL0_SETUP, ®s->mac_ctl0); | |
296 | ||
297 | /* Set MAC CTL1 */ | |
518ce472 | 298 | reg_val = 0; |
8145dea4 | 299 | if (priv->phydev->duplex == DUPLEX_FULL) |
518ce472 HN |
300 | reg_val = (0x1 << 0); |
301 | writel(EMAC_MAC_CTL1_SETUP | reg_val, ®s->mac_ctl1); | |
302 | ||
303 | /* Set up IPGT */ | |
304 | writel(EMAC_MAC_IPGT, ®s->mac_ipgt); | |
305 | ||
306 | /* Set up IPGR */ | |
307 | writel(EMAC_MAC_NBTB_IPG2 | (EMAC_MAC_NBTB_IPG1 << 8), ®s->mac_ipgr); | |
308 | ||
309 | /* Set up Collison window */ | |
310 | writel(EMAC_MAC_RM | (EMAC_MAC_CW << 8), ®s->mac_clrt); | |
311 | ||
312 | /* Set up Max Frame Length */ | |
313 | writel(EMAC_MAC_MFL, ®s->mac_maxf); | |
314 | } | |
315 | ||
f9f62d2d | 316 | static void emac_reset(struct emac_eth_dev *priv) |
518ce472 | 317 | { |
f9f62d2d | 318 | struct emac_regs *regs = priv->regs; |
518ce472 HN |
319 | |
320 | debug("resetting device\n"); | |
321 | ||
322 | /* RESET device */ | |
323 | writel(0, ®s->ctl); | |
324 | udelay(200); | |
325 | ||
326 | writel(1, ®s->ctl); | |
327 | udelay(200); | |
328 | } | |
329 | ||
ace1520c | 330 | static int _sunxi_write_hwaddr(struct emac_eth_dev *priv, u8 *enetaddr) |
331 | { | |
332 | struct emac_regs *regs = priv->regs; | |
333 | u32 enetaddr_lo, enetaddr_hi; | |
334 | ||
335 | enetaddr_lo = enetaddr[2] | (enetaddr[1] << 8) | (enetaddr[0] << 16); | |
336 | enetaddr_hi = enetaddr[5] | (enetaddr[4] << 8) | (enetaddr[3] << 16); | |
337 | ||
338 | writel(enetaddr_hi, ®s->mac_a1); | |
339 | writel(enetaddr_lo, ®s->mac_a0); | |
340 | ||
341 | return 0; | |
342 | } | |
343 | ||
f9f62d2d | 344 | static int _sunxi_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr) |
518ce472 | 345 | { |
f9f62d2d | 346 | struct emac_regs *regs = priv->regs; |
8145dea4 | 347 | int ret; |
518ce472 HN |
348 | |
349 | /* Init EMAC */ | |
350 | ||
351 | /* Flush RX FIFO */ | |
352 | setbits_le32(®s->rx_ctl, 0x8); | |
353 | udelay(1); | |
354 | ||
355 | /* Init MAC */ | |
356 | ||
357 | /* Soft reset MAC */ | |
b70ed300 | 358 | clrbits_le32(®s->mac_ctl0, 0x1 << 15); |
518ce472 HN |
359 | |
360 | /* Clear RX counter */ | |
361 | writel(0x0, ®s->rx_fbc); | |
362 | udelay(1); | |
363 | ||
364 | /* Set up EMAC */ | |
8145dea4 | 365 | emac_setup(priv); |
518ce472 | 366 | |
ace1520c | 367 | _sunxi_write_hwaddr(priv, enetaddr); |
518ce472 HN |
368 | |
369 | mdelay(1); | |
370 | ||
f9f62d2d | 371 | emac_reset(priv); |
518ce472 HN |
372 | |
373 | /* PHY POWER UP */ | |
8145dea4 HG |
374 | ret = phy_startup(priv->phydev); |
375 | if (ret) { | |
376 | printf("Could not initialize PHY %s\n", | |
377 | priv->phydev->dev->name); | |
378 | return ret; | |
379 | } | |
518ce472 HN |
380 | |
381 | /* Print link status only once */ | |
382 | if (!priv->link_printed) { | |
383 | printf("ENET Speed is %d Mbps - %s duplex connection\n", | |
8145dea4 HG |
384 | priv->phydev->speed, |
385 | priv->phydev->duplex ? "FULL" : "HALF"); | |
518ce472 HN |
386 | priv->link_printed = 1; |
387 | } | |
388 | ||
389 | /* Set EMAC SPEED depend on PHY */ | |
8145dea4 HG |
390 | if (priv->phydev->speed == SPEED_100) |
391 | setbits_le32(®s->mac_supp, 1 << 8); | |
392 | else | |
393 | clrbits_le32(®s->mac_supp, 1 << 8); | |
518ce472 HN |
394 | |
395 | /* Set duplex depend on phy */ | |
8145dea4 HG |
396 | if (priv->phydev->duplex == DUPLEX_FULL) |
397 | setbits_le32(®s->mac_ctl1, 1 << 0); | |
398 | else | |
399 | clrbits_le32(®s->mac_ctl1, 1 << 0); | |
518ce472 HN |
400 | |
401 | /* Enable RX/TX */ | |
402 | setbits_le32(®s->ctl, 0x7); | |
403 | ||
404 | return 0; | |
405 | } | |
406 | ||
f9f62d2d | 407 | static int _sunxi_emac_eth_recv(struct emac_eth_dev *priv, void *packet) |
518ce472 | 408 | { |
f9f62d2d | 409 | struct emac_regs *regs = priv->regs; |
b70ed300 | 410 | struct emac_rxhdr rxhdr; |
518ce472 HN |
411 | u32 rxcount; |
412 | u32 reg_val; | |
413 | int rx_len; | |
414 | int rx_status; | |
415 | int good_packet; | |
416 | ||
417 | /* Check packet ready or not */ | |
418 | ||
b70ed300 | 419 | /* Race warning: The first packet might arrive with |
518ce472 HN |
420 | * the interrupts disabled, but the second will fix |
421 | */ | |
422 | rxcount = readl(®s->rx_fbc); | |
423 | if (!rxcount) { | |
424 | /* Had one stuck? */ | |
425 | rxcount = readl(®s->rx_fbc); | |
426 | if (!rxcount) | |
f9f62d2d | 427 | return -EAGAIN; |
518ce472 HN |
428 | } |
429 | ||
430 | reg_val = readl(®s->rx_io_data); | |
431 | if (reg_val != 0x0143414d) { | |
432 | /* Disable RX */ | |
b70ed300 | 433 | clrbits_le32(®s->ctl, 0x1 << 2); |
518ce472 HN |
434 | |
435 | /* Flush RX FIFO */ | |
b70ed300 SR |
436 | setbits_le32(®s->rx_ctl, 0x1 << 3); |
437 | while (readl(®s->rx_ctl) & (0x1 << 3)) | |
518ce472 HN |
438 | ; |
439 | ||
440 | /* Enable RX */ | |
b70ed300 | 441 | setbits_le32(®s->ctl, 0x1 << 2); |
518ce472 | 442 | |
f9f62d2d | 443 | return -EAGAIN; |
518ce472 HN |
444 | } |
445 | ||
b70ed300 | 446 | /* A packet ready now |
518ce472 HN |
447 | * Get status/length |
448 | */ | |
449 | good_packet = 1; | |
450 | ||
b70ed300 | 451 | emac_inblk_32bit(®s->rx_io_data, &rxhdr, sizeof(rxhdr)); |
518ce472 HN |
452 | |
453 | rx_len = rxhdr.rx_len; | |
454 | rx_status = rxhdr.rx_status; | |
455 | ||
456 | /* Packet Status check */ | |
457 | if (rx_len < 0x40) { | |
458 | good_packet = 0; | |
459 | debug("RX: Bad Packet (runt)\n"); | |
460 | } | |
461 | ||
462 | /* rx_status is identical to RSR register. */ | |
463 | if (0 & rx_status & (EMAC_CRCERR | EMAC_LENERR)) { | |
464 | good_packet = 0; | |
465 | if (rx_status & EMAC_CRCERR) | |
466 | printf("crc error\n"); | |
467 | if (rx_status & EMAC_LENERR) | |
468 | printf("length error\n"); | |
469 | } | |
470 | ||
b70ed300 | 471 | /* Move data from EMAC */ |
518ce472 | 472 | if (good_packet) { |
d88c2f11 | 473 | if (rx_len > EMAC_RX_BUFSIZE) { |
518ce472 | 474 | printf("Received packet is too big (len=%d)\n", rx_len); |
f9f62d2d | 475 | return -EMSGSIZE; |
518ce472 | 476 | } |
f9f62d2d HG |
477 | emac_inblk_32bit((void *)®s->rx_io_data, packet, rx_len); |
478 | return rx_len; | |
518ce472 HN |
479 | } |
480 | ||
f9f62d2d | 481 | return -EIO; /* Bad packet */ |
518ce472 HN |
482 | } |
483 | ||
f9f62d2d HG |
484 | static int _sunxi_emac_eth_send(struct emac_eth_dev *priv, void *packet, |
485 | int len) | |
518ce472 | 486 | { |
f9f62d2d | 487 | struct emac_regs *regs = priv->regs; |
518ce472 HN |
488 | |
489 | /* Select channel 0 */ | |
490 | writel(0, ®s->tx_ins); | |
491 | ||
492 | /* Write packet */ | |
b70ed300 | 493 | emac_outblk_32bit((void *)®s->tx_io_data, packet, len); |
518ce472 HN |
494 | |
495 | /* Set TX len */ | |
496 | writel(len, ®s->tx_pl0); | |
497 | ||
498 | /* Start translate from fifo to phy */ | |
499 | setbits_le32(®s->tx_ctl0, 1); | |
500 | ||
501 | return 0; | |
502 | } | |
503 | ||
f9f62d2d | 504 | static void sunxi_emac_board_setup(struct emac_eth_dev *priv) |
518ce472 HN |
505 | { |
506 | struct sunxi_ccm_reg *const ccm = | |
507 | (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; | |
508 | struct sunxi_sramc_regs *sram = | |
509 | (struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE; | |
f9f62d2d HG |
510 | struct emac_regs *regs = priv->regs; |
511 | int pin; | |
512 | ||
513 | /* Map SRAM to EMAC */ | |
514 | setbits_le32(&sram->ctrl1, 0x5 << 2); | |
515 | ||
516 | /* Configure pin mux settings for MII Ethernet */ | |
517 | for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) | |
518 | sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC); | |
519 | ||
520 | /* Set up clock gating */ | |
521 | setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC); | |
522 | ||
523 | /* Set MII clock */ | |
524 | clrsetbits_le32(®s->mac_mcfg, 0xf << 2, 0xd << 2); | |
525 | } | |
526 | ||
939ed1cb HG |
527 | static int sunxi_emac_eth_start(struct udevice *dev) |
528 | { | |
529 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
530 | ||
531 | return _sunxi_emac_eth_init(dev->priv, pdata->enetaddr); | |
532 | } | |
533 | ||
534 | static int sunxi_emac_eth_send(struct udevice *dev, void *packet, int length) | |
535 | { | |
536 | struct emac_eth_dev *priv = dev_get_priv(dev); | |
537 | ||
538 | return _sunxi_emac_eth_send(priv, packet, length); | |
539 | } | |
540 | ||
a1ca92ea | 541 | static int sunxi_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp) |
939ed1cb HG |
542 | { |
543 | struct emac_eth_dev *priv = dev_get_priv(dev); | |
544 | int rx_len; | |
545 | ||
546 | rx_len = _sunxi_emac_eth_recv(priv, priv->rx_buf); | |
547 | *packetp = priv->rx_buf; | |
548 | ||
549 | return rx_len; | |
550 | } | |
551 | ||
552 | static void sunxi_emac_eth_stop(struct udevice *dev) | |
553 | { | |
554 | /* Nothing to do here */ | |
555 | } | |
556 | ||
557 | static int sunxi_emac_eth_probe(struct udevice *dev) | |
558 | { | |
559 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
560 | struct emac_eth_dev *priv = dev_get_priv(dev); | |
561 | ||
562 | priv->regs = (struct emac_regs *)pdata->iobase; | |
563 | sunxi_emac_board_setup(priv); | |
564 | ||
565 | return sunxi_emac_init_phy(priv, dev); | |
566 | } | |
567 | ||
568 | static const struct eth_ops sunxi_emac_eth_ops = { | |
569 | .start = sunxi_emac_eth_start, | |
570 | .send = sunxi_emac_eth_send, | |
571 | .recv = sunxi_emac_eth_recv, | |
572 | .stop = sunxi_emac_eth_stop, | |
573 | }; | |
574 | ||
575 | static int sunxi_emac_eth_ofdata_to_platdata(struct udevice *dev) | |
576 | { | |
577 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
578 | ||
a821c4af | 579 | pdata->iobase = devfdt_get_addr(dev); |
939ed1cb HG |
580 | |
581 | return 0; | |
582 | } | |
583 | ||
584 | static const struct udevice_id sunxi_emac_eth_ids[] = { | |
585 | { .compatible = "allwinner,sun4i-a10-emac" }, | |
586 | { } | |
587 | }; | |
588 | ||
589 | U_BOOT_DRIVER(eth_sunxi_emac) = { | |
590 | .name = "eth_sunxi_emac", | |
591 | .id = UCLASS_ETH, | |
592 | .of_match = sunxi_emac_eth_ids, | |
593 | .ofdata_to_platdata = sunxi_emac_eth_ofdata_to_platdata, | |
594 | .probe = sunxi_emac_eth_probe, | |
595 | .ops = &sunxi_emac_eth_ops, | |
596 | .priv_auto_alloc_size = sizeof(struct emac_eth_dev), | |
597 | .platdata_auto_alloc_size = sizeof(struct eth_pdata), | |
598 | }; |