[thirdparty/u-boot.git] / drivers / net / sunxi_emac.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * sunxi_emac.c -- Allwinner A10 ethernet driver
 *
 * (C) Copyright 2012, Stefan Roese <sr@denx.de>
 */

#include <common.h>
#include <dm.h>
#include <linux/err.h>
#include <malloc.h>
#include <miiphy.h>
#include <net.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>

/* EMAC register  */
struct emac_regs {
	u32 ctl;	/* 0x00 */
	u32 tx_mode;	/* 0x04 */
	u32 tx_flow;	/* 0x08 */
	u32 tx_ctl0;	/* 0x0c */
	u32 tx_ctl1;	/* 0x10 */
	u32 tx_ins;	/* 0x14 */
	u32 tx_pl0;	/* 0x18 */
	u32 tx_pl1;	/* 0x1c */
	u32 tx_sta;	/* 0x20 */
	u32 tx_io_data;	/* 0x24 */
	u32 tx_io_data1;/* 0x28 */
	u32 tx_tsvl0;	/* 0x2c */
	u32 tx_tsvh0;	/* 0x30 */
	u32 tx_tsvl1;	/* 0x34 */
	u32 tx_tsvh1;	/* 0x38 */
	u32 rx_ctl;	/* 0x3c */
	u32 rx_hash0;	/* 0x40 */
	u32 rx_hash1;	/* 0x44 */
	u32 rx_sta;	/* 0x48 */
	u32 rx_io_data;	/* 0x4c */
	u32 rx_fbc;	/* 0x50 */
	u32 int_ctl;	/* 0x54 */
	u32 int_sta;	/* 0x58 */
	u32 mac_ctl0;	/* 0x5c */
	u32 mac_ctl1;	/* 0x60 */
	u32 mac_ipgt;	/* 0x64 */
	u32 mac_ipgr;	/* 0x68 */
	u32 mac_clrt;	/* 0x6c */
	u32 mac_maxf;	/* 0x70 */
	u32 mac_supp;	/* 0x74 */
	u32 mac_test;	/* 0x78 */
	u32 mac_mcfg;	/* 0x7c */
	u32 mac_mcmd;	/* 0x80 */
	u32 mac_madr;	/* 0x84 */
	u32 mac_mwtd;	/* 0x88 */
	u32 mac_mrdd;	/* 0x8c */
	u32 mac_mind;	/* 0x90 */
	u32 mac_ssrr;	/* 0x94 */
	u32 mac_a0;	/* 0x98 */
	u32 mac_a1;	/* 0x9c */
};

/* SRAMC register  */
struct sunxi_sramc_regs {
	u32 ctrl0;
	u32 ctrl1;
};

/* 0: Disable       1: Aborted frame enable(default) */
#define EMAC_TX_AB_M		(0x1 << 0)
/* 0: CPU           1: DMA(default) */
#define EMAC_TX_TM		(0x1 << 1)

#define EMAC_TX_SETUP		(0)

/* 0: DRQ asserted  1: DRQ automatically(default) */
#define EMAC_RX_DRQ_MODE	(0x1 << 1)
/* 0: CPU           1: DMA(default) */
#define EMAC_RX_TM		(0x1 << 2)
/* 0: Normal(default)        1: Pass all Frames */
#define EMAC_RX_PA		(0x1 << 4)
/* 0: Normal(default)        1: Pass Control Frames */
#define EMAC_RX_PCF		(0x1 << 5)
/* 0: Normal(default)        1: Pass Frames with CRC Error */
#define EMAC_RX_PCRCE		(0x1 << 6)
/* 0: Normal(default)        1: Pass Frames with Length Error */
#define EMAC_RX_PLE		(0x1 << 7)
/* 0: Normal                 1: Pass Frames length out of range(default) */
#define EMAC_RX_POR		(0x1 << 8)
/* 0: Not accept             1: Accept unicast Packets(default) */
#define EMAC_RX_UCAD		(0x1 << 16)
/* 0: Normal(default)        1: DA Filtering */
#define EMAC_RX_DAF		(0x1 << 17)
/* 0: Not accept             1: Accept multicast Packets(default) */
#define EMAC_RX_MCO		(0x1 << 20)
/* 0: Disable(default)       1: Enable Hash filter */
#define EMAC_RX_MHF		(0x1 << 21)
/* 0: Not accept             1: Accept Broadcast Packets(default) */
#define EMAC_RX_BCO		(0x1 << 22)
/* 0: Disable(default)       1: Enable SA Filtering */
#define EMAC_RX_SAF		(0x1 << 24)
/* 0: Normal(default)        1: Inverse Filtering */
#define EMAC_RX_SAIF		(0x1 << 25)

#define EMAC_RX_SETUP		(EMAC_RX_POR | EMAC_RX_UCAD | EMAC_RX_DAF | \
				 EMAC_RX_MCO | EMAC_RX_BCO)

/* 0: Disable                1: Enable Receive Flow Control(default) */
#define EMAC_MAC_CTL0_RFC	(0x1 << 2)
/* 0: Disable                1: Enable Transmit Flow Control(default) */
#define EMAC_MAC_CTL0_TFC	(0x1 << 3)

#define EMAC_MAC_CTL0_SETUP	(EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC)

/* 0: Disable                1: Enable MAC Frame Length Checking(default) */
#define EMAC_MAC_CTL1_FLC	(0x1 << 1)
/* 0: Disable(default)       1: Enable Huge Frame */
#define EMAC_MAC_CTL1_HF	(0x1 << 2)
/* 0: Disable(default)       1: Enable MAC Delayed CRC */
#define EMAC_MAC_CTL1_DCRC	(0x1 << 3)
/* 0: Disable                1: Enable MAC CRC(default) */
#define EMAC_MAC_CTL1_CRC	(0x1 << 4)
/* 0: Disable                1: Enable MAC PAD Short frames(default) */
#define EMAC_MAC_CTL1_PC	(0x1 << 5)
/* 0: Disable(default)       1: Enable MAC PAD Short frames and append CRC */
#define EMAC_MAC_CTL1_VC	(0x1 << 6)
/* 0: Disable(default)       1: Enable MAC auto detect Short frames */
#define EMAC_MAC_CTL1_ADP	(0x1 << 7)
/* 0: Disable(default)       1: Enable */
#define EMAC_MAC_CTL1_PRE	(0x1 << 8)
/* 0: Disable(default)       1: Enable */
#define EMAC_MAC_CTL1_LPE	(0x1 << 9)
/* 0: Disable(default)       1: Enable no back off */
#define EMAC_MAC_CTL1_NB	(0x1 << 12)
/* 0: Disable(default)       1: Enable */
#define EMAC_MAC_CTL1_BNB	(0x1 << 13)
/* 0: Disable(default)       1: Enable */
#define EMAC_MAC_CTL1_ED	(0x1 << 14)

#define EMAC_MAC_CTL1_SETUP	(EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \
				 EMAC_MAC_CTL1_PC)

#define EMAC_MAC_IPGT		0x15

#define EMAC_MAC_NBTB_IPG1	0xc
#define EMAC_MAC_NBTB_IPG2	0x12

#define EMAC_MAC_CW		0x37
#define EMAC_MAC_RM		0xf

#define EMAC_MAC_MFL		0x0600

/* Receive status */
#define EMAC_CRCERR		(0x1 << 4)
#define EMAC_LENERR		(0x3 << 5)

#define EMAC_RX_BUFSIZE		2000

struct emac_eth_dev {
	struct emac_regs *regs;
	struct mii_dev *bus;
	struct phy_device *phydev;
	int link_printed;
#ifdef CONFIG_DM_ETH
	uchar rx_buf[EMAC_RX_BUFSIZE];
#endif
};

struct emac_rxhdr {
	s16 rx_len;
	u16 rx_status;
};

static void emac_inblk_32bit(void *reg, void *data, int count)
{
	int cnt = (count + 3) >> 2;

	if (cnt) {
		u32 *buf = data;

		do {
			u32 x = readl(reg);
			*buf++ = x;
		} while (--cnt);
	}
}

static void emac_outblk_32bit(void *reg, void *data, int count)
{
	int cnt = (count + 3) >> 2;

	if (cnt) {
		const u32 *buf = data;

		do {
			writel(*buf++, reg);
		} while (--cnt);
	}
}

/* Read a word from phyxcer */
static int emac_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
	struct emac_eth_dev *priv = bus->priv;
	struct emac_regs *regs = priv->regs;

	/* issue the phy address and reg */
	writel(addr << 8 | reg, &regs->mac_madr);

	/* pull up the phy io line */
	writel(0x1, &regs->mac_mcmd);

	/* Wait read complete */
	mdelay(1);

	/* push down the phy io line */
	writel(0x0, &regs->mac_mcmd);

	/* And read data */
	return readl(&regs->mac_mrdd);
}

/* Write a word to phyxcer */
static int emac_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
			  u16 value)
{
	struct emac_eth_dev *priv = bus->priv;
	struct emac_regs *regs = priv->regs;

	/* issue the phy address and reg */
	writel(addr << 8 | reg, &regs->mac_madr);

	/* pull up the phy io line */
	writel(0x1, &regs->mac_mcmd);

	/* Wait write complete */
	mdelay(1);

	/* push down the phy io line */
	writel(0x0, &regs->mac_mcmd);

	/* and write data */
	writel(value, &regs->mac_mwtd);

	return 0;
}

static int sunxi_emac_init_phy(struct emac_eth_dev *priv, void *dev)
{
	int ret, mask = 0xffffffff;

#ifdef CONFIG_PHY_ADDR
	mask = 1 << CONFIG_PHY_ADDR;
#endif

	priv->bus = mdio_alloc();
	if (!priv->bus) {
		printf("Failed to allocate MDIO bus\n");
		return -ENOMEM;
	}

	priv->bus->read = emac_mdio_read;
	priv->bus->write = emac_mdio_write;
	priv->bus->priv = priv;
	strcpy(priv->bus->name, "emac");

	ret = mdio_register(priv->bus);
	if (ret)
		return ret;

	priv->phydev = phy_find_by_mask(priv->bus, mask,
					PHY_INTERFACE_MODE_MII);
	if (!priv->phydev)
		return -ENODEV;

	phy_connect_dev(priv->phydev, dev);
	phy_config(priv->phydev);

	return 0;
}

static void emac_setup(struct emac_eth_dev *priv)
{
	struct emac_regs *regs = priv->regs;
	u32 reg_val;

	/* Set up TX */
	writel(EMAC_TX_SETUP, &regs->tx_mode);

	/* Set up RX */
	writel(EMAC_RX_SETUP, &regs->rx_ctl);

	/* Set MAC */
	/* Set MAC CTL0 */
	writel(EMAC_MAC_CTL0_SETUP, &regs->mac_ctl0);

	/* Set MAC CTL1 */
	reg_val = 0;
	if (priv->phydev->duplex == DUPLEX_FULL)
		reg_val = (0x1 << 0);
	writel(EMAC_MAC_CTL1_SETUP | reg_val, &regs->mac_ctl1);

	/* Set up IPGT */
	writel(EMAC_MAC_IPGT, &regs->mac_ipgt);

	/* Set up IPGR */
	writel(EMAC_MAC_NBTB_IPG2 | (EMAC_MAC_NBTB_IPG1 << 8), &regs->mac_ipgr);

	/* Set up Collison window */
	writel(EMAC_MAC_RM | (EMAC_MAC_CW << 8), &regs->mac_clrt);

	/* Set up Max Frame Length */
	writel(EMAC_MAC_MFL, &regs->mac_maxf);
}

static void emac_reset(struct emac_eth_dev *priv)
{
	struct emac_regs *regs = priv->regs;

	debug("resetting device\n");

	/* RESET device */
	writel(0, &regs->ctl);
	udelay(200);

	writel(1, &regs->ctl);
	udelay(200);
}

static int _sunxi_write_hwaddr(struct emac_eth_dev *priv, u8 *enetaddr)
{
	struct emac_regs *regs = priv->regs;
	u32 enetaddr_lo, enetaddr_hi;

	enetaddr_lo = enetaddr[2] | (enetaddr[1] << 8) | (enetaddr[0] << 16);
	enetaddr_hi = enetaddr[5] | (enetaddr[4] << 8) | (enetaddr[3] << 16);

	writel(enetaddr_hi, &regs->mac_a0);
	writel(enetaddr_lo, &regs->mac_a1);

	return 0;
}

static int _sunxi_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
{
	struct emac_regs *regs = priv->regs;
	int ret;

	/* Init EMAC */

	/* Flush RX FIFO */
	setbits_le32(&regs->rx_ctl, 0x8);
	udelay(1);

	/* Init MAC */

	/* Soft reset MAC */
	clrbits_le32(&regs->mac_ctl0, 0x1 << 15);

	/* Clear RX counter */
	writel(0x0, &regs->rx_fbc);
	udelay(1);

	/* Set up EMAC */
	emac_setup(priv);

	_sunxi_write_hwaddr(priv, enetaddr);

	mdelay(1);

	emac_reset(priv);

	/* PHY POWER UP */
	ret = phy_startup(priv->phydev);
	if (ret) {
		printf("Could not initialize PHY %s\n",
		       priv->phydev->dev->name);
		return ret;
	}

	/* Print link status only once */
	if (!priv->link_printed) {
		printf("ENET Speed is %d Mbps - %s duplex connection\n",
		       priv->phydev->speed,
		       priv->phydev->duplex ? "FULL" : "HALF");
		priv->link_printed = 1;
	}

	/* Set EMAC SPEED depend on PHY */
	if (priv->phydev->speed == SPEED_100)
		setbits_le32(&regs->mac_supp, 1 << 8);
	else
		clrbits_le32(&regs->mac_supp, 1 << 8);

	/* Set duplex depend on phy */
	if (priv->phydev->duplex == DUPLEX_FULL)
		setbits_le32(&regs->mac_ctl1, 1 << 0);
	else
		clrbits_le32(&regs->mac_ctl1, 1 << 0);

	/* Enable RX/TX */
	setbits_le32(&regs->ctl, 0x7);

	return 0;
}

static int _sunxi_emac_eth_recv(struct emac_eth_dev *priv, void *packet)
{
	struct emac_regs *regs = priv->regs;
	struct emac_rxhdr rxhdr;
	u32 rxcount;
	u32 reg_val;
	int rx_len;
	int rx_status;
	int good_packet;

	/* Check packet ready or not */

	/* Race warning: The first packet might arrive with
	 * the interrupts disabled, but the second will fix
	 */
	rxcount = readl(&regs->rx_fbc);
	if (!rxcount) {
		/* Had one stuck? */
		rxcount = readl(&regs->rx_fbc);
		if (!rxcount)
			return -EAGAIN;
	}

	reg_val = readl(&regs->rx_io_data);
	if (reg_val != 0x0143414d) {
		/* Disable RX */
		clrbits_le32(&regs->ctl, 0x1 << 2);

		/* Flush RX FIFO */
		setbits_le32(&regs->rx_ctl, 0x1 << 3);
		while (readl(&regs->rx_ctl) & (0x1 << 3))
			;

		/* Enable RX */
		setbits_le32(&regs->ctl, 0x1 << 2);

		return -EAGAIN;
	}

	/* A packet ready now
	 * Get status/length
	 */
	good_packet = 1;

	emac_inblk_32bit(&regs->rx_io_data, &rxhdr, sizeof(rxhdr));

	rx_len = rxhdr.rx_len;
	rx_status = rxhdr.rx_status;

	/* Packet Status check */
	if (rx_len < 0x40) {
		good_packet = 0;
		debug("RX: Bad Packet (runt)\n");
	}

	/* rx_status is identical to RSR register. */
	if (0 & rx_status & (EMAC_CRCERR | EMAC_LENERR)) {
		good_packet = 0;
		if (rx_status & EMAC_CRCERR)
			printf("crc error\n");
		if (rx_status & EMAC_LENERR)
			printf("length error\n");
	}

	/* Move data from EMAC */
	if (good_packet) {
		if (rx_len > EMAC_RX_BUFSIZE) {
			printf("Received packet is too big (len=%d)\n", rx_len);
			return -EMSGSIZE;
		}
		emac_inblk_32bit((void *)&regs->rx_io_data, packet, rx_len);
		return rx_len;
	}

	return -EIO; /* Bad packet */
}

static int _sunxi_emac_eth_send(struct emac_eth_dev *priv, void *packet,
				int len)
{
	struct emac_regs *regs = priv->regs;

	/* Select channel 0 */
	writel(0, &regs->tx_ins);

	/* Write packet */
	emac_outblk_32bit((void *)&regs->tx_io_data, packet, len);

	/* Set TX len */
	writel(len, &regs->tx_pl0);

	/* Start translate from fifo to phy */
	setbits_le32(&regs->tx_ctl0, 1);

	return 0;
}

static void sunxi_emac_board_setup(struct emac_eth_dev *priv)
{
	struct sunxi_ccm_reg *const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	struct sunxi_sramc_regs *sram =
		(struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
	struct emac_regs *regs = priv->regs;
	int pin;

	/* Map SRAM to EMAC */
	setbits_le32(&sram->ctrl1, 0x5 << 2);

	/* Configure pin mux settings for MII Ethernet */
	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
		sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC);

	/* Set up clock gating */
	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC);

	/* Set MII clock */
	clrsetbits_le32(&regs->mac_mcfg, 0xf << 2, 0xd << 2);
}

static int sunxi_emac_eth_start(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_platdata(dev);

	return _sunxi_emac_eth_init(dev->priv, pdata->enetaddr);
}

static int sunxi_emac_eth_send(struct udevice *dev, void *packet, int length)
{
	struct emac_eth_dev *priv = dev_get_priv(dev);

	return _sunxi_emac_eth_send(priv, packet, length);
}

static int sunxi_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
{
	struct emac_eth_dev *priv = dev_get_priv(dev);
	int rx_len;

	rx_len = _sunxi_emac_eth_recv(priv, priv->rx_buf);
	*packetp = priv->rx_buf;

	return rx_len;
}

static void sunxi_emac_eth_stop(struct udevice *dev)
{
	/* Nothing to do here */
}

static int sunxi_emac_eth_probe(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_platdata(dev);
	struct emac_eth_dev *priv = dev_get_priv(dev);

	priv->regs = (struct emac_regs *)pdata->iobase;
	sunxi_emac_board_setup(priv);

	return sunxi_emac_init_phy(priv, dev);
}

static const struct eth_ops sunxi_emac_eth_ops = {
	.start			= sunxi_emac_eth_start,
	.send			= sunxi_emac_eth_send,
	.recv			= sunxi_emac_eth_recv,
	.stop			= sunxi_emac_eth_stop,
};

static int sunxi_emac_eth_ofdata_to_platdata(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_platdata(dev);

	pdata->iobase = devfdt_get_addr(dev);

	return 0;
}

static const struct udevice_id sunxi_emac_eth_ids[] = {
	{ .compatible = "allwinner,sun4i-a10-emac" },
	{ }
};

U_BOOT_DRIVER(eth_sunxi_emac) = {
	.name	= "eth_sunxi_emac",
	.id	= UCLASS_ETH,
	.of_match = sunxi_emac_eth_ids,
	.ofdata_to_platdata = sunxi_emac_eth_ofdata_to_platdata,
	.probe	= sunxi_emac_eth_probe,
	.ops	= &sunxi_emac_eth_ops,
	.priv_auto_alloc_size = sizeof(struct emac_eth_dev),
	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
518ce472	2	/*
b70ed300	3	* sunxi_emac.c -- Allwinner A10 ethernet driver
518ce472 HN	4	*
518ce472 HN	5	* (C) Copyright 2012, Stefan Roese <sr@denx.de>
518ce472 HN	6	*/
	7
	8	#include <common.h>
939ed1cb	9	#include <dm.h>
b70ed300	10	#include <linux/err.h>
518ce472	11	#include <malloc.h>
518ce472	12	#include <miiphy.h>
b70ed300	13	#include <net.h>
518ce472 HN	14	#include <asm/io.h>
	15	#include <asm/arch/clock.h>
	16	#include <asm/arch/gpio.h>
	17
	18	/* EMAC register */
b70ed300	19	struct emac_regs {
518ce472 HN	20	u32 ctl; /* 0x00 */
	21	u32 tx_mode; /* 0x04 */
	22	u32 tx_flow; /* 0x08 */
	23	u32 tx_ctl0; /* 0x0c */
	24	u32 tx_ctl1; /* 0x10 */
	25	u32 tx_ins; /* 0x14 */
	26	u32 tx_pl0; /* 0x18 */
	27	u32 tx_pl1; /* 0x1c */
	28	u32 tx_sta; /* 0x20 */
	29	u32 tx_io_data; /* 0x24 */
b70ed300	30	u32 tx_io_data1;/* 0x28 */
518ce472 HN	31	u32 tx_tsvl0; /* 0x2c */
	32	u32 tx_tsvh0; /* 0x30 */
	33	u32 tx_tsvl1; /* 0x34 */
	34	u32 tx_tsvh1; /* 0x38 */
	35	u32 rx_ctl; /* 0x3c */
	36	u32 rx_hash0; /* 0x40 */
	37	u32 rx_hash1; /* 0x44 */
	38	u32 rx_sta; /* 0x48 */
	39	u32 rx_io_data; /* 0x4c */
	40	u32 rx_fbc; /* 0x50 */
	41	u32 int_ctl; /* 0x54 */
	42	u32 int_sta; /* 0x58 */
	43	u32 mac_ctl0; /* 0x5c */
	44	u32 mac_ctl1; /* 0x60 */
	45	u32 mac_ipgt; /* 0x64 */
	46	u32 mac_ipgr; /* 0x68 */
	47	u32 mac_clrt; /* 0x6c */
	48	u32 mac_maxf; /* 0x70 */
	49	u32 mac_supp; /* 0x74 */
	50	u32 mac_test; /* 0x78 */
	51	u32 mac_mcfg; /* 0x7c */
	52	u32 mac_mcmd; /* 0x80 */
	53	u32 mac_madr; /* 0x84 */
	54	u32 mac_mwtd; /* 0x88 */
	55	u32 mac_mrdd; /* 0x8c */
	56	u32 mac_mind; /* 0x90 */
	57	u32 mac_ssrr; /* 0x94 */
	58	u32 mac_a0; /* 0x98 */
	59	u32 mac_a1; /* 0x9c */
	60	};
	61
	62	/* SRAMC register */
	63	struct sunxi_sramc_regs {
	64	u32 ctrl0;
	65	u32 ctrl1;
	66	};
	67
	68	/* 0: Disable 1: Aborted frame enable(default) */
	69	#define EMAC_TX_AB_M (0x1 << 0)
	70	/* 0: CPU 1: DMA(default) */
	71	#define EMAC_TX_TM (0x1 << 1)
	72
	73	#define EMAC_TX_SETUP (0)
	74
	75	/* 0: DRQ asserted 1: DRQ automatically(default) */
	76	#define EMAC_RX_DRQ_MODE (0x1 << 1)
	77	/* 0: CPU 1: DMA(default) */
	78	#define EMAC_RX_TM (0x1 << 2)
	79	/* 0: Normal(default) 1: Pass all Frames */
	80	#define EMAC_RX_PA (0x1 << 4)
	81	/* 0: Normal(default) 1: Pass Control Frames */
	82	#define EMAC_RX_PCF (0x1 << 5)
	83	/* 0: Normal(default) 1: Pass Frames with CRC Error */
	84	#define EMAC_RX_PCRCE (0x1 << 6)
	85	/* 0: Normal(default) 1: Pass Frames with Length Error */
	86	#define EMAC_RX_PLE (0x1 << 7)
	87	/* 0: Normal 1: Pass Frames length out of range(default) */
	88	#define EMAC_RX_POR (0x1 << 8)
	89	/* 0: Not accept 1: Accept unicast Packets(default) */
	90	#define EMAC_RX_UCAD (0x1 << 16)
	91	/* 0: Normal(default) 1: DA Filtering */
	92	#define EMAC_RX_DAF (0x1 << 17)
	93	/* 0: Not accept 1: Accept multicast Packets(default) */
	94	#define EMAC_RX_MCO (0x1 << 20)
95	/* 0: Disable(default) 1: Enable Hash filter */
96	#define EMAC_RX_MHF (0x1 << 21)
97	/* 0: Not accept 1: Accept Broadcast Packets(default) */
98	#define EMAC_RX_BCO (0x1 << 22)
99	/* 0: Disable(default) 1: Enable SA Filtering */
100	#define EMAC_RX_SAF (0x1 << 24)
101	/* 0: Normal(default) 1: Inverse Filtering */
102	#define EMAC_RX_SAIF (0x1 << 25)
103
104	#define EMAC_RX_SETUP (EMAC_RX_POR \| EMAC_RX_UCAD \| EMAC_RX_DAF \| \
105	EMAC_RX_MCO \| EMAC_RX_BCO)
106
107	/* 0: Disable 1: Enable Receive Flow Control(default) */
108	#define EMAC_MAC_CTL0_RFC (0x1 << 2)
109	/* 0: Disable 1: Enable Transmit Flow Control(default) */
110	#define EMAC_MAC_CTL0_TFC (0x1 << 3)
111
112	#define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC \| EMAC_MAC_CTL0_TFC)
113
114	/* 0: Disable 1: Enable MAC Frame Length Checking(default) */
115	#define EMAC_MAC_CTL1_FLC (0x1 << 1)
116	/* 0: Disable(default) 1: Enable Huge Frame */
117	#define EMAC_MAC_CTL1_HF (0x1 << 2)
118	/* 0: Disable(default) 1: Enable MAC Delayed CRC */
119	#define EMAC_MAC_CTL1_DCRC (0x1 << 3)
120	/* 0: Disable 1: Enable MAC CRC(default) */
121	#define EMAC_MAC_CTL1_CRC (0x1 << 4)
122	/* 0: Disable 1: Enable MAC PAD Short frames(default) */
123	#define EMAC_MAC_CTL1_PC (0x1 << 5)
124	/* 0: Disable(default) 1: Enable MAC PAD Short frames and append CRC */
125	#define EMAC_MAC_CTL1_VC (0x1 << 6)
126	/* 0: Disable(default) 1: Enable MAC auto detect Short frames */
127	#define EMAC_MAC_CTL1_ADP (0x1 << 7)
128	/* 0: Disable(default) 1: Enable */
129	#define EMAC_MAC_CTL1_PRE (0x1 << 8)
130	/* 0: Disable(default) 1: Enable */
131	#define EMAC_MAC_CTL1_LPE (0x1 << 9)
132	/* 0: Disable(default) 1: Enable no back off */
133	#define EMAC_MAC_CTL1_NB (0x1 << 12)
134	/* 0: Disable(default) 1: Enable */
135	#define EMAC_MAC_CTL1_BNB (0x1 << 13)
136	/* 0: Disable(default) 1: Enable */
137	#define EMAC_MAC_CTL1_ED (0x1 << 14)
138
139	#define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC \| EMAC_MAC_CTL1_CRC \| \
140	EMAC_MAC_CTL1_PC)
141
142	#define EMAC_MAC_IPGT 0x15
143
b70ed300	144	#define EMAC_MAC_NBTB_IPG1 0xc
518ce472 HN	145	#define EMAC_MAC_NBTB_IPG2 0x12
	146
	147	#define EMAC_MAC_CW 0x37
b70ed300	148	#define EMAC_MAC_RM 0xf
518ce472 HN	149
	150	#define EMAC_MAC_MFL 0x0600
	151
	152	/* Receive status */
b70ed300 SR	153	#define EMAC_CRCERR (0x1 << 4)
b70ed300 SR	154	#define EMAC_LENERR (0x3 << 5)
518ce472	155
d88c2f11	156	#define EMAC_RX_BUFSIZE 2000
518ce472	157
b70ed300	158	struct emac_eth_dev {
8145dea4 HG	159	struct emac_regs *regs;
	160	struct mii_dev *bus;
	161	struct phy_device *phydev;
518ce472	162	int link_printed;
939ed1cb HG	163	#ifdef CONFIG_DM_ETH
	164	uchar rx_buf[EMAC_RX_BUFSIZE];
	165	#endif
518ce472 HN	166	};
518ce472 HN	167
b70ed300	168	struct emac_rxhdr {
518ce472 HN	169	s16 rx_len;
	170	u16 rx_status;
	171	};
	172
b70ed300	173	static void emac_inblk_32bit(void reg, void data, int count)
518ce472 HN	174	{
	175	int cnt = (count + 3) >> 2;
	176
	177	if (cnt) {
	178	u32 *buf = data;
	179
	180	do {
	181	u32 x = readl(reg);
	182	*buf++ = x;
	183	} while (--cnt);
	184	}
	185	}
	186
b70ed300	187	static void emac_outblk_32bit(void reg, void data, int count)
518ce472 HN	188	{
	189	int cnt = (count + 3) >> 2;
	190
	191	if (cnt) {
	192	const u32 *buf = data;
	193
	194	do {
	195	writel(*buf++, reg);
	196	} while (--cnt);
	197	}
	198	}
	199
b70ed300	200	/* Read a word from phyxcer */
8145dea4	201	static int emac_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
518ce472	202	{
8145dea4 HG	203	struct emac_eth_dev *priv = bus->priv;
8145dea4 HG	204	struct emac_regs *regs = priv->regs;
518ce472 HN	205
	206	/* issue the phy address and reg */
	207	writel(addr << 8 \| reg, &regs->mac_madr);
	208
	209	/* pull up the phy io line */
	210	writel(0x1, &regs->mac_mcmd);
	211
	212	/* Wait read complete */
	213	mdelay(1);
	214
	215	/* push down the phy io line */
	216	writel(0x0, &regs->mac_mcmd);
	217
8145dea4 HG	218	/* And read data */
8145dea4 HG	219	return readl(&regs->mac_mrdd);
518ce472 HN	220	}
518ce472 HN	221
b70ed300	222	/* Write a word to phyxcer */
8145dea4 HG	223	static int emac_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
8145dea4 HG	224	u16 value)
518ce472	225	{
8145dea4 HG	226	struct emac_eth_dev *priv = bus->priv;
8145dea4 HG	227	struct emac_regs *regs = priv->regs;
518ce472 HN	228
	229	/* issue the phy address and reg */
	230	writel(addr << 8 \| reg, &regs->mac_madr);
	231
	232	/* pull up the phy io line */
	233	writel(0x1, &regs->mac_mcmd);
	234
	235	/* Wait write complete */
	236	mdelay(1);
	237
	238	/* push down the phy io line */
	239	writel(0x0, &regs->mac_mcmd);
	240
	241	/* and write data */
	242	writel(value, &regs->mac_mwtd);
	243
	244	return 0;
	245	}
	246
8145dea4	247	static int sunxi_emac_init_phy(struct emac_eth_dev priv, void dev)
518ce472	248	{
8145dea4 HG	249	int ret, mask = 0xffffffff;
	250
	251	#ifdef CONFIG_PHY_ADDR
	252	mask = 1 << CONFIG_PHY_ADDR;
	253	#endif
	254
	255	priv->bus = mdio_alloc();
	256	if (!priv->bus) {
	257	printf("Failed to allocate MDIO bus\n");
	258	return -ENOMEM;
	259	}
	260
	261	priv->bus->read = emac_mdio_read;
	262	priv->bus->write = emac_mdio_write;
	263	priv->bus->priv = priv;
	264	strcpy(priv->bus->name, "emac");
	265
	266	ret = mdio_register(priv->bus);
	267	if (ret)
	268	return ret;
	269
	270	priv->phydev = phy_find_by_mask(priv->bus, mask,
	271	PHY_INTERFACE_MODE_MII);
	272	if (!priv->phydev)
	273	return -ENODEV;
	274
	275	phy_connect_dev(priv->phydev, dev);
	276	phy_config(priv->phydev);
	277
	278	return 0;
	279	}
	280
	281	static void emac_setup(struct emac_eth_dev *priv)
	282	{
	283	struct emac_regs *regs = priv->regs;
518ce472	284	u32 reg_val;
518ce472 HN	285
	286	/* Set up TX */
	287	writel(EMAC_TX_SETUP, &regs->tx_mode);
	288
	289	/* Set up RX */
	290	writel(EMAC_RX_SETUP, &regs->rx_ctl);
	291
	292	/* Set MAC */
	293	/* Set MAC CTL0 */
	294	writel(EMAC_MAC_CTL0_SETUP, &regs->mac_ctl0);
	295
	296	/* Set MAC CTL1 */
518ce472	297	reg_val = 0;
8145dea4	298	if (priv->phydev->duplex == DUPLEX_FULL)
518ce472 HN	299	reg_val = (0x1 << 0);
	300	writel(EMAC_MAC_CTL1_SETUP \| reg_val, &regs->mac_ctl1);
	301
	302	/* Set up IPGT */
	303	writel(EMAC_MAC_IPGT, &regs->mac_ipgt);
	304
	305	/* Set up IPGR */
	306	writel(EMAC_MAC_NBTB_IPG2 \| (EMAC_MAC_NBTB_IPG1 << 8), &regs->mac_ipgr);
	307
	308	/* Set up Collison window */
	309	writel(EMAC_MAC_RM \| (EMAC_MAC_CW << 8), &regs->mac_clrt);
	310
	311	/* Set up Max Frame Length */
	312	writel(EMAC_MAC_MFL, &regs->mac_maxf);
	313	}
	314
f9f62d2d	315	static void emac_reset(struct emac_eth_dev *priv)
518ce472	316	{
f9f62d2d	317	struct emac_regs *regs = priv->regs;
518ce472 HN	318
	319	debug("resetting device\n");
	320
	321	/* RESET device */
	322	writel(0, &regs->ctl);
	323	udelay(200);
	324
	325	writel(1, &regs->ctl);
	326	udelay(200);
	327	}
	328
ace1520c	329	static int _sunxi_write_hwaddr(struct emac_eth_dev priv, u8 enetaddr)
	330	{
	331	struct emac_regs *regs = priv->regs;
	332	u32 enetaddr_lo, enetaddr_hi;
	333
	334	enetaddr_lo = enetaddr[2] \| (enetaddr[1] << 8) \| (enetaddr[0] << 16);
	335	enetaddr_hi = enetaddr[5] \| (enetaddr[4] << 8) \| (enetaddr[3] << 16);
	336
6e35686d JH	337	writel(enetaddr_hi, &regs->mac_a0);
6e35686d JH	338	writel(enetaddr_lo, &regs->mac_a1);
ace1520c	339
	340	return 0;
	341	}
	342
f9f62d2d	343	static int _sunxi_emac_eth_init(struct emac_eth_dev priv, u8 enetaddr)
518ce472	344	{
f9f62d2d	345	struct emac_regs *regs = priv->regs;
8145dea4	346	int ret;
518ce472 HN	347
	348	/* Init EMAC */
	349
	350	/* Flush RX FIFO */
	351	setbits_le32(&regs->rx_ctl, 0x8);
	352	udelay(1);
	353
	354	/* Init MAC */
	355
	356	/* Soft reset MAC */
b70ed300	357	clrbits_le32(&regs->mac_ctl0, 0x1 << 15);
518ce472 HN	358
	359	/* Clear RX counter */
	360	writel(0x0, &regs->rx_fbc);
	361	udelay(1);
	362
	363	/* Set up EMAC */
8145dea4	364	emac_setup(priv);
518ce472	365
ace1520c	366	_sunxi_write_hwaddr(priv, enetaddr);
518ce472 HN	367
	368	mdelay(1);
	369
f9f62d2d	370	emac_reset(priv);
518ce472 HN	371
518ce472 HN	372	/* PHY POWER UP */
8145dea4 HG	373	ret = phy_startup(priv->phydev);
	374	if (ret) {
	375	printf("Could not initialize PHY %s\n",
	376	priv->phydev->dev->name);
	377	return ret;
	378	}
518ce472 HN	379
	380	/* Print link status only once */
	381	if (!priv->link_printed) {
	382	printf("ENET Speed is %d Mbps - %s duplex connection\n",
8145dea4 HG	383	priv->phydev->speed,
8145dea4 HG	384	priv->phydev->duplex ? "FULL" : "HALF");
518ce472 HN	385	priv->link_printed = 1;
	386	}
	387
	388	/* Set EMAC SPEED depend on PHY */
8145dea4 HG	389	if (priv->phydev->speed == SPEED_100)
	390	setbits_le32(&regs->mac_supp, 1 << 8);
	391	else
	392	clrbits_le32(&regs->mac_supp, 1 << 8);
518ce472 HN	393
518ce472 HN	394	/* Set duplex depend on phy */
8145dea4 HG	395	if (priv->phydev->duplex == DUPLEX_FULL)
	396	setbits_le32(&regs->mac_ctl1, 1 << 0);
	397	else
	398	clrbits_le32(&regs->mac_ctl1, 1 << 0);
518ce472 HN	399
	400	/* Enable RX/TX */
	401	setbits_le32(&regs->ctl, 0x7);
	402
	403	return 0;
	404	}
	405
f9f62d2d	406	static int _sunxi_emac_eth_recv(struct emac_eth_dev priv, void packet)
518ce472	407	{
f9f62d2d	408	struct emac_regs *regs = priv->regs;
b70ed300	409	struct emac_rxhdr rxhdr;
518ce472 HN	410	u32 rxcount;
	411	u32 reg_val;
	412	int rx_len;
	413	int rx_status;
	414	int good_packet;
	415
	416	/* Check packet ready or not */
	417
b70ed300	418	/* Race warning: The first packet might arrive with
518ce472 HN	419	* the interrupts disabled, but the second will fix
	420	*/
	421	rxcount = readl(&regs->rx_fbc);
	422	if (!rxcount) {
	423	/* Had one stuck? */
	424	rxcount = readl(&regs->rx_fbc);
	425	if (!rxcount)
f9f62d2d	426	return -EAGAIN;
518ce472 HN	427	}
	428
	429	reg_val = readl(&regs->rx_io_data);
	430	if (reg_val != 0x0143414d) {
	431	/* Disable RX */
b70ed300	432	clrbits_le32(&regs->ctl, 0x1 << 2);
518ce472 HN	433
518ce472 HN	434	/* Flush RX FIFO */
b70ed300 SR	435	setbits_le32(&regs->rx_ctl, 0x1 << 3);
b70ed300 SR	436	while (readl(&regs->rx_ctl) & (0x1 << 3))
518ce472 HN	437	;
	438
	439	/* Enable RX */
b70ed300	440	setbits_le32(&regs->ctl, 0x1 << 2);
518ce472	441
f9f62d2d	442	return -EAGAIN;
518ce472 HN	443	}
518ce472 HN	444
b70ed300	445	/* A packet ready now
518ce472 HN	446	* Get status/length
	447	*/
	448	good_packet = 1;
	449
b70ed300	450	emac_inblk_32bit(&regs->rx_io_data, &rxhdr, sizeof(rxhdr));
518ce472 HN	451
	452	rx_len = rxhdr.rx_len;
	453	rx_status = rxhdr.rx_status;
	454
	455	/* Packet Status check */
	456	if (rx_len < 0x40) {
	457	good_packet = 0;
	458	debug("RX: Bad Packet (runt)\n");
	459	}
	460
	461	/* rx_status is identical to RSR register. */
	462	if (0 & rx_status & (EMAC_CRCERR \| EMAC_LENERR)) {
	463	good_packet = 0;
	464	if (rx_status & EMAC_CRCERR)
	465	printf("crc error\n");
	466	if (rx_status & EMAC_LENERR)
	467	printf("length error\n");
	468	}
	469
b70ed300	470	/* Move data from EMAC */
518ce472	471	if (good_packet) {
d88c2f11	472	if (rx_len > EMAC_RX_BUFSIZE) {
518ce472	473	printf("Received packet is too big (len=%d)\n", rx_len);
f9f62d2d	474	return -EMSGSIZE;
518ce472	475	}
f9f62d2d HG	476	emac_inblk_32bit((void *)&regs->rx_io_data, packet, rx_len);
f9f62d2d HG	477	return rx_len;
518ce472 HN	478	}
518ce472 HN	479
f9f62d2d	480	return -EIO; /* Bad packet */
518ce472 HN	481	}
518ce472 HN	482
f9f62d2d HG	483	static int _sunxi_emac_eth_send(struct emac_eth_dev priv, void packet,
f9f62d2d HG	484	int len)
518ce472	485	{
f9f62d2d	486	struct emac_regs *regs = priv->regs;
518ce472 HN	487
	488	/* Select channel 0 */
	489	writel(0, &regs->tx_ins);
	490
	491	/* Write packet */
b70ed300	492	emac_outblk_32bit((void *)&regs->tx_io_data, packet, len);
518ce472 HN	493
	494	/* Set TX len */
	495	writel(len, &regs->tx_pl0);
	496
	497	/* Start translate from fifo to phy */
	498	setbits_le32(&regs->tx_ctl0, 1);
	499
	500	return 0;
	501	}
	502
f9f62d2d	503	static void sunxi_emac_board_setup(struct emac_eth_dev *priv)
518ce472 HN	504	{
	505	struct sunxi_ccm_reg *const ccm =
	506	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	507	struct sunxi_sramc_regs *sram =
	508	(struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
f9f62d2d HG	509	struct emac_regs *regs = priv->regs;
	510	int pin;
	511
	512	/* Map SRAM to EMAC */
	513	setbits_le32(&sram->ctrl1, 0x5 << 2);
	514
	515	/* Configure pin mux settings for MII Ethernet */
	516	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
	517	sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC);
	518
	519	/* Set up clock gating */
	520	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC);
	521
	522	/* Set MII clock */
	523	clrsetbits_le32(&regs->mac_mcfg, 0xf << 2, 0xd << 2);
	524	}
	525
939ed1cb HG	526	static int sunxi_emac_eth_start(struct udevice *dev)
	527	{
	528	struct eth_pdata *pdata = dev_get_platdata(dev);
	529
	530	return _sunxi_emac_eth_init(dev->priv, pdata->enetaddr);
	531	}
	532
	533	static int sunxi_emac_eth_send(struct udevice dev, void packet, int length)
	534	{
	535	struct emac_eth_dev *priv = dev_get_priv(dev);
	536
	537	return _sunxi_emac_eth_send(priv, packet, length);
	538	}
	539
a1ca92ea	540	static int sunxi_emac_eth_recv(struct udevice dev, int flags, uchar *packetp)
939ed1cb HG	541	{
	542	struct emac_eth_dev *priv = dev_get_priv(dev);
	543	int rx_len;
	544
	545	rx_len = _sunxi_emac_eth_recv(priv, priv->rx_buf);
	546	*packetp = priv->rx_buf;
	547
	548	return rx_len;
	549	}
	550
	551	static void sunxi_emac_eth_stop(struct udevice *dev)
	552	{
	553	/* Nothing to do here */
	554	}
	555
	556	static int sunxi_emac_eth_probe(struct udevice *dev)
	557	{
	558	struct eth_pdata *pdata = dev_get_platdata(dev);
	559	struct emac_eth_dev *priv = dev_get_priv(dev);
	560
	561	priv->regs = (struct emac_regs *)pdata->iobase;
	562	sunxi_emac_board_setup(priv);
	563
	564	return sunxi_emac_init_phy(priv, dev);
	565	}
	566
	567	static const struct eth_ops sunxi_emac_eth_ops = {
	568	.start = sunxi_emac_eth_start,
	569	.send = sunxi_emac_eth_send,
	570	.recv = sunxi_emac_eth_recv,
	571	.stop = sunxi_emac_eth_stop,
	572	};
	573
	574	static int sunxi_emac_eth_ofdata_to_platdata(struct udevice *dev)
	575	{
	576	struct eth_pdata *pdata = dev_get_platdata(dev);
	577
a821c4af	578	pdata->iobase = devfdt_get_addr(dev);
939ed1cb HG	579
	580	return 0;
	581	}
	582
	583	static const struct udevice_id sunxi_emac_eth_ids[] = {
	584	{ .compatible = "allwinner,sun4i-a10-emac" },
	585	{ }
	586	};
	587
	588	U_BOOT_DRIVER(eth_sunxi_emac) = {
	589	.name = "eth_sunxi_emac",
	590	.id = UCLASS_ETH,
	591	.of_match = sunxi_emac_eth_ids,
	592	.ofdata_to_platdata = sunxi_emac_eth_ofdata_to_platdata,
	593	.probe = sunxi_emac_eth_probe,
	594	.ops = &sunxi_emac_eth_ops,
	595	.priv_auto_alloc_size = sizeof(struct emac_eth_dev),
	596	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
	597	};