projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| d1927cee | 1 | /*********************************************************************** |
| 2 | * | |
| 3 | * Copyright (c) 2005 Freescale Semiconductor, Inc. | |
| 4 | * | |
| 1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| d1927cee | 6 | * |
| 7 | * Description: | |
| 8 | * Ethernet interface for Tundra TSI108 bridge chip | |
| 9 | * | |
| 10 | ***********************************************************************/ | |
| 11 | ||
| 12 | #include <config.h> | |
| 13 | ||
| d1927cee | 14 | #if !defined(CONFIG_TSI108_ETH_NUM_PORTS) || (CONFIG_TSI108_ETH_NUM_PORTS > 2) |
| 15 | #error "CONFIG_TSI108_ETH_NUM_PORTS must be defined as 1 or 2" | |
| 16 | #endif | |
| 17 | ||
| 18 | #include <common.h> | |
| 19 | #include <malloc.h> | |
| 20 | #include <net.h> | |
| ccdd12f8 | 21 | #include <netdev.h> |
| d1927cee | 22 | #include <asm/cache.h> |
| 23 | ||
| 24 | #ifdef DEBUG | |
| 25 | #define TSI108_ETH_DEBUG 7 | |
| 26 | #else | |
| 27 | #define TSI108_ETH_DEBUG 0 | |
| 28 | #endif | |
| 29 | ||
| 30 | #if TSI108_ETH_DEBUG > 0 | |
| ee311214 | 31 | #define debug_lev(lev, fmt, args...) \ |
| 32 | if (lev <= TSI108_ETH_DEBUG) \ | |
| 33 | printf ("%s %d: " fmt, __FUNCTION__, __LINE__, ##args) | |
| d1927cee | 34 | #else |
| 35 | #define debug_lev(lev, fmt, args...) do{}while(0) | |
| 36 | #endif | |
| 37 | ||
| 38 | #define RX_PRINT_ERRORS | |
| 39 | #define TX_PRINT_ERRORS | |
| 40 | ||
| 6d0f6bcf | 41 | #define ETH_BASE (CONFIG_SYS_TSI108_CSR_BASE + 0x6000) |
| d1927cee | 42 | |
| ee311214 | 43 | #define ETH_PORT_OFFSET 0x400 |
| d1927cee | 44 | |
| 45 | #define __REG32(base, offset) (*((volatile u32 *)((char *)(base) + (offset)))) | |
| 46 | ||
| ee311214 | 47 | #define reg_MAC_CONFIG_1(base) __REG32(base, 0x00000000) |
| 48 | #define MAC_CONFIG_1_TX_ENABLE (0x00000001) | |
| 49 | #define MAC_CONFIG_1_SYNC_TX_ENABLE (0x00000002) | |
| 50 | #define MAC_CONFIG_1_RX_ENABLE (0x00000004) | |
| 51 | #define MAC_CONFIG_1_SYNC_RX_ENABLE (0x00000008) | |
| 52 | #define MAC_CONFIG_1_TX_FLOW_CONTROL (0x00000010) | |
| 53 | #define MAC_CONFIG_1_RX_FLOW_CONTROL (0x00000020) | |
| 54 | #define MAC_CONFIG_1_LOOP_BACK (0x00000100) | |
| 55 | #define MAC_CONFIG_1_RESET_TX_FUNCTION (0x00010000) | |
| 56 | #define MAC_CONFIG_1_RESET_RX_FUNCTION (0x00020000) | |
| 57 | #define MAC_CONFIG_1_RESET_TX_MAC (0x00040000) | |
| 58 | #define MAC_CONFIG_1_RESET_RX_MAC (0x00080000) | |
| 59 | #define MAC_CONFIG_1_SIM_RESET (0x40000000) | |
| 60 | #define MAC_CONFIG_1_SOFT_RESET (0x80000000) | |
| 61 | ||
| 62 | #define reg_MAC_CONFIG_2(base) __REG32(base, 0x00000004) | |
| 63 | #define MAC_CONFIG_2_FULL_DUPLEX (0x00000001) | |
| 64 | #define MAC_CONFIG_2_CRC_ENABLE (0x00000002) | |
| 65 | #define MAC_CONFIG_2_PAD_CRC (0x00000004) | |
| 66 | #define MAC_CONFIG_2_LENGTH_CHECK (0x00000010) | |
| 67 | #define MAC_CONFIG_2_HUGE_FRAME (0x00000020) | |
| 68 | #define MAC_CONFIG_2_INTERFACE_MODE(val) (((val) & 0x3) << 8) | |
| 69 | #define MAC_CONFIG_2_PREAMBLE_LENGTH(val) (((val) & 0xf) << 12) | |
| 70 | #define INTERFACE_MODE_NIBBLE 1 /* 10/100 Mb/s MII) */ | |
| 71 | #define INTERFACE_MODE_BYTE 2 /* 1000 Mb/s GMII/TBI */ | |
| 72 | ||
| 73 | #define reg_MAXIMUM_FRAME_LENGTH(base) __REG32(base, 0x00000010) | |
| 74 | ||
| 75 | #define reg_MII_MGMT_CONFIG(base) __REG32(base, 0x00000020) | |
| 76 | #define MII_MGMT_CONFIG_MGMT_CLOCK_SELECT(val) ((val) & 0x7) | |
| 77 | #define MII_MGMT_CONFIG_NO_PREAMBLE (0x00000010) | |
| 78 | #define MII_MGMT_CONFIG_SCAN_INCREMENT (0x00000020) | |
| 79 | #define MII_MGMT_CONFIG_RESET_MGMT (0x80000000) | |
| 80 | ||
| 81 | #define reg_MII_MGMT_COMMAND(base) __REG32(base, 0x00000024) | |
| 82 | #define MII_MGMT_COMMAND_READ_CYCLE (0x00000001) | |
| 83 | #define MII_MGMT_COMMAND_SCAN_CYCLE (0x00000002) | |
| 84 | ||
| 85 | #define reg_MII_MGMT_ADDRESS(base) __REG32(base, 0x00000028) | |
| 86 | #define reg_MII_MGMT_CONTROL(base) __REG32(base, 0x0000002c) | |
| 87 | #define reg_MII_MGMT_STATUS(base) __REG32(base, 0x00000030) | |
| 88 | ||
| 89 | #define reg_MII_MGMT_INDICATORS(base) __REG32(base, 0x00000034) | |
| 90 | #define MII_MGMT_INDICATORS_BUSY (0x00000001) | |
| 91 | #define MII_MGMT_INDICATORS_SCAN (0x00000002) | |
| 92 | #define MII_MGMT_INDICATORS_NOT_VALID (0x00000004) | |
| 93 | ||
| 94 | #define reg_INTERFACE_STATUS(base) __REG32(base, 0x0000003c) | |
| 95 | #define INTERFACE_STATUS_LINK_FAIL (0x00000008) | |
| 96 | #define INTERFACE_STATUS_EXCESS_DEFER (0x00000200) | |
| 97 | ||
| 98 | #define reg_STATION_ADDRESS_1(base) __REG32(base, 0x00000040) | |
| 99 | #define reg_STATION_ADDRESS_2(base) __REG32(base, 0x00000044) | |
| 100 | ||
| 101 | #define reg_PORT_CONTROL(base) __REG32(base, 0x00000200) | |
| 102 | #define PORT_CONTROL_PRI (0x00000001) | |
| 103 | #define PORT_CONTROL_BPT (0x00010000) | |
| 104 | #define PORT_CONTROL_SPD (0x00040000) | |
| 105 | #define PORT_CONTROL_RBC (0x00080000) | |
| 106 | #define PORT_CONTROL_PRB (0x00200000) | |
| 107 | #define PORT_CONTROL_DIS (0x00400000) | |
| 108 | #define PORT_CONTROL_TBI (0x00800000) | |
| 109 | #define PORT_CONTROL_STE (0x10000000) | |
| 110 | #define PORT_CONTROL_ZOR (0x20000000) | |
| 111 | #define PORT_CONTROL_CLR (0x40000000) | |
| 112 | #define PORT_CONTROL_SRT (0x80000000) | |
| 113 | ||
| 114 | #define reg_TX_CONFIG(base) __REG32(base, 0x00000220) | |
| 115 | #define TX_CONFIG_START_Q (0x00000003) | |
| 116 | #define TX_CONFIG_EHP (0x00400000) | |
| 117 | #define TX_CONFIG_CHP (0x00800000) | |
| 118 | #define TX_CONFIG_RST (0x80000000) | |
| 119 | ||
| 120 | #define reg_TX_CONTROL(base) __REG32(base, 0x00000224) | |
| 121 | #define TX_CONTROL_GO (0x00008000) | |
| 122 | #define TX_CONTROL_MP (0x01000000) | |
| 123 | #define TX_CONTROL_EAI (0x20000000) | |
| 124 | #define TX_CONTROL_ABT (0x40000000) | |
| 125 | #define TX_CONTROL_EII (0x80000000) | |
| 126 | ||
| 127 | #define reg_TX_STATUS(base) __REG32(base, 0x00000228) | |
| 128 | #define TX_STATUS_QUEUE_USABLE (0x0000000f) | |
| 129 | #define TX_STATUS_CURR_Q (0x00000300) | |
| 130 | #define TX_STATUS_ACT (0x00008000) | |
| 131 | #define TX_STATUS_QUEUE_IDLE (0x000f0000) | |
| 132 | #define TX_STATUS_EOQ_PENDING (0x0f000000) | |
| 133 | ||
| 134 | #define reg_TX_EXTENDED_STATUS(base) __REG32(base, 0x0000022c) | |
| 135 | #define TX_EXTENDED_STATUS_END_OF_QUEUE_CONDITION (0x0000000f) | |
| 136 | #define TX_EXTENDED_STATUS_END_OF_FRAME_CONDITION (0x00000f00) | |
| 137 | #define TX_EXTENDED_STATUS_DESCRIPTOR_INTERRUPT_CONDITION (0x000f0000) | |
| 138 | #define TX_EXTENDED_STATUS_ERROR_FLAG (0x0f000000) | |
| 139 | ||
| 140 | #define reg_TX_THRESHOLDS(base) __REG32(base, 0x00000230) | |
| d1927cee | 141 | |
| 142 | #define reg_TX_DIAGNOSTIC_ADDR(base) __REG32(base, 0x00000270) | |
| ee311214 | 143 | #define TX_DIAGNOSTIC_ADDR_INDEX (0x0000007f) |
| 144 | #define TX_DIAGNOSTIC_ADDR_DFR (0x40000000) | |
| 145 | #define TX_DIAGNOSTIC_ADDR_AI (0x80000000) | |
| 146 | ||
| 147 | #define reg_TX_DIAGNOSTIC_DATA(base) __REG32(base, 0x00000274) | |
| 148 | ||
| 149 | #define reg_TX_ERROR_STATUS(base) __REG32(base, 0x00000278) | |
| 150 | #define TX_ERROR_STATUS (0x00000278) | |
| 151 | #define TX_ERROR_STATUS_QUEUE_0_ERROR_RESPONSE (0x0000000f) | |
| 152 | #define TX_ERROR_STATUS_TEA_ON_QUEUE_0 (0x00000010) | |
| 153 | #define TX_ERROR_STATUS_RER_ON_QUEUE_0 (0x00000020) | |
| 154 | #define TX_ERROR_STATUS_TER_ON_QUEUE_0 (0x00000040) | |
| 155 | #define TX_ERROR_STATUS_DER_ON_QUEUE_0 (0x00000080) | |
| 156 | #define TX_ERROR_STATUS_QUEUE_1_ERROR_RESPONSE (0x00000f00) | |
| 157 | #define TX_ERROR_STATUS_TEA_ON_QUEUE_1 (0x00001000) | |
| 158 | #define TX_ERROR_STATUS_RER_ON_QUEUE_1 (0x00002000) | |
| 159 | #define TX_ERROR_STATUS_TER_ON_QUEUE_1 (0x00004000) | |
| 160 | #define TX_ERROR_STATUS_DER_ON_QUEUE_1 (0x00008000) | |
| 161 | #define TX_ERROR_STATUS_QUEUE_2_ERROR_RESPONSE (0x000f0000) | |
| 162 | #define TX_ERROR_STATUS_TEA_ON_QUEUE_2 (0x00100000) | |
| 163 | #define TX_ERROR_STATUS_RER_ON_QUEUE_2 (0x00200000) | |
| 164 | #define TX_ERROR_STATUS_TER_ON_QUEUE_2 (0x00400000) | |
| 165 | #define TX_ERROR_STATUS_DER_ON_QUEUE_2 (0x00800000) | |
| 166 | #define TX_ERROR_STATUS_QUEUE_3_ERROR_RESPONSE (0x0f000000) | |
| 167 | #define TX_ERROR_STATUS_TEA_ON_QUEUE_3 (0x10000000) | |
| 168 | #define TX_ERROR_STATUS_RER_ON_QUEUE_3 (0x20000000) | |
| 169 | #define TX_ERROR_STATUS_TER_ON_QUEUE_3 (0x40000000) | |
| 170 | #define TX_ERROR_STATUS_DER_ON_QUEUE_3 (0x80000000) | |
| 171 | ||
| 172 | #define reg_TX_QUEUE_0_CONFIG(base) __REG32(base, 0x00000280) | |
| 173 | #define TX_QUEUE_0_CONFIG_OCN_PORT (0x0000003f) | |
| 174 | #define TX_QUEUE_0_CONFIG_BSWP (0x00000400) | |
| 175 | #define TX_QUEUE_0_CONFIG_WSWP (0x00000800) | |
| 176 | #define TX_QUEUE_0_CONFIG_AM (0x00004000) | |
| 177 | #define TX_QUEUE_0_CONFIG_GVI (0x00008000) | |
| 178 | #define TX_QUEUE_0_CONFIG_EEI (0x00010000) | |
| 179 | #define TX_QUEUE_0_CONFIG_ELI (0x00020000) | |
| 180 | #define TX_QUEUE_0_CONFIG_ENI (0x00040000) | |
| 181 | #define TX_QUEUE_0_CONFIG_ESI (0x00080000) | |
| 182 | #define TX_QUEUE_0_CONFIG_EDI (0x00100000) | |
| 183 | ||
| 184 | #define reg_TX_QUEUE_0_BUF_CONFIG(base) __REG32(base, 0x00000284) | |
| 185 | #define TX_QUEUE_0_BUF_CONFIG_OCN_PORT (0x0000003f) | |
| 186 | #define TX_QUEUE_0_BUF_CONFIG_BURST (0x00000300) | |
| 187 | #define TX_QUEUE_0_BUF_CONFIG_BSWP (0x00000400) | |
| 188 | #define TX_QUEUE_0_BUF_CONFIG_WSWP (0x00000800) | |
| 189 | ||
| 190 | #define OCN_PORT_HLP 0 /* HLP Interface */ | |
| 191 | #define OCN_PORT_PCI_X 1 /* PCI-X Interface */ | |
| d1927cee | 192 | #define OCN_PORT_PROCESSOR_MASTER 2 /* Processor Interface (master) */ |
| ee311214 | 193 | #define OCN_PORT_PROCESSOR_SLAVE 3 /* Processor Interface (slave) */ |
| 194 | #define OCN_PORT_MEMORY 4 /* Memory Controller */ | |
| 195 | #define OCN_PORT_DMA 5 /* DMA Controller */ | |
| 196 | #define OCN_PORT_ETHERNET 6 /* Ethernet Controller */ | |
| 197 | #define OCN_PORT_PRINT 7 /* Print Engine Interface */ | |
| 198 | ||
| 199 | #define reg_TX_QUEUE_0_PTR_LOW(base) __REG32(base, 0x00000288) | |
| 200 | ||
| 201 | #define reg_TX_QUEUE_0_PTR_HIGH(base) __REG32(base, 0x0000028c) | |
| 202 | #define TX_QUEUE_0_PTR_HIGH_VALID (0x80000000) | |
| 203 | ||
| 204 | #define reg_RX_CONFIG(base) __REG32(base, 0x00000320) | |
| 205 | #define RX_CONFIG_DEF_Q (0x00000003) | |
| 206 | #define RX_CONFIG_EMF (0x00000100) | |
| 207 | #define RX_CONFIG_EUF (0x00000200) | |
| 208 | #define RX_CONFIG_BFE (0x00000400) | |
| 209 | #define RX_CONFIG_MFE (0x00000800) | |
| 210 | #define RX_CONFIG_UFE (0x00001000) | |
| 211 | #define RX_CONFIG_SE (0x00002000) | |
| 212 | #define RX_CONFIG_ABF (0x00200000) | |
| 213 | #define RX_CONFIG_APE (0x00400000) | |
| 214 | #define RX_CONFIG_CHP (0x00800000) | |
| 215 | #define RX_CONFIG_RST (0x80000000) | |
| 216 | ||
| 217 | #define reg_RX_CONTROL(base) __REG32(base, 0x00000324) | |
| 218 | #define GE_E0_RX_CONTROL_QUEUE_ENABLES (0x0000000f) | |
| 219 | #define GE_E0_RX_CONTROL_GO (0x00008000) | |
| 220 | #define GE_E0_RX_CONTROL_EAI (0x20000000) | |
| 221 | #define GE_E0_RX_CONTROL_ABT (0x40000000) | |
| 222 | #define GE_E0_RX_CONTROL_EII (0x80000000) | |
| 223 | ||
| 224 | #define reg_RX_EXTENDED_STATUS(base) __REG32(base, 0x0000032c) | |
| 225 | #define RX_EXTENDED_STATUS (0x0000032c) | |
| 226 | #define RX_EXTENDED_STATUS_EOQ (0x0000000f) | |
| 227 | #define RX_EXTENDED_STATUS_EOQ_0 (0x00000001) | |
| 228 | #define RX_EXTENDED_STATUS_EOF (0x00000f00) | |
| 229 | #define RX_EXTENDED_STATUS_DESCRIPTOR_INTERRUPT_CONDITION (0x000f0000) | |
| 230 | #define RX_EXTENDED_STATUS_ERROR_FLAG (0x0f000000) | |
| 231 | ||
| 232 | #define reg_RX_THRESHOLDS(base) __REG32(base, 0x00000330) | |
| 233 | ||
| 234 | #define reg_RX_DIAGNOSTIC_ADDR(base) __REG32(base, 0x00000370) | |
| 235 | #define RX_DIAGNOSTIC_ADDR_INDEX (0x0000007f) | |
| 236 | #define RX_DIAGNOSTIC_ADDR_DFR (0x40000000) | |
| 237 | #define RX_DIAGNOSTIC_ADDR_AI (0x80000000) | |
| 238 | ||
| 239 | #define reg_RX_DIAGNOSTIC_DATA(base) __REG32(base, 0x00000374) | |
| 240 | ||
| 241 | #define reg_RX_QUEUE_0_CONFIG(base) __REG32(base, 0x00000380) | |
| 242 | #define RX_QUEUE_0_CONFIG_OCN_PORT (0x0000003f) | |
| 243 | #define RX_QUEUE_0_CONFIG_BSWP (0x00000400) | |
| 244 | #define RX_QUEUE_0_CONFIG_WSWP (0x00000800) | |
| 245 | #define RX_QUEUE_0_CONFIG_AM (0x00004000) | |
| 246 | #define RX_QUEUE_0_CONFIG_EEI (0x00010000) | |
| 247 | #define RX_QUEUE_0_CONFIG_ELI (0x00020000) | |
| 248 | #define RX_QUEUE_0_CONFIG_ENI (0x00040000) | |
| 249 | #define RX_QUEUE_0_CONFIG_ESI (0x00080000) | |
| 250 | #define RX_QUEUE_0_CONFIG_EDI (0x00100000) | |
| 251 | ||
| 252 | #define reg_RX_QUEUE_0_BUF_CONFIG(base) __REG32(base, 0x00000384) | |
| 253 | #define RX_QUEUE_0_BUF_CONFIG_OCN_PORT (0x0000003f) | |
| 254 | #define RX_QUEUE_0_BUF_CONFIG_BURST (0x00000300) | |
| 255 | #define RX_QUEUE_0_BUF_CONFIG_BSWP (0x00000400) | |
| 256 | #define RX_QUEUE_0_BUF_CONFIG_WSWP (0x00000800) | |
| 257 | ||
| 258 | #define reg_RX_QUEUE_0_PTR_LOW(base) __REG32(base, 0x00000388) | |
| 259 | ||
| 260 | #define reg_RX_QUEUE_0_PTR_HIGH(base) __REG32(base, 0x0000038c) | |
| 261 | #define RX_QUEUE_0_PTR_HIGH_VALID (0x80000000) | |
| d1927cee | 262 | |
| 263 | /* | |
| 264 | * PHY register definitions | |
| 265 | */ | |
| 266 | /* the first 15 PHY registers are standard. */ | |
| ee311214 | 267 | #define PHY_CTRL_REG 0 /* Control Register */ |
| 268 | #define PHY_STATUS_REG 1 /* Status Regiser */ | |
| 269 | #define PHY_ID1_REG 2 /* Phy Id Reg (word 1) */ | |
| 270 | #define PHY_ID2_REG 3 /* Phy Id Reg (word 2) */ | |
| 271 | #define PHY_AN_ADV_REG 4 /* Autoneg Advertisement */ | |
| 272 | #define PHY_LP_ABILITY_REG 5 /* Link Partner Ability (Base Page) */ | |
| 273 | #define PHY_AUTONEG_EXP_REG 6 /* Autoneg Expansion Reg */ | |
| 274 | #define PHY_NEXT_PAGE_TX_REG 7 /* Next Page TX */ | |
| 275 | #define PHY_LP_NEXT_PAGE_REG 8 /* Link Partner Next Page */ | |
| 276 | #define PHY_1000T_CTRL_REG 9 /* 1000Base-T Control Reg */ | |
| 277 | #define PHY_1000T_STATUS_REG 10 /* 1000Base-T Status Reg */ | |
| 278 | #define PHY_EXT_STATUS_REG 11 /* Extended Status Reg */ | |
| d1927cee | 279 | |
| 280 | /* | |
| 281 | * PHY Register bit masks. | |
| 282 | */ | |
| ee311214 | 283 | #define PHY_CTRL_RESET (1 << 15) |
| 284 | #define PHY_CTRL_LOOPBACK (1 << 14) | |
| 285 | #define PHY_CTRL_SPEED0 (1 << 13) | |
| 286 | #define PHY_CTRL_AN_EN (1 << 12) | |
| 287 | #define PHY_CTRL_PWR_DN (1 << 11) | |
| 288 | #define PHY_CTRL_ISOLATE (1 << 10) | |
| 289 | #define PHY_CTRL_RESTART_AN (1 << 9) | |
| 290 | #define PHY_CTRL_FULL_DUPLEX (1 << 8) | |
| 291 | #define PHY_CTRL_CT_EN (1 << 7) | |
| 292 | #define PHY_CTRL_SPEED1 (1 << 6) | |
| 293 | ||
| 294 | #define PHY_STAT_100BASE_T4 (1 << 15) | |
| 295 | #define PHY_STAT_100BASE_X_FD (1 << 14) | |
| 296 | #define PHY_STAT_100BASE_X_HD (1 << 13) | |
| 297 | #define PHY_STAT_10BASE_T_FD (1 << 12) | |
| 298 | #define PHY_STAT_10BASE_T_HD (1 << 11) | |
| 299 | #define PHY_STAT_100BASE_T2_FD (1 << 10) | |
| 300 | #define PHY_STAT_100BASE_T2_HD (1 << 9) | |
| 301 | #define PHY_STAT_EXT_STAT (1 << 8) | |
| 302 | #define PHY_STAT_RESERVED (1 << 7) | |
| 303 | #define PHY_STAT_MFPS (1 << 6) /* Management Frames Preamble Suppression */ | |
| 304 | #define PHY_STAT_AN_COMPLETE (1 << 5) | |
| 305 | #define PHY_STAT_REM_FAULT (1 << 4) | |
| 306 | #define PHY_STAT_AN_CAP (1 << 3) | |
| 307 | #define PHY_STAT_LINK_UP (1 << 2) | |
| 308 | #define PHY_STAT_JABBER (1 << 1) | |
| 309 | #define PHY_STAT_EXT_CAP (1 << 0) | |
| 310 | ||
| 311 | #define TBI_CONTROL_2 0x11 | |
| 312 | #define TBI_CONTROL_2_ENABLE_COMMA_DETECT 0x0001 | |
| 313 | #define TBI_CONTROL_2_ENABLE_WRAP 0x0002 | |
| 314 | #define TBI_CONTROL_2_G_MII_MODE 0x0010 | |
| 315 | #define TBI_CONTROL_2_RECEIVE_CLOCK_SELECT 0x0020 | |
| 316 | #define TBI_CONTROL_2_AUTO_NEGOTIATION_SENSE 0x0100 | |
| 317 | #define TBI_CONTROL_2_DISABLE_TRANSMIT_RUNNING_DISPARITY 0x1000 | |
| 318 | #define TBI_CONTROL_2_DISABLE_RECEIVE_RUNNING_DISPARITY 0x2000 | |
| 319 | #define TBI_CONTROL_2_SHORTCUT_LINK_TIMER 0x4000 | |
| 320 | #define TBI_CONTROL_2_SOFT_RESET 0x8000 | |
| d1927cee | 321 | |
| 322 | /* marvel specific */ | |
| ee311214 | 323 | #define MV1111_EXT_CTRL1_REG 16 /* PHY Specific Control Reg */ |
| 324 | #define MV1111_SPEC_STAT_REG 17 /* PHY Specific Status Reg */ | |
| 325 | #define MV1111_EXT_CTRL2_REG 20 /* Extended PHY Specific Control Reg */ | |
| d1927cee | 326 | |
| 327 | /* | |
| 328 | * MARVELL 88E1111 PHY register bit masks | |
| 329 | */ | |
| 330 | /* PHY Specific Status Register (MV1111_EXT_CTRL1_REG) */ | |
| 331 | ||
| ee311214 | 332 | #define SPEC_STAT_SPEED_MASK (3 << 14) |
| 333 | #define SPEC_STAT_FULL_DUP (1 << 13) | |
| 334 | #define SPEC_STAT_PAGE_RCVD (1 << 12) | |
| 335 | #define SPEC_STAT_RESOLVED (1 << 11) /* Speed and Duplex Resolved */ | |
| 336 | #define SPEC_STAT_LINK_UP (1 << 10) | |
| 337 | #define SPEC_STAT_CABLE_LEN_MASK (7 << 7)/* Cable Length (100/1000 modes only) */ | |
| 338 | #define SPEC_STAT_MDIX (1 << 6) | |
| 339 | #define SPEC_STAT_POLARITY (1 << 1) | |
| 340 | #define SPEC_STAT_JABBER (1 << 0) | |
| d1927cee | 341 | |
| ee311214 | 342 | #define SPEED_1000 (2 << 14) |
| 343 | #define SPEED_100 (1 << 14) | |
| 344 | #define SPEED_10 (0 << 14) | |
| d1927cee | 345 | |
| ee311214 | 346 | #define TBI_ADDR 0x1E /* Ten Bit Interface address */ |
| d1927cee | 347 | |
| 348 | /* negotiated link parameters */ | |
| ee311214 | 349 | #define LINK_SPEED_UNKNOWN 0 |
| 350 | #define LINK_SPEED_10 1 | |
| 351 | #define LINK_SPEED_100 2 | |
| 352 | #define LINK_SPEED_1000 3 | |
| d1927cee | 353 | |
| ee311214 | 354 | #define LINK_DUPLEX_UNKNOWN 0 |
| 355 | #define LINK_DUPLEX_HALF 1 | |
| 356 | #define LINK_DUPLEX_FULL 2 | |
| d1927cee | 357 | |
| 358 | static unsigned int phy_address[] = { 8, 9 }; | |
| 359 | ||
| 360 | #define vuint32 volatile u32 | |
| 361 | ||
| 362 | /* TX/RX buffer descriptors. MUST be cache line aligned in memory. (32 byte) | |
| 363 | * This structure is accessed by the ethernet DMA engine which means it | |
| 364 | * MUST be in LITTLE ENDIAN format */ | |
| 365 | struct dma_descriptor { | |
| 366 | vuint32 start_addr0; /* buffer address, least significant bytes. */ | |
| 367 | vuint32 start_addr1; /* buffer address, most significant bytes. */ | |
| 368 | vuint32 next_descr_addr0;/* next descriptor address, least significant bytes. Must be 64-bit aligned. */ | |
| 369 | vuint32 next_descr_addr1;/* next descriptor address, most significant bytes. */ | |
| 370 | vuint32 vlan_byte_count;/* VLAN tag(top 2 bytes) and byte countt (bottom 2 bytes). */ | |
| 371 | vuint32 config_status; /* Configuration/Status. */ | |
| 372 | vuint32 reserved1; /* reserved to make the descriptor cache line aligned. */ | |
| 373 | vuint32 reserved2; /* reserved to make the descriptor cache line aligned. */ | |
| 374 | }; | |
| 375 | ||
| 376 | /* last next descriptor address flag */ | |
| ee311214 | 377 | #define DMA_DESCR_LAST (1 << 31) |
| d1927cee | 378 | |
| 379 | /* TX DMA descriptor config status bits */ | |
| ee311214 | 380 | #define DMA_DESCR_TX_EOF (1 << 0) /* end of frame */ |
| 381 | #define DMA_DESCR_TX_SOF (1 << 1) /* start of frame */ | |
| 382 | #define DMA_DESCR_TX_PFVLAN (1 << 2) | |
| 383 | #define DMA_DESCR_TX_HUGE (1 << 3) | |
| 384 | #define DMA_DESCR_TX_PAD (1 << 4) | |
| 385 | #define DMA_DESCR_TX_CRC (1 << 5) | |
| 386 | #define DMA_DESCR_TX_DESCR_INT (1 << 14) | |
| 387 | #define DMA_DESCR_TX_RETRY_COUNT 0x000F0000 | |
| 388 | #define DMA_DESCR_TX_ONE_COLLISION (1 << 20) | |
| 389 | #define DMA_DESCR_TX_LATE_COLLISION (1 << 24) | |
| 390 | #define DMA_DESCR_TX_UNDERRUN (1 << 25) | |
| 391 | #define DMA_DESCR_TX_RETRY_LIMIT (1 << 26) | |
| 392 | #define DMA_DESCR_TX_OK (1 << 30) | |
| 393 | #define DMA_DESCR_TX_OWNER (1 << 31) | |
| d1927cee | 394 | |
| 395 | /* RX DMA descriptor status bits */ | |
| ee311214 | 396 | #define DMA_DESCR_RX_EOF (1 << 0) |
| 397 | #define DMA_DESCR_RX_SOF (1 << 1) | |
| 398 | #define DMA_DESCR_RX_VTF (1 << 2) | |
| 399 | #define DMA_DESCR_RX_FRAME_IS_TYPE (1 << 3) | |
| 400 | #define DMA_DESCR_RX_SHORT_FRAME (1 << 4) | |
| 401 | #define DMA_DESCR_RX_HASH_MATCH (1 << 7) | |
| 402 | #define DMA_DESCR_RX_BAD_FRAME (1 << 8) | |
| 403 | #define DMA_DESCR_RX_OVERRUN (1 << 9) | |
| 404 | #define DMA_DESCR_RX_MAX_FRAME_LEN (1 << 11) | |
| 405 | #define DMA_DESCR_RX_CRC_ERROR (1 << 12) | |
| 406 | #define DMA_DESCR_RX_DESCR_INT (1 << 13) | |
| 407 | #define DMA_DESCR_RX_OWNER (1 << 15) | |
| 408 | ||
| 409 | #define RX_BUFFER_SIZE PKTSIZE | |
| 410 | #define NUM_RX_DESC PKTBUFSRX | |
| d1927cee | 411 | |
| 412 | static struct dma_descriptor tx_descriptor __attribute__ ((aligned(32))); | |
| 413 | ||
| 414 | static struct dma_descriptor rx_descr_array[NUM_RX_DESC] | |
| ee311214 | 415 | __attribute__ ((aligned(32))); |
| d1927cee | 416 | |
| 417 | static struct dma_descriptor *rx_descr_current; | |
| 418 | ||
| ee311214 | 419 | static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis); |
| e5c83f33 | 420 | static int tsi108_eth_send(struct eth_device *dev, void *packet, int length); |
| ee311214 | 421 | static int tsi108_eth_recv (struct eth_device *dev); |
| 422 | static void tsi108_eth_halt (struct eth_device *dev); | |
| 423 | static unsigned int read_phy (unsigned int base, | |
| d1927cee | 424 | unsigned int phy_addr, unsigned int phy_reg); |
| ee311214 | 425 | static void write_phy (unsigned int base, |
| d1927cee | 426 | unsigned int phy_addr, |
| 427 | unsigned int phy_reg, unsigned int phy_data); | |
| 428 | ||
| 429 | #if TSI108_ETH_DEBUG > 100 | |
| 430 | /* | |
| 431 | * print phy debug infomation | |
| 432 | */ | |
| ee311214 | 433 | static void dump_phy_regs (unsigned int phy_addr) |
| d1927cee | 434 | { |
| 435 | int i; | |
| 436 | ||
| ee311214 | 437 | printf ("PHY %d registers\n", phy_addr); |
| d1927cee | 438 | for (i = 0; i <= 30; i++) { |
| ee311214 | 439 | printf ("%2d 0x%04x\n", i, read_phy (ETH_BASE, phy_addr, i)); |
| d1927cee | 440 | } |
| ee311214 | 441 | printf ("\n"); |
| d1927cee | 442 | |
| 443 | } | |
| 444 | #else | |
| 445 | #define dump_phy_regs(base) do{}while(0) | |
| 446 | #endif | |
| 447 | ||
| 448 | #if TSI108_ETH_DEBUG > 100 | |
| 449 | /* | |
| 450 | * print debug infomation | |
| 451 | */ | |
| ee311214 | 452 | static void tx_diag_regs (unsigned int base) |
| d1927cee | 453 | { |
| 454 | int i; | |
| 455 | unsigned long dummy; | |
| 456 | ||
| ee311214 | 457 | printf ("TX diagnostics registers\n"); |
| d1927cee | 458 | reg_TX_DIAGNOSTIC_ADDR(base) = 0x00 | TX_DIAGNOSTIC_ADDR_AI; |
| ee311214 | 459 | udelay (1000); |
| d1927cee | 460 | dummy = reg_TX_DIAGNOSTIC_DATA(base); |
| 461 | for (i = 0x00; i <= 0x05; i++) { | |
| ee311214 | 462 | udelay (1000); |
| 463 | printf ("0x%02x 0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base)); | |
| d1927cee | 464 | } |
| 465 | reg_TX_DIAGNOSTIC_ADDR(base) = 0x40 | TX_DIAGNOSTIC_ADDR_AI; | |
| ee311214 | 466 | udelay (1000); |
| d1927cee | 467 | dummy = reg_TX_DIAGNOSTIC_DATA(base); |
| 468 | for (i = 0x40; i <= 0x47; i++) { | |
| ee311214 | 469 | udelay (1000); |
| 470 | printf ("0x%02x 0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base)); | |
| d1927cee | 471 | } |
| ee311214 | 472 | printf ("\n"); |
| d1927cee | 473 | |
| 474 | } | |
| 475 | #else | |
| 476 | #define tx_diag_regs(base) do{}while(0) | |
| 477 | #endif | |
| 478 | ||
| 479 | #if TSI108_ETH_DEBUG > 100 | |
| 480 | /* | |
| 481 | * print debug infomation | |
| 482 | */ | |
| ee311214 | 483 | static void rx_diag_regs (unsigned int base) |
| d1927cee | 484 | { |
| 485 | int i; | |
| 486 | unsigned long dummy; | |
| 487 | ||
| ee311214 | 488 | printf ("RX diagnostics registers\n"); |
| d1927cee | 489 | reg_RX_DIAGNOSTIC_ADDR(base) = 0x00 | RX_DIAGNOSTIC_ADDR_AI; |
| ee311214 | 490 | udelay (1000); |
| d1927cee | 491 | dummy = reg_RX_DIAGNOSTIC_DATA(base); |
| 492 | for (i = 0x00; i <= 0x05; i++) { | |
| ee311214 | 493 | udelay (1000); |
| 494 | printf ("0x%02x 0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base)); | |
| d1927cee | 495 | } |
| 496 | reg_RX_DIAGNOSTIC_ADDR(base) = 0x40 | RX_DIAGNOSTIC_ADDR_AI; | |
| ee311214 | 497 | udelay (1000); |
| d1927cee | 498 | dummy = reg_RX_DIAGNOSTIC_DATA(base); |
| 499 | for (i = 0x08; i <= 0x0a; i++) { | |
| ee311214 | 500 | udelay (1000); |
| 501 | printf ("0x%02x 0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base)); | |
| d1927cee | 502 | } |
| ee311214 | 503 | printf ("\n"); |
| d1927cee | 504 | |
| 505 | } | |
| 506 | #else | |
| 507 | #define rx_diag_regs(base) do{}while(0) | |
| 508 | #endif | |
| 509 | ||
| 510 | #if TSI108_ETH_DEBUG > 100 | |
| 511 | /* | |
| 512 | * print debug infomation | |
| 513 | */ | |
| ee311214 | 514 | static void debug_mii_regs (unsigned int base) |
| d1927cee | 515 | { |
| ee311214 | 516 | printf ("MII_MGMT_CONFIG 0x%08x\n", reg_MII_MGMT_CONFIG(base)); |
| 517 | printf ("MII_MGMT_COMMAND 0x%08x\n", reg_MII_MGMT_COMMAND(base)); | |
| 518 | printf ("MII_MGMT_ADDRESS 0x%08x\n", reg_MII_MGMT_ADDRESS(base)); | |
| 519 | printf ("MII_MGMT_CONTROL 0x%08x\n", reg_MII_MGMT_CONTROL(base)); | |
| 520 | printf ("MII_MGMT_STATUS 0x%08x\n", reg_MII_MGMT_STATUS(base)); | |
| 521 | printf ("MII_MGMT_INDICATORS 0x%08x\n", reg_MII_MGMT_INDICATORS(base)); | |
| 522 | printf ("\n"); | |
| d1927cee | 523 | |
| 524 | } | |
| 525 | #else | |
| 526 | #define debug_mii_regs(base) do{}while(0) | |
| 527 | #endif | |
| 528 | ||
| 529 | /* | |
| 530 | * Wait until the phy bus is non-busy | |
| 531 | */ | |
| ee311214 | 532 | static void phy_wait (unsigned int base, unsigned int condition) |
| d1927cee | 533 | { |
| 534 | int timeout; | |
| 535 | ||
| 536 | timeout = 0; | |
| 537 | while (reg_MII_MGMT_INDICATORS(base) & condition) { | |
| ee311214 | 538 | udelay (10); |
| d1927cee | 539 | if (++timeout > 10000) { |
| ee311214 | 540 | printf ("ERROR: timeout waiting for phy bus (%d)\n", |
| d1927cee | 541 | condition); |
| 542 | break; | |
| 543 | } | |
| 544 | } | |
| 545 | } | |
| 546 | ||
| 547 | /* | |
| 548 | * read phy register | |
| 549 | */ | |
| ee311214 | 550 | static unsigned int read_phy (unsigned int base, |
| d1927cee | 551 | unsigned int phy_addr, unsigned int phy_reg) |
| 552 | { | |
| 553 | unsigned int value; | |
| 554 | ||
| ee311214 | 555 | phy_wait (base, MII_MGMT_INDICATORS_BUSY); |
| d1927cee | 556 | |
| 557 | reg_MII_MGMT_ADDRESS(base) = (phy_addr << 8) | phy_reg; | |
| 558 | ||
| 559 | /* Ensure that the Read Cycle bit is cleared prior to next read cycle */ | |
| 560 | reg_MII_MGMT_COMMAND(base) = 0; | |
| 561 | ||
| 562 | /* start the read */ | |
| 563 | reg_MII_MGMT_COMMAND(base) = MII_MGMT_COMMAND_READ_CYCLE; | |
| 564 | ||
| 565 | /* wait for the read to complete */ | |
| ee311214 | 566 | phy_wait (base, |
| d1927cee | 567 | MII_MGMT_INDICATORS_NOT_VALID | MII_MGMT_INDICATORS_BUSY); |
| 568 | ||
| 569 | value = reg_MII_MGMT_STATUS(base); | |
| 570 | ||
| 571 | reg_MII_MGMT_COMMAND(base) = 0; | |
| 572 | ||
| 573 | return value; | |
| 574 | } | |
| 575 | ||
| 576 | /* | |
| 577 | * write phy register | |
| 578 | */ | |
| ee311214 | 579 | static void write_phy (unsigned int base, |
| d1927cee | 580 | unsigned int phy_addr, |
| 581 | unsigned int phy_reg, unsigned int phy_data) | |
| 582 | { | |
| ee311214 | 583 | phy_wait (base, MII_MGMT_INDICATORS_BUSY); |
| d1927cee | 584 | |
| 585 | reg_MII_MGMT_ADDRESS(base) = (phy_addr << 8) | phy_reg; | |
| 586 | ||
| 587 | /* Ensure that the Read Cycle bit is cleared prior to next cycle */ | |
| 588 | reg_MII_MGMT_COMMAND(base) = 0; | |
| 589 | ||
| 590 | /* start the write */ | |
| 591 | reg_MII_MGMT_CONTROL(base) = phy_data; | |
| 592 | } | |
| 593 | ||
| 594 | /* | |
| 595 | * configure the marvell 88e1111 phy | |
| 596 | */ | |
| ee311214 | 597 | static int marvell_88e_phy_config (struct eth_device *dev, int *speed, |
| d1927cee | 598 | int *duplex) |
| 599 | { | |
| 600 | unsigned long base; | |
| 601 | unsigned long phy_addr; | |
| 602 | unsigned int phy_status; | |
| 603 | unsigned int phy_spec_status; | |
| 604 | int timeout; | |
| 605 | int phy_speed; | |
| 606 | int phy_duplex; | |
| 607 | unsigned int value; | |
| 608 | ||
| 609 | phy_speed = LINK_SPEED_UNKNOWN; | |
| 610 | phy_duplex = LINK_DUPLEX_UNKNOWN; | |
| 611 | ||
| 612 | base = dev->iobase; | |
| 613 | phy_addr = (unsigned long)dev->priv; | |
| 614 | ||
| 615 | /* Take the PHY out of reset. */ | |
| ee311214 | 616 | write_phy (ETH_BASE, phy_addr, PHY_CTRL_REG, PHY_CTRL_RESET); |
| d1927cee | 617 | |
| 618 | /* Wait for the reset process to complete. */ | |
| ee311214 | 619 | udelay (10); |
| d1927cee | 620 | timeout = 0; |
| 621 | while ((phy_status = | |
| ee311214 | 622 | read_phy (ETH_BASE, phy_addr, PHY_CTRL_REG)) & PHY_CTRL_RESET) { |
| 623 | udelay (10); | |
| d1927cee | 624 | if (++timeout > 10000) { |
| ee311214 | 625 | printf ("ERROR: timeout waiting for phy reset\n"); |
| d1927cee | 626 | break; |
| 627 | } | |
| 628 | } | |
| 629 | ||
| 630 | /* TBI Configuration. */ | |
| ee311214 | 631 | write_phy (base, TBI_ADDR, TBI_CONTROL_2, TBI_CONTROL_2_G_MII_MODE | |
| d1927cee | 632 | TBI_CONTROL_2_RECEIVE_CLOCK_SELECT); |
| 633 | /* Wait for the link to be established. */ | |
| 634 | timeout = 0; | |
| 635 | do { | |
| ee311214 | 636 | udelay (20000); |
| 637 | phy_status = read_phy (ETH_BASE, phy_addr, PHY_STATUS_REG); | |
| d1927cee | 638 | if (++timeout > 100) { |
| 639 | debug_lev(1, "ERROR: unable to establish link!!!\n"); | |
| 640 | break; | |
| 641 | } | |
| 642 | } while ((phy_status & PHY_STAT_LINK_UP) == 0); | |
| 643 | ||
| ee311214 | 644 | if ((phy_status & PHY_STAT_LINK_UP) == 0) |
| d1927cee | 645 | return 0; |
| d1927cee | 646 | |
| 647 | value = 0; | |
| ee311214 | 648 | phy_spec_status = read_phy (ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG); |
| d1927cee | 649 | if (phy_spec_status & SPEC_STAT_RESOLVED) { |
| 650 | switch (phy_spec_status & SPEC_STAT_SPEED_MASK) { | |
| 651 | case SPEED_1000: | |
| 652 | phy_speed = LINK_SPEED_1000; | |
| 653 | value |= PHY_CTRL_SPEED1; | |
| 654 | break; | |
| 655 | case SPEED_100: | |
| 656 | phy_speed = LINK_SPEED_100; | |
| 657 | value |= PHY_CTRL_SPEED0; | |
| 658 | break; | |
| 659 | case SPEED_10: | |
| 660 | phy_speed = LINK_SPEED_10; | |
| 661 | break; | |
| 662 | } | |
| 663 | if (phy_spec_status & SPEC_STAT_FULL_DUP) { | |
| 664 | phy_duplex = LINK_DUPLEX_FULL; | |
| 665 | value |= PHY_CTRL_FULL_DUPLEX; | |
| ee311214 | 666 | } else |
| d1927cee | 667 | phy_duplex = LINK_DUPLEX_HALF; |
| d1927cee | 668 | } |
| 669 | /* set TBI speed */ | |
| ee311214 | 670 | write_phy (base, TBI_ADDR, PHY_CTRL_REG, value); |
| 671 | write_phy (base, TBI_ADDR, PHY_AN_ADV_REG, 0x0060); | |
| d1927cee | 672 | |
| 673 | #if TSI108_ETH_DEBUG > 0 | |
| ee311214 | 674 | printf ("%s link is up", dev->name); |
| 675 | phy_spec_status = read_phy (ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG); | |
| d1927cee | 676 | if (phy_spec_status & SPEC_STAT_RESOLVED) { |
| 677 | switch (phy_speed) { | |
| 678 | case LINK_SPEED_1000: | |
| ee311214 | 679 | printf (", 1000 Mbps"); |
| d1927cee | 680 | break; |
| 681 | case LINK_SPEED_100: | |
| ee311214 | 682 | printf (", 100 Mbps"); |
| d1927cee | 683 | break; |
| 684 | case LINK_SPEED_10: | |
| ee311214 | 685 | printf (", 10 Mbps"); |
| d1927cee | 686 | break; |
| 687 | } | |
| ee311214 | 688 | if (phy_duplex == LINK_DUPLEX_FULL) |
| 689 | printf (", Full duplex"); | |
| 690 | else | |
| 691 | printf (", Half duplex"); | |
| d1927cee | 692 | } |
| ee311214 | 693 | printf ("\n"); |
| d1927cee | 694 | #endif |
| 695 | ||
| ee311214 | 696 | dump_phy_regs (TBI_ADDR); |
| 697 | if (speed) | |
| d1927cee | 698 | *speed = phy_speed; |
| ee311214 | 699 | if (duplex) |
| d1927cee | 700 | *duplex = phy_duplex; |
| d1927cee | 701 | |
| 702 | return 1; | |
| 703 | } | |
| 704 | ||
| 705 | /* | |
| 706 | * External interface | |
| 707 | * | |
| 708 | * register the tsi108 ethernet controllers with the multi-ethernet system | |
| 709 | */ | |
| ee311214 | 710 | int tsi108_eth_initialize (bd_t * bis) |
| d1927cee | 711 | { |
| 712 | struct eth_device *dev; | |
| 713 | int index; | |
| 714 | ||
| 715 | for (index = 0; index < CONFIG_TSI108_ETH_NUM_PORTS; index++) { | |
| 716 | dev = (struct eth_device *)malloc(sizeof(struct eth_device)); | |
| 7faeb997 NI |
717 | if (!dev) { |
| 718 | printf("tsi108: Can not allocate memory\n"); | |
| 719 | break; | |
| 720 | } | |
| 721 | memset(dev, 0, sizeof(*dev)); | |
| ee311214 | 722 | sprintf (dev->name, "TSI108_eth%d", index); |
| d1927cee | 723 | |
| 724 | dev->iobase = ETH_BASE + (index * ETH_PORT_OFFSET); | |
| 725 | dev->priv = (void *)(phy_address[index]); | |
| 726 | dev->init = tsi108_eth_probe; | |
| 727 | dev->halt = tsi108_eth_halt; | |
| 728 | dev->send = tsi108_eth_send; | |
| 729 | dev->recv = tsi108_eth_recv; | |
| 730 | ||
| 731 | eth_register(dev); | |
| 732 | } | |
| 733 | return index; | |
| 734 | } | |
| 735 | ||
| 736 | /* | |
| 737 | * probe for and initialize a single ethernet interface | |
| 738 | */ | |
| ee311214 | 739 | static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis) |
| d1927cee | 740 | { |
| 741 | unsigned long base; | |
| 742 | unsigned long value; | |
| 743 | int index; | |
| 744 | struct dma_descriptor *tx_descr; | |
| 745 | struct dma_descriptor *rx_descr; | |
| 746 | int speed; | |
| 747 | int duplex; | |
| 748 | ||
| 749 | base = dev->iobase; | |
| 750 | ||
| 751 | reg_PORT_CONTROL(base) = PORT_CONTROL_STE | PORT_CONTROL_BPT; | |
| 752 | ||
| 753 | /* Bring DMA/FIFO out of reset. */ | |
| 754 | reg_TX_CONFIG(base) = 0x00000000; | |
| 755 | reg_RX_CONFIG(base) = 0x00000000; | |
| 756 | ||
| 757 | reg_TX_THRESHOLDS(base) = (192 << 16) | 192; | |
| 758 | reg_RX_THRESHOLDS(base) = (192 << 16) | 112; | |
| 759 | ||
| 760 | /* Bring MAC out of reset. */ | |
| 761 | reg_MAC_CONFIG_1(base) = 0x00000000; | |
| 762 | ||
| 763 | /* DMA MAC configuration. */ | |
| 764 | reg_MAC_CONFIG_1(base) = | |
| 765 | MAC_CONFIG_1_RX_ENABLE | MAC_CONFIG_1_TX_ENABLE; | |
| 766 | ||
| 767 | reg_MII_MGMT_CONFIG(base) = MII_MGMT_CONFIG_NO_PREAMBLE; | |
| 768 | reg_MAXIMUM_FRAME_LENGTH(base) = RX_BUFFER_SIZE; | |
| 769 | ||
| 770 | /* Note: Early tsi108 manual did not have correct byte order | |
| 771 | * for the station address.*/ | |
| 772 | reg_STATION_ADDRESS_1(base) = (dev->enetaddr[5] << 24) | | |
| 773 | (dev->enetaddr[4] << 16) | | |
| 774 | (dev->enetaddr[3] << 8) | (dev->enetaddr[2] << 0); | |
| 775 | ||
| 776 | reg_STATION_ADDRESS_2(base) = (dev->enetaddr[1] << 24) | | |
| 777 | (dev->enetaddr[0] << 16); | |
| 778 | ||
| ee311214 | 779 | if (marvell_88e_phy_config(dev, &speed, &duplex) == 0) |
| 422b1a01 | 780 | return -1; |
| d1927cee | 781 | |
| 782 | value = | |
| 783 | MAC_CONFIG_2_PREAMBLE_LENGTH(7) | MAC_CONFIG_2_PAD_CRC | | |
| 784 | MAC_CONFIG_2_CRC_ENABLE; | |
| ee311214 | 785 | if (speed == LINK_SPEED_1000) |
| d1927cee | 786 | value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_BYTE); |
| ee311214 | 787 | else { |
| d1927cee | 788 | value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_NIBBLE); |
| 789 | reg_PORT_CONTROL(base) |= PORT_CONTROL_SPD; | |
| 790 | } | |
| 791 | if (duplex == LINK_DUPLEX_FULL) { | |
| 792 | value |= MAC_CONFIG_2_FULL_DUPLEX; | |
| 793 | reg_PORT_CONTROL(base) &= ~PORT_CONTROL_BPT; | |
| ee311214 | 794 | } else |
| d1927cee | 795 | reg_PORT_CONTROL(base) |= PORT_CONTROL_BPT; |
| d1927cee | 796 | reg_MAC_CONFIG_2(base) = value; |
| 797 | ||
| 798 | reg_RX_CONFIG(base) = RX_CONFIG_SE; | |
| 799 | reg_RX_QUEUE_0_CONFIG(base) = OCN_PORT_MEMORY; | |
| 800 | reg_RX_QUEUE_0_BUF_CONFIG(base) = OCN_PORT_MEMORY; | |
| 801 | ||
| 802 | /* initialize the RX DMA descriptors */ | |
| 803 | rx_descr = &rx_descr_array[0]; | |
| 804 | rx_descr_current = rx_descr; | |
| 805 | for (index = 0; index < NUM_RX_DESC; index++) { | |
| 806 | /* make sure the receive buffers are not in cache */ | |
| 1fd92db8 JH |
807 | invalidate_dcache_range((unsigned long)net_rx_packets[index], |
| 808 | (unsigned long)net_rx_packets[index] + | |
| d1927cee | 809 | RX_BUFFER_SIZE); |
| 810 | rx_descr->start_addr0 = | |
| 1fd92db8 | 811 | cpu_to_le32((vuint32) net_rx_packets[index]); |
| d1927cee | 812 | rx_descr->start_addr1 = 0; |
| 813 | rx_descr->next_descr_addr0 = | |
| 814 | cpu_to_le32((vuint32) (rx_descr + 1)); | |
| 815 | rx_descr->next_descr_addr1 = 0; | |
| 816 | rx_descr->vlan_byte_count = 0; | |
| 817 | rx_descr->config_status = cpu_to_le32((RX_BUFFER_SIZE << 16) | | |
| 818 | DMA_DESCR_RX_OWNER); | |
| 819 | rx_descr++; | |
| 820 | } | |
| 821 | rx_descr--; | |
| 822 | rx_descr->next_descr_addr0 = 0; | |
| 823 | rx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST); | |
| 824 | /* Push the descriptors to RAM so the ethernet DMA can see them */ | |
| 825 | invalidate_dcache_range((unsigned long)rx_descr_array, | |
| 826 | (unsigned long)rx_descr_array + | |
| 827 | sizeof(rx_descr_array)); | |
| 828 | ||
| 829 | /* enable RX queue */ | |
| 830 | reg_RX_CONTROL(base) = TX_CONTROL_GO | 0x01; | |
| 831 | reg_RX_QUEUE_0_PTR_LOW(base) = (u32) rx_descr_current; | |
| 832 | /* enable receive DMA */ | |
| 833 | reg_RX_QUEUE_0_PTR_HIGH(base) = RX_QUEUE_0_PTR_HIGH_VALID; | |
| 834 | ||
| 835 | reg_TX_QUEUE_0_CONFIG(base) = OCN_PORT_MEMORY; | |
| 836 | reg_TX_QUEUE_0_BUF_CONFIG(base) = OCN_PORT_MEMORY; | |
| 837 | ||
| 838 | /* initialize the TX DMA descriptor */ | |
| 839 | tx_descr = &tx_descriptor; | |
| 840 | ||
| 841 | tx_descr->start_addr0 = 0; | |
| 842 | tx_descr->start_addr1 = 0; | |
| 843 | tx_descr->next_descr_addr0 = 0; | |
| 844 | tx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST); | |
| 845 | tx_descr->vlan_byte_count = 0; | |
| 846 | tx_descr->config_status = cpu_to_le32(DMA_DESCR_TX_OK | | |
| 847 | DMA_DESCR_TX_SOF | | |
| 848 | DMA_DESCR_TX_EOF); | |
| 849 | /* enable TX queue */ | |
| 850 | reg_TX_CONTROL(base) = TX_CONTROL_GO | 0x01; | |
| 851 | ||
| 422b1a01 | 852 | return 0; |
| d1927cee | 853 | } |
| 854 | ||
| 855 | /* | |
| 856 | * send a packet | |
| 857 | */ | |
| e5c83f33 | 858 | static int tsi108_eth_send(struct eth_device *dev, void *packet, int length) |
| d1927cee | 859 | { |
| 860 | unsigned long base; | |
| 861 | int timeout; | |
| 862 | struct dma_descriptor *tx_descr; | |
| 863 | unsigned long status; | |
| 864 | ||
| 865 | base = dev->iobase; | |
| 866 | tx_descr = &tx_descriptor; | |
| 867 | ||
| 868 | /* Wait until the last packet has been transmitted. */ | |
| 869 | timeout = 0; | |
| 870 | do { | |
| 871 | /* make sure we see the changes made by the DMA engine */ | |
| 872 | invalidate_dcache_range((unsigned long)tx_descr, | |
| 873 | (unsigned long)tx_descr + | |
| 874 | sizeof(struct dma_descriptor)); | |
| 875 | ||
| ee311214 | 876 | if (timeout != 0) |
| 877 | udelay (15); | |
| d1927cee | 878 | if (++timeout > 10000) { |
| 879 | tx_diag_regs(base); | |
| 880 | debug_lev(1, | |
| 881 | "ERROR: timeout waiting for last transmit packet to be sent\n"); | |
| 882 | return 0; | |
| 883 | } | |
| 884 | } while (tx_descr->config_status & cpu_to_le32(DMA_DESCR_TX_OWNER)); | |
| 885 | ||
| 886 | status = le32_to_cpu(tx_descr->config_status); | |
| 887 | if ((status & DMA_DESCR_TX_OK) == 0) { | |
| 888 | #ifdef TX_PRINT_ERRORS | |
| bde63587 | 889 | printf ("TX packet error: 0x%08lx\n %s%s%s%s\n", status, |
| d1927cee | 890 | status & DMA_DESCR_TX_OK ? "tx error, " : "", |
| 891 | status & DMA_DESCR_TX_RETRY_LIMIT ? | |
| 892 | "retry limit reached, " : "", | |
| 893 | status & DMA_DESCR_TX_UNDERRUN ? "underrun, " : "", | |
| 894 | status & DMA_DESCR_TX_LATE_COLLISION ? "late collision, " | |
| 895 | : ""); | |
| 896 | #endif | |
| 897 | } | |
| 898 | ||
| ee311214 | 899 | debug_lev (9, "sending packet %d\n", length); |
| d1927cee | 900 | tx_descr->start_addr0 = cpu_to_le32((vuint32) packet); |
| 901 | tx_descr->start_addr1 = 0; | |
| 902 | tx_descr->next_descr_addr0 = 0; | |
| 903 | tx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST); | |
| 904 | tx_descr->vlan_byte_count = cpu_to_le32(length); | |
| 905 | tx_descr->config_status = cpu_to_le32(DMA_DESCR_TX_OWNER | | |
| 906 | DMA_DESCR_TX_CRC | | |
| 907 | DMA_DESCR_TX_PAD | | |
| 908 | DMA_DESCR_TX_SOF | | |
| 909 | DMA_DESCR_TX_EOF); | |
| 910 | ||
| 911 | invalidate_dcache_range((unsigned long)tx_descr, | |
| 912 | (unsigned long)tx_descr + | |
| 913 | sizeof(struct dma_descriptor)); | |
| 914 | ||
| 915 | invalidate_dcache_range((unsigned long)packet, | |
| 916 | (unsigned long)packet + length); | |
| 917 | ||
| 918 | reg_TX_QUEUE_0_PTR_LOW(base) = (u32) tx_descr; | |
| 919 | reg_TX_QUEUE_0_PTR_HIGH(base) = TX_QUEUE_0_PTR_HIGH_VALID; | |
| 920 | ||
| 921 | return length; | |
| 922 | } | |
| 923 | ||
| 924 | /* | |
| 925 | * Check for received packets and send them up the protocal stack | |
| 926 | */ | |
| ee311214 | 927 | static int tsi108_eth_recv (struct eth_device *dev) |
| d1927cee | 928 | { |
| 929 | struct dma_descriptor *rx_descr; | |
| 930 | unsigned long base; | |
| 931 | int length = 0; | |
| 932 | unsigned long status; | |
| e5c83f33 | 933 | uchar *buffer; |
| d1927cee | 934 | |
| 935 | base = dev->iobase; | |
| 936 | ||
| 937 | /* make sure we see the changes made by the DMA engine */ | |
| ee311214 | 938 | invalidate_dcache_range ((unsigned long)rx_descr_array, |
| d1927cee | 939 | (unsigned long)rx_descr_array + |
| 940 | sizeof(rx_descr_array)); | |
| 941 | ||
| 942 | /* process all of the received packets */ | |
| 943 | rx_descr = rx_descr_current; | |
| 944 | while ((rx_descr->config_status & cpu_to_le32(DMA_DESCR_RX_OWNER)) == 0) { | |
| 945 | /* check for error */ | |
| 946 | status = le32_to_cpu(rx_descr->config_status); | |
| 947 | if (status & DMA_DESCR_RX_BAD_FRAME) { | |
| 948 | #ifdef RX_PRINT_ERRORS | |
| bde63587 | 949 | printf ("RX packet error: 0x%08lx\n %s%s%s%s%s%s\n", |
| d1927cee | 950 | status, |
| 951 | status & DMA_DESCR_RX_FRAME_IS_TYPE ? "too big, " | |
| 952 | : "", | |
| 953 | status & DMA_DESCR_RX_SHORT_FRAME ? "too short, " | |
| 954 | : "", | |
| 955 | status & DMA_DESCR_RX_BAD_FRAME ? "bad frame, " : | |
| 956 | "", | |
| 957 | status & DMA_DESCR_RX_OVERRUN ? "overrun, " : "", | |
| 958 | status & DMA_DESCR_RX_MAX_FRAME_LEN ? | |
| 959 | "max length, " : "", | |
| 960 | status & DMA_DESCR_RX_CRC_ERROR ? "CRC error, " : | |
| 961 | ""); | |
| 962 | #endif | |
| 963 | } else { | |
| 964 | length = | |
| 965 | le32_to_cpu(rx_descr->vlan_byte_count) & 0xFFFF; | |
| 966 | ||
| 967 | /*** process packet ***/ | |
| e5c83f33 | 968 | buffer = (uchar *)(le32_to_cpu(rx_descr->start_addr0)); |
| 1fd92db8 | 969 | net_process_received_packet(buffer, length); |
| d1927cee | 970 | |
| ee311214 | 971 | invalidate_dcache_range ((unsigned long)buffer, |
| d1927cee | 972 | (unsigned long)buffer + |
| 973 | RX_BUFFER_SIZE); | |
| 974 | } | |
| 975 | /* Give this buffer back to the DMA engine */ | |
| 976 | rx_descr->vlan_byte_count = 0; | |
| ee311214 | 977 | rx_descr->config_status = cpu_to_le32 ((RX_BUFFER_SIZE << 16) | |
| d1927cee | 978 | DMA_DESCR_RX_OWNER); |
| 979 | /* move descriptor pointer forward */ | |
| 980 | rx_descr = | |
| 981 | (struct dma_descriptor | |
| ee311214 | 982 | *)(le32_to_cpu (rx_descr->next_descr_addr0)); |
| 983 | if (rx_descr == 0) | |
| d1927cee | 984 | rx_descr = &rx_descr_array[0]; |
| d1927cee | 985 | } |
| 986 | /* remember where we are for next time */ | |
| 987 | rx_descr_current = rx_descr; | |
| 988 | ||
| 989 | /* If the DMA engine has reached the end of the queue | |
| 990 | * start over at the begining */ | |
| 991 | if (reg_RX_EXTENDED_STATUS(base) & RX_EXTENDED_STATUS_EOQ_0) { | |
| 992 | ||
| 993 | reg_RX_EXTENDED_STATUS(base) = RX_EXTENDED_STATUS_EOQ_0; | |
| 994 | reg_RX_QUEUE_0_PTR_LOW(base) = (u32) & rx_descr_array[0]; | |
| 995 | reg_RX_QUEUE_0_PTR_HIGH(base) = RX_QUEUE_0_PTR_HIGH_VALID; | |
| 996 | } | |
| 997 | ||
| 998 | return length; | |
| 999 | } | |
| 1000 | ||
| 1001 | /* | |
| 1002 | * disable an ethernet interface | |
| 1003 | */ | |
| ee311214 | 1004 | static void tsi108_eth_halt (struct eth_device *dev) |
| d1927cee | 1005 | { |
| 1006 | unsigned long base; | |
| 1007 | ||
| 1008 | base = dev->iobase; | |
| 1009 | ||
| 1010 | /* Put DMA/FIFO into reset state. */ | |
| 1011 | reg_TX_CONFIG(base) = TX_CONFIG_RST; | |
| 1012 | reg_RX_CONFIG(base) = RX_CONFIG_RST; | |
| 1013 | ||
| 1014 | /* Put MAC into reset state. */ | |
| 1015 | reg_MAC_CONFIG_1(base) = MAC_CONFIG_1_SOFT_RESET; | |
| 1016 | } |