projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| d1927cee | 1 | /*********************************************************************** |
| 2 | * | |
| 3 | * Copyright (c) 2005 Freescale Semiconductor, Inc. | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | * | |
| 23 | * Description: | |
| 24 | * Ethernet interface for Tundra TSI108 bridge chip | |
| 25 | * | |
| 26 | ***********************************************************************/ | |
| 27 | ||
| 28 | #include <config.h> | |
| 29 | ||
| d1927cee | 30 | #if !defined(CONFIG_TSI108_ETH_NUM_PORTS) || (CONFIG_TSI108_ETH_NUM_PORTS > 2) |
| 31 | #error "CONFIG_TSI108_ETH_NUM_PORTS must be defined as 1 or 2" | |
| 32 | #endif | |
| 33 | ||
| 34 | #include <common.h> | |
| 35 | #include <malloc.h> | |
| 36 | #include <net.h> | |
| ccdd12f8 | 37 | #include <netdev.h> |
| d1927cee | 38 | #include <asm/cache.h> |
| 39 | ||
| 40 | #ifdef DEBUG | |
| 41 | #define TSI108_ETH_DEBUG 7 | |
| 42 | #else | |
| 43 | #define TSI108_ETH_DEBUG 0 | |
| 44 | #endif | |
| 45 | ||
| 46 | #if TSI108_ETH_DEBUG > 0 | |
| ee311214 | 47 | #define debug_lev(lev, fmt, args...) \ |
| 48 | if (lev <= TSI108_ETH_DEBUG) \ | |
| 49 | printf ("%s %d: " fmt, __FUNCTION__, __LINE__, ##args) | |
| d1927cee | 50 | #else |
| 51 | #define debug_lev(lev, fmt, args...) do{}while(0) | |
| 52 | #endif | |
| 53 | ||
| 54 | #define RX_PRINT_ERRORS | |
| 55 | #define TX_PRINT_ERRORS | |
| 56 | ||
| 6d0f6bcf | 57 | #define ETH_BASE (CONFIG_SYS_TSI108_CSR_BASE + 0x6000) |
| d1927cee | 58 | |
| ee311214 | 59 | #define ETH_PORT_OFFSET 0x400 |
| d1927cee | 60 | |
| 61 | #define __REG32(base, offset) (*((volatile u32 *)((char *)(base) + (offset)))) | |
| 62 | ||
| ee311214 | 63 | #define reg_MAC_CONFIG_1(base) __REG32(base, 0x00000000) |
| 64 | #define MAC_CONFIG_1_TX_ENABLE (0x00000001) | |
| 65 | #define MAC_CONFIG_1_SYNC_TX_ENABLE (0x00000002) | |
| 66 | #define MAC_CONFIG_1_RX_ENABLE (0x00000004) | |
| 67 | #define MAC_CONFIG_1_SYNC_RX_ENABLE (0x00000008) | |
| 68 | #define MAC_CONFIG_1_TX_FLOW_CONTROL (0x00000010) | |
| 69 | #define MAC_CONFIG_1_RX_FLOW_CONTROL (0x00000020) | |
| 70 | #define MAC_CONFIG_1_LOOP_BACK (0x00000100) | |
| 71 | #define MAC_CONFIG_1_RESET_TX_FUNCTION (0x00010000) | |
| 72 | #define MAC_CONFIG_1_RESET_RX_FUNCTION (0x00020000) | |
| 73 | #define MAC_CONFIG_1_RESET_TX_MAC (0x00040000) | |
| 74 | #define MAC_CONFIG_1_RESET_RX_MAC (0x00080000) | |
| 75 | #define MAC_CONFIG_1_SIM_RESET (0x40000000) | |
| 76 | #define MAC_CONFIG_1_SOFT_RESET (0x80000000) | |
| 77 | ||
| 78 | #define reg_MAC_CONFIG_2(base) __REG32(base, 0x00000004) | |
| 79 | #define MAC_CONFIG_2_FULL_DUPLEX (0x00000001) | |
| 80 | #define MAC_CONFIG_2_CRC_ENABLE (0x00000002) | |
| 81 | #define MAC_CONFIG_2_PAD_CRC (0x00000004) | |
| 82 | #define MAC_CONFIG_2_LENGTH_CHECK (0x00000010) | |
| 83 | #define MAC_CONFIG_2_HUGE_FRAME (0x00000020) | |
| 84 | #define MAC_CONFIG_2_INTERFACE_MODE(val) (((val) & 0x3) << 8) | |
| 85 | #define MAC_CONFIG_2_PREAMBLE_LENGTH(val) (((val) & 0xf) << 12) | |
| 86 | #define INTERFACE_MODE_NIBBLE 1 /* 10/100 Mb/s MII) */ | |
| 87 | #define INTERFACE_MODE_BYTE 2 /* 1000 Mb/s GMII/TBI */ | |
| 88 | ||
| 89 | #define reg_MAXIMUM_FRAME_LENGTH(base) __REG32(base, 0x00000010) | |
| 90 | ||
| 91 | #define reg_MII_MGMT_CONFIG(base) __REG32(base, 0x00000020) | |
| 92 | #define MII_MGMT_CONFIG_MGMT_CLOCK_SELECT(val) ((val) & 0x7) | |
| 93 | #define MII_MGMT_CONFIG_NO_PREAMBLE (0x00000010) | |
| 94 | #define MII_MGMT_CONFIG_SCAN_INCREMENT (0x00000020) | |
| 95 | #define MII_MGMT_CONFIG_RESET_MGMT (0x80000000) | |
| 96 | ||
| 97 | #define reg_MII_MGMT_COMMAND(base) __REG32(base, 0x00000024) | |
| 98 | #define MII_MGMT_COMMAND_READ_CYCLE (0x00000001) | |
| 99 | #define MII_MGMT_COMMAND_SCAN_CYCLE (0x00000002) | |
| 100 | ||
| 101 | #define reg_MII_MGMT_ADDRESS(base) __REG32(base, 0x00000028) | |
| 102 | #define reg_MII_MGMT_CONTROL(base) __REG32(base, 0x0000002c) | |
| 103 | #define reg_MII_MGMT_STATUS(base) __REG32(base, 0x00000030) | |
| 104 | ||
| 105 | #define reg_MII_MGMT_INDICATORS(base) __REG32(base, 0x00000034) | |
| 106 | #define MII_MGMT_INDICATORS_BUSY (0x00000001) | |
| 107 | #define MII_MGMT_INDICATORS_SCAN (0x00000002) | |
| 108 | #define MII_MGMT_INDICATORS_NOT_VALID (0x00000004) | |
| 109 | ||
| 110 | #define reg_INTERFACE_STATUS(base) __REG32(base, 0x0000003c) | |
| 111 | #define INTERFACE_STATUS_LINK_FAIL (0x00000008) | |
| 112 | #define INTERFACE_STATUS_EXCESS_DEFER (0x00000200) | |
| 113 | ||
| 114 | #define reg_STATION_ADDRESS_1(base) __REG32(base, 0x00000040) | |
| 115 | #define reg_STATION_ADDRESS_2(base) __REG32(base, 0x00000044) | |
| 116 | ||
| 117 | #define reg_PORT_CONTROL(base) __REG32(base, 0x00000200) | |
| 118 | #define PORT_CONTROL_PRI (0x00000001) | |
| 119 | #define PORT_CONTROL_BPT (0x00010000) | |
| 120 | #define PORT_CONTROL_SPD (0x00040000) | |
| 121 | #define PORT_CONTROL_RBC (0x00080000) | |
| 122 | #define PORT_CONTROL_PRB (0x00200000) | |
| 123 | #define PORT_CONTROL_DIS (0x00400000) | |
| 124 | #define PORT_CONTROL_TBI (0x00800000) | |
| 125 | #define PORT_CONTROL_STE (0x10000000) | |
| 126 | #define PORT_CONTROL_ZOR (0x20000000) | |
| 127 | #define PORT_CONTROL_CLR (0x40000000) | |
| 128 | #define PORT_CONTROL_SRT (0x80000000) | |
| 129 | ||
| 130 | #define reg_TX_CONFIG(base) __REG32(base, 0x00000220) | |
| 131 | #define TX_CONFIG_START_Q (0x00000003) | |
| 132 | #define TX_CONFIG_EHP (0x00400000) | |
| 133 | #define TX_CONFIG_CHP (0x00800000) | |
| 134 | #define TX_CONFIG_RST (0x80000000) | |
| 135 | ||
| 136 | #define reg_TX_CONTROL(base) __REG32(base, 0x00000224) | |
| 137 | #define TX_CONTROL_GO (0x00008000) | |
| 138 | #define TX_CONTROL_MP (0x01000000) | |
| 139 | #define TX_CONTROL_EAI (0x20000000) | |
| 140 | #define TX_CONTROL_ABT (0x40000000) | |
| 141 | #define TX_CONTROL_EII (0x80000000) | |
| 142 | ||
| 143 | #define reg_TX_STATUS(base) __REG32(base, 0x00000228) | |
| 144 | #define TX_STATUS_QUEUE_USABLE (0x0000000f) | |
| 145 | #define TX_STATUS_CURR_Q (0x00000300) | |
| 146 | #define TX_STATUS_ACT (0x00008000) | |
| 147 | #define TX_STATUS_QUEUE_IDLE (0x000f0000) | |
| 148 | #define TX_STATUS_EOQ_PENDING (0x0f000000) | |
| 149 | ||
| 150 | #define reg_TX_EXTENDED_STATUS(base) __REG32(base, 0x0000022c) | |
| 151 | #define TX_EXTENDED_STATUS_END_OF_QUEUE_CONDITION (0x0000000f) | |
| 152 | #define TX_EXTENDED_STATUS_END_OF_FRAME_CONDITION (0x00000f00) | |
| 153 | #define TX_EXTENDED_STATUS_DESCRIPTOR_INTERRUPT_CONDITION (0x000f0000) | |
| 154 | #define TX_EXTENDED_STATUS_ERROR_FLAG (0x0f000000) | |
| 155 | ||
| 156 | #define reg_TX_THRESHOLDS(base) __REG32(base, 0x00000230) | |
| d1927cee | 157 | |
| 158 | #define reg_TX_DIAGNOSTIC_ADDR(base) __REG32(base, 0x00000270) | |
| ee311214 | 159 | #define TX_DIAGNOSTIC_ADDR_INDEX (0x0000007f) |
| 160 | #define TX_DIAGNOSTIC_ADDR_DFR (0x40000000) | |
| 161 | #define TX_DIAGNOSTIC_ADDR_AI (0x80000000) | |
| 162 | ||
| 163 | #define reg_TX_DIAGNOSTIC_DATA(base) __REG32(base, 0x00000274) | |
| 164 | ||
| 165 | #define reg_TX_ERROR_STATUS(base) __REG32(base, 0x00000278) | |
| 166 | #define TX_ERROR_STATUS (0x00000278) | |
| 167 | #define TX_ERROR_STATUS_QUEUE_0_ERROR_RESPONSE (0x0000000f) | |
| 168 | #define TX_ERROR_STATUS_TEA_ON_QUEUE_0 (0x00000010) | |
| 169 | #define TX_ERROR_STATUS_RER_ON_QUEUE_0 (0x00000020) | |
| 170 | #define TX_ERROR_STATUS_TER_ON_QUEUE_0 (0x00000040) | |
| 171 | #define TX_ERROR_STATUS_DER_ON_QUEUE_0 (0x00000080) | |
| 172 | #define TX_ERROR_STATUS_QUEUE_1_ERROR_RESPONSE (0x00000f00) | |
| 173 | #define TX_ERROR_STATUS_TEA_ON_QUEUE_1 (0x00001000) | |
| 174 | #define TX_ERROR_STATUS_RER_ON_QUEUE_1 (0x00002000) | |
| 175 | #define TX_ERROR_STATUS_TER_ON_QUEUE_1 (0x00004000) | |
| 176 | #define TX_ERROR_STATUS_DER_ON_QUEUE_1 (0x00008000) | |
| 177 | #define TX_ERROR_STATUS_QUEUE_2_ERROR_RESPONSE (0x000f0000) | |
| 178 | #define TX_ERROR_STATUS_TEA_ON_QUEUE_2 (0x00100000) | |
| 179 | #define TX_ERROR_STATUS_RER_ON_QUEUE_2 (0x00200000) | |
| 180 | #define TX_ERROR_STATUS_TER_ON_QUEUE_2 (0x00400000) | |
| 181 | #define TX_ERROR_STATUS_DER_ON_QUEUE_2 (0x00800000) | |
| 182 | #define TX_ERROR_STATUS_QUEUE_3_ERROR_RESPONSE (0x0f000000) | |
| 183 | #define TX_ERROR_STATUS_TEA_ON_QUEUE_3 (0x10000000) | |
| 184 | #define TX_ERROR_STATUS_RER_ON_QUEUE_3 (0x20000000) | |
| 185 | #define TX_ERROR_STATUS_TER_ON_QUEUE_3 (0x40000000) | |
| 186 | #define TX_ERROR_STATUS_DER_ON_QUEUE_3 (0x80000000) | |
| 187 | ||
| 188 | #define reg_TX_QUEUE_0_CONFIG(base) __REG32(base, 0x00000280) | |
| 189 | #define TX_QUEUE_0_CONFIG_OCN_PORT (0x0000003f) | |
| 190 | #define TX_QUEUE_0_CONFIG_BSWP (0x00000400) | |
| 191 | #define TX_QUEUE_0_CONFIG_WSWP (0x00000800) | |
| 192 | #define TX_QUEUE_0_CONFIG_AM (0x00004000) | |
| 193 | #define TX_QUEUE_0_CONFIG_GVI (0x00008000) | |
| 194 | #define TX_QUEUE_0_CONFIG_EEI (0x00010000) | |
| 195 | #define TX_QUEUE_0_CONFIG_ELI (0x00020000) | |
| 196 | #define TX_QUEUE_0_CONFIG_ENI (0x00040000) | |
| 197 | #define TX_QUEUE_0_CONFIG_ESI (0x00080000) | |
| 198 | #define TX_QUEUE_0_CONFIG_EDI (0x00100000) | |
| 199 | ||
| 200 | #define reg_TX_QUEUE_0_BUF_CONFIG(base) __REG32(base, 0x00000284) | |
| 201 | #define TX_QUEUE_0_BUF_CONFIG_OCN_PORT (0x0000003f) | |
| 202 | #define TX_QUEUE_0_BUF_CONFIG_BURST (0x00000300) | |
| 203 | #define TX_QUEUE_0_BUF_CONFIG_BSWP (0x00000400) | |
| 204 | #define TX_QUEUE_0_BUF_CONFIG_WSWP (0x00000800) | |
| 205 | ||
| 206 | #define OCN_PORT_HLP 0 /* HLP Interface */ | |
| 207 | #define OCN_PORT_PCI_X 1 /* PCI-X Interface */ | |
| d1927cee | 208 | #define OCN_PORT_PROCESSOR_MASTER 2 /* Processor Interface (master) */ |
| ee311214 | 209 | #define OCN_PORT_PROCESSOR_SLAVE 3 /* Processor Interface (slave) */ |
| 210 | #define OCN_PORT_MEMORY 4 /* Memory Controller */ | |
| 211 | #define OCN_PORT_DMA 5 /* DMA Controller */ | |
| 212 | #define OCN_PORT_ETHERNET 6 /* Ethernet Controller */ | |
| 213 | #define OCN_PORT_PRINT 7 /* Print Engine Interface */ | |
| 214 | ||
| 215 | #define reg_TX_QUEUE_0_PTR_LOW(base) __REG32(base, 0x00000288) | |
| 216 | ||
| 217 | #define reg_TX_QUEUE_0_PTR_HIGH(base) __REG32(base, 0x0000028c) | |
| 218 | #define TX_QUEUE_0_PTR_HIGH_VALID (0x80000000) | |
| 219 | ||
| 220 | #define reg_RX_CONFIG(base) __REG32(base, 0x00000320) | |
| 221 | #define RX_CONFIG_DEF_Q (0x00000003) | |
| 222 | #define RX_CONFIG_EMF (0x00000100) | |
| 223 | #define RX_CONFIG_EUF (0x00000200) | |
| 224 | #define RX_CONFIG_BFE (0x00000400) | |
| 225 | #define RX_CONFIG_MFE (0x00000800) | |
| 226 | #define RX_CONFIG_UFE (0x00001000) | |
| 227 | #define RX_CONFIG_SE (0x00002000) | |
| 228 | #define RX_CONFIG_ABF (0x00200000) | |
| 229 | #define RX_CONFIG_APE (0x00400000) | |
| 230 | #define RX_CONFIG_CHP (0x00800000) | |
| 231 | #define RX_CONFIG_RST (0x80000000) | |
| 232 | ||
| 233 | #define reg_RX_CONTROL(base) __REG32(base, 0x00000324) | |
| 234 | #define GE_E0_RX_CONTROL_QUEUE_ENABLES (0x0000000f) | |
| 235 | #define GE_E0_RX_CONTROL_GO (0x00008000) | |
| 236 | #define GE_E0_RX_CONTROL_EAI (0x20000000) | |
| 237 | #define GE_E0_RX_CONTROL_ABT (0x40000000) | |
| 238 | #define GE_E0_RX_CONTROL_EII (0x80000000) | |
| 239 | ||
| 240 | #define reg_RX_EXTENDED_STATUS(base) __REG32(base, 0x0000032c) | |
| 241 | #define RX_EXTENDED_STATUS (0x0000032c) | |
| 242 | #define RX_EXTENDED_STATUS_EOQ (0x0000000f) | |
| 243 | #define RX_EXTENDED_STATUS_EOQ_0 (0x00000001) | |
| 244 | #define RX_EXTENDED_STATUS_EOF (0x00000f00) | |
| 245 | #define RX_EXTENDED_STATUS_DESCRIPTOR_INTERRUPT_CONDITION (0x000f0000) | |
| 246 | #define RX_EXTENDED_STATUS_ERROR_FLAG (0x0f000000) | |
| 247 | ||
| 248 | #define reg_RX_THRESHOLDS(base) __REG32(base, 0x00000330) | |
| 249 | ||
| 250 | #define reg_RX_DIAGNOSTIC_ADDR(base) __REG32(base, 0x00000370) | |
| 251 | #define RX_DIAGNOSTIC_ADDR_INDEX (0x0000007f) | |
| 252 | #define RX_DIAGNOSTIC_ADDR_DFR (0x40000000) | |
| 253 | #define RX_DIAGNOSTIC_ADDR_AI (0x80000000) | |
| 254 | ||
| 255 | #define reg_RX_DIAGNOSTIC_DATA(base) __REG32(base, 0x00000374) | |
| 256 | ||
| 257 | #define reg_RX_QUEUE_0_CONFIG(base) __REG32(base, 0x00000380) | |
| 258 | #define RX_QUEUE_0_CONFIG_OCN_PORT (0x0000003f) | |
| 259 | #define RX_QUEUE_0_CONFIG_BSWP (0x00000400) | |
| 260 | #define RX_QUEUE_0_CONFIG_WSWP (0x00000800) | |
| 261 | #define RX_QUEUE_0_CONFIG_AM (0x00004000) | |
| 262 | #define RX_QUEUE_0_CONFIG_EEI (0x00010000) | |
| 263 | #define RX_QUEUE_0_CONFIG_ELI (0x00020000) | |
| 264 | #define RX_QUEUE_0_CONFIG_ENI (0x00040000) | |
| 265 | #define RX_QUEUE_0_CONFIG_ESI (0x00080000) | |
| 266 | #define RX_QUEUE_0_CONFIG_EDI (0x00100000) | |
| 267 | ||
| 268 | #define reg_RX_QUEUE_0_BUF_CONFIG(base) __REG32(base, 0x00000384) | |
| 269 | #define RX_QUEUE_0_BUF_CONFIG_OCN_PORT (0x0000003f) | |
| 270 | #define RX_QUEUE_0_BUF_CONFIG_BURST (0x00000300) | |
| 271 | #define RX_QUEUE_0_BUF_CONFIG_BSWP (0x00000400) | |
| 272 | #define RX_QUEUE_0_BUF_CONFIG_WSWP (0x00000800) | |
| 273 | ||
| 274 | #define reg_RX_QUEUE_0_PTR_LOW(base) __REG32(base, 0x00000388) | |
| 275 | ||
| 276 | #define reg_RX_QUEUE_0_PTR_HIGH(base) __REG32(base, 0x0000038c) | |
| 277 | #define RX_QUEUE_0_PTR_HIGH_VALID (0x80000000) | |
| d1927cee | 278 | |
| 279 | /* | |
| 280 | * PHY register definitions | |
| 281 | */ | |
| 282 | /* the first 15 PHY registers are standard. */ | |
| ee311214 | 283 | #define PHY_CTRL_REG 0 /* Control Register */ |
| 284 | #define PHY_STATUS_REG 1 /* Status Regiser */ | |
| 285 | #define PHY_ID1_REG 2 /* Phy Id Reg (word 1) */ | |
| 286 | #define PHY_ID2_REG 3 /* Phy Id Reg (word 2) */ | |
| 287 | #define PHY_AN_ADV_REG 4 /* Autoneg Advertisement */ | |
| 288 | #define PHY_LP_ABILITY_REG 5 /* Link Partner Ability (Base Page) */ | |
| 289 | #define PHY_AUTONEG_EXP_REG 6 /* Autoneg Expansion Reg */ | |
| 290 | #define PHY_NEXT_PAGE_TX_REG 7 /* Next Page TX */ | |
| 291 | #define PHY_LP_NEXT_PAGE_REG 8 /* Link Partner Next Page */ | |
| 292 | #define PHY_1000T_CTRL_REG 9 /* 1000Base-T Control Reg */ | |
| 293 | #define PHY_1000T_STATUS_REG 10 /* 1000Base-T Status Reg */ | |
| 294 | #define PHY_EXT_STATUS_REG 11 /* Extended Status Reg */ | |
| d1927cee | 295 | |
| 296 | /* | |
| 297 | * PHY Register bit masks. | |
| 298 | */ | |
| ee311214 | 299 | #define PHY_CTRL_RESET (1 << 15) |
| 300 | #define PHY_CTRL_LOOPBACK (1 << 14) | |
| 301 | #define PHY_CTRL_SPEED0 (1 << 13) | |
| 302 | #define PHY_CTRL_AN_EN (1 << 12) | |
| 303 | #define PHY_CTRL_PWR_DN (1 << 11) | |
| 304 | #define PHY_CTRL_ISOLATE (1 << 10) | |
| 305 | #define PHY_CTRL_RESTART_AN (1 << 9) | |
| 306 | #define PHY_CTRL_FULL_DUPLEX (1 << 8) | |
| 307 | #define PHY_CTRL_CT_EN (1 << 7) | |
| 308 | #define PHY_CTRL_SPEED1 (1 << 6) | |
| 309 | ||
| 310 | #define PHY_STAT_100BASE_T4 (1 << 15) | |
| 311 | #define PHY_STAT_100BASE_X_FD (1 << 14) | |
| 312 | #define PHY_STAT_100BASE_X_HD (1 << 13) | |
| 313 | #define PHY_STAT_10BASE_T_FD (1 << 12) | |
| 314 | #define PHY_STAT_10BASE_T_HD (1 << 11) | |
| 315 | #define PHY_STAT_100BASE_T2_FD (1 << 10) | |
| 316 | #define PHY_STAT_100BASE_T2_HD (1 << 9) | |
| 317 | #define PHY_STAT_EXT_STAT (1 << 8) | |
| 318 | #define PHY_STAT_RESERVED (1 << 7) | |
| 319 | #define PHY_STAT_MFPS (1 << 6) /* Management Frames Preamble Suppression */ | |
| 320 | #define PHY_STAT_AN_COMPLETE (1 << 5) | |
| 321 | #define PHY_STAT_REM_FAULT (1 << 4) | |
| 322 | #define PHY_STAT_AN_CAP (1 << 3) | |
| 323 | #define PHY_STAT_LINK_UP (1 << 2) | |
| 324 | #define PHY_STAT_JABBER (1 << 1) | |
| 325 | #define PHY_STAT_EXT_CAP (1 << 0) | |
| 326 | ||
| 327 | #define TBI_CONTROL_2 0x11 | |
| 328 | #define TBI_CONTROL_2_ENABLE_COMMA_DETECT 0x0001 | |
| 329 | #define TBI_CONTROL_2_ENABLE_WRAP 0x0002 | |
| 330 | #define TBI_CONTROL_2_G_MII_MODE 0x0010 | |
| 331 | #define TBI_CONTROL_2_RECEIVE_CLOCK_SELECT 0x0020 | |
| 332 | #define TBI_CONTROL_2_AUTO_NEGOTIATION_SENSE 0x0100 | |
| 333 | #define TBI_CONTROL_2_DISABLE_TRANSMIT_RUNNING_DISPARITY 0x1000 | |
| 334 | #define TBI_CONTROL_2_DISABLE_RECEIVE_RUNNING_DISPARITY 0x2000 | |
| 335 | #define TBI_CONTROL_2_SHORTCUT_LINK_TIMER 0x4000 | |
| 336 | #define TBI_CONTROL_2_SOFT_RESET 0x8000 | |
| d1927cee | 337 | |
| 338 | /* marvel specific */ | |
| ee311214 | 339 | #define MV1111_EXT_CTRL1_REG 16 /* PHY Specific Control Reg */ |
| 340 | #define MV1111_SPEC_STAT_REG 17 /* PHY Specific Status Reg */ | |
| 341 | #define MV1111_EXT_CTRL2_REG 20 /* Extended PHY Specific Control Reg */ | |
| d1927cee | 342 | |
| 343 | /* | |
| 344 | * MARVELL 88E1111 PHY register bit masks | |
| 345 | */ | |
| 346 | /* PHY Specific Status Register (MV1111_EXT_CTRL1_REG) */ | |
| 347 | ||
| ee311214 | 348 | #define SPEC_STAT_SPEED_MASK (3 << 14) |
| 349 | #define SPEC_STAT_FULL_DUP (1 << 13) | |
| 350 | #define SPEC_STAT_PAGE_RCVD (1 << 12) | |
| 351 | #define SPEC_STAT_RESOLVED (1 << 11) /* Speed and Duplex Resolved */ | |
| 352 | #define SPEC_STAT_LINK_UP (1 << 10) | |
| 353 | #define SPEC_STAT_CABLE_LEN_MASK (7 << 7)/* Cable Length (100/1000 modes only) */ | |
| 354 | #define SPEC_STAT_MDIX (1 << 6) | |
| 355 | #define SPEC_STAT_POLARITY (1 << 1) | |
| 356 | #define SPEC_STAT_JABBER (1 << 0) | |
| d1927cee | 357 | |
| ee311214 | 358 | #define SPEED_1000 (2 << 14) |
| 359 | #define SPEED_100 (1 << 14) | |
| 360 | #define SPEED_10 (0 << 14) | |
| d1927cee | 361 | |
| ee311214 | 362 | #define TBI_ADDR 0x1E /* Ten Bit Interface address */ |
| d1927cee | 363 | |
| 364 | /* negotiated link parameters */ | |
| ee311214 | 365 | #define LINK_SPEED_UNKNOWN 0 |
| 366 | #define LINK_SPEED_10 1 | |
| 367 | #define LINK_SPEED_100 2 | |
| 368 | #define LINK_SPEED_1000 3 | |
| d1927cee | 369 | |
| ee311214 | 370 | #define LINK_DUPLEX_UNKNOWN 0 |
| 371 | #define LINK_DUPLEX_HALF 1 | |
| 372 | #define LINK_DUPLEX_FULL 2 | |
| d1927cee | 373 | |
| 374 | static unsigned int phy_address[] = { 8, 9 }; | |
| 375 | ||
| 376 | #define vuint32 volatile u32 | |
| 377 | ||
| 378 | /* TX/RX buffer descriptors. MUST be cache line aligned in memory. (32 byte) | |
| 379 | * This structure is accessed by the ethernet DMA engine which means it | |
| 380 | * MUST be in LITTLE ENDIAN format */ | |
| 381 | struct dma_descriptor { | |
| 382 | vuint32 start_addr0; /* buffer address, least significant bytes. */ | |
| 383 | vuint32 start_addr1; /* buffer address, most significant bytes. */ | |
| 384 | vuint32 next_descr_addr0;/* next descriptor address, least significant bytes. Must be 64-bit aligned. */ | |
| 385 | vuint32 next_descr_addr1;/* next descriptor address, most significant bytes. */ | |
| 386 | vuint32 vlan_byte_count;/* VLAN tag(top 2 bytes) and byte countt (bottom 2 bytes). */ | |
| 387 | vuint32 config_status; /* Configuration/Status. */ | |
| 388 | vuint32 reserved1; /* reserved to make the descriptor cache line aligned. */ | |
| 389 | vuint32 reserved2; /* reserved to make the descriptor cache line aligned. */ | |
| 390 | }; | |
| 391 | ||
| 392 | /* last next descriptor address flag */ | |
| ee311214 | 393 | #define DMA_DESCR_LAST (1 << 31) |
| d1927cee | 394 | |
| 395 | /* TX DMA descriptor config status bits */ | |
| ee311214 | 396 | #define DMA_DESCR_TX_EOF (1 << 0) /* end of frame */ |
| 397 | #define DMA_DESCR_TX_SOF (1 << 1) /* start of frame */ | |
| 398 | #define DMA_DESCR_TX_PFVLAN (1 << 2) | |
| 399 | #define DMA_DESCR_TX_HUGE (1 << 3) | |
| 400 | #define DMA_DESCR_TX_PAD (1 << 4) | |
| 401 | #define DMA_DESCR_TX_CRC (1 << 5) | |
| 402 | #define DMA_DESCR_TX_DESCR_INT (1 << 14) | |
| 403 | #define DMA_DESCR_TX_RETRY_COUNT 0x000F0000 | |
| 404 | #define DMA_DESCR_TX_ONE_COLLISION (1 << 20) | |
| 405 | #define DMA_DESCR_TX_LATE_COLLISION (1 << 24) | |
| 406 | #define DMA_DESCR_TX_UNDERRUN (1 << 25) | |
| 407 | #define DMA_DESCR_TX_RETRY_LIMIT (1 << 26) | |
| 408 | #define DMA_DESCR_TX_OK (1 << 30) | |
| 409 | #define DMA_DESCR_TX_OWNER (1 << 31) | |
| d1927cee | 410 | |
| 411 | /* RX DMA descriptor status bits */ | |
| ee311214 | 412 | #define DMA_DESCR_RX_EOF (1 << 0) |
| 413 | #define DMA_DESCR_RX_SOF (1 << 1) | |
| 414 | #define DMA_DESCR_RX_VTF (1 << 2) | |
| 415 | #define DMA_DESCR_RX_FRAME_IS_TYPE (1 << 3) | |
| 416 | #define DMA_DESCR_RX_SHORT_FRAME (1 << 4) | |
| 417 | #define DMA_DESCR_RX_HASH_MATCH (1 << 7) | |
| 418 | #define DMA_DESCR_RX_BAD_FRAME (1 << 8) | |
| 419 | #define DMA_DESCR_RX_OVERRUN (1 << 9) | |
| 420 | #define DMA_DESCR_RX_MAX_FRAME_LEN (1 << 11) | |
| 421 | #define DMA_DESCR_RX_CRC_ERROR (1 << 12) | |
| 422 | #define DMA_DESCR_RX_DESCR_INT (1 << 13) | |
| 423 | #define DMA_DESCR_RX_OWNER (1 << 15) | |
| 424 | ||
| 425 | #define RX_BUFFER_SIZE PKTSIZE | |
| 426 | #define NUM_RX_DESC PKTBUFSRX | |
| d1927cee | 427 | |
| 428 | static struct dma_descriptor tx_descriptor __attribute__ ((aligned(32))); | |
| 429 | ||
| 430 | static struct dma_descriptor rx_descr_array[NUM_RX_DESC] | |
| ee311214 | 431 | __attribute__ ((aligned(32))); |
| d1927cee | 432 | |
| 433 | static struct dma_descriptor *rx_descr_current; | |
| 434 | ||
| ee311214 | 435 | static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis); |
| e5c83f33 | 436 | static int tsi108_eth_send(struct eth_device *dev, void *packet, int length); |
| ee311214 | 437 | static int tsi108_eth_recv (struct eth_device *dev); |
| 438 | static void tsi108_eth_halt (struct eth_device *dev); | |
| 439 | static unsigned int read_phy (unsigned int base, | |
| d1927cee | 440 | unsigned int phy_addr, unsigned int phy_reg); |
| ee311214 | 441 | static void write_phy (unsigned int base, |
| d1927cee | 442 | unsigned int phy_addr, |
| 443 | unsigned int phy_reg, unsigned int phy_data); | |
| 444 | ||
| 445 | #if TSI108_ETH_DEBUG > 100 | |
| 446 | /* | |
| 447 | * print phy debug infomation | |
| 448 | */ | |
| ee311214 | 449 | static void dump_phy_regs (unsigned int phy_addr) |
| d1927cee | 450 | { |
| 451 | int i; | |
| 452 | ||
| ee311214 | 453 | printf ("PHY %d registers\n", phy_addr); |
| d1927cee | 454 | for (i = 0; i <= 30; i++) { |
| ee311214 | 455 | printf ("%2d 0x%04x\n", i, read_phy (ETH_BASE, phy_addr, i)); |
| d1927cee | 456 | } |
| ee311214 | 457 | printf ("\n"); |
| d1927cee | 458 | |
| 459 | } | |
| 460 | #else | |
| 461 | #define dump_phy_regs(base) do{}while(0) | |
| 462 | #endif | |
| 463 | ||
| 464 | #if TSI108_ETH_DEBUG > 100 | |
| 465 | /* | |
| 466 | * print debug infomation | |
| 467 | */ | |
| ee311214 | 468 | static void tx_diag_regs (unsigned int base) |
| d1927cee | 469 | { |
| 470 | int i; | |
| 471 | unsigned long dummy; | |
| 472 | ||
| ee311214 | 473 | printf ("TX diagnostics registers\n"); |
| d1927cee | 474 | reg_TX_DIAGNOSTIC_ADDR(base) = 0x00 | TX_DIAGNOSTIC_ADDR_AI; |
| ee311214 | 475 | udelay (1000); |
| d1927cee | 476 | dummy = reg_TX_DIAGNOSTIC_DATA(base); |
| 477 | for (i = 0x00; i <= 0x05; i++) { | |
| ee311214 | 478 | udelay (1000); |
| 479 | printf ("0x%02x 0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base)); | |
| d1927cee | 480 | } |
| 481 | reg_TX_DIAGNOSTIC_ADDR(base) = 0x40 | TX_DIAGNOSTIC_ADDR_AI; | |
| ee311214 | 482 | udelay (1000); |
| d1927cee | 483 | dummy = reg_TX_DIAGNOSTIC_DATA(base); |
| 484 | for (i = 0x40; i <= 0x47; i++) { | |
| ee311214 | 485 | udelay (1000); |
| 486 | printf ("0x%02x 0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base)); | |
| d1927cee | 487 | } |
| ee311214 | 488 | printf ("\n"); |
| d1927cee | 489 | |
| 490 | } | |
| 491 | #else | |
| 492 | #define tx_diag_regs(base) do{}while(0) | |
| 493 | #endif | |
| 494 | ||
| 495 | #if TSI108_ETH_DEBUG > 100 | |
| 496 | /* | |
| 497 | * print debug infomation | |
| 498 | */ | |
| ee311214 | 499 | static void rx_diag_regs (unsigned int base) |
| d1927cee | 500 | { |
| 501 | int i; | |
| 502 | unsigned long dummy; | |
| 503 | ||
| ee311214 | 504 | printf ("RX diagnostics registers\n"); |
| d1927cee | 505 | reg_RX_DIAGNOSTIC_ADDR(base) = 0x00 | RX_DIAGNOSTIC_ADDR_AI; |
| ee311214 | 506 | udelay (1000); |
| d1927cee | 507 | dummy = reg_RX_DIAGNOSTIC_DATA(base); |
| 508 | for (i = 0x00; i <= 0x05; i++) { | |
| ee311214 | 509 | udelay (1000); |
| 510 | printf ("0x%02x 0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base)); | |
| d1927cee | 511 | } |
| 512 | reg_RX_DIAGNOSTIC_ADDR(base) = 0x40 | RX_DIAGNOSTIC_ADDR_AI; | |
| ee311214 | 513 | udelay (1000); |
| d1927cee | 514 | dummy = reg_RX_DIAGNOSTIC_DATA(base); |
| 515 | for (i = 0x08; i <= 0x0a; i++) { | |
| ee311214 | 516 | udelay (1000); |
| 517 | printf ("0x%02x 0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base)); | |
| d1927cee | 518 | } |
| ee311214 | 519 | printf ("\n"); |
| d1927cee | 520 | |
| 521 | } | |
| 522 | #else | |
| 523 | #define rx_diag_regs(base) do{}while(0) | |
| 524 | #endif | |
| 525 | ||
| 526 | #if TSI108_ETH_DEBUG > 100 | |
| 527 | /* | |
| 528 | * print debug infomation | |
| 529 | */ | |
| ee311214 | 530 | static void debug_mii_regs (unsigned int base) |
| d1927cee | 531 | { |
| ee311214 | 532 | printf ("MII_MGMT_CONFIG 0x%08x\n", reg_MII_MGMT_CONFIG(base)); |
| 533 | printf ("MII_MGMT_COMMAND 0x%08x\n", reg_MII_MGMT_COMMAND(base)); | |
| 534 | printf ("MII_MGMT_ADDRESS 0x%08x\n", reg_MII_MGMT_ADDRESS(base)); | |
| 535 | printf ("MII_MGMT_CONTROL 0x%08x\n", reg_MII_MGMT_CONTROL(base)); | |
| 536 | printf ("MII_MGMT_STATUS 0x%08x\n", reg_MII_MGMT_STATUS(base)); | |
| 537 | printf ("MII_MGMT_INDICATORS 0x%08x\n", reg_MII_MGMT_INDICATORS(base)); | |
| 538 | printf ("\n"); | |
| d1927cee | 539 | |
| 540 | } | |
| 541 | #else | |
| 542 | #define debug_mii_regs(base) do{}while(0) | |
| 543 | #endif | |
| 544 | ||
| 545 | /* | |
| 546 | * Wait until the phy bus is non-busy | |
| 547 | */ | |
| ee311214 | 548 | static void phy_wait (unsigned int base, unsigned int condition) |
| d1927cee | 549 | { |
| 550 | int timeout; | |
| 551 | ||
| 552 | timeout = 0; | |
| 553 | while (reg_MII_MGMT_INDICATORS(base) & condition) { | |
| ee311214 | 554 | udelay (10); |
| d1927cee | 555 | if (++timeout > 10000) { |
| ee311214 | 556 | printf ("ERROR: timeout waiting for phy bus (%d)\n", |
| d1927cee | 557 | condition); |
| 558 | break; | |
| 559 | } | |
| 560 | } | |
| 561 | } | |
| 562 | ||
| 563 | /* | |
| 564 | * read phy register | |
| 565 | */ | |
| ee311214 | 566 | static unsigned int read_phy (unsigned int base, |
| d1927cee | 567 | unsigned int phy_addr, unsigned int phy_reg) |
| 568 | { | |
| 569 | unsigned int value; | |
| 570 | ||
| ee311214 | 571 | phy_wait (base, MII_MGMT_INDICATORS_BUSY); |
| d1927cee | 572 | |
| 573 | reg_MII_MGMT_ADDRESS(base) = (phy_addr << 8) | phy_reg; | |
| 574 | ||
| 575 | /* Ensure that the Read Cycle bit is cleared prior to next read cycle */ | |
| 576 | reg_MII_MGMT_COMMAND(base) = 0; | |
| 577 | ||
| 578 | /* start the read */ | |
| 579 | reg_MII_MGMT_COMMAND(base) = MII_MGMT_COMMAND_READ_CYCLE; | |
| 580 | ||
| 581 | /* wait for the read to complete */ | |
| ee311214 | 582 | phy_wait (base, |
| d1927cee | 583 | MII_MGMT_INDICATORS_NOT_VALID | MII_MGMT_INDICATORS_BUSY); |
| 584 | ||
| 585 | value = reg_MII_MGMT_STATUS(base); | |
| 586 | ||
| 587 | reg_MII_MGMT_COMMAND(base) = 0; | |
| 588 | ||
| 589 | return value; | |
| 590 | } | |
| 591 | ||
| 592 | /* | |
| 593 | * write phy register | |
| 594 | */ | |
| ee311214 | 595 | static void write_phy (unsigned int base, |
| d1927cee | 596 | unsigned int phy_addr, |
| 597 | unsigned int phy_reg, unsigned int phy_data) | |
| 598 | { | |
| ee311214 | 599 | phy_wait (base, MII_MGMT_INDICATORS_BUSY); |
| d1927cee | 600 | |
| 601 | reg_MII_MGMT_ADDRESS(base) = (phy_addr << 8) | phy_reg; | |
| 602 | ||
| 603 | /* Ensure that the Read Cycle bit is cleared prior to next cycle */ | |
| 604 | reg_MII_MGMT_COMMAND(base) = 0; | |
| 605 | ||
| 606 | /* start the write */ | |
| 607 | reg_MII_MGMT_CONTROL(base) = phy_data; | |
| 608 | } | |
| 609 | ||
| 610 | /* | |
| 611 | * configure the marvell 88e1111 phy | |
| 612 | */ | |
| ee311214 | 613 | static int marvell_88e_phy_config (struct eth_device *dev, int *speed, |
| d1927cee | 614 | int *duplex) |
| 615 | { | |
| 616 | unsigned long base; | |
| 617 | unsigned long phy_addr; | |
| 618 | unsigned int phy_status; | |
| 619 | unsigned int phy_spec_status; | |
| 620 | int timeout; | |
| 621 | int phy_speed; | |
| 622 | int phy_duplex; | |
| 623 | unsigned int value; | |
| 624 | ||
| 625 | phy_speed = LINK_SPEED_UNKNOWN; | |
| 626 | phy_duplex = LINK_DUPLEX_UNKNOWN; | |
| 627 | ||
| 628 | base = dev->iobase; | |
| 629 | phy_addr = (unsigned long)dev->priv; | |
| 630 | ||
| 631 | /* Take the PHY out of reset. */ | |
| ee311214 | 632 | write_phy (ETH_BASE, phy_addr, PHY_CTRL_REG, PHY_CTRL_RESET); |
| d1927cee | 633 | |
| 634 | /* Wait for the reset process to complete. */ | |
| ee311214 | 635 | udelay (10); |
| d1927cee | 636 | timeout = 0; |
| 637 | while ((phy_status = | |
| ee311214 | 638 | read_phy (ETH_BASE, phy_addr, PHY_CTRL_REG)) & PHY_CTRL_RESET) { |
| 639 | udelay (10); | |
| d1927cee | 640 | if (++timeout > 10000) { |
| ee311214 | 641 | printf ("ERROR: timeout waiting for phy reset\n"); |
| d1927cee | 642 | break; |
| 643 | } | |
| 644 | } | |
| 645 | ||
| 646 | /* TBI Configuration. */ | |
| ee311214 | 647 | write_phy (base, TBI_ADDR, TBI_CONTROL_2, TBI_CONTROL_2_G_MII_MODE | |
| d1927cee | 648 | TBI_CONTROL_2_RECEIVE_CLOCK_SELECT); |
| 649 | /* Wait for the link to be established. */ | |
| 650 | timeout = 0; | |
| 651 | do { | |
| ee311214 | 652 | udelay (20000); |
| 653 | phy_status = read_phy (ETH_BASE, phy_addr, PHY_STATUS_REG); | |
| d1927cee | 654 | if (++timeout > 100) { |
| 655 | debug_lev(1, "ERROR: unable to establish link!!!\n"); | |
| 656 | break; | |
| 657 | } | |
| 658 | } while ((phy_status & PHY_STAT_LINK_UP) == 0); | |
| 659 | ||
| ee311214 | 660 | if ((phy_status & PHY_STAT_LINK_UP) == 0) |
| d1927cee | 661 | return 0; |
| d1927cee | 662 | |
| 663 | value = 0; | |
| ee311214 | 664 | phy_spec_status = read_phy (ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG); |
| d1927cee | 665 | if (phy_spec_status & SPEC_STAT_RESOLVED) { |
| 666 | switch (phy_spec_status & SPEC_STAT_SPEED_MASK) { | |
| 667 | case SPEED_1000: | |
| 668 | phy_speed = LINK_SPEED_1000; | |
| 669 | value |= PHY_CTRL_SPEED1; | |
| 670 | break; | |
| 671 | case SPEED_100: | |
| 672 | phy_speed = LINK_SPEED_100; | |
| 673 | value |= PHY_CTRL_SPEED0; | |
| 674 | break; | |
| 675 | case SPEED_10: | |
| 676 | phy_speed = LINK_SPEED_10; | |
| 677 | break; | |
| 678 | } | |
| 679 | if (phy_spec_status & SPEC_STAT_FULL_DUP) { | |
| 680 | phy_duplex = LINK_DUPLEX_FULL; | |
| 681 | value |= PHY_CTRL_FULL_DUPLEX; | |
| ee311214 | 682 | } else |
| d1927cee | 683 | phy_duplex = LINK_DUPLEX_HALF; |
| d1927cee | 684 | } |
| 685 | /* set TBI speed */ | |
| ee311214 | 686 | write_phy (base, TBI_ADDR, PHY_CTRL_REG, value); |
| 687 | write_phy (base, TBI_ADDR, PHY_AN_ADV_REG, 0x0060); | |
| d1927cee | 688 | |
| 689 | #if TSI108_ETH_DEBUG > 0 | |
| ee311214 | 690 | printf ("%s link is up", dev->name); |
| 691 | phy_spec_status = read_phy (ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG); | |
| d1927cee | 692 | if (phy_spec_status & SPEC_STAT_RESOLVED) { |
| 693 | switch (phy_speed) { | |
| 694 | case LINK_SPEED_1000: | |
| ee311214 | 695 | printf (", 1000 Mbps"); |
| d1927cee | 696 | break; |
| 697 | case LINK_SPEED_100: | |
| ee311214 | 698 | printf (", 100 Mbps"); |
| d1927cee | 699 | break; |
| 700 | case LINK_SPEED_10: | |
| ee311214 | 701 | printf (", 10 Mbps"); |
| d1927cee | 702 | break; |
| 703 | } | |
| ee311214 | 704 | if (phy_duplex == LINK_DUPLEX_FULL) |
| 705 | printf (", Full duplex"); | |
| 706 | else | |
| 707 | printf (", Half duplex"); | |
| d1927cee | 708 | } |
| ee311214 | 709 | printf ("\n"); |
| d1927cee | 710 | #endif |
| 711 | ||
| ee311214 | 712 | dump_phy_regs (TBI_ADDR); |
| 713 | if (speed) | |
| d1927cee | 714 | *speed = phy_speed; |
| ee311214 | 715 | if (duplex) |
| d1927cee | 716 | *duplex = phy_duplex; |
| d1927cee | 717 | |
| 718 | return 1; | |
| 719 | } | |
| 720 | ||
| 721 | /* | |
| 722 | * External interface | |
| 723 | * | |
| 724 | * register the tsi108 ethernet controllers with the multi-ethernet system | |
| 725 | */ | |
| ee311214 | 726 | int tsi108_eth_initialize (bd_t * bis) |
| d1927cee | 727 | { |
| 728 | struct eth_device *dev; | |
| 729 | int index; | |
| 730 | ||
| 731 | for (index = 0; index < CONFIG_TSI108_ETH_NUM_PORTS; index++) { | |
| 732 | dev = (struct eth_device *)malloc(sizeof(struct eth_device)); | |
| 7faeb997 NI |
733 | if (!dev) { |
| 734 | printf("tsi108: Can not allocate memory\n"); | |
| 735 | break; | |
| 736 | } | |
| 737 | memset(dev, 0, sizeof(*dev)); | |
| ee311214 | 738 | sprintf (dev->name, "TSI108_eth%d", index); |
| d1927cee | 739 | |
| 740 | dev->iobase = ETH_BASE + (index * ETH_PORT_OFFSET); | |
| 741 | dev->priv = (void *)(phy_address[index]); | |
| 742 | dev->init = tsi108_eth_probe; | |
| 743 | dev->halt = tsi108_eth_halt; | |
| 744 | dev->send = tsi108_eth_send; | |
| 745 | dev->recv = tsi108_eth_recv; | |
| 746 | ||
| 747 | eth_register(dev); | |
| 748 | } | |
| 749 | return index; | |
| 750 | } | |
| 751 | ||
| 752 | /* | |
| 753 | * probe for and initialize a single ethernet interface | |
| 754 | */ | |
| ee311214 | 755 | static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis) |
| d1927cee | 756 | { |
| 757 | unsigned long base; | |
| 758 | unsigned long value; | |
| 759 | int index; | |
| 760 | struct dma_descriptor *tx_descr; | |
| 761 | struct dma_descriptor *rx_descr; | |
| 762 | int speed; | |
| 763 | int duplex; | |
| 764 | ||
| 765 | base = dev->iobase; | |
| 766 | ||
| 767 | reg_PORT_CONTROL(base) = PORT_CONTROL_STE | PORT_CONTROL_BPT; | |
| 768 | ||
| 769 | /* Bring DMA/FIFO out of reset. */ | |
| 770 | reg_TX_CONFIG(base) = 0x00000000; | |
| 771 | reg_RX_CONFIG(base) = 0x00000000; | |
| 772 | ||
| 773 | reg_TX_THRESHOLDS(base) = (192 << 16) | 192; | |
| 774 | reg_RX_THRESHOLDS(base) = (192 << 16) | 112; | |
| 775 | ||
| 776 | /* Bring MAC out of reset. */ | |
| 777 | reg_MAC_CONFIG_1(base) = 0x00000000; | |
| 778 | ||
| 779 | /* DMA MAC configuration. */ | |
| 780 | reg_MAC_CONFIG_1(base) = | |
| 781 | MAC_CONFIG_1_RX_ENABLE | MAC_CONFIG_1_TX_ENABLE; | |
| 782 | ||
| 783 | reg_MII_MGMT_CONFIG(base) = MII_MGMT_CONFIG_NO_PREAMBLE; | |
| 784 | reg_MAXIMUM_FRAME_LENGTH(base) = RX_BUFFER_SIZE; | |
| 785 | ||
| 786 | /* Note: Early tsi108 manual did not have correct byte order | |
| 787 | * for the station address.*/ | |
| 788 | reg_STATION_ADDRESS_1(base) = (dev->enetaddr[5] << 24) | | |
| 789 | (dev->enetaddr[4] << 16) | | |
| 790 | (dev->enetaddr[3] << 8) | (dev->enetaddr[2] << 0); | |
| 791 | ||
| 792 | reg_STATION_ADDRESS_2(base) = (dev->enetaddr[1] << 24) | | |
| 793 | (dev->enetaddr[0] << 16); | |
| 794 | ||
| ee311214 | 795 | if (marvell_88e_phy_config(dev, &speed, &duplex) == 0) |
| 422b1a01 | 796 | return -1; |
| d1927cee | 797 | |
| 798 | value = | |
| 799 | MAC_CONFIG_2_PREAMBLE_LENGTH(7) | MAC_CONFIG_2_PAD_CRC | | |
| 800 | MAC_CONFIG_2_CRC_ENABLE; | |
| ee311214 | 801 | if (speed == LINK_SPEED_1000) |
| d1927cee | 802 | value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_BYTE); |
| ee311214 | 803 | else { |
| d1927cee | 804 | value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_NIBBLE); |
| 805 | reg_PORT_CONTROL(base) |= PORT_CONTROL_SPD; | |
| 806 | } | |
| 807 | if (duplex == LINK_DUPLEX_FULL) { | |
| 808 | value |= MAC_CONFIG_2_FULL_DUPLEX; | |
| 809 | reg_PORT_CONTROL(base) &= ~PORT_CONTROL_BPT; | |
| ee311214 | 810 | } else |
| d1927cee | 811 | reg_PORT_CONTROL(base) |= PORT_CONTROL_BPT; |
| d1927cee | 812 | reg_MAC_CONFIG_2(base) = value; |
| 813 | ||
| 814 | reg_RX_CONFIG(base) = RX_CONFIG_SE; | |
| 815 | reg_RX_QUEUE_0_CONFIG(base) = OCN_PORT_MEMORY; | |
| 816 | reg_RX_QUEUE_0_BUF_CONFIG(base) = OCN_PORT_MEMORY; | |
| 817 | ||
| 818 | /* initialize the RX DMA descriptors */ | |
| 819 | rx_descr = &rx_descr_array[0]; | |
| 820 | rx_descr_current = rx_descr; | |
| 821 | for (index = 0; index < NUM_RX_DESC; index++) { | |
| 822 | /* make sure the receive buffers are not in cache */ | |
| 823 | invalidate_dcache_range((unsigned long)NetRxPackets[index], | |
| 824 | (unsigned long)NetRxPackets[index] + | |
| 825 | RX_BUFFER_SIZE); | |
| 826 | rx_descr->start_addr0 = | |
| 827 | cpu_to_le32((vuint32) NetRxPackets[index]); | |
| 828 | rx_descr->start_addr1 = 0; | |
| 829 | rx_descr->next_descr_addr0 = | |
| 830 | cpu_to_le32((vuint32) (rx_descr + 1)); | |
| 831 | rx_descr->next_descr_addr1 = 0; | |
| 832 | rx_descr->vlan_byte_count = 0; | |
| 833 | rx_descr->config_status = cpu_to_le32((RX_BUFFER_SIZE << 16) | | |
| 834 | DMA_DESCR_RX_OWNER); | |
| 835 | rx_descr++; | |
| 836 | } | |
| 837 | rx_descr--; | |
| 838 | rx_descr->next_descr_addr0 = 0; | |
| 839 | rx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST); | |
| 840 | /* Push the descriptors to RAM so the ethernet DMA can see them */ | |
| 841 | invalidate_dcache_range((unsigned long)rx_descr_array, | |
| 842 | (unsigned long)rx_descr_array + | |
| 843 | sizeof(rx_descr_array)); | |
| 844 | ||
| 845 | /* enable RX queue */ | |
| 846 | reg_RX_CONTROL(base) = TX_CONTROL_GO | 0x01; | |
| 847 | reg_RX_QUEUE_0_PTR_LOW(base) = (u32) rx_descr_current; | |
| 848 | /* enable receive DMA */ | |
| 849 | reg_RX_QUEUE_0_PTR_HIGH(base) = RX_QUEUE_0_PTR_HIGH_VALID; | |
| 850 | ||
| 851 | reg_TX_QUEUE_0_CONFIG(base) = OCN_PORT_MEMORY; | |
| 852 | reg_TX_QUEUE_0_BUF_CONFIG(base) = OCN_PORT_MEMORY; | |
| 853 | ||
| 854 | /* initialize the TX DMA descriptor */ | |
| 855 | tx_descr = &tx_descriptor; | |
| 856 | ||
| 857 | tx_descr->start_addr0 = 0; | |
| 858 | tx_descr->start_addr1 = 0; | |
| 859 | tx_descr->next_descr_addr0 = 0; | |
| 860 | tx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST); | |
| 861 | tx_descr->vlan_byte_count = 0; | |
| 862 | tx_descr->config_status = cpu_to_le32(DMA_DESCR_TX_OK | | |
| 863 | DMA_DESCR_TX_SOF | | |
| 864 | DMA_DESCR_TX_EOF); | |
| 865 | /* enable TX queue */ | |
| 866 | reg_TX_CONTROL(base) = TX_CONTROL_GO | 0x01; | |
| 867 | ||
| 422b1a01 | 868 | return 0; |
| d1927cee | 869 | } |
| 870 | ||
| 871 | /* | |
| 872 | * send a packet | |
| 873 | */ | |
| e5c83f33 | 874 | static int tsi108_eth_send(struct eth_device *dev, void *packet, int length) |
| d1927cee | 875 | { |
| 876 | unsigned long base; | |
| 877 | int timeout; | |
| 878 | struct dma_descriptor *tx_descr; | |
| 879 | unsigned long status; | |
| 880 | ||
| 881 | base = dev->iobase; | |
| 882 | tx_descr = &tx_descriptor; | |
| 883 | ||
| 884 | /* Wait until the last packet has been transmitted. */ | |
| 885 | timeout = 0; | |
| 886 | do { | |
| 887 | /* make sure we see the changes made by the DMA engine */ | |
| 888 | invalidate_dcache_range((unsigned long)tx_descr, | |
| 889 | (unsigned long)tx_descr + | |
| 890 | sizeof(struct dma_descriptor)); | |
| 891 | ||
| ee311214 | 892 | if (timeout != 0) |
| 893 | udelay (15); | |
| d1927cee | 894 | if (++timeout > 10000) { |
| 895 | tx_diag_regs(base); | |
| 896 | debug_lev(1, | |
| 897 | "ERROR: timeout waiting for last transmit packet to be sent\n"); | |
| 898 | return 0; | |
| 899 | } | |
| 900 | } while (tx_descr->config_status & cpu_to_le32(DMA_DESCR_TX_OWNER)); | |
| 901 | ||
| 902 | status = le32_to_cpu(tx_descr->config_status); | |
| 903 | if ((status & DMA_DESCR_TX_OK) == 0) { | |
| 904 | #ifdef TX_PRINT_ERRORS | |
| bde63587 | 905 | printf ("TX packet error: 0x%08lx\n %s%s%s%s\n", status, |
| d1927cee | 906 | status & DMA_DESCR_TX_OK ? "tx error, " : "", |
| 907 | status & DMA_DESCR_TX_RETRY_LIMIT ? | |
| 908 | "retry limit reached, " : "", | |
| 909 | status & DMA_DESCR_TX_UNDERRUN ? "underrun, " : "", | |
| 910 | status & DMA_DESCR_TX_LATE_COLLISION ? "late collision, " | |
| 911 | : ""); | |
| 912 | #endif | |
| 913 | } | |
| 914 | ||
| ee311214 | 915 | debug_lev (9, "sending packet %d\n", length); |
| d1927cee | 916 | tx_descr->start_addr0 = cpu_to_le32((vuint32) packet); |
| 917 | tx_descr->start_addr1 = 0; | |
| 918 | tx_descr->next_descr_addr0 = 0; | |
| 919 | tx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST); | |
| 920 | tx_descr->vlan_byte_count = cpu_to_le32(length); | |
| 921 | tx_descr->config_status = cpu_to_le32(DMA_DESCR_TX_OWNER | | |
| 922 | DMA_DESCR_TX_CRC | | |
| 923 | DMA_DESCR_TX_PAD | | |
| 924 | DMA_DESCR_TX_SOF | | |
| 925 | DMA_DESCR_TX_EOF); | |
| 926 | ||
| 927 | invalidate_dcache_range((unsigned long)tx_descr, | |
| 928 | (unsigned long)tx_descr + | |
| 929 | sizeof(struct dma_descriptor)); | |
| 930 | ||
| 931 | invalidate_dcache_range((unsigned long)packet, | |
| 932 | (unsigned long)packet + length); | |
| 933 | ||
| 934 | reg_TX_QUEUE_0_PTR_LOW(base) = (u32) tx_descr; | |
| 935 | reg_TX_QUEUE_0_PTR_HIGH(base) = TX_QUEUE_0_PTR_HIGH_VALID; | |
| 936 | ||
| 937 | return length; | |
| 938 | } | |
| 939 | ||
| 940 | /* | |
| 941 | * Check for received packets and send them up the protocal stack | |
| 942 | */ | |
| ee311214 | 943 | static int tsi108_eth_recv (struct eth_device *dev) |
| d1927cee | 944 | { |
| 945 | struct dma_descriptor *rx_descr; | |
| 946 | unsigned long base; | |
| 947 | int length = 0; | |
| 948 | unsigned long status; | |
| e5c83f33 | 949 | uchar *buffer; |
| d1927cee | 950 | |
| 951 | base = dev->iobase; | |
| 952 | ||
| 953 | /* make sure we see the changes made by the DMA engine */ | |
| ee311214 | 954 | invalidate_dcache_range ((unsigned long)rx_descr_array, |
| d1927cee | 955 | (unsigned long)rx_descr_array + |
| 956 | sizeof(rx_descr_array)); | |
| 957 | ||
| 958 | /* process all of the received packets */ | |
| 959 | rx_descr = rx_descr_current; | |
| 960 | while ((rx_descr->config_status & cpu_to_le32(DMA_DESCR_RX_OWNER)) == 0) { | |
| 961 | /* check for error */ | |
| 962 | status = le32_to_cpu(rx_descr->config_status); | |
| 963 | if (status & DMA_DESCR_RX_BAD_FRAME) { | |
| 964 | #ifdef RX_PRINT_ERRORS | |
| bde63587 | 965 | printf ("RX packet error: 0x%08lx\n %s%s%s%s%s%s\n", |
| d1927cee | 966 | status, |
| 967 | status & DMA_DESCR_RX_FRAME_IS_TYPE ? "too big, " | |
| 968 | : "", | |
| 969 | status & DMA_DESCR_RX_SHORT_FRAME ? "too short, " | |
| 970 | : "", | |
| 971 | status & DMA_DESCR_RX_BAD_FRAME ? "bad frame, " : | |
| 972 | "", | |
| 973 | status & DMA_DESCR_RX_OVERRUN ? "overrun, " : "", | |
| 974 | status & DMA_DESCR_RX_MAX_FRAME_LEN ? | |
| 975 | "max length, " : "", | |
| 976 | status & DMA_DESCR_RX_CRC_ERROR ? "CRC error, " : | |
| 977 | ""); | |
| 978 | #endif | |
| 979 | } else { | |
| 980 | length = | |
| 981 | le32_to_cpu(rx_descr->vlan_byte_count) & 0xFFFF; | |
| 982 | ||
| 983 | /*** process packet ***/ | |
| e5c83f33 JH |
984 | buffer = (uchar *)(le32_to_cpu(rx_descr->start_addr0)); |
| 985 | NetReceive(buffer, length); | |
| d1927cee | 986 | |
| ee311214 | 987 | invalidate_dcache_range ((unsigned long)buffer, |
| d1927cee | 988 | (unsigned long)buffer + |
| 989 | RX_BUFFER_SIZE); | |
| 990 | } | |
| 991 | /* Give this buffer back to the DMA engine */ | |
| 992 | rx_descr->vlan_byte_count = 0; | |
| ee311214 | 993 | rx_descr->config_status = cpu_to_le32 ((RX_BUFFER_SIZE << 16) | |
| d1927cee | 994 | DMA_DESCR_RX_OWNER); |
| 995 | /* move descriptor pointer forward */ | |
| 996 | rx_descr = | |
| 997 | (struct dma_descriptor | |
| ee311214 | 998 | *)(le32_to_cpu (rx_descr->next_descr_addr0)); |
| 999 | if (rx_descr == 0) | |
| d1927cee | 1000 | rx_descr = &rx_descr_array[0]; |
| d1927cee | 1001 | } |
| 1002 | /* remember where we are for next time */ | |
| 1003 | rx_descr_current = rx_descr; | |
| 1004 | ||
| 1005 | /* If the DMA engine has reached the end of the queue | |
| 1006 | * start over at the begining */ | |
| 1007 | if (reg_RX_EXTENDED_STATUS(base) & RX_EXTENDED_STATUS_EOQ_0) { | |
| 1008 | ||
| 1009 | reg_RX_EXTENDED_STATUS(base) = RX_EXTENDED_STATUS_EOQ_0; | |
| 1010 | reg_RX_QUEUE_0_PTR_LOW(base) = (u32) & rx_descr_array[0]; | |
| 1011 | reg_RX_QUEUE_0_PTR_HIGH(base) = RX_QUEUE_0_PTR_HIGH_VALID; | |
| 1012 | } | |
| 1013 | ||
| 1014 | return length; | |
| 1015 | } | |
| 1016 | ||
| 1017 | /* | |
| 1018 | * disable an ethernet interface | |
| 1019 | */ | |
| ee311214 | 1020 | static void tsi108_eth_halt (struct eth_device *dev) |
| d1927cee | 1021 | { |
| 1022 | unsigned long base; | |
| 1023 | ||
| 1024 | base = dev->iobase; | |
| 1025 | ||
| 1026 | /* Put DMA/FIFO into reset state. */ | |
| 1027 | reg_TX_CONFIG(base) = TX_CONFIG_RST; | |
| 1028 | reg_RX_CONFIG(base) = RX_CONFIG_RST; | |
| 1029 | ||
| 1030 | /* Put MAC into reset state. */ | |
| 1031 | reg_MAC_CONFIG_1(base) = MAC_CONFIG_1_SOFT_RESET; | |
| 1032 | } |