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1da177e4
LT		 1/* tulip_core.c: A DEC 21x4x-family ethernet driver for Linux. */
2
3/*
6b92801b 4 Maintained by Valerie Henson <val_henson@linux.intel.com>
1da177e4
LT		 5 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker.
7
8 This software may be used and distributed according to the terms
9 of the GNU General Public License, incorporated herein by reference.
10
11 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
12 for more information on this driver, or visit the project
13 Web page at http://sourceforge.net/projects/tulip/
14
15*/
16
1da177e4
LT		 17
18#define DRV_NAME "tulip"
19#ifdef CONFIG_TULIP_NAPI
6bab99be 20#define DRV_VERSION "1.1.15-NAPI" /* Keep at least for test */
1da177e4 21#else
6bab99be 22#define DRV_VERSION "1.1.15"
1da177e4 23#endif
6bab99be 24#define DRV_RELDATE "Feb 27, 2007"
1da177e4
LT		 25
26
27#include <linux/module.h>
28#include <linux/pci.h>
29#include "tulip.h"
30#include <linux/init.h>
31#include <linux/etherdevice.h>
32#include <linux/delay.h>
33#include <linux/mii.h>
34#include <linux/ethtool.h>
35#include <linux/crc32.h>
36#include <asm/unaligned.h>
37#include <asm/uaccess.h>
38
49345103 39#ifdef CONFIG_SPARC
d297c31f 40#include <asm/prom.h>
1da177e4
LT		 41#endif
42
43static char version[] __devinitdata =
44 "Linux Tulip driver version " DRV_VERSION " (" DRV_RELDATE ")\n";
45
46
47/* A few user-configurable values. */
48
49/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
50static unsigned int max_interrupt_work = 25;
51
52#define MAX_UNITS 8
53/* Used to pass the full-duplex flag, etc. */
54static int full_duplex[MAX_UNITS];
55static int options[MAX_UNITS];
56static int mtu[MAX_UNITS]; /* Jumbo MTU for interfaces. */
57
58/* The possible media types that can be set in options[] are: */
59const char * const medianame[32] = {
60 "10baseT", "10base2", "AUI", "100baseTx",
61 "10baseT-FDX", "100baseTx-FDX", "100baseT4", "100baseFx",
62 "100baseFx-FDX", "MII 10baseT", "MII 10baseT-FDX", "MII",
63 "10baseT(forced)", "MII 100baseTx", "MII 100baseTx-FDX", "MII 100baseT4",
64 "MII 100baseFx-HDX", "MII 100baseFx-FDX", "Home-PNA 1Mbps", "Invalid-19",
65 "","","","", "","","","", "","","","Transceiver reset",
66};
67
68/* Set the copy breakpoint for the copy-only-tiny-buffer Rx structure. */
69#if defined(__alpha__) || defined(__arm__) || defined(__hppa__) \
49345103 70 || defined(CONFIG_SPARC) || defined(__ia64__) \
1da177e4
LT		 71 || defined(__sh__) || defined(__mips__)
72static int rx_copybreak = 1518;
73#else
74static int rx_copybreak = 100;
75#endif
76
77/*
78 Set the bus performance register.
79 Typical: Set 16 longword cache alignment, no burst limit.
80 Cache alignment bits 15:14 Burst length 13:8
81 0000 No alignment 0x00000000 unlimited 0800 8 longwords
82 4000 8 longwords 0100 1 longword 1000 16 longwords
83 8000 16 longwords 0200 2 longwords 2000 32 longwords
84 C000 32 longwords 0400 4 longwords
85 Warning: many older 486 systems are broken and require setting 0x00A04800
86 8 longword cache alignment, 8 longword burst.
87 ToDo: Non-Intel setting could be better.
88*/
89
90#if defined(__alpha__) || defined(__ia64__)
91static int csr0 = 0x01A00000 | 0xE000;
92#elif defined(__i386__) || defined(__powerpc__) || defined(__x86_64__)
93static int csr0 = 0x01A00000 | 0x8000;
49345103 94#elif defined(CONFIG_SPARC) || defined(__hppa__)
1da177e4
LT		 95/* The UltraSparc PCI controllers will disconnect at every 64-byte
96 * crossing anyways so it makes no sense to tell Tulip to burst
97 * any more than that.
98 */
99static int csr0 = 0x01A00000 | 0x9000;
100#elif defined(__arm__) || defined(__sh__)
101static int csr0 = 0x01A00000 | 0x4800;
102#elif defined(__mips__)
103static int csr0 = 0x00200000 | 0x4000;
104#else
105#warning Processor architecture undefined!
106static int csr0 = 0x00A00000 | 0x4800;
107#endif
108
109/* Operational parameters that usually are not changed. */
110/* Time in jiffies before concluding the transmitter is hung. */
111#define TX_TIMEOUT (4*HZ)
112
113
114MODULE_AUTHOR("The Linux Kernel Team");
115MODULE_DESCRIPTION("Digital 21*4* Tulip ethernet driver");
116MODULE_LICENSE("GPL");
117MODULE_VERSION(DRV_VERSION);
118module_param(tulip_debug, int, 0);
119module_param(max_interrupt_work, int, 0);
120module_param(rx_copybreak, int, 0);
121module_param(csr0, int, 0);
122module_param_array(options, int, NULL, 0);
123module_param_array(full_duplex, int, NULL, 0);
124
125#define PFX DRV_NAME ": "
126
127#ifdef TULIP_DEBUG
128int tulip_debug = TULIP_DEBUG;
129#else
130int tulip_debug = 1;
131#endif
132
0bb3cf72
FR		 133static void tulip_timer(unsigned long data)
134{
135 struct net_device *dev = (struct net_device *)data;
136 struct tulip_private *tp = netdev_priv(dev);
1da177e4 137
0bb3cf72
FR		 138 if (netif_running(dev))
139 schedule_work(&tp->media_work);
140}
1da177e4
LT		 141
142/*
143 * This table use during operation for capabilities and media timer.
144 *
145 * It is indexed via the values in 'enum chips'
146 */
147
148struct tulip_chip_table tulip_tbl[] = {
149 { }, /* placeholder for array, slot unused currently */
150 { }, /* placeholder for array, slot unused currently */
151
152 /* DC21140 */
153 { "Digital DS21140 Tulip", 128, 0x0001ebef,
0bb3cf72
FR		 154 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_PCI_MWI, tulip_timer,
155 tulip_media_task },
1da177e4
LT		 156
157 /* DC21142, DC21143 */
b892de0b 158 { "Digital DS21142/43 Tulip", 128, 0x0801fbff,
1da177e4 159 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI | HAS_NWAY
0bb3cf72 160 | HAS_INTR_MITIGATION | HAS_PCI_MWI, tulip_timer, t21142_media_task },
1da177e4
LT		 161
162 /* LC82C168 */
163 { "Lite-On 82c168 PNIC", 256, 0x0001fbef,
0bb3cf72 164 HAS_MII | HAS_PNICNWAY, pnic_timer, },
1da177e4
LT		 165
166 /* MX98713 */
167 { "Macronix 98713 PMAC", 128, 0x0001ebef,
0bb3cf72 168 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
1da177e4
LT		 169
170 /* MX98715 */
171 { "Macronix 98715 PMAC", 256, 0x0001ebef,
0bb3cf72 172 HAS_MEDIA_TABLE, mxic_timer, },
1da177e4
LT		 173
174 /* MX98725 */
175 { "Macronix 98725 PMAC", 256, 0x0001ebef,
0bb3cf72 176 HAS_MEDIA_TABLE, mxic_timer, },
1da177e4
LT		 177
178 /* AX88140 */
179 { "ASIX AX88140", 128, 0x0001fbff,
180 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | MC_HASH_ONLY
0bb3cf72 181 | IS_ASIX, tulip_timer, tulip_media_task },
1da177e4
LT		 182
183 /* PNIC2 */
184 { "Lite-On PNIC-II", 256, 0x0801fbff,
0bb3cf72 185 HAS_MII | HAS_NWAY | HAS_8023X | HAS_PCI_MWI, pnic2_timer, },
1da177e4
LT		 186
187 /* COMET */
188 { "ADMtek Comet", 256, 0x0001abef,
0bb3cf72 189 HAS_MII | MC_HASH_ONLY | COMET_MAC_ADDR, comet_timer, },
1da177e4
LT		 190
191 /* COMPEX9881 */
192 { "Compex 9881 PMAC", 128, 0x0001ebef,
0bb3cf72 193 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
1da177e4
LT		 194
195 /* I21145 */
196 { "Intel DS21145 Tulip", 128, 0x0801fbff,
197 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI
0bb3cf72 198 | HAS_NWAY | HAS_PCI_MWI, tulip_timer, tulip_media_task },
1da177e4
LT		 199
200 /* DM910X */
201 { "Davicom DM9102/DM9102A", 128, 0x0001ebef,
202 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_ACPI,
0bb3cf72 203 tulip_timer, tulip_media_task },
1da177e4
LT		 204
205 /* RS7112 */
206 { "Conexant LANfinity", 256, 0x0001ebef,
0bb3cf72 207 HAS_MII | HAS_ACPI, tulip_timer, tulip_media_task },
1da177e4 208
1da177e4
LT		 209};
210
211
212static struct pci_device_id tulip_pci_tbl[] = {
213 { 0x1011, 0x0009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21140 },
214 { 0x1011, 0x0019, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21143 },
215 { 0x11AD, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, LC82C168 },
216 { 0x10d9, 0x0512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98713 },
217 { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
218/* { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98725 },*/
219 { 0x125B, 0x1400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AX88140 },
220 { 0x11AD, 0xc115, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PNIC2 },
221 { 0x1317, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
222 { 0x1317, 0x0985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
223 { 0x1317, 0x1985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
224 { 0x1317, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
225 { 0x13D1, 0xAB02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
226 { 0x13D1, 0xAB03, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
227 { 0x13D1, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
228 { 0x104A, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
229 { 0x104A, 0x2774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
230 { 0x1259, 0xa120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
231 { 0x11F6, 0x9881, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMPEX9881 },
232 { 0x8086, 0x0039, PCI_ANY_ID, PCI_ANY_ID, 0, 0, I21145 },
233 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
234 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
235 { 0x1113, 0x1216, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
236 { 0x1113, 0x1217, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
237 { 0x1113, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
238 { 0x1186, 0x1541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
239 { 0x1186, 0x1561, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
240 { 0x1186, 0x1591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
241 { 0x14f1, 0x1803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CONEXANT },
242 { 0x1626, 0x8410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
243 { 0x1737, 0xAB09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
244 { 0x1737, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
245 { 0x17B3, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
1da177e4 246 { 0x10b7, 0x9300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* 3Com 3CSOHO100B-TX */
9b25978e 247 { 0x14ea, 0xab08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* Planex FNW-3602-TX */
1a449358 248 { 0x1414, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
1da177e4
LT		 249 { } /* terminate list */
250};
251MODULE_DEVICE_TABLE(pci, tulip_pci_tbl);
252
253
254/* A full-duplex map for media types. */
255const char tulip_media_cap[32] =
256{0,0,0,16, 3,19,16,24, 27,4,7,5, 0,20,23,20, 28,31,0,0, };
257
258static void tulip_tx_timeout(struct net_device *dev);
259static void tulip_init_ring(struct net_device *dev);
260static int tulip_start_xmit(struct sk_buff *skb, struct net_device *dev);
261static int tulip_open(struct net_device *dev);
262static int tulip_close(struct net_device *dev);
263static void tulip_up(struct net_device *dev);
264static void tulip_down(struct net_device *dev);
265static struct net_device_stats *tulip_get_stats(struct net_device *dev);
266static int private_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
267static void set_rx_mode(struct net_device *dev);
268#ifdef CONFIG_NET_POLL_CONTROLLER
269static void poll_tulip(struct net_device *dev);
270#endif
271
272static void tulip_set_power_state (struct tulip_private *tp,
273 int sleep, int snooze)
274{
275 if (tp->flags & HAS_ACPI) {
276 u32 tmp, newtmp;
277 pci_read_config_dword (tp->pdev, CFDD, &tmp);
278 newtmp = tmp & ~(CFDD_Sleep | CFDD_Snooze);
279 if (sleep)
280 newtmp |= CFDD_Sleep;
281 else if (snooze)
282 newtmp |= CFDD_Snooze;
283 if (tmp != newtmp)
284 pci_write_config_dword (tp->pdev, CFDD, newtmp);
285 }
286
287}
288
289
290static void tulip_up(struct net_device *dev)
291{
292 struct tulip_private *tp = netdev_priv(dev);
293 void __iomem *ioaddr = tp->base_addr;
294 int next_tick = 3*HZ;
b4482a4b 295 u32 reg;
1da177e4
LT		 296 int i;
297
bea3348e
SH		 298#ifdef CONFIG_TULIP_NAPI
299 napi_enable(&tp->napi);
300#endif
301
1da177e4
LT		 302 /* Wake the chip from sleep/snooze mode. */
303 tulip_set_power_state (tp, 0, 0);
304
305 /* On some chip revs we must set the MII/SYM port before the reset!? */
306 if (tp->mii_cnt || (tp->mtable && tp->mtable->has_mii))
307 iowrite32(0x00040000, ioaddr + CSR6);
308
309 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
310 iowrite32(0x00000001, ioaddr + CSR0);
b4482a4b 311 pci_read_config_dword(tp->pdev, PCI_COMMAND, &reg); /* flush write */
1da177e4
LT		 312 udelay(100);
313
314 /* Deassert reset.
315 Wait the specified 50 PCI cycles after a reset by initializing
316 Tx and Rx queues and the address filter list. */
317 iowrite32(tp->csr0, ioaddr + CSR0);
b4482a4b 318 pci_read_config_dword(tp->pdev, PCI_COMMAND, &reg); /* flush write */
1da177e4
LT		 319 udelay(100);
320
321 if (tulip_debug > 1)
322 printk(KERN_DEBUG "%s: tulip_up(), irq==%d.\n", dev->name, dev->irq);
323
324 iowrite32(tp->rx_ring_dma, ioaddr + CSR3);
325 iowrite32(tp->tx_ring_dma, ioaddr + CSR4);
326 tp->cur_rx = tp->cur_tx = 0;
327 tp->dirty_rx = tp->dirty_tx = 0;
328
329 if (tp->flags & MC_HASH_ONLY) {
c559a5bc
AV		 330 u32 addr_low = le32_to_cpu(get_unaligned((__le32 *)dev->dev_addr));
331 u32 addr_high = le16_to_cpu(get_unaligned((__le16 *)(dev->dev_addr+4)));
1da177e4
LT		 332 if (tp->chip_id == AX88140) {
333 iowrite32(0, ioaddr + CSR13);
334 iowrite32(addr_low, ioaddr + CSR14);
335 iowrite32(1, ioaddr + CSR13);
336 iowrite32(addr_high, ioaddr + CSR14);
337 } else if (tp->flags & COMET_MAC_ADDR) {
338 iowrite32(addr_low, ioaddr + 0xA4);
339 iowrite32(addr_high, ioaddr + 0xA8);
340 iowrite32(0, ioaddr + 0xAC);
341 iowrite32(0, ioaddr + 0xB0);
342 }
343 } else {
344 /* This is set_rx_mode(), but without starting the transmitter. */
345 u16 *eaddrs = (u16 *)dev->dev_addr;
346 u16 *setup_frm = &tp->setup_frame[15*6];
347 dma_addr_t mapping;
348
349 /* 21140 bug: you must add the broadcast address. */
350 memset(tp->setup_frame, 0xff, sizeof(tp->setup_frame));
351 /* Fill the final entry of the table with our physical address. */
352 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
353 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
354 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
355
356 mapping = pci_map_single(tp->pdev, tp->setup_frame,
357 sizeof(tp->setup_frame),
358 PCI_DMA_TODEVICE);
359 tp->tx_buffers[tp->cur_tx].skb = NULL;
360 tp->tx_buffers[tp->cur_tx].mapping = mapping;
361
362 /* Put the setup frame on the Tx list. */
363 tp->tx_ring[tp->cur_tx].length = cpu_to_le32(0x08000000 | 192);
364 tp->tx_ring[tp->cur_tx].buffer1 = cpu_to_le32(mapping);
365 tp->tx_ring[tp->cur_tx].status = cpu_to_le32(DescOwned);
366
367 tp->cur_tx++;
368 }
369
370 tp->saved_if_port = dev->if_port;
371 if (dev->if_port == 0)
372 dev->if_port = tp->default_port;
373
374 /* Allow selecting a default media. */
375 i = 0;
376 if (tp->mtable == NULL)
377 goto media_picked;
378 if (dev->if_port) {
379 int looking_for = tulip_media_cap[dev->if_port] & MediaIsMII ? 11 :
380 (dev->if_port == 12 ? 0 : dev->if_port);
381 for (i = 0; i < tp->mtable->leafcount; i++)
382 if (tp->mtable->mleaf[i].media == looking_for) {
383 printk(KERN_INFO "%s: Using user-specified media %s.\n",
384 dev->name, medianame[dev->if_port]);
385 goto media_picked;
386 }
387 }
388 if ((tp->mtable->defaultmedia & 0x0800) == 0) {
389 int looking_for = tp->mtable->defaultmedia & MEDIA_MASK;
390 for (i = 0; i < tp->mtable->leafcount; i++)
391 if (tp->mtable->mleaf[i].media == looking_for) {
392 printk(KERN_INFO "%s: Using EEPROM-set media %s.\n",
393 dev->name, medianame[looking_for]);
394 goto media_picked;
395 }
396 }
397 /* Start sensing first non-full-duplex media. */
398 for (i = tp->mtable->leafcount - 1;
399 (tulip_media_cap[tp->mtable->mleaf[i].media] & MediaAlwaysFD) && i > 0; i--)
400 ;
401media_picked:
402
403 tp->csr6 = 0;
404 tp->cur_index = i;
405 tp->nwayset = 0;
406
407 if (dev->if_port) {
408 if (tp->chip_id == DC21143 &&
409 (tulip_media_cap[dev->if_port] & MediaIsMII)) {
410 /* We must reset the media CSRs when we force-select MII mode. */
411 iowrite32(0x0000, ioaddr + CSR13);
412 iowrite32(0x0000, ioaddr + CSR14);
413 iowrite32(0x0008, ioaddr + CSR15);
414 }
415 tulip_select_media(dev, 1);
416 } else if (tp->chip_id == DC21142) {
417 if (tp->mii_cnt) {
418 tulip_select_media(dev, 1);
419 if (tulip_debug > 1)
420 printk(KERN_INFO "%s: Using MII transceiver %d, status "
421 "%4.4x.\n",
422 dev->name, tp->phys[0], tulip_mdio_read(dev, tp->phys[0], 1));
423 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
424 tp->csr6 = csr6_mask_hdcap;
425 dev->if_port = 11;
426 iowrite32(0x0000, ioaddr + CSR13);
427 iowrite32(0x0000, ioaddr + CSR14);
428 } else
429 t21142_start_nway(dev);
430 } else if (tp->chip_id == PNIC2) {
431 /* for initial startup advertise 10/100 Full and Half */
432 tp->sym_advertise = 0x01E0;
433 /* enable autonegotiate end interrupt */
434 iowrite32(ioread32(ioaddr+CSR5)| 0x00008010, ioaddr + CSR5);
435 iowrite32(ioread32(ioaddr+CSR7)| 0x00008010, ioaddr + CSR7);
436 pnic2_start_nway(dev);
437 } else if (tp->chip_id == LC82C168 && ! tp->medialock) {
438 if (tp->mii_cnt) {
439 dev->if_port = 11;
440 tp->csr6 = 0x814C0000 | (tp->full_duplex ? 0x0200 : 0);
441 iowrite32(0x0001, ioaddr + CSR15);
442 } else if (ioread32(ioaddr + CSR5) & TPLnkPass)
443 pnic_do_nway(dev);
444 else {
445 /* Start with 10mbps to do autonegotiation. */
446 iowrite32(0x32, ioaddr + CSR12);
447 tp->csr6 = 0x00420000;
448 iowrite32(0x0001B078, ioaddr + 0xB8);
449 iowrite32(0x0201B078, ioaddr + 0xB8);
450 next_tick = 1*HZ;
451 }
452 } else if ((tp->chip_id == MX98713 || tp->chip_id == COMPEX9881)
453 && ! tp->medialock) {
454 dev->if_port = 0;
455 tp->csr6 = 0x01880000 | (tp->full_duplex ? 0x0200 : 0);
456 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
457 } else if (tp->chip_id == MX98715 || tp->chip_id == MX98725) {
458 /* Provided by BOLO, Macronix - 12/10/1998. */
459 dev->if_port = 0;
460 tp->csr6 = 0x01a80200;
461 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
462 iowrite32(0x11000 | ioread16(ioaddr + 0xa0), ioaddr + 0xa0);
463 } else if (tp->chip_id == COMET || tp->chip_id == CONEXANT) {
464 /* Enable automatic Tx underrun recovery. */
465 iowrite32(ioread32(ioaddr + 0x88) | 1, ioaddr + 0x88);
466 dev->if_port = tp->mii_cnt ? 11 : 0;
467 tp->csr6 = 0x00040000;
468 } else if (tp->chip_id == AX88140) {
469 tp->csr6 = tp->mii_cnt ? 0x00040100 : 0x00000100;
470 } else
471 tulip_select_media(dev, 1);
472
473 /* Start the chip's Tx to process setup frame. */
474 tulip_stop_rxtx(tp);
475 barrier();
476 udelay(5);
477 iowrite32(tp->csr6 | TxOn, ioaddr + CSR6);
478
479 /* Enable interrupts by setting the interrupt mask. */
480 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5);
481 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
482 tulip_start_rxtx(tp);
483 iowrite32(0, ioaddr + CSR2); /* Rx poll demand */
484
485 if (tulip_debug > 2) {
486 printk(KERN_DEBUG "%s: Done tulip_up(), CSR0 %8.8x, CSR5 %8.8x CSR6 %8.8x.\n",
487 dev->name, ioread32(ioaddr + CSR0), ioread32(ioaddr + CSR5),
488 ioread32(ioaddr + CSR6));
489 }
490
491 /* Set the timer to switch to check for link beat and perhaps switch
492 to an alternate media type. */
493 tp->timer.expires = RUN_AT(next_tick);
494 add_timer(&tp->timer);
495#ifdef CONFIG_TULIP_NAPI
496 init_timer(&tp->oom_timer);
497 tp->oom_timer.data = (unsigned long)dev;
498 tp->oom_timer.function = oom_timer;
499#endif
500}
501
502static int
503tulip_open(struct net_device *dev)
504{
505 int retval;
506
1fb9df5d 507 if ((retval = request_irq(dev->irq, &tulip_interrupt, IRQF_SHARED, dev->name, dev)))
1da177e4
LT		 508 return retval;
509
510 tulip_init_ring (dev);
511
512 tulip_up (dev);
513
514 netif_start_queue (dev);
515
516 return 0;
517}
518
519
520static void tulip_tx_timeout(struct net_device *dev)
521{
522 struct tulip_private *tp = netdev_priv(dev);
523 void __iomem *ioaddr = tp->base_addr;
524 unsigned long flags;
525
526 spin_lock_irqsave (&tp->lock, flags);
527
528 if (tulip_media_cap[dev->if_port] & MediaIsMII) {
529 /* Do nothing -- the media monitor should handle this. */
530 if (tulip_debug > 1)
531 printk(KERN_WARNING "%s: Transmit timeout using MII device.\n",
532 dev->name);
533 } else if (tp->chip_id == DC21140 || tp->chip_id == DC21142
534 || tp->chip_id == MX98713 || tp->chip_id == COMPEX9881
ea8f400c 535 || tp->chip_id == DM910X) {
1da177e4
LT		 536 printk(KERN_WARNING "%s: 21140 transmit timed out, status %8.8x, "
537 "SIA %8.8x %8.8x %8.8x %8.8x, resetting...\n",
538 dev->name, ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12),
539 ioread32(ioaddr + CSR13), ioread32(ioaddr + CSR14), ioread32(ioaddr + CSR15));
0bb3cf72
FR		 540 tp->timeout_recovery = 1;
541 schedule_work(&tp->media_work);
542 goto out_unlock;
1da177e4
LT		 543 } else if (tp->chip_id == PNIC2) {
544 printk(KERN_WARNING "%s: PNIC2 transmit timed out, status %8.8x, "
545 "CSR6/7 %8.8x / %8.8x CSR12 %8.8x, resetting...\n",
546 dev->name, (int)ioread32(ioaddr + CSR5), (int)ioread32(ioaddr + CSR6),
547 (int)ioread32(ioaddr + CSR7), (int)ioread32(ioaddr + CSR12));
548 } else {
549 printk(KERN_WARNING "%s: Transmit timed out, status %8.8x, CSR12 "
550 "%8.8x, resetting...\n",
551 dev->name, ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12));
552 dev->if_port = 0;
553 }
554
555#if defined(way_too_many_messages)
556 if (tulip_debug > 3) {
557 int i;
558 for (i = 0; i < RX_RING_SIZE; i++) {
559 u8 *buf = (u8 *)(tp->rx_ring[i].buffer1);
560 int j;
561 printk(KERN_DEBUG "%2d: %8.8x %8.8x %8.8x %8.8x "
562 "%2.2x %2.2x %2.2x.\n",
563 i, (unsigned int)tp->rx_ring[i].status,
564 (unsigned int)tp->rx_ring[i].length,
565 (unsigned int)tp->rx_ring[i].buffer1,
566 (unsigned int)tp->rx_ring[i].buffer2,
567 buf[0], buf[1], buf[2]);
568 for (j = 0; buf[j] != 0xee && j < 1600; j++)
569 if (j < 100) printk(" %2.2x", buf[j]);
570 printk(" j=%d.\n", j);
571 }
572 printk(KERN_DEBUG " Rx ring %8.8x: ", (int)tp->rx_ring);
573 for (i = 0; i < RX_RING_SIZE; i++)
574 printk(" %8.8x", (unsigned int)tp->rx_ring[i].status);
575 printk("\n" KERN_DEBUG " Tx ring %8.8x: ", (int)tp->tx_ring);
576 for (i = 0; i < TX_RING_SIZE; i++)
577 printk(" %8.8x", (unsigned int)tp->tx_ring[i].status);
578 printk("\n");
579 }
580#endif
581
0bb3cf72 582 tulip_tx_timeout_complete(tp, ioaddr);
1da177e4 583
0bb3cf72 584out_unlock:
1da177e4
LT		 585 spin_unlock_irqrestore (&tp->lock, flags);
586 dev->trans_start = jiffies;
587 netif_wake_queue (dev);
588}
589
590
591/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
592static void tulip_init_ring(struct net_device *dev)
593{
594 struct tulip_private *tp = netdev_priv(dev);
595 int i;
596
597 tp->susp_rx = 0;
598 tp->ttimer = 0;
599 tp->nir = 0;
600
601 for (i = 0; i < RX_RING_SIZE; i++) {
602 tp->rx_ring[i].status = 0x00000000;
603 tp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ);
604 tp->rx_ring[i].buffer2 = cpu_to_le32(tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * (i + 1));
605 tp->rx_buffers[i].skb = NULL;
606 tp->rx_buffers[i].mapping = 0;
607 }
608 /* Mark the last entry as wrapping the ring. */
609 tp->rx_ring[i-1].length = cpu_to_le32(PKT_BUF_SZ | DESC_RING_WRAP);
610 tp->rx_ring[i-1].buffer2 = cpu_to_le32(tp->rx_ring_dma);
611
612 for (i = 0; i < RX_RING_SIZE; i++) {
613 dma_addr_t mapping;
614
615 /* Note the receive buffer must be longword aligned.
616 dev_alloc_skb() provides 16 byte alignment. But do *not*
617 use skb_reserve() to align the IP header! */
618 struct sk_buff *skb = dev_alloc_skb(PKT_BUF_SZ);
619 tp->rx_buffers[i].skb = skb;
620 if (skb == NULL)
621 break;
689be439 622 mapping = pci_map_single(tp->pdev, skb->data,
1da177e4
LT		 623 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
624 tp->rx_buffers[i].mapping = mapping;
625 skb->dev = dev; /* Mark as being used by this device. */
626 tp->rx_ring[i].status = cpu_to_le32(DescOwned); /* Owned by Tulip chip */
627 tp->rx_ring[i].buffer1 = cpu_to_le32(mapping);
628 }
629 tp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
630
631 /* The Tx buffer descriptor is filled in as needed, but we
632 do need to clear the ownership bit. */
633 for (i = 0; i < TX_RING_SIZE; i++) {
634 tp->tx_buffers[i].skb = NULL;
635 tp->tx_buffers[i].mapping = 0;
636 tp->tx_ring[i].status = 0x00000000;
637 tp->tx_ring[i].buffer2 = cpu_to_le32(tp->tx_ring_dma + sizeof(struct tulip_tx_desc) * (i + 1));
638 }
639 tp->tx_ring[i-1].buffer2 = cpu_to_le32(tp->tx_ring_dma);
640}
641
642static int
643tulip_start_xmit(struct sk_buff *skb, struct net_device *dev)
644{
645 struct tulip_private *tp = netdev_priv(dev);
646 int entry;
647 u32 flag;
648 dma_addr_t mapping;
649
650 spin_lock_irq(&tp->lock);
651
652 /* Calculate the next Tx descriptor entry. */
653 entry = tp->cur_tx % TX_RING_SIZE;
654
655 tp->tx_buffers[entry].skb = skb;
656 mapping = pci_map_single(tp->pdev, skb->data,
657 skb->len, PCI_DMA_TODEVICE);
658 tp->tx_buffers[entry].mapping = mapping;
659 tp->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
660
661 if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE/2) {/* Typical path */
662 flag = 0x60000000; /* No interrupt */
663 } else if (tp->cur_tx - tp->dirty_tx == TX_RING_SIZE/2) {
664 flag = 0xe0000000; /* Tx-done intr. */
665 } else if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE - 2) {
666 flag = 0x60000000; /* No Tx-done intr. */
667 } else { /* Leave room for set_rx_mode() to fill entries. */
668 flag = 0xe0000000; /* Tx-done intr. */
669 netif_stop_queue(dev);
670 }
671 if (entry == TX_RING_SIZE-1)
672 flag = 0xe0000000 | DESC_RING_WRAP;
673
674 tp->tx_ring[entry].length = cpu_to_le32(skb->len | flag);
675 /* if we were using Transmit Automatic Polling, we would need a
676 * wmb() here. */
677 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
678 wmb();
679
680 tp->cur_tx++;
681
682 /* Trigger an immediate transmit demand. */
683 iowrite32(0, tp->base_addr + CSR1);
684
685 spin_unlock_irq(&tp->lock);
686
687 dev->trans_start = jiffies;
688
689 return 0;
690}
691
692static void tulip_clean_tx_ring(struct tulip_private *tp)
693{
694 unsigned int dirty_tx;
695
696 for (dirty_tx = tp->dirty_tx ; tp->cur_tx - dirty_tx > 0;
697 dirty_tx++) {
698 int entry = dirty_tx % TX_RING_SIZE;
699 int status = le32_to_cpu(tp->tx_ring[entry].status);
700
701 if (status < 0) {
702 tp->stats.tx_errors++; /* It wasn't Txed */
703 tp->tx_ring[entry].status = 0;
704 }
705
706 /* Check for Tx filter setup frames. */
707 if (tp->tx_buffers[entry].skb == NULL) {
708 /* test because dummy frames not mapped */
709 if (tp->tx_buffers[entry].mapping)
710 pci_unmap_single(tp->pdev,
711 tp->tx_buffers[entry].mapping,
712 sizeof(tp->setup_frame),
713 PCI_DMA_TODEVICE);
714 continue;
715 }
716
717 pci_unmap_single(tp->pdev, tp->tx_buffers[entry].mapping,
718 tp->tx_buffers[entry].skb->len,
719 PCI_DMA_TODEVICE);
720
721 /* Free the original skb. */
722 dev_kfree_skb_irq(tp->tx_buffers[entry].skb);
723 tp->tx_buffers[entry].skb = NULL;
724 tp->tx_buffers[entry].mapping = 0;
725 }
726}
727
728static void tulip_down (struct net_device *dev)
729{
730 struct tulip_private *tp = netdev_priv(dev);
731 void __iomem *ioaddr = tp->base_addr;
732 unsigned long flags;
733
0bb3cf72
FR		 734 flush_scheduled_work();
735
bea3348e
SH		 736#ifdef CONFIG_TULIP_NAPI
737 napi_disable(&tp->napi);
738#endif
739
1da177e4
LT		 740 del_timer_sync (&tp->timer);
741#ifdef CONFIG_TULIP_NAPI
742 del_timer_sync (&tp->oom_timer);
743#endif
744 spin_lock_irqsave (&tp->lock, flags);
745
746 /* Disable interrupts by clearing the interrupt mask. */
747 iowrite32 (0x00000000, ioaddr + CSR7);
748
749 /* Stop the Tx and Rx processes. */
750 tulip_stop_rxtx(tp);
751
752 /* prepare receive buffers */
753 tulip_refill_rx(dev);
754
755 /* release any unconsumed transmit buffers */
756 tulip_clean_tx_ring(tp);
757
758 if (ioread32 (ioaddr + CSR6) != 0xffffffff)
759 tp->stats.rx_missed_errors += ioread32 (ioaddr + CSR8) & 0xffff;
760
761 spin_unlock_irqrestore (&tp->lock, flags);
762
763 init_timer(&tp->timer);
764 tp->timer.data = (unsigned long)dev;
765 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
766
767 dev->if_port = tp->saved_if_port;
768
769 /* Leave the driver in snooze, not sleep, mode. */
770 tulip_set_power_state (tp, 0, 1);
771}
772
773
774static int tulip_close (struct net_device *dev)
775{
776 struct tulip_private *tp = netdev_priv(dev);
777 void __iomem *ioaddr = tp->base_addr;
778 int i;
779
780 netif_stop_queue (dev);
781
782 tulip_down (dev);
783
784 if (tulip_debug > 1)
785 printk (KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
786 dev->name, ioread32 (ioaddr + CSR5));
787
788 free_irq (dev->irq, dev);
789
790 /* Free all the skbuffs in the Rx queue. */
791 for (i = 0; i < RX_RING_SIZE; i++) {
792 struct sk_buff *skb = tp->rx_buffers[i].skb;
793 dma_addr_t mapping = tp->rx_buffers[i].mapping;
794
795 tp->rx_buffers[i].skb = NULL;
796 tp->rx_buffers[i].mapping = 0;
797
798 tp->rx_ring[i].status = 0; /* Not owned by Tulip chip. */
799 tp->rx_ring[i].length = 0;
800 tp->rx_ring[i].buffer1 = 0xBADF00D0; /* An invalid address. */
801 if (skb) {
802 pci_unmap_single(tp->pdev, mapping, PKT_BUF_SZ,
803 PCI_DMA_FROMDEVICE);
804 dev_kfree_skb (skb);
805 }
806 }
807 for (i = 0; i < TX_RING_SIZE; i++) {
808 struct sk_buff *skb = tp->tx_buffers[i].skb;
809
810 if (skb != NULL) {
811 pci_unmap_single(tp->pdev, tp->tx_buffers[i].mapping,
812 skb->len, PCI_DMA_TODEVICE);
813 dev_kfree_skb (skb);
814 }
815 tp->tx_buffers[i].skb = NULL;
816 tp->tx_buffers[i].mapping = 0;
817 }
818
819 return 0;
820}
821
822static struct net_device_stats *tulip_get_stats(struct net_device *dev)
823{
824 struct tulip_private *tp = netdev_priv(dev);
825 void __iomem *ioaddr = tp->base_addr;
826
827 if (netif_running(dev)) {
828 unsigned long flags;
829
830 spin_lock_irqsave (&tp->lock, flags);
831
832 tp->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
833
834 spin_unlock_irqrestore(&tp->lock, flags);
835 }
836
837 return &tp->stats;
838}
839
840
841static void tulip_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
842{
843 struct tulip_private *np = netdev_priv(dev);
844 strcpy(info->driver, DRV_NAME);
845 strcpy(info->version, DRV_VERSION);
846 strcpy(info->bus_info, pci_name(np->pdev));
847}
848
7282d491 849static const struct ethtool_ops ops = {
1da177e4
LT		 850 .get_drvinfo = tulip_get_drvinfo
851};
852
853/* Provide ioctl() calls to examine the MII xcvr state. */
854static int private_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
855{
856 struct tulip_private *tp = netdev_priv(dev);
857 void __iomem *ioaddr = tp->base_addr;
858 struct mii_ioctl_data *data = if_mii(rq);
859 const unsigned int phy_idx = 0;
860 int phy = tp->phys[phy_idx] & 0x1f;
861 unsigned int regnum = data->reg_num;
862
863 switch (cmd) {
864 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
865 if (tp->mii_cnt)
866 data->phy_id = phy;
867 else if (tp->flags & HAS_NWAY)
868 data->phy_id = 32;
869 else if (tp->chip_id == COMET)
870 data->phy_id = 1;
871 else
872 return -ENODEV;
873
874 case SIOCGMIIREG: /* Read MII PHY register. */
875 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
876 int csr12 = ioread32 (ioaddr + CSR12);
877 int csr14 = ioread32 (ioaddr + CSR14);
878 switch (regnum) {
879 case 0:
880 if (((csr14<<5) & 0x1000) ||
881 (dev->if_port == 5 && tp->nwayset))
882 data->val_out = 0x1000;
883 else
884 data->val_out = (tulip_media_cap[dev->if_port]&MediaIs100 ? 0x2000 : 0)
885 | (tulip_media_cap[dev->if_port]&MediaIsFD ? 0x0100 : 0);
886 break;
887 case 1:
888 data->val_out =
889 0x1848 +
890 ((csr12&0x7000) == 0x5000 ? 0x20 : 0) +
891 ((csr12&0x06) == 6 ? 0 : 4);
892 data->val_out |= 0x6048;
893 break;
894 case 4:
895 /* Advertised value, bogus 10baseTx-FD value from CSR6. */
896 data->val_out =
897 ((ioread32(ioaddr + CSR6) >> 3) & 0x0040) +
898 ((csr14 >> 1) & 0x20) + 1;
899 data->val_out |= ((csr14 >> 9) & 0x03C0);
900 break;
901 case 5: data->val_out = tp->lpar; break;
902 default: data->val_out = 0; break;
903 }
904 } else {
905 data->val_out = tulip_mdio_read (dev, data->phy_id & 0x1f, regnum);
906 }
907 return 0;
908
909 case SIOCSMIIREG: /* Write MII PHY register. */
910 if (!capable (CAP_NET_ADMIN))
911 return -EPERM;
912 if (regnum & ~0x1f)
913 return -EINVAL;
914 if (data->phy_id == phy) {
915 u16 value = data->val_in;
916 switch (regnum) {
917 case 0: /* Check for autonegotiation on or reset. */
918 tp->full_duplex_lock = (value & 0x9000) ? 0 : 1;
919 if (tp->full_duplex_lock)
920 tp->full_duplex = (value & 0x0100) ? 1 : 0;
921 break;
922 case 4:
923 tp->advertising[phy_idx] =
924 tp->mii_advertise = data->val_in;
925 break;
926 }
927 }
928 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
929 u16 value = data->val_in;
930 if (regnum == 0) {
931 if ((value & 0x1200) == 0x1200) {
932 if (tp->chip_id == PNIC2) {
933 pnic2_start_nway (dev);
934 } else {
935 t21142_start_nway (dev);
936 }
937 }
938 } else if (regnum == 4)
939 tp->sym_advertise = value;
940 } else {
941 tulip_mdio_write (dev, data->phy_id & 0x1f, regnum, data->val_in);
942 }
943 return 0;
944 default:
945 return -EOPNOTSUPP;
946 }
947
948 return -EOPNOTSUPP;
949}
950
951
952/* Set or clear the multicast filter for this adaptor.
953 Note that we only use exclusion around actually queueing the
954 new frame, not around filling tp->setup_frame. This is non-deterministic
955 when re-entered but still correct. */
956
957#undef set_bit_le
958#define set_bit_le(i,p) do { ((char *)(p))[(i)/8] |= (1<<((i)%8)); } while(0)
959
960static void build_setup_frame_hash(u16 *setup_frm, struct net_device *dev)
961{
962 struct tulip_private *tp = netdev_priv(dev);
963 u16 hash_table[32];
964 struct dev_mc_list *mclist;
965 int i;
966 u16 *eaddrs;
967
968 memset(hash_table, 0, sizeof(hash_table));
969 set_bit_le(255, hash_table); /* Broadcast entry */
970 /* This should work on big-endian machines as well. */
971 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
972 i++, mclist = mclist->next) {
973 int index = ether_crc_le(ETH_ALEN, mclist->dmi_addr) & 0x1ff;
974
975 set_bit_le(index, hash_table);
976
977 }
978 for (i = 0; i < 32; i++) {
979 *setup_frm++ = hash_table[i];
980 *setup_frm++ = hash_table[i];
981 }
982 setup_frm = &tp->setup_frame[13*6];
983
984 /* Fill the final entry with our physical address. */
985 eaddrs = (u16 *)dev->dev_addr;
986 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
987 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
988 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
989}
990
991static void build_setup_frame_perfect(u16 *setup_frm, struct net_device *dev)
992{
993 struct tulip_private *tp = netdev_priv(dev);
994 struct dev_mc_list *mclist;
995 int i;
996 u16 *eaddrs;
997
998 /* We have <= 14 addresses so we can use the wonderful
999 16 address perfect filtering of the Tulip. */
1000 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
1001 i++, mclist = mclist->next) {
1002 eaddrs = (u16 *)mclist->dmi_addr;
1003 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1004 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1005 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1006 }
1007 /* Fill the unused entries with the broadcast address. */
1008 memset(setup_frm, 0xff, (15-i)*12);
1009 setup_frm = &tp->setup_frame[15*6];
1010
1011 /* Fill the final entry with our physical address. */
1012 eaddrs = (u16 *)dev->dev_addr;
1013 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
1014 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
1015 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
1016}
1017
1018
1019static void set_rx_mode(struct net_device *dev)
1020{
1021 struct tulip_private *tp = netdev_priv(dev);
1022 void __iomem *ioaddr = tp->base_addr;
1023 int csr6;
1024
1025 csr6 = ioread32(ioaddr + CSR6) & ~0x00D5;
1026
1027 tp->csr6 &= ~0x00D5;
1028 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1029 tp->csr6 |= AcceptAllMulticast | AcceptAllPhys;
1030 csr6 |= AcceptAllMulticast | AcceptAllPhys;
1da177e4
LT		 1031 } else if ((dev->mc_count > 1000) || (dev->flags & IFF_ALLMULTI)) {
1032 /* Too many to filter well -- accept all multicasts. */
1033 tp->csr6 |= AcceptAllMulticast;
1034 csr6 |= AcceptAllMulticast;
1035 } else if (tp->flags & MC_HASH_ONLY) {
1036 /* Some work-alikes have only a 64-entry hash filter table. */
1037 /* Should verify correctness on big-endian/__powerpc__ */
1038 struct dev_mc_list *mclist;
1039 int i;
1040 if (dev->mc_count > 64) { /* Arbitrary non-effective limit. */
1041 tp->csr6 |= AcceptAllMulticast;
1042 csr6 |= AcceptAllMulticast;
1043 } else {
1044 u32 mc_filter[2] = {0, 0}; /* Multicast hash filter */
1045 int filterbit;
1046 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1047 i++, mclist = mclist->next) {
1048 if (tp->flags & COMET_MAC_ADDR)
1049 filterbit = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1050 else
1051 filterbit = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1052 filterbit &= 0x3f;
1053 mc_filter[filterbit >> 5] |= 1 << (filterbit & 31);
1054 if (tulip_debug > 2) {
0795af57
JP		 1055 DECLARE_MAC_BUF(mac);
1056 printk(KERN_INFO "%s: Added filter for %s"
1057 " %8.8x bit %d.\n",
1058 dev->name, print_mac(mac, mclist->dmi_addr),
1059 ether_crc(ETH_ALEN, mclist->dmi_addr), filterbit);
1da177e4
LT		 1060 }
1061 }
1062 if (mc_filter[0] == tp->mc_filter[0] &&
1063 mc_filter[1] == tp->mc_filter[1])
1064 ; /* No change. */
1065 else if (tp->flags & IS_ASIX) {
1066 iowrite32(2, ioaddr + CSR13);
1067 iowrite32(mc_filter[0], ioaddr + CSR14);
1068 iowrite32(3, ioaddr + CSR13);
1069 iowrite32(mc_filter[1], ioaddr + CSR14);
1070 } else if (tp->flags & COMET_MAC_ADDR) {
1071 iowrite32(mc_filter[0], ioaddr + 0xAC);
1072 iowrite32(mc_filter[1], ioaddr + 0xB0);
1073 }
1074 tp->mc_filter[0] = mc_filter[0];
1075 tp->mc_filter[1] = mc_filter[1];
1076 }
1077 } else {
1078 unsigned long flags;
1079 u32 tx_flags = 0x08000000 | 192;
1080
1081 /* Note that only the low-address shortword of setup_frame is valid!
1082 The values are doubled for big-endian architectures. */
1083 if (dev->mc_count > 14) { /* Must use a multicast hash table. */
1084 build_setup_frame_hash(tp->setup_frame, dev);
1085 tx_flags = 0x08400000 | 192;
1086 } else {
1087 build_setup_frame_perfect(tp->setup_frame, dev);
1088 }
1089
1090 spin_lock_irqsave(&tp->lock, flags);
1091
1092 if (tp->cur_tx - tp->dirty_tx > TX_RING_SIZE - 2) {
1093 /* Same setup recently queued, we need not add it. */
1094 } else {
1095 unsigned int entry;
1096 int dummy = -1;
1097
1098 /* Now add this frame to the Tx list. */
1099
1100 entry = tp->cur_tx++ % TX_RING_SIZE;
1101
1102 if (entry != 0) {
ea8f400c
PC		 1103 /* Avoid a chip errata by prefixing a dummy entry. */
1104 tp->tx_buffers[entry].skb = NULL;
1105 tp->tx_buffers[entry].mapping = 0;
1106 tp->tx_ring[entry].length =
1107 (entry == TX_RING_SIZE-1) ? cpu_to_le32(DESC_RING_WRAP) : 0;
1108 tp->tx_ring[entry].buffer1 = 0;
1109 /* Must set DescOwned later to avoid race with chip */
1110 dummy = entry;
1111 entry = tp->cur_tx++ % TX_RING_SIZE;
1112
1da177e4
LT		 1113 }
1114
1115 tp->tx_buffers[entry].skb = NULL;
1116 tp->tx_buffers[entry].mapping =
1117 pci_map_single(tp->pdev, tp->setup_frame,
1118 sizeof(tp->setup_frame),
1119 PCI_DMA_TODEVICE);
1120 /* Put the setup frame on the Tx list. */
1121 if (entry == TX_RING_SIZE-1)
1122 tx_flags |= DESC_RING_WRAP; /* Wrap ring. */
1123 tp->tx_ring[entry].length = cpu_to_le32(tx_flags);
1124 tp->tx_ring[entry].buffer1 =
1125 cpu_to_le32(tp->tx_buffers[entry].mapping);
1126 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
1127 if (dummy >= 0)
1128 tp->tx_ring[dummy].status = cpu_to_le32(DescOwned);
1129 if (tp->cur_tx - tp->dirty_tx >= TX_RING_SIZE - 2)
1130 netif_stop_queue(dev);
1131
1132 /* Trigger an immediate transmit demand. */
1133 iowrite32(0, ioaddr + CSR1);
1134 }
1135
1136 spin_unlock_irqrestore(&tp->lock, flags);
1137 }
1138
1139 iowrite32(csr6, ioaddr + CSR6);
1140}
1141
1142#ifdef CONFIG_TULIP_MWI
1143static void __devinit tulip_mwi_config (struct pci_dev *pdev,
1144 struct net_device *dev)
1145{
1146 struct tulip_private *tp = netdev_priv(dev);
1147 u8 cache;
1148 u16 pci_command;
1149 u32 csr0;
1150
1151 if (tulip_debug > 3)
1152 printk(KERN_DEBUG "%s: tulip_mwi_config()\n", pci_name(pdev));
1153
1154 tp->csr0 = csr0 = 0;
1155
1156 /* if we have any cache line size at all, we can do MRM */
1157 csr0 |= MRM;
1158
1159 /* ...and barring hardware bugs, MWI */
1160 if (!(tp->chip_id == DC21143 && tp->revision == 65))
1161 csr0 |= MWI;
1162
1163 /* set or disable MWI in the standard PCI command bit.
1164 * Check for the case where mwi is desired but not available
1165 */
694625c0 1166 if (csr0 & MWI) pci_try_set_mwi(pdev);
1da177e4
LT		 1167 else pci_clear_mwi(pdev);
1168
1169 /* read result from hardware (in case bit refused to enable) */
1170 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1171 if ((csr0 & MWI) && (!(pci_command & PCI_COMMAND_INVALIDATE)))
1172 csr0 &= ~MWI;
1173
1174 /* if cache line size hardwired to zero, no MWI */
1175 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache);
1176 if ((csr0 & MWI) && (cache == 0)) {
1177 csr0 &= ~MWI;
1178 pci_clear_mwi(pdev);
1179 }
1180
1181 /* assign per-cacheline-size cache alignment and
1182 * burst length values
1183 */
1184 switch (cache) {
1185 case 8:
1186 csr0 |= MRL | (1 << CALShift) | (16 << BurstLenShift);
1187 break;
1188 case 16:
1189 csr0 |= MRL | (2 << CALShift) | (16 << BurstLenShift);
1190 break;
1191 case 32:
1192 csr0 |= MRL | (3 << CALShift) | (32 << BurstLenShift);
1193 break;
1194 default:
1195 cache = 0;
1196 break;
1197 }
1198
1199 /* if we have a good cache line size, we by now have a good
1200 * csr0, so save it and exit
1201 */
1202 if (cache)
1203 goto out;
1204
1205 /* we don't have a good csr0 or cache line size, disable MWI */
1206 if (csr0 & MWI) {
1207 pci_clear_mwi(pdev);
1208 csr0 &= ~MWI;
1209 }
1210
1211 /* sane defaults for burst length and cache alignment
1212 * originally from de4x5 driver
1213 */
1214 csr0 |= (8 << BurstLenShift) | (1 << CALShift);
1215
1216out:
1217 tp->csr0 = csr0;
1218 if (tulip_debug > 2)
1219 printk(KERN_DEBUG "%s: MWI config cacheline=%d, csr0=%08x\n",
1220 pci_name(pdev), cache, csr0);
1221}
1222#endif
1223
1224/*
1225 * Chips that have the MRM/reserved bit quirk and the burst quirk. That
1226 * is the DM910X and the on chip ULi devices
1227 */
f3b197ac 1228
1da177e4
LT		 1229static int tulip_uli_dm_quirk(struct pci_dev *pdev)
1230{
1231 if (pdev->vendor == 0x1282 && pdev->device == 0x9102)
1232 return 1;
1da177e4
LT		 1233 return 0;
1234}
1235
1236static int __devinit tulip_init_one (struct pci_dev *pdev,
1237 const struct pci_device_id *ent)
1238{
1239 struct tulip_private *tp;
1240 /* See note below on the multiport cards. */
1241 static unsigned char last_phys_addr[6] = {0x00, 'L', 'i', 'n', 'u', 'x'};
1242 static struct pci_device_id early_486_chipsets[] = {
1243 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82424) },
1244 { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496) },
1245 { },
1246 };
1247 static int last_irq;
1248 static int multiport_cnt; /* For four-port boards w/one EEPROM */
1da177e4
LT		 1249 int i, irq;
1250 unsigned short sum;
1251 unsigned char *ee_data;
1252 struct net_device *dev;
1253 void __iomem *ioaddr;
1254 static int board_idx = -1;
1255 int chip_idx = ent->driver_data;
1256 const char *chip_name = tulip_tbl[chip_idx].chip_name;
1257 unsigned int eeprom_missing = 0;
1258 unsigned int force_csr0 = 0;
0795af57 1259 DECLARE_MAC_BUF(mac);
1da177e4
LT		 1260
1261#ifndef MODULE
1262 static int did_version; /* Already printed version info. */
1263 if (tulip_debug > 0 && did_version++ == 0)
1264 printk (KERN_INFO "%s", version);
1265#endif
1266
1267 board_idx++;
1268
1269 /*
1270 * Lan media wire a tulip chip to a wan interface. Needs a very
1271 * different driver (lmc driver)
1272 */
1273
1274 if (pdev->subsystem_vendor == PCI_VENDOR_ID_LMC) {
1275 printk (KERN_ERR PFX "skipping LMC card.\n");
1276 return -ENODEV;
1277 }
1278
1279 /*
1280 * Early DM9100's need software CRC and the DMFE driver
1281 */
1282
1283 if (pdev->vendor == 0x1282 && pdev->device == 0x9100)
1284 {
1da177e4 1285 /* Read Chip revision */
8ca7ee6b 1286 if (pdev->revision < 0x30)
1da177e4
LT		 1287 {
1288 printk(KERN_ERR PFX "skipping early DM9100 with Crc bug (use dmfe)\n");
1289 return -ENODEV;
1290 }
1291 }
1292
1293 /*
1294 * Looks for early PCI chipsets where people report hangs
1295 * without the workarounds being on.
1296 */
1297
1298 /* 1. Intel Saturn. Switch to 8 long words burst, 8 long word cache
f3b197ac 1299 aligned. Aries might need this too. The Saturn errata are not
1da177e4
LT		 1300 pretty reading but thankfully it's an old 486 chipset.
1301
1302 2. The dreaded SiS496 486 chipset. Same workaround as Intel
1303 Saturn.
1304 */
1305
1306 if (pci_dev_present(early_486_chipsets)) {
1307 csr0 = MRL | MRM | (8 << BurstLenShift) | (1 << CALShift);
1308 force_csr0 = 1;
1309 }
1310
1311 /* bugfix: the ASIX must have a burst limit or horrible things happen. */
1312 if (chip_idx == AX88140) {
1313 if ((csr0 & 0x3f00) == 0)
1314 csr0 |= 0x2000;
1315 }
1316
1317 /* PNIC doesn't have MWI/MRL/MRM... */
1318 if (chip_idx == LC82C168)
1319 csr0 &= ~0xfff10000; /* zero reserved bits 31:20, 16 */
1320
1321 /* DM9102A has troubles with MRM & clear reserved bits 24:22, 20, 16, 7:1 */
1322 if (tulip_uli_dm_quirk(pdev)) {
1323 csr0 &= ~0x01f100ff;
49345103 1324#if defined(CONFIG_SPARC)
1da177e4
LT		 1325 csr0 = (csr0 & ~0xff00) | 0xe000;
1326#endif
1327 }
1328 /*
1329 * And back to business
1330 */
1331
1332 i = pci_enable_device(pdev);
1333 if (i) {
1334 printk (KERN_ERR PFX
1335 "Cannot enable tulip board #%d, aborting\n",
1336 board_idx);
1337 return i;
1338 }
1339
1340 irq = pdev->irq;
1341
1342 /* alloc_etherdev ensures aligned and zeroed private structures */
1343 dev = alloc_etherdev (sizeof (*tp));
1344 if (!dev) {
1345 printk (KERN_ERR PFX "ether device alloc failed, aborting\n");
1346 return -ENOMEM;
1347 }
1348
1da177e4
LT		 1349 SET_NETDEV_DEV(dev, &pdev->dev);
1350 if (pci_resource_len (pdev, 0) < tulip_tbl[chip_idx].io_size) {
7c7459d1 1351 printk (KERN_ERR PFX "%s: I/O region (0x%llx@0x%llx) too small, "
1da177e4 1352 "aborting\n", pci_name(pdev),
7c7459d1
GKH		 1353 (unsigned long long)pci_resource_len (pdev, 0),
1354 (unsigned long long)pci_resource_start (pdev, 0));
1da177e4
LT		 1355 goto err_out_free_netdev;
1356 }
1357
1358 /* grab all resources from both PIO and MMIO regions, as we
1359 * don't want anyone else messing around with our hardware */
1360 if (pci_request_regions (pdev, "tulip"))
1361 goto err_out_free_netdev;
1362
7f2b1248
GG		 1363 ioaddr = pci_iomap(pdev, TULIP_BAR, tulip_tbl[chip_idx].io_size);
1364
1da177e4
LT		 1365 if (!ioaddr)
1366 goto err_out_free_res;
1367
1da177e4
LT		 1368 /*
1369 * initialize private data structure 'tp'
1370 * it is zeroed and aligned in alloc_etherdev
1371 */
1372 tp = netdev_priv(dev);
c4028958 1373 tp->dev = dev;
1da177e4
LT		 1374
1375 tp->rx_ring = pci_alloc_consistent(pdev,
1376 sizeof(struct tulip_rx_desc) * RX_RING_SIZE +
1377 sizeof(struct tulip_tx_desc) * TX_RING_SIZE,
1378 &tp->rx_ring_dma);
1379 if (!tp->rx_ring)
1380 goto err_out_mtable;
1381 tp->tx_ring = (struct tulip_tx_desc *)(tp->rx_ring + RX_RING_SIZE);
1382 tp->tx_ring_dma = tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * RX_RING_SIZE;
1383
1384 tp->chip_id = chip_idx;
1385 tp->flags = tulip_tbl[chip_idx].flags;
1386 tp->pdev = pdev;
1387 tp->base_addr = ioaddr;
44c10138 1388 tp->revision = pdev->revision;
1da177e4
LT		 1389 tp->csr0 = csr0;
1390 spin_lock_init(&tp->lock);
1391 spin_lock_init(&tp->mii_lock);
1392 init_timer(&tp->timer);
1393 tp->timer.data = (unsigned long)dev;
1394 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
1395
c4028958 1396 INIT_WORK(&tp->media_work, tulip_tbl[tp->chip_id].media_task);
0bb3cf72 1397
1da177e4
LT		 1398 dev->base_addr = (unsigned long)ioaddr;
1399
1400#ifdef CONFIG_TULIP_MWI
1401 if (!force_csr0 && (tp->flags & HAS_PCI_MWI))
1402 tulip_mwi_config (pdev, dev);
1403#else
1404 /* MWI is broken for DC21143 rev 65... */
44c10138 1405 if (chip_idx == DC21143 && pdev->revision == 65)
1da177e4
LT		 1406 tp->csr0 &= ~MWI;
1407#endif
1408
1409 /* Stop the chip's Tx and Rx processes. */
1410 tulip_stop_rxtx(tp);
1411
1412 pci_set_master(pdev);
1413
1414#ifdef CONFIG_GSC
1415 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP) {
1416 switch (pdev->subsystem_device) {
1417 default:
1418 break;
1419 case 0x1061:
1420 case 0x1062:
1421 case 0x1063:
1422 case 0x1098:
1423 case 0x1099:
1424 case 0x10EE:
1425 tp->flags |= HAS_SWAPPED_SEEPROM | NEEDS_FAKE_MEDIA_TABLE;
1426 chip_name = "GSC DS21140 Tulip";
1427 }
1428 }
1429#endif
1430
1431 /* Clear the missed-packet counter. */
1432 ioread32(ioaddr + CSR8);
1433
1434 /* The station address ROM is read byte serially. The register must
1435 be polled, waiting for the value to be read bit serially from the
1436 EEPROM.
1437 */
1438 ee_data = tp->eeprom;
1439 sum = 0;
1440 if (chip_idx == LC82C168) {
1441 for (i = 0; i < 3; i++) {
1442 int value, boguscnt = 100000;
1443 iowrite32(0x600 | i, ioaddr + 0x98);
1444 do
1445 value = ioread32(ioaddr + CSR9);
1446 while (value < 0 && --boguscnt > 0);
c559a5bc 1447 put_unaligned(cpu_to_le16(value), ((__le16*)dev->dev_addr) + i);
1da177e4
LT		 1448 sum += value & 0xffff;
1449 }
1450 } else if (chip_idx == COMET) {
1451 /* No need to read the EEPROM. */
c559a5bc
AV		 1452 put_unaligned(cpu_to_le32(ioread32(ioaddr + 0xA4)), (__le32 *)dev->dev_addr);
1453 put_unaligned(cpu_to_le16(ioread32(ioaddr + 0xA8)), (__le16 *)(dev->dev_addr + 4));
1da177e4
LT		 1454 for (i = 0; i < 6; i ++)
1455 sum += dev->dev_addr[i];
1456 } else {
1457 /* A serial EEPROM interface, we read now and sort it out later. */
1458 int sa_offset = 0;
1459 int ee_addr_size = tulip_read_eeprom(dev, 0xff, 8) & 0x40000 ? 8 : 6;
1460
1461 for (i = 0; i < sizeof(tp->eeprom); i+=2) {
1462 u16 data = tulip_read_eeprom(dev, i/2, ee_addr_size);
1463 ee_data[i] = data & 0xff;
1464 ee_data[i + 1] = data >> 8;
1465 }
1466
1467 /* DEC now has a specification (see Notes) but early board makers
1468 just put the address in the first EEPROM locations. */
1469 /* This does memcmp(ee_data, ee_data+16, 8) */
1470 for (i = 0; i < 8; i ++)
1471 if (ee_data[i] != ee_data[16+i])
1472 sa_offset = 20;
1473 if (chip_idx == CONEXANT) {
1474 /* Check that the tuple type and length is correct. */
1475 if (ee_data[0x198] == 0x04 && ee_data[0x199] == 6)
1476 sa_offset = 0x19A;
1477 } else if (ee_data[0] == 0xff && ee_data[1] == 0xff &&
1478 ee_data[2] == 0) {
1479 sa_offset = 2; /* Grrr, damn Matrox boards. */
1480 multiport_cnt = 4;
1481 }
1da177e4 1482#ifdef CONFIG_MIPS_COBALT
f3b197ac 1483 if ((pdev->bus->number == 0) &&
1da177e4
LT		 1484 ((PCI_SLOT(pdev->devfn) == 7) ||
1485 (PCI_SLOT(pdev->devfn) == 12))) {
1486 /* Cobalt MAC address in first EEPROM locations. */
1487 sa_offset = 0;
12755c16
RB		 1488 /* Ensure our media table fixup get's applied */
1489 memcpy(ee_data + 16, ee_data, 8);
1da177e4
LT		 1490 }
1491#endif
1492#ifdef CONFIG_GSC
1493 /* Check to see if we have a broken srom */
1494 if (ee_data[0] == 0x61 && ee_data[1] == 0x10) {
1495 /* pci_vendor_id and subsystem_id are swapped */
1496 ee_data[0] = ee_data[2];
1497 ee_data[1] = ee_data[3];
1498 ee_data[2] = 0x61;
1499 ee_data[3] = 0x10;
1500
1501 /* HSC-PCI boards need to be byte-swaped and shifted
1502 * up 1 word. This shift needs to happen at the end
1503 * of the MAC first because of the 2 byte overlap.
1504 */
1505 for (i = 4; i >= 0; i -= 2) {
1506 ee_data[17 + i + 3] = ee_data[17 + i];
1507 ee_data[16 + i + 5] = ee_data[16 + i];
1508 }
1509 }
1510#endif
1511
1512 for (i = 0; i < 6; i ++) {
1513 dev->dev_addr[i] = ee_data[i + sa_offset];
1514 sum += ee_data[i + sa_offset];
1515 }
1516 }
1517 /* Lite-On boards have the address byte-swapped. */
1518 if ((dev->dev_addr[0] == 0xA0 || dev->dev_addr[0] == 0xC0 || dev->dev_addr[0] == 0x02)
1519 && dev->dev_addr[1] == 0x00)
1520 for (i = 0; i < 6; i+=2) {
1521 char tmp = dev->dev_addr[i];
1522 dev->dev_addr[i] = dev->dev_addr[i+1];
1523 dev->dev_addr[i+1] = tmp;
1524 }
1525 /* On the Zynx 315 Etherarray and other multiport boards only the
1526 first Tulip has an EEPROM.
1527 On Sparc systems the mac address is held in the OBP property
1528 "local-mac-address".
1529 The addresses of the subsequent ports are derived from the first.
1530 Many PCI BIOSes also incorrectly report the IRQ line, so we correct
1531 that here as well. */
1532 if (sum == 0 || sum == 6*0xff) {
49345103 1533#if defined(CONFIG_SPARC)
d297c31f
DM		 1534 struct device_node *dp = pci_device_to_OF_node(pdev);
1535 const unsigned char *addr;
1536 int len;
1da177e4
LT		 1537#endif
1538 eeprom_missing = 1;
1539 for (i = 0; i < 5; i++)
1540 dev->dev_addr[i] = last_phys_addr[i];
1541 dev->dev_addr[i] = last_phys_addr[i] + 1;
49345103 1542#if defined(CONFIG_SPARC)
d297c31f
DM		 1543 addr = of_get_property(dp, "local-mac-address", &len);
1544 if (addr && len == 6)
1545 memcpy(dev->dev_addr, addr, 6);
1da177e4 1546#endif
b9c4c609 1547#if defined(__i386__) || defined(__x86_64__) /* Patch up x86 BIOS bug. */
1da177e4
LT		 1548 if (last_irq)
1549 irq = last_irq;
1550#endif
1551 }
1552
1553 for (i = 0; i < 6; i++)
1554 last_phys_addr[i] = dev->dev_addr[i];
1555 last_irq = irq;
1556 dev->irq = irq;
1557
1558 /* The lower four bits are the media type. */
1559 if (board_idx >= 0 && board_idx < MAX_UNITS) {
1560 if (options[board_idx] & MEDIA_MASK)
1561 tp->default_port = options[board_idx] & MEDIA_MASK;
1562 if ((options[board_idx] & FullDuplex) || full_duplex[board_idx] > 0)
1563 tp->full_duplex = 1;
1564 if (mtu[board_idx] > 0)
1565 dev->mtu = mtu[board_idx];
1566 }
1567 if (dev->mem_start & MEDIA_MASK)
1568 tp->default_port = dev->mem_start & MEDIA_MASK;
1569 if (tp->default_port) {
1570 printk(KERN_INFO "tulip%d: Transceiver selection forced to %s.\n",
1571 board_idx, medianame[tp->default_port & MEDIA_MASK]);
1572 tp->medialock = 1;
1573 if (tulip_media_cap[tp->default_port] & MediaAlwaysFD)
1574 tp->full_duplex = 1;
1575 }
1576 if (tp->full_duplex)
1577 tp->full_duplex_lock = 1;
1578
1579 if (tulip_media_cap[tp->default_port] & MediaIsMII) {
1580 u16 media2advert[] = { 0x20, 0x40, 0x03e0, 0x60, 0x80, 0x100, 0x200 };
1581 tp->mii_advertise = media2advert[tp->default_port - 9];
1582 tp->mii_advertise |= (tp->flags & HAS_8023X); /* Matching bits! */
1583 }
1584
1585 if (tp->flags & HAS_MEDIA_TABLE) {
1586 sprintf(dev->name, "tulip%d", board_idx); /* hack */
1587 tulip_parse_eeprom(dev);
1588 strcpy(dev->name, "eth%d"); /* un-hack */
1589 }
1590
1591 if ((tp->flags & ALWAYS_CHECK_MII) ||
1592 (tp->mtable && tp->mtable->has_mii) ||
1593 ( ! tp->mtable && (tp->flags & HAS_MII))) {
1594 if (tp->mtable && tp->mtable->has_mii) {
1595 for (i = 0; i < tp->mtable->leafcount; i++)
1596 if (tp->mtable->mleaf[i].media == 11) {
1597 tp->cur_index = i;
1598 tp->saved_if_port = dev->if_port;
1599 tulip_select_media(dev, 2);
1600 dev->if_port = tp->saved_if_port;
1601 break;
1602 }
1603 }
1604
1605 /* Find the connected MII xcvrs.
1606 Doing this in open() would allow detecting external xcvrs
1607 later, but takes much time. */
1608 tulip_find_mii (dev, board_idx);
1609 }
1610
1611 /* The Tulip-specific entries in the device structure. */
1612 dev->open = tulip_open;
1613 dev->hard_start_xmit = tulip_start_xmit;
1614 dev->tx_timeout = tulip_tx_timeout;
1615 dev->watchdog_timeo = TX_TIMEOUT;
1616#ifdef CONFIG_TULIP_NAPI
bea3348e 1617 netif_napi_add(dev, &tp->napi, tulip_poll, 16);
1da177e4
LT		 1618#endif
1619 dev->stop = tulip_close;
1620 dev->get_stats = tulip_get_stats;
1621 dev->do_ioctl = private_ioctl;
1622 dev->set_multicast_list = set_rx_mode;
1623#ifdef CONFIG_NET_POLL_CONTROLLER
1624 dev->poll_controller = &poll_tulip;
1625#endif
1626 SET_ETHTOOL_OPS(dev, &ops);
1627
1628 if (register_netdev(dev))
1629 goto err_out_free_ring;
1630
c69f4122
GG		 1631 printk(KERN_INFO "%s: %s rev %d at "
1632#ifdef CONFIG_TULIP_MMIO
1633 "MMIO"
1634#else
1635 "Port"
1636#endif
44c10138 1637 " %#llx,", dev->name, chip_name, pdev->revision,
c69f4122 1638 (unsigned long long) pci_resource_start(pdev, TULIP_BAR));
1da177e4
LT		 1639 pci_set_drvdata(pdev, dev);
1640
1641 if (eeprom_missing)
1642 printk(" EEPROM not present,");
0795af57 1643 printk(" %s", print_mac(mac, dev->dev_addr));
1da177e4
LT		 1644 printk(", IRQ %d.\n", irq);
1645
1646 if (tp->chip_id == PNIC2)
1647 tp->link_change = pnic2_lnk_change;
1648 else if (tp->flags & HAS_NWAY)
1649 tp->link_change = t21142_lnk_change;
1650 else if (tp->flags & HAS_PNICNWAY)
1651 tp->link_change = pnic_lnk_change;
1652
1653 /* Reset the xcvr interface and turn on heartbeat. */
1654 switch (chip_idx) {
1655 case DC21140:
1656 case DM910X:
1da177e4
LT		 1657 default:
1658 if (tp->mtable)
1659 iowrite32(tp->mtable->csr12dir | 0x100, ioaddr + CSR12);
1660 break;
1661 case DC21142:
1662 if (tp->mii_cnt || tulip_media_cap[dev->if_port] & MediaIsMII) {
1663 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
1664 iowrite32(0x0000, ioaddr + CSR13);
1665 iowrite32(0x0000, ioaddr + CSR14);
1666 iowrite32(csr6_mask_hdcap, ioaddr + CSR6);
1667 } else
1668 t21142_start_nway(dev);
1669 break;
1670 case PNIC2:
1671 /* just do a reset for sanity sake */
1672 iowrite32(0x0000, ioaddr + CSR13);
1673 iowrite32(0x0000, ioaddr + CSR14);
1674 break;
1675 case LC82C168:
1676 if ( ! tp->mii_cnt) {
1677 tp->nway = 1;
1678 tp->nwayset = 0;
1679 iowrite32(csr6_ttm | csr6_ca, ioaddr + CSR6);
1680 iowrite32(0x30, ioaddr + CSR12);
1681 iowrite32(0x0001F078, ioaddr + CSR6);
1682 iowrite32(0x0201F078, ioaddr + CSR6); /* Turn on autonegotiation. */
1683 }
1684 break;
1685 case MX98713:
1686 case COMPEX9881:
1687 iowrite32(0x00000000, ioaddr + CSR6);
1688 iowrite32(0x000711C0, ioaddr + CSR14); /* Turn on NWay. */
1689 iowrite32(0x00000001, ioaddr + CSR13);
1690 break;
1691 case MX98715:
1692 case MX98725:
1693 iowrite32(0x01a80000, ioaddr + CSR6);
1694 iowrite32(0xFFFFFFFF, ioaddr + CSR14);
1695 iowrite32(0x00001000, ioaddr + CSR12);
1696 break;
1697 case COMET:
1698 /* No initialization necessary. */
1699 break;
1700 }
1701
1702 /* put the chip in snooze mode until opened */
1703 tulip_set_power_state (tp, 0, 1);
1704
1705 return 0;
1706
1707err_out_free_ring:
1708 pci_free_consistent (pdev,
1709 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1710 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1711 tp->rx_ring, tp->rx_ring_dma);
1712
1713err_out_mtable:
b4558ea9 1714 kfree (tp->mtable);
1da177e4
LT		 1715 pci_iounmap(pdev, ioaddr);
1716
1717err_out_free_res:
1718 pci_release_regions (pdev);
1719
1720err_out_free_netdev:
1721 free_netdev (dev);
1722 return -ENODEV;
1723}
1724
1725
1726#ifdef CONFIG_PM
1727
1728static int tulip_suspend (struct pci_dev *pdev, pm_message_t state)
1729{
1730 struct net_device *dev = pci_get_drvdata(pdev);
1731
1fe2cb32
AB		 1732 if (!dev)
1733 return -EINVAL;
1734
1735 if (netif_running(dev))
1736 tulip_down(dev);
1737
1738 netif_device_detach(dev);
1739 free_irq(dev->irq, dev);
1740
1741 pci_save_state(pdev);
1742 pci_disable_device(pdev);
1743 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1744
1da177e4
LT		 1745 return 0;
1746}
1747
1748
1749static int tulip_resume(struct pci_dev *pdev)
1750{
1751 struct net_device *dev = pci_get_drvdata(pdev);
1fe2cb32 1752 int retval;
1da177e4 1753
1fe2cb32
AB		 1754 if (!dev)
1755 return -EINVAL;
1756
1757 pci_set_power_state(pdev, PCI_D0);
1758 pci_restore_state(pdev);
1759
9f486ae1
VH		 1760 if ((retval = pci_enable_device(pdev))) {
1761 printk (KERN_ERR "tulip: pci_enable_device failed in resume\n");
1762 return retval;
1763 }
1fe2cb32 1764
1fb9df5d 1765 if ((retval = request_irq(dev->irq, &tulip_interrupt, IRQF_SHARED, dev->name, dev))) {
1fe2cb32
AB		 1766 printk (KERN_ERR "tulip: request_irq failed in resume\n");
1767 return retval;
1da177e4 1768 }
1fe2cb32
AB		 1769
1770 netif_device_attach(dev);
1771
1772 if (netif_running(dev))
1773 tulip_up(dev);
1774
1da177e4
LT		 1775 return 0;
1776}
1777
1778#endif /* CONFIG_PM */
1779
1780
1781static void __devexit tulip_remove_one (struct pci_dev *pdev)
1782{
1783 struct net_device *dev = pci_get_drvdata (pdev);
1784 struct tulip_private *tp;
1785
1786 if (!dev)
1787 return;
1788
1789 tp = netdev_priv(dev);
1790 unregister_netdev(dev);
1791 pci_free_consistent (pdev,
1792 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1793 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1794 tp->rx_ring, tp->rx_ring_dma);
b4558ea9 1795 kfree (tp->mtable);
1da177e4
LT		 1796 pci_iounmap(pdev, tp->base_addr);
1797 free_netdev (dev);
1798 pci_release_regions (pdev);
1799 pci_set_drvdata (pdev, NULL);
1800
1801 /* pci_power_off (pdev, -1); */
1802}
1803
1804#ifdef CONFIG_NET_POLL_CONTROLLER
1805/*
1806 * Polling 'interrupt' - used by things like netconsole to send skbs
1807 * without having to re-enable interrupts. It's not called while
1808 * the interrupt routine is executing.
1809 */
1810
1811static void poll_tulip (struct net_device *dev)
1812{
1813 /* disable_irq here is not very nice, but with the lockless
1814 interrupt handler we have no other choice. */
1815 disable_irq(dev->irq);
7d12e780 1816 tulip_interrupt (dev->irq, dev);
1da177e4
LT		 1817 enable_irq(dev->irq);
1818}
1819#endif
1820
1821static struct pci_driver tulip_driver = {
1822 .name = DRV_NAME,
1823 .id_table = tulip_pci_tbl,
1824 .probe = tulip_init_one,
1825 .remove = __devexit_p(tulip_remove_one),
1826#ifdef CONFIG_PM
1827 .suspend = tulip_suspend,
1828 .resume = tulip_resume,
1829#endif /* CONFIG_PM */
1830};
1831
1832
1833static int __init tulip_init (void)
1834{
1835#ifdef MODULE
1836 printk (KERN_INFO "%s", version);
1837#endif
1838
1839 /* copy module parms into globals */
1840 tulip_rx_copybreak = rx_copybreak;
1841 tulip_max_interrupt_work = max_interrupt_work;
1842
1843 /* probe for and init boards */
29917620 1844 return pci_register_driver(&tulip_driver);
1da177e4
LT		 1845}
1846
1847
1848static void __exit tulip_cleanup (void)
1849{
1850 pci_unregister_driver (&tulip_driver);
1851}
1852
1853
1854module_init(tulip_init);
1855module_exit(tulip_cleanup);
Michael's Linux tree.