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FEC: Properly align address over the buffers for cache ops
[people/ms/u-boot.git] / drivers / net / uli526x.c
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1f103105 1/*
0ef91193 2 * Copyright 2007, 2010 Freescale Semiconductor, Inc.
1f103105
RZ		 3 *
4 * Author: Roy Zang <tie-fei.zang@freescale.com>, Sep, 2007
5 *
6 * Description:
7 * ULI 526x Ethernet port driver.
8 * Based on the Linux driver: drivers/net/tulip/uli526x.c
9 *
10 * This is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#include <common.h>
17#include <malloc.h>
18#include <net.h>
89973f8a 19#include <netdev.h>
1f103105
RZ		 20#include <asm/io.h>
21#include <pci.h>
22#include <miiphy.h>
23
24/* some kernel function compatible define */
25
1f103105
RZ		 26#undef DEBUG
27
28/* Board/System/Debug information/definition */
29#define ULI_VENDOR_ID 0x10B9
30#define ULI5261_DEVICE_ID 0x5261
31#define ULI5263_DEVICE_ID 0x5263
32/* ULi M5261 ID*/
e845e07e 33#define PCI_ULI5261_ID (ULI5261_DEVICE_ID << 16 | ULI_VENDOR_ID)
1f103105 34/* ULi M5263 ID*/
e845e07e 35#define PCI_ULI5263_ID (ULI5263_DEVICE_ID << 16 | ULI_VENDOR_ID)
1f103105
RZ		 36
37#define ULI526X_IO_SIZE 0x100
38#define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
39#define RX_DESC_CNT PKTBUFSRX /* Allocated Rx descriptors */
40#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
41#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
42#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
43#define TX_BUF_ALLOC 0x300
44#define RX_ALLOC_SIZE PKTSIZE
45#define ULI526X_RESET 1
46#define CR0_DEFAULT 0
47#define CR6_DEFAULT 0x22200000
48#define CR7_DEFAULT 0x180c1
49#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
50#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
51#define MAX_PACKET_SIZE 1514
52#define ULI5261_MAX_MULTICAST 14
53#define RX_COPY_SIZE 100
54#define MAX_CHECK_PACKET 0x8000
55
56#define ULI526X_10MHF 0
57#define ULI526X_100MHF 1
58#define ULI526X_10MFD 4
59#define ULI526X_100MFD 5
60#define ULI526X_AUTO 8
61
62#define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
63#define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
64#define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
65#define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
66#define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
67#define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
68
69/* CR9 definition: SROM/MII */
70#define CR9_SROM_READ 0x4800
71#define CR9_SRCS 0x1
72#define CR9_SRCLK 0x2
73#define CR9_CRDOUT 0x8
74#define SROM_DATA_0 0x0
75#define SROM_DATA_1 0x4
76#define PHY_DATA_1 0x20000
77#define PHY_DATA_0 0x00000
78#define MDCLKH 0x10000
79
80#define PHY_POWER_DOWN 0x800
81
82#define SROM_V41_CODE 0x14
83
84#define SROM_CLK_WRITE(data, ioaddr) do { \
85 outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
86 udelay(5); \
87 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK, ioaddr); \
88 udelay(5); \
89 outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
90 udelay(5); \
91 } while (0)
92
93/* Structure/enum declaration */
94
95struct tx_desc {
96 u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
97 char *tx_buf_ptr; /* Data for us */
98 struct tx_desc *next_tx_desc;
99};
100
101struct rx_desc {
102 u32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
103 char *rx_buf_ptr; /* Data for us */
104 struct rx_desc *next_rx_desc;
105};
106
107struct uli526x_board_info {
108 u32 chip_id; /* Chip vendor/Device ID */
109 pci_dev_t pdev;
110
111 long ioaddr; /* I/O base address */
112 u32 cr0_data;
113 u32 cr5_data;
114 u32 cr6_data;
115 u32 cr7_data;
116 u32 cr15_data;
117
118 /* pointer for memory physical address */
119 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
120 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
121 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
122 dma_addr_t first_tx_desc_dma;
123 dma_addr_t first_rx_desc_dma;
124
125 /* descriptor pointer */
126 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
127 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
128 unsigned char *desc_pool_ptr; /* descriptor pool memory */
129 struct tx_desc *first_tx_desc;
130 struct tx_desc *tx_insert_ptr;
131 struct tx_desc *tx_remove_ptr;
132 struct rx_desc *first_rx_desc;
133 struct rx_desc *rx_ready_ptr; /* packet come pointer */
134 unsigned long tx_packet_cnt; /* transmitted packet count */
135
136 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
137
138 u8 media_mode; /* user specify media mode */
139 u8 op_mode; /* real work dedia mode */
140 u8 phy_addr;
141
142 /* NIC SROM data */
143 unsigned char srom[128];
144};
145
146enum uli526x_offsets {
147 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
148 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
149 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
150 DCR15 = 0x78
151};
152
153enum uli526x_CR6_bits {
154 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
155 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
156 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
157};
158
159/* Global variable declaration -- */
160
161static unsigned char uli526x_media_mode = ULI526X_AUTO;
162
163static struct tx_desc desc_pool_array[DESC_ALL_CNT + 0x20]
164 __attribute__ ((aligned(32)));
165static char buf_pool[TX_BUF_ALLOC * TX_DESC_CNT + 4];
166
167/* For module input parameter */
168static int mode = 8;
169
170/* function declaration -- */
4b942150 171static int uli526x_start_xmit(struct eth_device *dev, void *packet, int length);
1f103105
RZ		 172static const struct ethtool_ops netdev_ethtool_ops;
173static u16 read_srom_word(long, int);
174static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long);
175static void allocate_rx_buffer(struct uli526x_board_info *);
176static void update_cr6(u32, unsigned long);
09c04c20 177static u16 uli_phy_read(unsigned long, u8, u8, u32);
1f103105 178static u16 phy_readby_cr10(unsigned long, u8, u8);
09c04c20 179static void uli_phy_write(unsigned long, u8, u8, u16, u32);
1f103105
RZ		 180static void phy_writeby_cr10(unsigned long, u8, u8, u16);
181static void phy_write_1bit(unsigned long, u32, u32);
182static u16 phy_read_1bit(unsigned long, u32);
183static int uli526x_rx_packet(struct eth_device *);
184static void uli526x_free_tx_pkt(struct eth_device *,
185 struct uli526x_board_info *);
186static void uli526x_reuse_buf(struct rx_desc *);
187static void uli526x_init(struct eth_device *);
188static void uli526x_set_phyxcer(struct uli526x_board_info *);
189
190
191static int uli526x_init_one(struct eth_device *, bd_t *);
192static void uli526x_disable(struct eth_device *);
193static void set_mac_addr(struct eth_device *);
194
195static struct pci_device_id uli526x_pci_tbl[] = {
196 { ULI_VENDOR_ID, ULI5261_DEVICE_ID}, /* 5261 device */
197 { ULI_VENDOR_ID, ULI5263_DEVICE_ID}, /* 5263 device */
198 {}
199};
200
201/* ULI526X network board routine */
202
203/*
204 * Search ULI526X board, register it
205 */
206
207int uli526x_initialize(bd_t *bis)
208{
209 pci_dev_t devno;
210 int card_number = 0;
211 struct eth_device *dev;
212 struct uli526x_board_info *db; /* board information structure */
213
214 u32 iobase;
215 int idx = 0;
216
217 while (1) {
218 /* Find PCI device */
219 devno = pci_find_devices(uli526x_pci_tbl, idx++);
220 if (devno < 0)
221 break;
222
223 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
224 iobase &= ~0xf;
225
226 dev = (struct eth_device *)malloc(sizeof *dev);
fe7f1883
NI		 227 if (!dev) {
228 printf("uli526x: Can not allocate memory\n");
229 break;
230 }
231 memset(dev, 0, sizeof(*dev));
ec0d879f 232 sprintf(dev->name, "uli526x#%d", card_number);
1f103105
RZ		 233 db = (struct uli526x_board_info *)
234 malloc(sizeof(struct uli526x_board_info));
235
236 dev->priv = db;
237 db->pdev = devno;
238 dev->iobase = iobase;
239
240 dev->init = uli526x_init_one;
241 dev->halt = uli526x_disable;
242 dev->send = uli526x_start_xmit;
243 dev->recv = uli526x_rx_packet;
244
245 /* init db */
246 db->ioaddr = dev->iobase;
247 /* get chip id */
248
249 pci_read_config_dword(devno, PCI_VENDOR_ID, &db->chip_id);
250#ifdef DEBUG
251 printf("uli526x: uli526x @0x%x\n", iobase);
252 printf("uli526x: chip_id%x\n", db->chip_id);
253#endif
254 eth_register(dev);
255 card_number++;
256 pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
257 udelay(10 * 1000);
258 }
259 return card_number;
260}
261
262static int uli526x_init_one(struct eth_device *dev, bd_t *bis)
263{
264
265 struct uli526x_board_info *db = dev->priv;
266 int i;
267
268 switch (mode) {
269 case ULI526X_10MHF:
270 case ULI526X_100MHF:
271 case ULI526X_10MFD:
272 case ULI526X_100MFD:
273 uli526x_media_mode = mode;
274 break;
275 default:
276 uli526x_media_mode = ULI526X_AUTO;
277 break;
278 }
279
280 /* Allocate Tx/Rx descriptor memory */
281 db->desc_pool_ptr = (uchar *)&desc_pool_array[0];
282 db->desc_pool_dma_ptr = (dma_addr_t)&desc_pool_array[0];
283 if (db->desc_pool_ptr == NULL)
422b1a01 284 return -1;
1f103105 285
e845e07e 286 db->buf_pool_ptr = (uchar *)&buf_pool[0];
1f103105
RZ		 287 db->buf_pool_dma_ptr = (dma_addr_t)&buf_pool[0];
288 if (db->buf_pool_ptr == NULL)
422b1a01 289 return -1;
1f103105
RZ		 290
291 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
292 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
293
294 db->buf_pool_start = db->buf_pool_ptr;
295 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
296
297#ifdef DEBUG
298 printf("%s(): db->ioaddr= 0x%x\n",
299 __FUNCTION__, db->ioaddr);
300 printf("%s(): media_mode= 0x%x\n",
301 __FUNCTION__, uli526x_media_mode);
302 printf("%s(): db->desc_pool_ptr= 0x%x\n",
303 __FUNCTION__, db->desc_pool_ptr);
304 printf("%s(): db->desc_pool_dma_ptr= 0x%x\n",
305 __FUNCTION__, db->desc_pool_dma_ptr);
306 printf("%s(): db->buf_pool_ptr= 0x%x\n",
307 __FUNCTION__, db->buf_pool_ptr);
308 printf("%s(): db->buf_pool_dma_ptr= 0x%x\n",
309 __FUNCTION__, db->buf_pool_dma_ptr);
310#endif
311
312 /* read 64 word srom data */
313 for (i = 0; i < 64; i++)
314 ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr,
315 i));
316
317 /* Set Node address */
0ef91193
KG		 318 if (((db->srom[0] == 0xff) && (db->srom[1] == 0xff)) ||
319 ((db->srom[0] == 0x00) && (db->srom[1] == 0x00)))
1f103105
RZ		 320 /* SROM absent, so write MAC address to ID Table */
321 set_mac_addr(dev);
322 else { /*Exist SROM*/
323 for (i = 0; i < 6; i++)
324 dev->enetaddr[i] = db->srom[20 + i];
325 }
326#ifdef DEBUG
327 for (i = 0; i < 6; i++)
328 printf("%c%02x", i ? ':' : ' ', dev->enetaddr[i]);
329#endif
330 db->PHY_reg4 = 0x1e0;
331
332 /* system variable init */
333 db->cr6_data = CR6_DEFAULT ;
334 db->cr6_data |= ULI526X_TXTH_256;
335 db->cr0_data = CR0_DEFAULT;
336 uli526x_init(dev);
422b1a01 337 return 0;
1f103105
RZ		 338}
339
340static void uli526x_disable(struct eth_device *dev)
341{
342#ifdef DEBUG
343 printf("uli526x_disable\n");
344#endif
345 struct uli526x_board_info *db = dev->priv;
346
347 if (!((inl(db->ioaddr + DCR12)) & 0x8)) {
348 /* Reset & stop ULI526X board */
349 outl(ULI526X_RESET, db->ioaddr + DCR0);
350 udelay(5);
09c04c20 351 uli_phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
1f103105
RZ		 352
353 /* reset the board */
354 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
355 update_cr6(db->cr6_data, dev->iobase);
356 outl(0, dev->iobase + DCR7); /* Disable Interrupt */
357 outl(inl(dev->iobase + DCR5), dev->iobase + DCR5);
358 }
359}
360
361/* Initialize ULI526X board
362 * Reset ULI526X board
363 * Initialize TX/Rx descriptor chain structure
364 * Send the set-up frame
365 * Enable Tx/Rx machine
366 */
367
368static void uli526x_init(struct eth_device *dev)
369{
370
371 struct uli526x_board_info *db = dev->priv;
372 u8 phy_tmp;
373 u16 phy_value;
374 u16 phy_reg_reset;
375
376 /* Reset M526x MAC controller */
377 outl(ULI526X_RESET, db->ioaddr + DCR0); /* RESET MAC */
378 udelay(100);
379 outl(db->cr0_data, db->ioaddr + DCR0);
380 udelay(5);
381
382 /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
383 db->phy_addr = 1;
384 db->tx_packet_cnt = 0;
385 for (phy_tmp = 0; phy_tmp < 32; phy_tmp++) {
386 /* peer add */
09c04c20 387 phy_value = uli_phy_read(db->ioaddr, phy_tmp, 3, db->chip_id);
1f103105
RZ		 388 if (phy_value != 0xffff && phy_value != 0) {
389 db->phy_addr = phy_tmp;
390 break;
391 }
392 }
393
394#ifdef DEBUG
395 printf("%s(): db->ioaddr= 0x%x\n", __FUNCTION__, db->ioaddr);
396 printf("%s(): db->phy_addr= 0x%x\n", __FUNCTION__, db->phy_addr);
397#endif
398 if (phy_tmp == 32)
399 printf("Can not find the phy address!!!");
400
401 /* Parser SROM and media mode */
402 db->media_mode = uli526x_media_mode;
403
404 if (!(inl(db->ioaddr + DCR12) & 0x8)) {
405 /* Phyxcer capability setting */
09c04c20 406 phy_reg_reset = uli_phy_read(db->ioaddr,
1f103105
RZ		 407 db->phy_addr, 0, db->chip_id);
408 phy_reg_reset = (phy_reg_reset | 0x8000);
09c04c20 409 uli_phy_write(db->ioaddr, db->phy_addr, 0,
1f103105
RZ		 410 phy_reg_reset, db->chip_id);
411 udelay(500);
412
413 /* Process Phyxcer Media Mode */
414 uli526x_set_phyxcer(db);
415 }
416 /* Media Mode Process */
417 if (!(db->media_mode & ULI526X_AUTO))
53677ef1 418 db->op_mode = db->media_mode; /* Force Mode */
1f103105
RZ		 419
420 /* Initialize Transmit/Receive decriptor and CR3/4 */
421 uli526x_descriptor_init(db, db->ioaddr);
422
423 /* Init CR6 to program M526X operation */
424 update_cr6(db->cr6_data, db->ioaddr);
425
426 /* Init CR7, interrupt active bit */
427 db->cr7_data = CR7_DEFAULT;
428 outl(db->cr7_data, db->ioaddr + DCR7);
429
430 /* Init CR15, Tx jabber and Rx watchdog timer */
431 outl(db->cr15_data, db->ioaddr + DCR15);
432
433 /* Enable ULI526X Tx/Rx function */
434 db->cr6_data |= CR6_RXSC | CR6_TXSC;
435 update_cr6(db->cr6_data, db->ioaddr);
436 while (!(inl(db->ioaddr + DCR12) & 0x8))
437 udelay(10);
438}
439
440/*
441 * Hardware start transmission.
442 * Send a packet to media from the upper layer.
443 */
444
4b942150 445static int uli526x_start_xmit(struct eth_device *dev, void *packet, int length)
1f103105
RZ		 446{
447 struct uli526x_board_info *db = dev->priv;
448 struct tx_desc *txptr;
449 unsigned int len = length;
450 /* Too large packet check */
451 if (len > MAX_PACKET_SIZE) {
452 printf(": big packet = %d\n", len);
453 return 0;
454 }
455
456 /* No Tx resource check, it never happen nromally */
457 if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
458 printf("No Tx resource %ld\n", db->tx_packet_cnt);
459 return 0;
460 }
461
462 /* Disable NIC interrupt */
463 outl(0, dev->iobase + DCR7);
464
465 /* transmit this packet */
466 txptr = db->tx_insert_ptr;
467 memcpy((char *)txptr->tx_buf_ptr, (char *)packet, (int)length);
468 txptr->tdes1 = cpu_to_le32(0xe1000000 | length);
469
470 /* Point to next transmit free descriptor */
471 db->tx_insert_ptr = txptr->next_tx_desc;
472
473 /* Transmit Packet Process */
474 if ((db->tx_packet_cnt < TX_DESC_CNT)) {
475 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
476 db->tx_packet_cnt++; /* Ready to send */
477 outl(0x1, dev->iobase + DCR1); /* Issue Tx polling */
478 }
479
480 /* Got ULI526X status */
481 db->cr5_data = inl(db->ioaddr + DCR5);
482 outl(db->cr5_data, db->ioaddr + DCR5);
483
484#ifdef TX_DEBUG
485 printf("%s(): length = 0x%x\n", __FUNCTION__, length);
486 printf("%s(): cr5_data=%x\n", __FUNCTION__, db->cr5_data);
487#endif
488
489 outl(db->cr7_data, dev->iobase + DCR7);
490 uli526x_free_tx_pkt(dev, db);
491
492 return length;
493}
494
495/*
496 * Free TX resource after TX complete
497 */
498
499static void uli526x_free_tx_pkt(struct eth_device *dev,
500 struct uli526x_board_info *db)
501{
502 struct tx_desc *txptr;
503 u32 tdes0;
504
505 txptr = db->tx_remove_ptr;
506 while (db->tx_packet_cnt) {
507 tdes0 = le32_to_cpu(txptr->tdes0);
508 /* printf(DRV_NAME ": tdes0=%x\n", tdes0); */
509 if (tdes0 & 0x80000000)
510 break;
511
512 /* A packet sent completed */
513 db->tx_packet_cnt--;
514
515 if (tdes0 != 0x7fffffff) {
516#ifdef TX_DEBUG
517 printf("%s()tdes0=%x\n", __FUNCTION__, tdes0);
518#endif
519 if (tdes0 & TDES0_ERR_MASK) {
520 if (tdes0 & 0x0002) { /* UnderRun */
521 if (!(db->cr6_data & CR6_SFT)) {
522 db->cr6_data = db->cr6_data |
523 CR6_SFT;
524 update_cr6(db->cr6_data,
525 db->ioaddr);
526 }
527 }
528 }
529 }
530
531 txptr = txptr->next_tx_desc;
532 }/* End of while */
533
534 /* Update TX remove pointer to next */
535 db->tx_remove_ptr = txptr;
536}
537
538
539/*
540 * Receive the come packet and pass to upper layer
541 */
542
543static int uli526x_rx_packet(struct eth_device *dev)
544{
545 struct uli526x_board_info *db = dev->priv;
546 struct rx_desc *rxptr;
547 int rxlen = 0;
548 u32 rdes0;
549
550 rxptr = db->rx_ready_ptr;
551
552 rdes0 = le32_to_cpu(rxptr->rdes0);
553#ifdef RX_DEBUG
554 printf("%s(): rxptr->rdes0=%x:%x\n", __FUNCTION__, rxptr->rdes0);
555#endif
556 if (!(rdes0 & 0x80000000)) { /* packet owner check */
557 if ((rdes0 & 0x300) != 0x300) {
558 /* A packet without First/Last flag */
559 /* reuse this buf */
560 printf("A packet without First/Last flag");
561 uli526x_reuse_buf(rxptr);
562 } else {
563 /* A packet with First/Last flag */
564 rxlen = ((rdes0 >> 16) & 0x3fff) - 4;
565#ifdef RX_DEBUG
566 printf("%s(): rxlen =%x\n", __FUNCTION__, rxlen);
567#endif
568 /* error summary bit check */
569 if (rdes0 & 0x8000) {
570 /* This is a error packet */
9b55a253 571 printf("Error: rdes0: %x\n", rdes0);
1f103105
RZ		 572 }
573
574 if (!(rdes0 & 0x8000) ||
575 ((db->cr6_data & CR6_PM) && (rxlen > 6))) {
576
577#ifdef RX_DEBUG
578 printf("%s(): rx_skb_ptr =%x\n",
579 __FUNCTION__, rxptr->rx_buf_ptr);
580 printf("%s(): rxlen =%x\n",
581 __FUNCTION__, rxlen);
582
583 printf("%s(): buf addr =%x\n",
584 __FUNCTION__, rxptr->rx_buf_ptr);
585 printf("%s(): rxlen =%x\n",
586 __FUNCTION__, rxlen);
587 int i;
588 for (i = 0; i < 0x20; i++)
589 printf("%s(): data[%x] =%x\n",
590 __FUNCTION__, i, rxptr->rx_buf_ptr[i]);
591#endif
592
e845e07e 593 NetReceive((uchar *)rxptr->rx_buf_ptr, rxlen);
1f103105
RZ		 594 uli526x_reuse_buf(rxptr);
595
596 } else {
597 /* Reuse SKB buffer when the packet is error */
598 printf("Reuse buffer, rdes0");
599 uli526x_reuse_buf(rxptr);
600 }
601 }
602
603 rxptr = rxptr->next_rx_desc;
604 }
605
606 db->rx_ready_ptr = rxptr;
607 return rxlen;
608}
609
610/*
611 * Reuse the RX buffer
612 */
613
614static void uli526x_reuse_buf(struct rx_desc *rxptr)
615{
616
617 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000)))
618 rxptr->rdes0 = cpu_to_le32(0x80000000);
619 else
620 printf("Buffer reuse method error");
621}
622/*
623 * Initialize transmit/Receive descriptor
624 * Using Chain structure, and allocate Tx/Rx buffer
625 */
626
627static void uli526x_descriptor_init(struct uli526x_board_info *db,
628 unsigned long ioaddr)
629{
630 struct tx_desc *tmp_tx;
631 struct rx_desc *tmp_rx;
632 unsigned char *tmp_buf;
633 dma_addr_t tmp_tx_dma, tmp_rx_dma;
634 dma_addr_t tmp_buf_dma;
635 int i;
636 /* tx descriptor start pointer */
637 db->tx_insert_ptr = db->first_tx_desc;
638 db->tx_remove_ptr = db->first_tx_desc;
639
640 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
641
642 /* rx descriptor start pointer */
643 db->first_rx_desc = (void *)db->first_tx_desc +
644 sizeof(struct tx_desc) * TX_DESC_CNT;
645 db->first_rx_desc_dma = db->first_tx_desc_dma +
646 sizeof(struct tx_desc) * TX_DESC_CNT;
647 db->rx_ready_ptr = db->first_rx_desc;
648 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
649#ifdef DEBUG
650 printf("%s(): db->first_tx_desc= 0x%x\n",
651 __FUNCTION__, db->first_tx_desc);
652 printf("%s(): db->first_rx_desc_dma= 0x%x\n",
653 __FUNCTION__, db->first_rx_desc_dma);
654#endif
655 /* Init Transmit chain */
656 tmp_buf = db->buf_pool_start;
657 tmp_buf_dma = db->buf_pool_dma_start;
658 tmp_tx_dma = db->first_tx_desc_dma;
659 for (tmp_tx = db->first_tx_desc, i = 0;
660 i < TX_DESC_CNT; i++, tmp_tx++) {
e845e07e 661 tmp_tx->tx_buf_ptr = (char *)tmp_buf;
1f103105
RZ		 662 tmp_tx->tdes0 = cpu_to_le32(0);
663 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
664 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
665 tmp_tx_dma += sizeof(struct tx_desc);
666 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
667 tmp_tx->next_tx_desc = tmp_tx + 1;
668 tmp_buf = tmp_buf + TX_BUF_ALLOC;
669 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
670 }
671 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
672 tmp_tx->next_tx_desc = db->first_tx_desc;
673
674 /* Init Receive descriptor chain */
675 tmp_rx_dma = db->first_rx_desc_dma;
676 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT;
677 i++, tmp_rx++) {
678 tmp_rx->rdes0 = cpu_to_le32(0);
679 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
680 tmp_rx_dma += sizeof(struct rx_desc);
681 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
682 tmp_rx->next_rx_desc = tmp_rx + 1;
683 }
684 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
685 tmp_rx->next_rx_desc = db->first_rx_desc;
686
687 /* pre-allocate Rx buffer */
688 allocate_rx_buffer(db);
689}
690
691/*
692 * Update CR6 value
693 * Firstly stop ULI526X, then written value and start
694 */
695
696static void update_cr6(u32 cr6_data, unsigned long ioaddr)
697{
698
699 outl(cr6_data, ioaddr + DCR6);
700 udelay(5);
701}
702
703/*
704 * Allocate rx buffer,
705 */
706
707static void allocate_rx_buffer(struct uli526x_board_info *db)
708{
709 int index;
710 struct rx_desc *rxptr;
711 rxptr = db->first_rx_desc;
712 u32 addr;
713
714 for (index = 0; index < RX_DESC_CNT; index++) {
715 addr = (u32)NetRxPackets[index];
716 addr += (16 - (addr & 15));
717 rxptr->rx_buf_ptr = (char *) addr;
718 rxptr->rdes2 = cpu_to_le32(addr);
719 rxptr->rdes0 = cpu_to_le32(0x80000000);
720#ifdef DEBUG
721 printf("%s(): Number 0x%x:\n", __FUNCTION__, index);
722 printf("%s(): addr 0x%x:\n", __FUNCTION__, addr);
723 printf("%s(): rxptr address = 0x%x\n", __FUNCTION__, rxptr);
724 printf("%s(): rxptr buf address = 0x%x\n", \
725 __FUNCTION__, rxptr->rx_buf_ptr);
726 printf("%s(): rdes2 = 0x%x\n", __FUNCTION__, rxptr->rdes2);
727#endif
728 rxptr = rxptr->next_rx_desc;
729 }
730}
731
732/*
733 * Read one word data from the serial ROM
734 */
735
736static u16 read_srom_word(long ioaddr, int offset)
737{
738 int i;
739 u16 srom_data = 0;
740 long cr9_ioaddr = ioaddr + DCR9;
741
742 outl(CR9_SROM_READ, cr9_ioaddr);
743 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
744
745 /* Send the Read Command 110b */
746 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
747 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
748 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
749
750 /* Send the offset */
751 for (i = 5; i >= 0; i--) {
752 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
753 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
754 }
755
756 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
757
758 for (i = 16; i > 0; i--) {
759 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
760 udelay(5);
761 srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT)
762 ? 1 : 0);
763 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
764 udelay(5);
765 }
766
767 outl(CR9_SROM_READ, cr9_ioaddr);
768 return srom_data;
769}
770
771/*
772 * Set 10/100 phyxcer capability
773 * AUTO mode : phyxcer register4 is NIC capability
774 * Force mode: phyxcer register4 is the force media
775 */
776
777static void uli526x_set_phyxcer(struct uli526x_board_info *db)
778{
779 u16 phy_reg;
780
781 /* Phyxcer capability setting */
09c04c20
AF		 782 phy_reg = uli_phy_read(db->ioaddr,
783 db->phy_addr, 4, db->chip_id) & ~0x01e0;
1f103105
RZ		 784
785 if (db->media_mode & ULI526X_AUTO) {
786 /* AUTO Mode */
787 phy_reg |= db->PHY_reg4;
788 } else {
789 /* Force Mode */
790 switch (db->media_mode) {
791 case ULI526X_10MHF: phy_reg |= 0x20; break;
792 case ULI526X_10MFD: phy_reg |= 0x40; break;
793 case ULI526X_100MHF: phy_reg |= 0x80; break;
794 case ULI526X_100MFD: phy_reg |= 0x100; break;
795 }
796
797 }
798
799 /* Write new capability to Phyxcer Reg4 */
800 if (!(phy_reg & 0x01e0)) {
801 phy_reg |= db->PHY_reg4;
802 db->media_mode |= ULI526X_AUTO;
803 }
09c04c20 804 uli_phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1f103105
RZ		 805
806 /* Restart Auto-Negotiation */
09c04c20 807 uli_phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1f103105
RZ		 808 udelay(50);
809}
810
811/*
812 * Write a word to Phy register
813 */
814
09c04c20 815static void uli_phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
1f103105
RZ		 816 u16 phy_data, u32 chip_id)
817{
818 u16 i;
819 unsigned long ioaddr;
820
821 if (chip_id == PCI_ULI5263_ID) {
822 phy_writeby_cr10(iobase, phy_addr, offset, phy_data);
823 return;
824 }
825 /* M5261/M5263 Chip */
826 ioaddr = iobase + DCR9;
827
828 /* Send 33 synchronization clock to Phy controller */
829 for (i = 0; i < 35; i++)
830 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
831
832 /* Send start command(01) to Phy */
833 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
834 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
835
836 /* Send write command(01) to Phy */
837 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
838 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
839
840 /* Send Phy address */
841 for (i = 0x10; i > 0; i = i >> 1)
842 phy_write_1bit(ioaddr, phy_addr & i ?
843 PHY_DATA_1 : PHY_DATA_0, chip_id);
844
845 /* Send register address */
846 for (i = 0x10; i > 0; i = i >> 1)
847 phy_write_1bit(ioaddr, offset & i ?
848 PHY_DATA_1 : PHY_DATA_0, chip_id);
849
850 /* written trasnition */
851 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
852 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
853
854 /* Write a word data to PHY controller */
855 for (i = 0x8000; i > 0; i >>= 1)
856 phy_write_1bit(ioaddr, phy_data & i ?
857 PHY_DATA_1 : PHY_DATA_0, chip_id);
858}
859
860/*
861 * Read a word data from phy register
862 */
863
09c04c20
AF		 864static u16 uli_phy_read(unsigned long iobase, u8 phy_addr, u8 offset,
865 u32 chip_id)
1f103105
RZ		 866{
867 int i;
868 u16 phy_data;
869 unsigned long ioaddr;
870
871 if (chip_id == PCI_ULI5263_ID)
872 return phy_readby_cr10(iobase, phy_addr, offset);
873 /* M5261/M5263 Chip */
874 ioaddr = iobase + DCR9;
875
876 /* Send 33 synchronization clock to Phy controller */
877 for (i = 0; i < 35; i++)
878 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
879
880 /* Send start command(01) to Phy */
881 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
882 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
883
884 /* Send read command(10) to Phy */
885 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
886 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
887
888 /* Send Phy address */
889 for (i = 0x10; i > 0; i = i >> 1)
890 phy_write_1bit(ioaddr, phy_addr & i ?
891 PHY_DATA_1 : PHY_DATA_0, chip_id);
892
893 /* Send register address */
894 for (i = 0x10; i > 0; i = i >> 1)
895 phy_write_1bit(ioaddr, offset & i ?
896 PHY_DATA_1 : PHY_DATA_0, chip_id);
897
898 /* Skip transition state */
899 phy_read_1bit(ioaddr, chip_id);
900
901 /* read 16bit data */
902 for (phy_data = 0, i = 0; i < 16; i++) {
903 phy_data <<= 1;
904 phy_data |= phy_read_1bit(ioaddr, chip_id);
905 }
906
907 return phy_data;
908}
909
910static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset)
911{
912 unsigned long ioaddr, cr10_value;
913
914 ioaddr = iobase + DCR10;
915 cr10_value = phy_addr;
916 cr10_value = (cr10_value<<5) + offset;
917 cr10_value = (cr10_value<<16) + 0x08000000;
918 outl(cr10_value, ioaddr);
919 udelay(1);
920 while (1) {
921 cr10_value = inl(ioaddr);
922 if (cr10_value & 0x10000000)
923 break;
924 }
925 return (cr10_value&0x0ffff);
926}
927
928static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr,
929 u8 offset, u16 phy_data)
930{
931 unsigned long ioaddr, cr10_value;
932
933 ioaddr = iobase + DCR10;
934 cr10_value = phy_addr;
935 cr10_value = (cr10_value<<5) + offset;
936 cr10_value = (cr10_value<<16) + 0x04000000 + phy_data;
937 outl(cr10_value, ioaddr);
938 udelay(1);
939}
940/*
941 * Write one bit data to Phy Controller
942 */
943
944static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id)
945{
946 outl(phy_data , ioaddr); /* MII Clock Low */
947 udelay(1);
948 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
949 udelay(1);
950 outl(phy_data , ioaddr); /* MII Clock Low */
951 udelay(1);
952}
953
954/*
955 * Read one bit phy data from PHY controller
956 */
957
958static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id)
959{
960 u16 phy_data;
961
962 outl(0x50000 , ioaddr);
963 udelay(1);
964 phy_data = (inl(ioaddr) >> 19) & 0x1;
965 outl(0x40000 , ioaddr);
966 udelay(1);
967
968 return phy_data;
969}
970
971/*
972 * Set MAC address to ID Table
973 */
974
975static void set_mac_addr(struct eth_device *dev)
976{
977 int i;
978 u16 addr;
979 struct uli526x_board_info *db = dev->priv;
980 outl(0x10000, db->ioaddr + DCR0); /* Diagnosis mode */
981 /* Reset dianostic pointer port */
982 outl(0x1c0, db->ioaddr + DCR13);
983 outl(0, db->ioaddr + DCR14); /* Clear reset port */
984 outl(0x10, db->ioaddr + DCR14); /* Reset ID Table pointer */
985 outl(0, db->ioaddr + DCR14); /* Clear reset port */
986 outl(0, db->ioaddr + DCR13); /* Clear CR13 */
987 /* Select ID Table access port */
988 outl(0x1b0, db->ioaddr + DCR13);
989 /* Read MAC address from CR14 */
990 for (i = 0; i < 3; i++) {
991 addr = dev->enetaddr[2 * i] | (dev->enetaddr[2 * i + 1] << 8);
992 outl(addr, db->ioaddr + DCR14);
993 }
994 /* write end */
995 outl(0, db->ioaddr + DCR13); /* Clear CR13 */
996 outl(0, db->ioaddr + DCR0); /* Clear CR0 */
997 udelay(10);
998 return;
999}
"Das U-Boot" Source Tree