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ac718b69 | 1 | /* |
c7de7dec | 2 | * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. |
ac718b69 | 3 | * |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * version 2 as published by the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | ||
ac718b69 | 10 | #include <linux/signal.h> |
11 | #include <linux/slab.h> | |
12 | #include <linux/module.h> | |
ac718b69 | 13 | #include <linux/netdevice.h> |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/mii.h> | |
16 | #include <linux/ethtool.h> | |
17 | #include <linux/usb.h> | |
18 | #include <linux/crc32.h> | |
19 | #include <linux/if_vlan.h> | |
20 | #include <linux/uaccess.h> | |
ebc2ec48 | 21 | #include <linux/list.h> |
5bd23881 | 22 | #include <linux/ip.h> |
23 | #include <linux/ipv6.h> | |
ac718b69 | 24 | |
25 | /* Version Information */ | |
21ff2e89 | 26 | #define DRIVER_VERSION "v1.05.0 (2014/02/18)" |
ac718b69 | 27 | #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" |
44d942a9 | 28 | #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" |
ac718b69 | 29 | #define MODULENAME "r8152" |
30 | ||
31 | #define R8152_PHY_ID 32 | |
32 | ||
33 | #define PLA_IDR 0xc000 | |
34 | #define PLA_RCR 0xc010 | |
35 | #define PLA_RMS 0xc016 | |
36 | #define PLA_RXFIFO_CTRL0 0xc0a0 | |
37 | #define PLA_RXFIFO_CTRL1 0xc0a4 | |
38 | #define PLA_RXFIFO_CTRL2 0xc0a8 | |
39 | #define PLA_FMC 0xc0b4 | |
40 | #define PLA_CFG_WOL 0xc0b6 | |
43779f8d | 41 | #define PLA_TEREDO_CFG 0xc0bc |
ac718b69 | 42 | #define PLA_MAR 0xcd00 |
43779f8d | 43 | #define PLA_BACKUP 0xd000 |
ac718b69 | 44 | #define PAL_BDC_CR 0xd1a0 |
43779f8d | 45 | #define PLA_TEREDO_TIMER 0xd2cc |
46 | #define PLA_REALWOW_TIMER 0xd2e8 | |
ac718b69 | 47 | #define PLA_LEDSEL 0xdd90 |
48 | #define PLA_LED_FEATURE 0xdd92 | |
49 | #define PLA_PHYAR 0xde00 | |
43779f8d | 50 | #define PLA_BOOT_CTRL 0xe004 |
ac718b69 | 51 | #define PLA_GPHY_INTR_IMR 0xe022 |
52 | #define PLA_EEE_CR 0xe040 | |
53 | #define PLA_EEEP_CR 0xe080 | |
54 | #define PLA_MAC_PWR_CTRL 0xe0c0 | |
43779f8d | 55 | #define PLA_MAC_PWR_CTRL2 0xe0ca |
56 | #define PLA_MAC_PWR_CTRL3 0xe0cc | |
57 | #define PLA_MAC_PWR_CTRL4 0xe0ce | |
58 | #define PLA_WDT6_CTRL 0xe428 | |
ac718b69 | 59 | #define PLA_TCR0 0xe610 |
60 | #define PLA_TCR1 0xe612 | |
61 | #define PLA_TXFIFO_CTRL 0xe618 | |
62 | #define PLA_RSTTELLY 0xe800 | |
63 | #define PLA_CR 0xe813 | |
64 | #define PLA_CRWECR 0xe81c | |
21ff2e89 | 65 | #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ |
66 | #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ | |
ac718b69 | 67 | #define PLA_CONFIG5 0xe822 |
68 | #define PLA_PHY_PWR 0xe84c | |
69 | #define PLA_OOB_CTRL 0xe84f | |
70 | #define PLA_CPCR 0xe854 | |
71 | #define PLA_MISC_0 0xe858 | |
72 | #define PLA_MISC_1 0xe85a | |
73 | #define PLA_OCP_GPHY_BASE 0xe86c | |
74 | #define PLA_TELLYCNT 0xe890 | |
75 | #define PLA_SFF_STS_7 0xe8de | |
76 | #define PLA_PHYSTATUS 0xe908 | |
77 | #define PLA_BP_BA 0xfc26 | |
78 | #define PLA_BP_0 0xfc28 | |
79 | #define PLA_BP_1 0xfc2a | |
80 | #define PLA_BP_2 0xfc2c | |
81 | #define PLA_BP_3 0xfc2e | |
82 | #define PLA_BP_4 0xfc30 | |
83 | #define PLA_BP_5 0xfc32 | |
84 | #define PLA_BP_6 0xfc34 | |
85 | #define PLA_BP_7 0xfc36 | |
43779f8d | 86 | #define PLA_BP_EN 0xfc38 |
ac718b69 | 87 | |
43779f8d | 88 | #define USB_U2P3_CTRL 0xb460 |
ac718b69 | 89 | #define USB_DEV_STAT 0xb808 |
90 | #define USB_USB_CTRL 0xd406 | |
91 | #define USB_PHY_CTRL 0xd408 | |
92 | #define USB_TX_AGG 0xd40a | |
93 | #define USB_RX_BUF_TH 0xd40c | |
94 | #define USB_USB_TIMER 0xd428 | |
43779f8d | 95 | #define USB_RX_EARLY_AGG 0xd42c |
ac718b69 | 96 | #define USB_PM_CTRL_STATUS 0xd432 |
97 | #define USB_TX_DMA 0xd434 | |
43779f8d | 98 | #define USB_TOLERANCE 0xd490 |
99 | #define USB_LPM_CTRL 0xd41a | |
ac718b69 | 100 | #define USB_UPS_CTRL 0xd800 |
43779f8d | 101 | #define USB_MISC_0 0xd81a |
102 | #define USB_POWER_CUT 0xd80a | |
103 | #define USB_AFE_CTRL2 0xd824 | |
104 | #define USB_WDT11_CTRL 0xe43c | |
ac718b69 | 105 | #define USB_BP_BA 0xfc26 |
106 | #define USB_BP_0 0xfc28 | |
107 | #define USB_BP_1 0xfc2a | |
108 | #define USB_BP_2 0xfc2c | |
109 | #define USB_BP_3 0xfc2e | |
110 | #define USB_BP_4 0xfc30 | |
111 | #define USB_BP_5 0xfc32 | |
112 | #define USB_BP_6 0xfc34 | |
113 | #define USB_BP_7 0xfc36 | |
43779f8d | 114 | #define USB_BP_EN 0xfc38 |
ac718b69 | 115 | |
116 | /* OCP Registers */ | |
117 | #define OCP_ALDPS_CONFIG 0x2010 | |
118 | #define OCP_EEE_CONFIG1 0x2080 | |
119 | #define OCP_EEE_CONFIG2 0x2092 | |
120 | #define OCP_EEE_CONFIG3 0x2094 | |
ac244d3e | 121 | #define OCP_BASE_MII 0xa400 |
ac718b69 | 122 | #define OCP_EEE_AR 0xa41a |
123 | #define OCP_EEE_DATA 0xa41c | |
43779f8d | 124 | #define OCP_PHY_STATUS 0xa420 |
125 | #define OCP_POWER_CFG 0xa430 | |
126 | #define OCP_EEE_CFG 0xa432 | |
127 | #define OCP_SRAM_ADDR 0xa436 | |
128 | #define OCP_SRAM_DATA 0xa438 | |
129 | #define OCP_DOWN_SPEED 0xa442 | |
130 | #define OCP_EEE_CFG2 0xa5d0 | |
131 | #define OCP_ADC_CFG 0xbc06 | |
132 | ||
133 | /* SRAM Register */ | |
134 | #define SRAM_LPF_CFG 0x8012 | |
135 | #define SRAM_10M_AMP1 0x8080 | |
136 | #define SRAM_10M_AMP2 0x8082 | |
137 | #define SRAM_IMPEDANCE 0x8084 | |
ac718b69 | 138 | |
139 | /* PLA_RCR */ | |
140 | #define RCR_AAP 0x00000001 | |
141 | #define RCR_APM 0x00000002 | |
142 | #define RCR_AM 0x00000004 | |
143 | #define RCR_AB 0x00000008 | |
144 | #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) | |
145 | ||
146 | /* PLA_RXFIFO_CTRL0 */ | |
147 | #define RXFIFO_THR1_NORMAL 0x00080002 | |
148 | #define RXFIFO_THR1_OOB 0x01800003 | |
149 | ||
150 | /* PLA_RXFIFO_CTRL1 */ | |
151 | #define RXFIFO_THR2_FULL 0x00000060 | |
152 | #define RXFIFO_THR2_HIGH 0x00000038 | |
153 | #define RXFIFO_THR2_OOB 0x0000004a | |
43779f8d | 154 | #define RXFIFO_THR2_NORMAL 0x00a0 |
ac718b69 | 155 | |
156 | /* PLA_RXFIFO_CTRL2 */ | |
157 | #define RXFIFO_THR3_FULL 0x00000078 | |
158 | #define RXFIFO_THR3_HIGH 0x00000048 | |
159 | #define RXFIFO_THR3_OOB 0x0000005a | |
43779f8d | 160 | #define RXFIFO_THR3_NORMAL 0x0110 |
ac718b69 | 161 | |
162 | /* PLA_TXFIFO_CTRL */ | |
163 | #define TXFIFO_THR_NORMAL 0x00400008 | |
43779f8d | 164 | #define TXFIFO_THR_NORMAL2 0x01000008 |
ac718b69 | 165 | |
166 | /* PLA_FMC */ | |
167 | #define FMC_FCR_MCU_EN 0x0001 | |
168 | ||
169 | /* PLA_EEEP_CR */ | |
170 | #define EEEP_CR_EEEP_TX 0x0002 | |
171 | ||
43779f8d | 172 | /* PLA_WDT6_CTRL */ |
173 | #define WDT6_SET_MODE 0x0010 | |
174 | ||
ac718b69 | 175 | /* PLA_TCR0 */ |
176 | #define TCR0_TX_EMPTY 0x0800 | |
177 | #define TCR0_AUTO_FIFO 0x0080 | |
178 | ||
179 | /* PLA_TCR1 */ | |
180 | #define VERSION_MASK 0x7cf0 | |
181 | ||
182 | /* PLA_CR */ | |
183 | #define CR_RST 0x10 | |
184 | #define CR_RE 0x08 | |
185 | #define CR_TE 0x04 | |
186 | ||
187 | /* PLA_CRWECR */ | |
188 | #define CRWECR_NORAML 0x00 | |
189 | #define CRWECR_CONFIG 0xc0 | |
190 | ||
191 | /* PLA_OOB_CTRL */ | |
192 | #define NOW_IS_OOB 0x80 | |
193 | #define TXFIFO_EMPTY 0x20 | |
194 | #define RXFIFO_EMPTY 0x10 | |
195 | #define LINK_LIST_READY 0x02 | |
196 | #define DIS_MCU_CLROOB 0x01 | |
197 | #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) | |
198 | ||
199 | /* PLA_MISC_1 */ | |
200 | #define RXDY_GATED_EN 0x0008 | |
201 | ||
202 | /* PLA_SFF_STS_7 */ | |
203 | #define RE_INIT_LL 0x8000 | |
204 | #define MCU_BORW_EN 0x4000 | |
205 | ||
206 | /* PLA_CPCR */ | |
207 | #define CPCR_RX_VLAN 0x0040 | |
208 | ||
209 | /* PLA_CFG_WOL */ | |
210 | #define MAGIC_EN 0x0001 | |
211 | ||
43779f8d | 212 | /* PLA_TEREDO_CFG */ |
213 | #define TEREDO_SEL 0x8000 | |
214 | #define TEREDO_WAKE_MASK 0x7f00 | |
215 | #define TEREDO_RS_EVENT_MASK 0x00fe | |
216 | #define OOB_TEREDO_EN 0x0001 | |
217 | ||
ac718b69 | 218 | /* PAL_BDC_CR */ |
219 | #define ALDPS_PROXY_MODE 0x0001 | |
220 | ||
21ff2e89 | 221 | /* PLA_CONFIG34 */ |
222 | #define LINK_ON_WAKE_EN 0x0010 | |
223 | #define LINK_OFF_WAKE_EN 0x0008 | |
224 | ||
ac718b69 | 225 | /* PLA_CONFIG5 */ |
21ff2e89 | 226 | #define BWF_EN 0x0040 |
227 | #define MWF_EN 0x0020 | |
228 | #define UWF_EN 0x0010 | |
ac718b69 | 229 | #define LAN_WAKE_EN 0x0002 |
230 | ||
231 | /* PLA_LED_FEATURE */ | |
232 | #define LED_MODE_MASK 0x0700 | |
233 | ||
234 | /* PLA_PHY_PWR */ | |
235 | #define TX_10M_IDLE_EN 0x0080 | |
236 | #define PFM_PWM_SWITCH 0x0040 | |
237 | ||
238 | /* PLA_MAC_PWR_CTRL */ | |
239 | #define D3_CLK_GATED_EN 0x00004000 | |
240 | #define MCU_CLK_RATIO 0x07010f07 | |
241 | #define MCU_CLK_RATIO_MASK 0x0f0f0f0f | |
43779f8d | 242 | #define ALDPS_SPDWN_RATIO 0x0f87 |
243 | ||
244 | /* PLA_MAC_PWR_CTRL2 */ | |
245 | #define EEE_SPDWN_RATIO 0x8007 | |
246 | ||
247 | /* PLA_MAC_PWR_CTRL3 */ | |
248 | #define PKT_AVAIL_SPDWN_EN 0x0100 | |
249 | #define SUSPEND_SPDWN_EN 0x0004 | |
250 | #define U1U2_SPDWN_EN 0x0002 | |
251 | #define L1_SPDWN_EN 0x0001 | |
252 | ||
253 | /* PLA_MAC_PWR_CTRL4 */ | |
254 | #define PWRSAVE_SPDWN_EN 0x1000 | |
255 | #define RXDV_SPDWN_EN 0x0800 | |
256 | #define TX10MIDLE_EN 0x0100 | |
257 | #define TP100_SPDWN_EN 0x0020 | |
258 | #define TP500_SPDWN_EN 0x0010 | |
259 | #define TP1000_SPDWN_EN 0x0008 | |
260 | #define EEE_SPDWN_EN 0x0001 | |
ac718b69 | 261 | |
262 | /* PLA_GPHY_INTR_IMR */ | |
263 | #define GPHY_STS_MSK 0x0001 | |
264 | #define SPEED_DOWN_MSK 0x0002 | |
265 | #define SPDWN_RXDV_MSK 0x0004 | |
266 | #define SPDWN_LINKCHG_MSK 0x0008 | |
267 | ||
268 | /* PLA_PHYAR */ | |
269 | #define PHYAR_FLAG 0x80000000 | |
270 | ||
271 | /* PLA_EEE_CR */ | |
272 | #define EEE_RX_EN 0x0001 | |
273 | #define EEE_TX_EN 0x0002 | |
274 | ||
43779f8d | 275 | /* PLA_BOOT_CTRL */ |
276 | #define AUTOLOAD_DONE 0x0002 | |
277 | ||
ac718b69 | 278 | /* USB_DEV_STAT */ |
279 | #define STAT_SPEED_MASK 0x0006 | |
280 | #define STAT_SPEED_HIGH 0x0000 | |
281 | #define STAT_SPEED_FULL 0x0001 | |
282 | ||
283 | /* USB_TX_AGG */ | |
284 | #define TX_AGG_MAX_THRESHOLD 0x03 | |
285 | ||
286 | /* USB_RX_BUF_TH */ | |
43779f8d | 287 | #define RX_THR_SUPPER 0x0c350180 |
8e1f51bd | 288 | #define RX_THR_HIGH 0x7a120180 |
43779f8d | 289 | #define RX_THR_SLOW 0xffff0180 |
ac718b69 | 290 | |
291 | /* USB_TX_DMA */ | |
292 | #define TEST_MODE_DISABLE 0x00000001 | |
293 | #define TX_SIZE_ADJUST1 0x00000100 | |
294 | ||
295 | /* USB_UPS_CTRL */ | |
296 | #define POWER_CUT 0x0100 | |
297 | ||
298 | /* USB_PM_CTRL_STATUS */ | |
8e1f51bd | 299 | #define RESUME_INDICATE 0x0001 |
ac718b69 | 300 | |
301 | /* USB_USB_CTRL */ | |
302 | #define RX_AGG_DISABLE 0x0010 | |
303 | ||
43779f8d | 304 | /* USB_U2P3_CTRL */ |
305 | #define U2P3_ENABLE 0x0001 | |
306 | ||
307 | /* USB_POWER_CUT */ | |
308 | #define PWR_EN 0x0001 | |
309 | #define PHASE2_EN 0x0008 | |
310 | ||
311 | /* USB_MISC_0 */ | |
312 | #define PCUT_STATUS 0x0001 | |
313 | ||
314 | /* USB_RX_EARLY_AGG */ | |
315 | #define EARLY_AGG_SUPPER 0x0e832981 | |
316 | #define EARLY_AGG_HIGH 0x0e837a12 | |
317 | #define EARLY_AGG_SLOW 0x0e83ffff | |
318 | ||
319 | /* USB_WDT11_CTRL */ | |
320 | #define TIMER11_EN 0x0001 | |
321 | ||
322 | /* USB_LPM_CTRL */ | |
323 | #define LPM_TIMER_MASK 0x0c | |
324 | #define LPM_TIMER_500MS 0x04 /* 500 ms */ | |
325 | #define LPM_TIMER_500US 0x0c /* 500 us */ | |
326 | ||
327 | /* USB_AFE_CTRL2 */ | |
328 | #define SEN_VAL_MASK 0xf800 | |
329 | #define SEN_VAL_NORMAL 0xa000 | |
330 | #define SEL_RXIDLE 0x0100 | |
331 | ||
ac718b69 | 332 | /* OCP_ALDPS_CONFIG */ |
333 | #define ENPWRSAVE 0x8000 | |
334 | #define ENPDNPS 0x0200 | |
335 | #define LINKENA 0x0100 | |
336 | #define DIS_SDSAVE 0x0010 | |
337 | ||
43779f8d | 338 | /* OCP_PHY_STATUS */ |
339 | #define PHY_STAT_MASK 0x0007 | |
340 | #define PHY_STAT_LAN_ON 3 | |
341 | #define PHY_STAT_PWRDN 5 | |
342 | ||
343 | /* OCP_POWER_CFG */ | |
344 | #define EEE_CLKDIV_EN 0x8000 | |
345 | #define EN_ALDPS 0x0004 | |
346 | #define EN_10M_PLLOFF 0x0001 | |
347 | ||
ac718b69 | 348 | /* OCP_EEE_CONFIG1 */ |
349 | #define RG_TXLPI_MSK_HFDUP 0x8000 | |
350 | #define RG_MATCLR_EN 0x4000 | |
351 | #define EEE_10_CAP 0x2000 | |
352 | #define EEE_NWAY_EN 0x1000 | |
353 | #define TX_QUIET_EN 0x0200 | |
354 | #define RX_QUIET_EN 0x0100 | |
355 | #define SDRISETIME 0x0010 /* bit 4 ~ 6 */ | |
356 | #define RG_RXLPI_MSK_HFDUP 0x0008 | |
357 | #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ | |
358 | ||
359 | /* OCP_EEE_CONFIG2 */ | |
360 | #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ | |
361 | #define RG_DACQUIET_EN 0x0400 | |
362 | #define RG_LDVQUIET_EN 0x0200 | |
363 | #define RG_CKRSEL 0x0020 | |
364 | #define RG_EEEPRG_EN 0x0010 | |
365 | ||
366 | /* OCP_EEE_CONFIG3 */ | |
367 | #define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */ | |
368 | #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ | |
369 | #define MSK_PH 0x0006 /* bit 0 ~ 3 */ | |
370 | ||
371 | /* OCP_EEE_AR */ | |
372 | /* bit[15:14] function */ | |
373 | #define FUN_ADDR 0x0000 | |
374 | #define FUN_DATA 0x4000 | |
375 | /* bit[4:0] device addr */ | |
376 | #define DEVICE_ADDR 0x0007 | |
377 | ||
378 | /* OCP_EEE_DATA */ | |
379 | #define EEE_ADDR 0x003C | |
380 | #define EEE_DATA 0x0002 | |
381 | ||
43779f8d | 382 | /* OCP_EEE_CFG */ |
383 | #define CTAP_SHORT_EN 0x0040 | |
384 | #define EEE10_EN 0x0010 | |
385 | ||
386 | /* OCP_DOWN_SPEED */ | |
387 | #define EN_10M_BGOFF 0x0080 | |
388 | ||
389 | /* OCP_EEE_CFG2 */ | |
390 | #define MY1000_EEE 0x0004 | |
391 | #define MY100_EEE 0x0002 | |
392 | ||
393 | /* OCP_ADC_CFG */ | |
394 | #define CKADSEL_L 0x0100 | |
395 | #define ADC_EN 0x0080 | |
396 | #define EN_EMI_L 0x0040 | |
397 | ||
398 | /* SRAM_LPF_CFG */ | |
399 | #define LPF_AUTO_TUNE 0x8000 | |
400 | ||
401 | /* SRAM_10M_AMP1 */ | |
402 | #define GDAC_IB_UPALL 0x0008 | |
403 | ||
404 | /* SRAM_10M_AMP2 */ | |
405 | #define AMP_DN 0x0200 | |
406 | ||
407 | /* SRAM_IMPEDANCE */ | |
408 | #define RX_DRIVING_MASK 0x6000 | |
409 | ||
ac718b69 | 410 | enum rtl_register_content { |
43779f8d | 411 | _1000bps = 0x10, |
ac718b69 | 412 | _100bps = 0x08, |
413 | _10bps = 0x04, | |
414 | LINK_STATUS = 0x02, | |
415 | FULL_DUP = 0x01, | |
416 | }; | |
417 | ||
ebc2ec48 | 418 | #define RTL8152_MAX_TX 10 |
419 | #define RTL8152_MAX_RX 10 | |
40a82917 | 420 | #define INTBUFSIZE 2 |
8e1f51bd | 421 | #define CRC_SIZE 4 |
422 | #define TX_ALIGN 4 | |
423 | #define RX_ALIGN 8 | |
40a82917 | 424 | |
425 | #define INTR_LINK 0x0004 | |
ebc2ec48 | 426 | |
ac718b69 | 427 | #define RTL8152_REQT_READ 0xc0 |
428 | #define RTL8152_REQT_WRITE 0x40 | |
429 | #define RTL8152_REQ_GET_REGS 0x05 | |
430 | #define RTL8152_REQ_SET_REGS 0x05 | |
431 | ||
432 | #define BYTE_EN_DWORD 0xff | |
433 | #define BYTE_EN_WORD 0x33 | |
434 | #define BYTE_EN_BYTE 0x11 | |
435 | #define BYTE_EN_SIX_BYTES 0x3f | |
436 | #define BYTE_EN_START_MASK 0x0f | |
437 | #define BYTE_EN_END_MASK 0xf0 | |
438 | ||
439 | #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) | |
440 | #define RTL8152_TX_TIMEOUT (HZ) | |
441 | ||
442 | /* rtl8152 flags */ | |
443 | enum rtl8152_flags { | |
444 | RTL8152_UNPLUG = 0, | |
ac718b69 | 445 | RTL8152_SET_RX_MODE, |
40a82917 | 446 | WORK_ENABLE, |
447 | RTL8152_LINK_CHG, | |
9a4be1bd | 448 | SELECTIVE_SUSPEND, |
aa66a5f1 | 449 | PHY_RESET, |
0c3121fc | 450 | SCHEDULE_TASKLET, |
ac718b69 | 451 | }; |
452 | ||
453 | /* Define these values to match your device */ | |
454 | #define VENDOR_ID_REALTEK 0x0bda | |
455 | #define PRODUCT_ID_RTL8152 0x8152 | |
43779f8d | 456 | #define PRODUCT_ID_RTL8153 0x8153 |
457 | ||
458 | #define VENDOR_ID_SAMSUNG 0x04e8 | |
459 | #define PRODUCT_ID_SAMSUNG 0xa101 | |
ac718b69 | 460 | |
461 | #define MCU_TYPE_PLA 0x0100 | |
462 | #define MCU_TYPE_USB 0x0000 | |
463 | ||
c7de7dec | 464 | #define REALTEK_USB_DEVICE(vend, prod) \ |
465 | USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC) | |
466 | ||
ac718b69 | 467 | struct rx_desc { |
500b6d7e | 468 | __le32 opts1; |
ac718b69 | 469 | #define RX_LEN_MASK 0x7fff |
565cab0a | 470 | |
500b6d7e | 471 | __le32 opts2; |
565cab0a | 472 | #define RD_UDP_CS (1 << 23) |
473 | #define RD_TCP_CS (1 << 22) | |
474 | #define RD_IPV4_CS (1 << 19) | |
475 | ||
500b6d7e | 476 | __le32 opts3; |
565cab0a | 477 | #define IPF (1 << 23) /* IP checksum fail */ |
478 | #define UDPF (1 << 22) /* UDP checksum fail */ | |
479 | #define TCPF (1 << 21) /* TCP checksum fail */ | |
480 | ||
500b6d7e | 481 | __le32 opts4; |
482 | __le32 opts5; | |
483 | __le32 opts6; | |
ac718b69 | 484 | }; |
485 | ||
486 | struct tx_desc { | |
500b6d7e | 487 | __le32 opts1; |
ac718b69 | 488 | #define TX_FS (1 << 31) /* First segment of a packet */ |
489 | #define TX_LS (1 << 30) /* Final segment of a packet */ | |
5bd23881 | 490 | #define TX_LEN_MASK 0x3ffff |
491 | ||
500b6d7e | 492 | __le32 opts2; |
5bd23881 | 493 | #define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */ |
494 | #define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */ | |
495 | #define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */ | |
496 | #define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */ | |
ac718b69 | 497 | }; |
498 | ||
dff4e8ad | 499 | struct r8152; |
500 | ||
ebc2ec48 | 501 | struct rx_agg { |
502 | struct list_head list; | |
503 | struct urb *urb; | |
dff4e8ad | 504 | struct r8152 *context; |
ebc2ec48 | 505 | void *buffer; |
506 | void *head; | |
507 | }; | |
508 | ||
509 | struct tx_agg { | |
510 | struct list_head list; | |
511 | struct urb *urb; | |
dff4e8ad | 512 | struct r8152 *context; |
ebc2ec48 | 513 | void *buffer; |
514 | void *head; | |
515 | u32 skb_num; | |
516 | u32 skb_len; | |
517 | }; | |
518 | ||
ac718b69 | 519 | struct r8152 { |
520 | unsigned long flags; | |
521 | struct usb_device *udev; | |
522 | struct tasklet_struct tl; | |
40a82917 | 523 | struct usb_interface *intf; |
ac718b69 | 524 | struct net_device *netdev; |
40a82917 | 525 | struct urb *intr_urb; |
ebc2ec48 | 526 | struct tx_agg tx_info[RTL8152_MAX_TX]; |
527 | struct rx_agg rx_info[RTL8152_MAX_RX]; | |
528 | struct list_head rx_done, tx_free; | |
529 | struct sk_buff_head tx_queue; | |
530 | spinlock_t rx_lock, tx_lock; | |
ac718b69 | 531 | struct delayed_work schedule; |
532 | struct mii_if_info mii; | |
c81229c9 | 533 | |
534 | struct rtl_ops { | |
535 | void (*init)(struct r8152 *); | |
536 | int (*enable)(struct r8152 *); | |
537 | void (*disable)(struct r8152 *); | |
7e9da481 | 538 | void (*up)(struct r8152 *); |
c81229c9 | 539 | void (*down)(struct r8152 *); |
540 | void (*unload)(struct r8152 *); | |
541 | } rtl_ops; | |
542 | ||
40a82917 | 543 | int intr_interval; |
21ff2e89 | 544 | u32 saved_wolopts; |
ac718b69 | 545 | u32 msg_enable; |
dd1b119c | 546 | u32 tx_qlen; |
ac718b69 | 547 | u16 ocp_base; |
40a82917 | 548 | u8 *intr_buff; |
ac718b69 | 549 | u8 version; |
550 | u8 speed; | |
551 | }; | |
552 | ||
553 | enum rtl_version { | |
554 | RTL_VER_UNKNOWN = 0, | |
555 | RTL_VER_01, | |
43779f8d | 556 | RTL_VER_02, |
557 | RTL_VER_03, | |
558 | RTL_VER_04, | |
559 | RTL_VER_05, | |
560 | RTL_VER_MAX | |
ac718b69 | 561 | }; |
562 | ||
563 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). | |
564 | * The RTL chips use a 64 element hash table based on the Ethernet CRC. | |
565 | */ | |
566 | static const int multicast_filter_limit = 32; | |
ebc2ec48 | 567 | static unsigned int rx_buf_sz = 16384; |
ac718b69 | 568 | |
569 | static | |
570 | int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
571 | { | |
31787f53 | 572 | int ret; |
573 | void *tmp; | |
574 | ||
575 | tmp = kmalloc(size, GFP_KERNEL); | |
576 | if (!tmp) | |
577 | return -ENOMEM; | |
578 | ||
579 | ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), | |
ac718b69 | 580 | RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, |
31787f53 | 581 | value, index, tmp, size, 500); |
582 | ||
583 | memcpy(data, tmp, size); | |
584 | kfree(tmp); | |
585 | ||
586 | return ret; | |
ac718b69 | 587 | } |
588 | ||
589 | static | |
590 | int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
591 | { | |
31787f53 | 592 | int ret; |
593 | void *tmp; | |
594 | ||
595 | tmp = kmalloc(size, GFP_KERNEL); | |
596 | if (!tmp) | |
597 | return -ENOMEM; | |
598 | ||
599 | memcpy(tmp, data, size); | |
600 | ||
601 | ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), | |
ac718b69 | 602 | RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, |
31787f53 | 603 | value, index, tmp, size, 500); |
604 | ||
605 | kfree(tmp); | |
db8515ef | 606 | |
31787f53 | 607 | return ret; |
ac718b69 | 608 | } |
609 | ||
610 | static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, | |
611 | void *data, u16 type) | |
612 | { | |
45f4a19f | 613 | u16 limit = 64; |
614 | int ret = 0; | |
ac718b69 | 615 | |
616 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
617 | return -ENODEV; | |
618 | ||
619 | /* both size and indix must be 4 bytes align */ | |
620 | if ((size & 3) || !size || (index & 3) || !data) | |
621 | return -EPERM; | |
622 | ||
623 | if ((u32)index + (u32)size > 0xffff) | |
624 | return -EPERM; | |
625 | ||
626 | while (size) { | |
627 | if (size > limit) { | |
628 | ret = get_registers(tp, index, type, limit, data); | |
629 | if (ret < 0) | |
630 | break; | |
631 | ||
632 | index += limit; | |
633 | data += limit; | |
634 | size -= limit; | |
635 | } else { | |
636 | ret = get_registers(tp, index, type, size, data); | |
637 | if (ret < 0) | |
638 | break; | |
639 | ||
640 | index += size; | |
641 | data += size; | |
642 | size = 0; | |
643 | break; | |
644 | } | |
645 | } | |
646 | ||
647 | return ret; | |
648 | } | |
649 | ||
650 | static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, | |
651 | u16 size, void *data, u16 type) | |
652 | { | |
45f4a19f | 653 | int ret; |
654 | u16 byteen_start, byteen_end, byen; | |
655 | u16 limit = 512; | |
ac718b69 | 656 | |
657 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
658 | return -ENODEV; | |
659 | ||
660 | /* both size and indix must be 4 bytes align */ | |
661 | if ((size & 3) || !size || (index & 3) || !data) | |
662 | return -EPERM; | |
663 | ||
664 | if ((u32)index + (u32)size > 0xffff) | |
665 | return -EPERM; | |
666 | ||
667 | byteen_start = byteen & BYTE_EN_START_MASK; | |
668 | byteen_end = byteen & BYTE_EN_END_MASK; | |
669 | ||
670 | byen = byteen_start | (byteen_start << 4); | |
671 | ret = set_registers(tp, index, type | byen, 4, data); | |
672 | if (ret < 0) | |
673 | goto error1; | |
674 | ||
675 | index += 4; | |
676 | data += 4; | |
677 | size -= 4; | |
678 | ||
679 | if (size) { | |
680 | size -= 4; | |
681 | ||
682 | while (size) { | |
683 | if (size > limit) { | |
684 | ret = set_registers(tp, index, | |
685 | type | BYTE_EN_DWORD, | |
686 | limit, data); | |
687 | if (ret < 0) | |
688 | goto error1; | |
689 | ||
690 | index += limit; | |
691 | data += limit; | |
692 | size -= limit; | |
693 | } else { | |
694 | ret = set_registers(tp, index, | |
695 | type | BYTE_EN_DWORD, | |
696 | size, data); | |
697 | if (ret < 0) | |
698 | goto error1; | |
699 | ||
700 | index += size; | |
701 | data += size; | |
702 | size = 0; | |
703 | break; | |
704 | } | |
705 | } | |
706 | ||
707 | byen = byteen_end | (byteen_end >> 4); | |
708 | ret = set_registers(tp, index, type | byen, 4, data); | |
709 | if (ret < 0) | |
710 | goto error1; | |
711 | } | |
712 | ||
713 | error1: | |
714 | return ret; | |
715 | } | |
716 | ||
717 | static inline | |
718 | int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
719 | { | |
720 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); | |
721 | } | |
722 | ||
723 | static inline | |
724 | int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
725 | { | |
726 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); | |
727 | } | |
728 | ||
729 | static inline | |
730 | int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
731 | { | |
732 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB); | |
733 | } | |
734 | ||
735 | static inline | |
736 | int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
737 | { | |
738 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); | |
739 | } | |
740 | ||
741 | static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) | |
742 | { | |
c8826de8 | 743 | __le32 data; |
ac718b69 | 744 | |
c8826de8 | 745 | generic_ocp_read(tp, index, sizeof(data), &data, type); |
ac718b69 | 746 | |
747 | return __le32_to_cpu(data); | |
748 | } | |
749 | ||
750 | static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) | |
751 | { | |
c8826de8 | 752 | __le32 tmp = __cpu_to_le32(data); |
753 | ||
754 | generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); | |
ac718b69 | 755 | } |
756 | ||
757 | static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) | |
758 | { | |
759 | u32 data; | |
c8826de8 | 760 | __le32 tmp; |
ac718b69 | 761 | u8 shift = index & 2; |
762 | ||
763 | index &= ~3; | |
764 | ||
c8826de8 | 765 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 766 | |
c8826de8 | 767 | data = __le32_to_cpu(tmp); |
ac718b69 | 768 | data >>= (shift * 8); |
769 | data &= 0xffff; | |
770 | ||
771 | return (u16)data; | |
772 | } | |
773 | ||
774 | static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) | |
775 | { | |
c8826de8 | 776 | u32 mask = 0xffff; |
777 | __le32 tmp; | |
ac718b69 | 778 | u16 byen = BYTE_EN_WORD; |
779 | u8 shift = index & 2; | |
780 | ||
781 | data &= mask; | |
782 | ||
783 | if (index & 2) { | |
784 | byen <<= shift; | |
785 | mask <<= (shift * 8); | |
786 | data <<= (shift * 8); | |
787 | index &= ~3; | |
788 | } | |
789 | ||
c8826de8 | 790 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 791 | |
c8826de8 | 792 | data |= __le32_to_cpu(tmp) & ~mask; |
793 | tmp = __cpu_to_le32(data); | |
ac718b69 | 794 | |
c8826de8 | 795 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 796 | } |
797 | ||
798 | static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) | |
799 | { | |
800 | u32 data; | |
c8826de8 | 801 | __le32 tmp; |
ac718b69 | 802 | u8 shift = index & 3; |
803 | ||
804 | index &= ~3; | |
805 | ||
c8826de8 | 806 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 807 | |
c8826de8 | 808 | data = __le32_to_cpu(tmp); |
ac718b69 | 809 | data >>= (shift * 8); |
810 | data &= 0xff; | |
811 | ||
812 | return (u8)data; | |
813 | } | |
814 | ||
815 | static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) | |
816 | { | |
c8826de8 | 817 | u32 mask = 0xff; |
818 | __le32 tmp; | |
ac718b69 | 819 | u16 byen = BYTE_EN_BYTE; |
820 | u8 shift = index & 3; | |
821 | ||
822 | data &= mask; | |
823 | ||
824 | if (index & 3) { | |
825 | byen <<= shift; | |
826 | mask <<= (shift * 8); | |
827 | data <<= (shift * 8); | |
828 | index &= ~3; | |
829 | } | |
830 | ||
c8826de8 | 831 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 832 | |
c8826de8 | 833 | data |= __le32_to_cpu(tmp) & ~mask; |
834 | tmp = __cpu_to_le32(data); | |
ac718b69 | 835 | |
c8826de8 | 836 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 837 | } |
838 | ||
ac244d3e | 839 | static u16 ocp_reg_read(struct r8152 *tp, u16 addr) |
e3fe0b1a | 840 | { |
841 | u16 ocp_base, ocp_index; | |
842 | ||
843 | ocp_base = addr & 0xf000; | |
844 | if (ocp_base != tp->ocp_base) { | |
845 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
846 | tp->ocp_base = ocp_base; | |
847 | } | |
848 | ||
849 | ocp_index = (addr & 0x0fff) | 0xb000; | |
ac244d3e | 850 | return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); |
e3fe0b1a | 851 | } |
852 | ||
ac244d3e | 853 | static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) |
ac718b69 | 854 | { |
ac244d3e | 855 | u16 ocp_base, ocp_index; |
ac718b69 | 856 | |
ac244d3e | 857 | ocp_base = addr & 0xf000; |
858 | if (ocp_base != tp->ocp_base) { | |
859 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
860 | tp->ocp_base = ocp_base; | |
ac718b69 | 861 | } |
ac244d3e | 862 | |
863 | ocp_index = (addr & 0x0fff) | 0xb000; | |
864 | ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); | |
ac718b69 | 865 | } |
866 | ||
ac244d3e | 867 | static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) |
ac718b69 | 868 | { |
ac244d3e | 869 | ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); |
870 | } | |
ac718b69 | 871 | |
ac244d3e | 872 | static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) |
873 | { | |
874 | return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); | |
ac718b69 | 875 | } |
876 | ||
43779f8d | 877 | static void sram_write(struct r8152 *tp, u16 addr, u16 data) |
878 | { | |
879 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
880 | ocp_reg_write(tp, OCP_SRAM_DATA, data); | |
881 | } | |
882 | ||
883 | static u16 sram_read(struct r8152 *tp, u16 addr) | |
884 | { | |
885 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
886 | return ocp_reg_read(tp, OCP_SRAM_DATA); | |
887 | } | |
888 | ||
ac718b69 | 889 | static int read_mii_word(struct net_device *netdev, int phy_id, int reg) |
890 | { | |
891 | struct r8152 *tp = netdev_priv(netdev); | |
9a4be1bd | 892 | int ret; |
ac718b69 | 893 | |
894 | if (phy_id != R8152_PHY_ID) | |
895 | return -EINVAL; | |
896 | ||
9a4be1bd | 897 | ret = usb_autopm_get_interface(tp->intf); |
898 | if (ret < 0) | |
899 | goto out; | |
900 | ||
901 | ret = r8152_mdio_read(tp, reg); | |
902 | ||
903 | usb_autopm_put_interface(tp->intf); | |
904 | ||
905 | out: | |
906 | return ret; | |
ac718b69 | 907 | } |
908 | ||
909 | static | |
910 | void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) | |
911 | { | |
912 | struct r8152 *tp = netdev_priv(netdev); | |
913 | ||
914 | if (phy_id != R8152_PHY_ID) | |
915 | return; | |
916 | ||
9a4be1bd | 917 | if (usb_autopm_get_interface(tp->intf) < 0) |
918 | return; | |
919 | ||
ac718b69 | 920 | r8152_mdio_write(tp, reg, val); |
9a4be1bd | 921 | |
922 | usb_autopm_put_interface(tp->intf); | |
ac718b69 | 923 | } |
924 | ||
ebc2ec48 | 925 | static |
926 | int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); | |
927 | ||
ac718b69 | 928 | static inline void set_ethernet_addr(struct r8152 *tp) |
929 | { | |
930 | struct net_device *dev = tp->netdev; | |
8a91c824 | 931 | int ret; |
31787f53 | 932 | u8 node_id[8] = {0}; |
ac718b69 | 933 | |
8a91c824 | 934 | if (tp->version == RTL_VER_01) |
935 | ret = pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id); | |
936 | else | |
937 | ret = pla_ocp_read(tp, PLA_BACKUP, sizeof(node_id), node_id); | |
938 | ||
939 | if (ret < 0) { | |
ac718b69 | 940 | netif_notice(tp, probe, dev, "inet addr fail\n"); |
8a91c824 | 941 | } else { |
942 | if (tp->version != RTL_VER_01) { | |
943 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, | |
944 | CRWECR_CONFIG); | |
945 | pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, | |
946 | sizeof(node_id), node_id); | |
947 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, | |
948 | CRWECR_NORAML); | |
949 | } | |
950 | ||
ac718b69 | 951 | memcpy(dev->dev_addr, node_id, dev->addr_len); |
952 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); | |
953 | } | |
ac718b69 | 954 | } |
955 | ||
956 | static int rtl8152_set_mac_address(struct net_device *netdev, void *p) | |
957 | { | |
958 | struct r8152 *tp = netdev_priv(netdev); | |
959 | struct sockaddr *addr = p; | |
960 | ||
961 | if (!is_valid_ether_addr(addr->sa_data)) | |
962 | return -EADDRNOTAVAIL; | |
963 | ||
964 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
965 | ||
966 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
967 | pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); | |
968 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
969 | ||
970 | return 0; | |
971 | } | |
972 | ||
ac718b69 | 973 | static void read_bulk_callback(struct urb *urb) |
974 | { | |
ac718b69 | 975 | struct net_device *netdev; |
ac718b69 | 976 | int status = urb->status; |
ebc2ec48 | 977 | struct rx_agg *agg; |
978 | struct r8152 *tp; | |
ac718b69 | 979 | int result; |
ac718b69 | 980 | |
ebc2ec48 | 981 | agg = urb->context; |
982 | if (!agg) | |
983 | return; | |
984 | ||
985 | tp = agg->context; | |
ac718b69 | 986 | if (!tp) |
987 | return; | |
ebc2ec48 | 988 | |
ac718b69 | 989 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
990 | return; | |
ebc2ec48 | 991 | |
992 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
993 | return; | |
994 | ||
ac718b69 | 995 | netdev = tp->netdev; |
7559fb2f | 996 | |
997 | /* When link down, the driver would cancel all bulks. */ | |
998 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 999 | if (!netif_carrier_ok(netdev)) |
ac718b69 | 1000 | return; |
1001 | ||
9a4be1bd | 1002 | usb_mark_last_busy(tp->udev); |
1003 | ||
ac718b69 | 1004 | switch (status) { |
1005 | case 0: | |
ebc2ec48 | 1006 | if (urb->actual_length < ETH_ZLEN) |
1007 | break; | |
1008 | ||
2685d410 | 1009 | spin_lock(&tp->rx_lock); |
ebc2ec48 | 1010 | list_add_tail(&agg->list, &tp->rx_done); |
2685d410 | 1011 | spin_unlock(&tp->rx_lock); |
ebc2ec48 | 1012 | tasklet_schedule(&tp->tl); |
1013 | return; | |
ac718b69 | 1014 | case -ESHUTDOWN: |
1015 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
1016 | netif_device_detach(tp->netdev); | |
ebc2ec48 | 1017 | return; |
ac718b69 | 1018 | case -ENOENT: |
1019 | return; /* the urb is in unlink state */ | |
1020 | case -ETIME: | |
4a8deae2 HW |
1021 | if (net_ratelimit()) |
1022 | netdev_warn(netdev, "maybe reset is needed?\n"); | |
ebc2ec48 | 1023 | break; |
ac718b69 | 1024 | default: |
4a8deae2 HW |
1025 | if (net_ratelimit()) |
1026 | netdev_warn(netdev, "Rx status %d\n", status); | |
ebc2ec48 | 1027 | break; |
ac718b69 | 1028 | } |
1029 | ||
ebc2ec48 | 1030 | result = r8152_submit_rx(tp, agg, GFP_ATOMIC); |
ac718b69 | 1031 | if (result == -ENODEV) { |
1032 | netif_device_detach(tp->netdev); | |
1033 | } else if (result) { | |
2685d410 | 1034 | spin_lock(&tp->rx_lock); |
ebc2ec48 | 1035 | list_add_tail(&agg->list, &tp->rx_done); |
2685d410 | 1036 | spin_unlock(&tp->rx_lock); |
ebc2ec48 | 1037 | tasklet_schedule(&tp->tl); |
ac718b69 | 1038 | } |
ac718b69 | 1039 | } |
1040 | ||
ebc2ec48 | 1041 | static void write_bulk_callback(struct urb *urb) |
ac718b69 | 1042 | { |
ebc2ec48 | 1043 | struct net_device_stats *stats; |
d104eafa | 1044 | struct net_device *netdev; |
ebc2ec48 | 1045 | struct tx_agg *agg; |
ac718b69 | 1046 | struct r8152 *tp; |
ebc2ec48 | 1047 | int status = urb->status; |
ac718b69 | 1048 | |
ebc2ec48 | 1049 | agg = urb->context; |
1050 | if (!agg) | |
ac718b69 | 1051 | return; |
1052 | ||
ebc2ec48 | 1053 | tp = agg->context; |
1054 | if (!tp) | |
1055 | return; | |
1056 | ||
d104eafa | 1057 | netdev = tp->netdev; |
05e0f1aa | 1058 | stats = &netdev->stats; |
ebc2ec48 | 1059 | if (status) { |
4a8deae2 | 1060 | if (net_ratelimit()) |
d104eafa | 1061 | netdev_warn(netdev, "Tx status %d\n", status); |
ebc2ec48 | 1062 | stats->tx_errors += agg->skb_num; |
ac718b69 | 1063 | } else { |
ebc2ec48 | 1064 | stats->tx_packets += agg->skb_num; |
1065 | stats->tx_bytes += agg->skb_len; | |
ac718b69 | 1066 | } |
1067 | ||
2685d410 | 1068 | spin_lock(&tp->tx_lock); |
ebc2ec48 | 1069 | list_add_tail(&agg->list, &tp->tx_free); |
2685d410 | 1070 | spin_unlock(&tp->tx_lock); |
ebc2ec48 | 1071 | |
9a4be1bd | 1072 | usb_autopm_put_interface_async(tp->intf); |
1073 | ||
d104eafa | 1074 | if (!netif_carrier_ok(netdev)) |
ebc2ec48 | 1075 | return; |
1076 | ||
1077 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1078 | return; | |
1079 | ||
1080 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1081 | return; | |
1082 | ||
1083 | if (!skb_queue_empty(&tp->tx_queue)) | |
0c3121fc | 1084 | tasklet_schedule(&tp->tl); |
ac718b69 | 1085 | } |
1086 | ||
40a82917 | 1087 | static void intr_callback(struct urb *urb) |
1088 | { | |
1089 | struct r8152 *tp; | |
500b6d7e | 1090 | __le16 *d; |
40a82917 | 1091 | int status = urb->status; |
1092 | int res; | |
1093 | ||
1094 | tp = urb->context; | |
1095 | if (!tp) | |
1096 | return; | |
1097 | ||
1098 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1099 | return; | |
1100 | ||
1101 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1102 | return; | |
1103 | ||
1104 | switch (status) { | |
1105 | case 0: /* success */ | |
1106 | break; | |
1107 | case -ECONNRESET: /* unlink */ | |
1108 | case -ESHUTDOWN: | |
1109 | netif_device_detach(tp->netdev); | |
1110 | case -ENOENT: | |
1111 | return; | |
1112 | case -EOVERFLOW: | |
1113 | netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); | |
1114 | goto resubmit; | |
1115 | /* -EPIPE: should clear the halt */ | |
1116 | default: | |
1117 | netif_info(tp, intr, tp->netdev, "intr status %d\n", status); | |
1118 | goto resubmit; | |
1119 | } | |
1120 | ||
1121 | d = urb->transfer_buffer; | |
1122 | if (INTR_LINK & __le16_to_cpu(d[0])) { | |
1123 | if (!(tp->speed & LINK_STATUS)) { | |
1124 | set_bit(RTL8152_LINK_CHG, &tp->flags); | |
1125 | schedule_delayed_work(&tp->schedule, 0); | |
1126 | } | |
1127 | } else { | |
1128 | if (tp->speed & LINK_STATUS) { | |
1129 | set_bit(RTL8152_LINK_CHG, &tp->flags); | |
1130 | schedule_delayed_work(&tp->schedule, 0); | |
1131 | } | |
1132 | } | |
1133 | ||
1134 | resubmit: | |
1135 | res = usb_submit_urb(urb, GFP_ATOMIC); | |
1136 | if (res == -ENODEV) | |
1137 | netif_device_detach(tp->netdev); | |
1138 | else if (res) | |
1139 | netif_err(tp, intr, tp->netdev, | |
4a8deae2 | 1140 | "can't resubmit intr, status %d\n", res); |
40a82917 | 1141 | } |
1142 | ||
ebc2ec48 | 1143 | static inline void *rx_agg_align(void *data) |
1144 | { | |
8e1f51bd | 1145 | return (void *)ALIGN((uintptr_t)data, RX_ALIGN); |
ebc2ec48 | 1146 | } |
1147 | ||
1148 | static inline void *tx_agg_align(void *data) | |
1149 | { | |
8e1f51bd | 1150 | return (void *)ALIGN((uintptr_t)data, TX_ALIGN); |
ebc2ec48 | 1151 | } |
1152 | ||
1153 | static void free_all_mem(struct r8152 *tp) | |
1154 | { | |
1155 | int i; | |
1156 | ||
1157 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
9629e3c0 | 1158 | usb_free_urb(tp->rx_info[i].urb); |
1159 | tp->rx_info[i].urb = NULL; | |
ebc2ec48 | 1160 | |
9629e3c0 | 1161 | kfree(tp->rx_info[i].buffer); |
1162 | tp->rx_info[i].buffer = NULL; | |
1163 | tp->rx_info[i].head = NULL; | |
ebc2ec48 | 1164 | } |
1165 | ||
1166 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
9629e3c0 | 1167 | usb_free_urb(tp->tx_info[i].urb); |
1168 | tp->tx_info[i].urb = NULL; | |
ebc2ec48 | 1169 | |
9629e3c0 | 1170 | kfree(tp->tx_info[i].buffer); |
1171 | tp->tx_info[i].buffer = NULL; | |
1172 | tp->tx_info[i].head = NULL; | |
ebc2ec48 | 1173 | } |
40a82917 | 1174 | |
9629e3c0 | 1175 | usb_free_urb(tp->intr_urb); |
1176 | tp->intr_urb = NULL; | |
40a82917 | 1177 | |
9629e3c0 | 1178 | kfree(tp->intr_buff); |
1179 | tp->intr_buff = NULL; | |
ebc2ec48 | 1180 | } |
1181 | ||
1182 | static int alloc_all_mem(struct r8152 *tp) | |
1183 | { | |
1184 | struct net_device *netdev = tp->netdev; | |
40a82917 | 1185 | struct usb_interface *intf = tp->intf; |
1186 | struct usb_host_interface *alt = intf->cur_altsetting; | |
1187 | struct usb_host_endpoint *ep_intr = alt->endpoint + 2; | |
ebc2ec48 | 1188 | struct urb *urb; |
1189 | int node, i; | |
1190 | u8 *buf; | |
1191 | ||
1192 | node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; | |
1193 | ||
1194 | spin_lock_init(&tp->rx_lock); | |
1195 | spin_lock_init(&tp->tx_lock); | |
1196 | INIT_LIST_HEAD(&tp->rx_done); | |
1197 | INIT_LIST_HEAD(&tp->tx_free); | |
1198 | skb_queue_head_init(&tp->tx_queue); | |
1199 | ||
1200 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
1201 | buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); | |
1202 | if (!buf) | |
1203 | goto err1; | |
1204 | ||
1205 | if (buf != rx_agg_align(buf)) { | |
1206 | kfree(buf); | |
8e1f51bd | 1207 | buf = kmalloc_node(rx_buf_sz + RX_ALIGN, GFP_KERNEL, |
1208 | node); | |
ebc2ec48 | 1209 | if (!buf) |
1210 | goto err1; | |
1211 | } | |
1212 | ||
1213 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1214 | if (!urb) { | |
1215 | kfree(buf); | |
1216 | goto err1; | |
1217 | } | |
1218 | ||
1219 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
1220 | tp->rx_info[i].context = tp; | |
1221 | tp->rx_info[i].urb = urb; | |
1222 | tp->rx_info[i].buffer = buf; | |
1223 | tp->rx_info[i].head = rx_agg_align(buf); | |
1224 | } | |
1225 | ||
1226 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
1227 | buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); | |
1228 | if (!buf) | |
1229 | goto err1; | |
1230 | ||
1231 | if (buf != tx_agg_align(buf)) { | |
1232 | kfree(buf); | |
8e1f51bd | 1233 | buf = kmalloc_node(rx_buf_sz + TX_ALIGN, GFP_KERNEL, |
1234 | node); | |
ebc2ec48 | 1235 | if (!buf) |
1236 | goto err1; | |
1237 | } | |
1238 | ||
1239 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1240 | if (!urb) { | |
1241 | kfree(buf); | |
1242 | goto err1; | |
1243 | } | |
1244 | ||
1245 | INIT_LIST_HEAD(&tp->tx_info[i].list); | |
1246 | tp->tx_info[i].context = tp; | |
1247 | tp->tx_info[i].urb = urb; | |
1248 | tp->tx_info[i].buffer = buf; | |
1249 | tp->tx_info[i].head = tx_agg_align(buf); | |
1250 | ||
1251 | list_add_tail(&tp->tx_info[i].list, &tp->tx_free); | |
1252 | } | |
1253 | ||
40a82917 | 1254 | tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); |
1255 | if (!tp->intr_urb) | |
1256 | goto err1; | |
1257 | ||
1258 | tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); | |
1259 | if (!tp->intr_buff) | |
1260 | goto err1; | |
1261 | ||
1262 | tp->intr_interval = (int)ep_intr->desc.bInterval; | |
1263 | usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), | |
1264 | tp->intr_buff, INTBUFSIZE, intr_callback, | |
1265 | tp, tp->intr_interval); | |
1266 | ||
ebc2ec48 | 1267 | return 0; |
1268 | ||
1269 | err1: | |
1270 | free_all_mem(tp); | |
1271 | return -ENOMEM; | |
1272 | } | |
1273 | ||
0de98f6c | 1274 | static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) |
1275 | { | |
1276 | struct tx_agg *agg = NULL; | |
1277 | unsigned long flags; | |
1278 | ||
21949ab7 | 1279 | if (list_empty(&tp->tx_free)) |
1280 | return NULL; | |
1281 | ||
0de98f6c | 1282 | spin_lock_irqsave(&tp->tx_lock, flags); |
1283 | if (!list_empty(&tp->tx_free)) { | |
1284 | struct list_head *cursor; | |
1285 | ||
1286 | cursor = tp->tx_free.next; | |
1287 | list_del_init(cursor); | |
1288 | agg = list_entry(cursor, struct tx_agg, list); | |
1289 | } | |
1290 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1291 | ||
1292 | return agg; | |
1293 | } | |
1294 | ||
5bd23881 | 1295 | static void |
1296 | r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, struct sk_buff *skb) | |
1297 | { | |
1298 | memset(desc, 0, sizeof(*desc)); | |
1299 | ||
1300 | desc->opts1 = cpu_to_le32((skb->len & TX_LEN_MASK) | TX_FS | TX_LS); | |
1301 | ||
1302 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1303 | __be16 protocol; | |
1304 | u8 ip_protocol; | |
1305 | u32 opts2 = 0; | |
1306 | ||
1307 | if (skb->protocol == htons(ETH_P_8021Q)) | |
1308 | protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto; | |
1309 | else | |
1310 | protocol = skb->protocol; | |
1311 | ||
1312 | switch (protocol) { | |
1313 | case htons(ETH_P_IP): | |
1314 | opts2 |= IPV4_CS; | |
1315 | ip_protocol = ip_hdr(skb)->protocol; | |
1316 | break; | |
1317 | ||
1318 | case htons(ETH_P_IPV6): | |
1319 | opts2 |= IPV6_CS; | |
1320 | ip_protocol = ipv6_hdr(skb)->nexthdr; | |
1321 | break; | |
1322 | ||
1323 | default: | |
1324 | ip_protocol = IPPROTO_RAW; | |
1325 | break; | |
1326 | } | |
1327 | ||
1328 | if (ip_protocol == IPPROTO_TCP) { | |
1329 | opts2 |= TCP_CS; | |
1330 | opts2 |= (skb_transport_offset(skb) & 0x7fff) << 17; | |
1331 | } else if (ip_protocol == IPPROTO_UDP) { | |
1332 | opts2 |= UDP_CS; | |
1333 | } else { | |
1334 | WARN_ON_ONCE(1); | |
1335 | } | |
1336 | ||
1337 | desc->opts2 = cpu_to_le32(opts2); | |
1338 | } | |
1339 | } | |
1340 | ||
b1379d9a | 1341 | static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) |
1342 | { | |
d84130a1 | 1343 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
9a4be1bd | 1344 | int remain, ret; |
b1379d9a | 1345 | u8 *tx_data; |
1346 | ||
d84130a1 | 1347 | __skb_queue_head_init(&skb_head); |
0c3121fc | 1348 | spin_lock(&tx_queue->lock); |
d84130a1 | 1349 | skb_queue_splice_init(tx_queue, &skb_head); |
0c3121fc | 1350 | spin_unlock(&tx_queue->lock); |
d84130a1 | 1351 | |
b1379d9a | 1352 | tx_data = agg->head; |
1353 | agg->skb_num = agg->skb_len = 0; | |
7937f9e5 | 1354 | remain = rx_buf_sz; |
b1379d9a | 1355 | |
7937f9e5 | 1356 | while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { |
b1379d9a | 1357 | struct tx_desc *tx_desc; |
1358 | struct sk_buff *skb; | |
1359 | unsigned int len; | |
1360 | ||
d84130a1 | 1361 | skb = __skb_dequeue(&skb_head); |
b1379d9a | 1362 | if (!skb) |
1363 | break; | |
1364 | ||
7937f9e5 | 1365 | remain -= sizeof(*tx_desc); |
b1379d9a | 1366 | len = skb->len; |
1367 | if (remain < len) { | |
d84130a1 | 1368 | __skb_queue_head(&skb_head, skb); |
b1379d9a | 1369 | break; |
1370 | } | |
1371 | ||
7937f9e5 | 1372 | tx_data = tx_agg_align(tx_data); |
b1379d9a | 1373 | tx_desc = (struct tx_desc *)tx_data; |
1374 | tx_data += sizeof(*tx_desc); | |
1375 | ||
1376 | r8152_tx_csum(tp, tx_desc, skb); | |
1377 | memcpy(tx_data, skb->data, len); | |
1378 | agg->skb_num++; | |
1379 | agg->skb_len += len; | |
1380 | dev_kfree_skb_any(skb); | |
1381 | ||
7937f9e5 | 1382 | tx_data += len; |
1383 | remain = rx_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); | |
b1379d9a | 1384 | } |
1385 | ||
d84130a1 | 1386 | if (!skb_queue_empty(&skb_head)) { |
0c3121fc | 1387 | spin_lock(&tx_queue->lock); |
d84130a1 | 1388 | skb_queue_splice(&skb_head, tx_queue); |
0c3121fc | 1389 | spin_unlock(&tx_queue->lock); |
d84130a1 | 1390 | } |
1391 | ||
0c3121fc | 1392 | netif_tx_lock(tp->netdev); |
dd1b119c | 1393 | |
1394 | if (netif_queue_stopped(tp->netdev) && | |
1395 | skb_queue_len(&tp->tx_queue) < tp->tx_qlen) | |
1396 | netif_wake_queue(tp->netdev); | |
1397 | ||
0c3121fc | 1398 | netif_tx_unlock(tp->netdev); |
9a4be1bd | 1399 | |
0c3121fc | 1400 | ret = usb_autopm_get_interface_async(tp->intf); |
9a4be1bd | 1401 | if (ret < 0) |
1402 | goto out_tx_fill; | |
dd1b119c | 1403 | |
b1379d9a | 1404 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), |
1405 | agg->head, (int)(tx_data - (u8 *)agg->head), | |
1406 | (usb_complete_t)write_bulk_callback, agg); | |
1407 | ||
0c3121fc | 1408 | ret = usb_submit_urb(agg->urb, GFP_ATOMIC); |
9a4be1bd | 1409 | if (ret < 0) |
0c3121fc | 1410 | usb_autopm_put_interface_async(tp->intf); |
9a4be1bd | 1411 | |
1412 | out_tx_fill: | |
1413 | return ret; | |
b1379d9a | 1414 | } |
1415 | ||
565cab0a | 1416 | static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) |
1417 | { | |
1418 | u8 checksum = CHECKSUM_NONE; | |
1419 | u32 opts2, opts3; | |
1420 | ||
1421 | if (tp->version == RTL_VER_01) | |
1422 | goto return_result; | |
1423 | ||
1424 | opts2 = le32_to_cpu(rx_desc->opts2); | |
1425 | opts3 = le32_to_cpu(rx_desc->opts3); | |
1426 | ||
1427 | if (opts2 & RD_IPV4_CS) { | |
1428 | if (opts3 & IPF) | |
1429 | checksum = CHECKSUM_NONE; | |
1430 | else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF)) | |
1431 | checksum = CHECKSUM_NONE; | |
1432 | else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF)) | |
1433 | checksum = CHECKSUM_NONE; | |
1434 | else | |
1435 | checksum = CHECKSUM_UNNECESSARY; | |
1436 | } | |
1437 | ||
1438 | return_result: | |
1439 | return checksum; | |
1440 | } | |
1441 | ||
ebc2ec48 | 1442 | static void rx_bottom(struct r8152 *tp) |
1443 | { | |
a5a4f468 | 1444 | unsigned long flags; |
d84130a1 | 1445 | struct list_head *cursor, *next, rx_queue; |
ebc2ec48 | 1446 | |
d84130a1 | 1447 | if (list_empty(&tp->rx_done)) |
1448 | return; | |
1449 | ||
1450 | INIT_LIST_HEAD(&rx_queue); | |
a5a4f468 | 1451 | spin_lock_irqsave(&tp->rx_lock, flags); |
d84130a1 | 1452 | list_splice_init(&tp->rx_done, &rx_queue); |
1453 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
1454 | ||
1455 | list_for_each_safe(cursor, next, &rx_queue) { | |
43a4478d | 1456 | struct rx_desc *rx_desc; |
1457 | struct rx_agg *agg; | |
43a4478d | 1458 | int len_used = 0; |
1459 | struct urb *urb; | |
1460 | u8 *rx_data; | |
1461 | int ret; | |
1462 | ||
ebc2ec48 | 1463 | list_del_init(cursor); |
ebc2ec48 | 1464 | |
1465 | agg = list_entry(cursor, struct rx_agg, list); | |
1466 | urb = agg->urb; | |
0de98f6c | 1467 | if (urb->actual_length < ETH_ZLEN) |
1468 | goto submit; | |
ebc2ec48 | 1469 | |
ebc2ec48 | 1470 | rx_desc = agg->head; |
1471 | rx_data = agg->head; | |
7937f9e5 | 1472 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1473 | |
7937f9e5 | 1474 | while (urb->actual_length > len_used) { |
43a4478d | 1475 | struct net_device *netdev = tp->netdev; |
05e0f1aa | 1476 | struct net_device_stats *stats = &netdev->stats; |
7937f9e5 | 1477 | unsigned int pkt_len; |
43a4478d | 1478 | struct sk_buff *skb; |
1479 | ||
7937f9e5 | 1480 | pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; |
ebc2ec48 | 1481 | if (pkt_len < ETH_ZLEN) |
1482 | break; | |
1483 | ||
7937f9e5 | 1484 | len_used += pkt_len; |
1485 | if (urb->actual_length < len_used) | |
1486 | break; | |
1487 | ||
8e1f51bd | 1488 | pkt_len -= CRC_SIZE; |
ebc2ec48 | 1489 | rx_data += sizeof(struct rx_desc); |
1490 | ||
1491 | skb = netdev_alloc_skb_ip_align(netdev, pkt_len); | |
1492 | if (!skb) { | |
1493 | stats->rx_dropped++; | |
5e2f7485 | 1494 | goto find_next_rx; |
ebc2ec48 | 1495 | } |
565cab0a | 1496 | |
1497 | skb->ip_summed = r8152_rx_csum(tp, rx_desc); | |
ebc2ec48 | 1498 | memcpy(skb->data, rx_data, pkt_len); |
1499 | skb_put(skb, pkt_len); | |
1500 | skb->protocol = eth_type_trans(skb, netdev); | |
9d9aafa1 | 1501 | netif_receive_skb(skb); |
ebc2ec48 | 1502 | stats->rx_packets++; |
1503 | stats->rx_bytes += pkt_len; | |
1504 | ||
5e2f7485 | 1505 | find_next_rx: |
8e1f51bd | 1506 | rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE); |
ebc2ec48 | 1507 | rx_desc = (struct rx_desc *)rx_data; |
ebc2ec48 | 1508 | len_used = (int)(rx_data - (u8 *)agg->head); |
7937f9e5 | 1509 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1510 | } |
1511 | ||
0de98f6c | 1512 | submit: |
ebc2ec48 | 1513 | ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); |
ebc2ec48 | 1514 | if (ret && ret != -ENODEV) { |
d84130a1 | 1515 | spin_lock_irqsave(&tp->rx_lock, flags); |
1516 | list_add_tail(&agg->list, &tp->rx_done); | |
1517 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
ebc2ec48 | 1518 | tasklet_schedule(&tp->tl); |
1519 | } | |
1520 | } | |
ebc2ec48 | 1521 | } |
1522 | ||
1523 | static void tx_bottom(struct r8152 *tp) | |
1524 | { | |
ebc2ec48 | 1525 | int res; |
1526 | ||
b1379d9a | 1527 | do { |
1528 | struct tx_agg *agg; | |
ebc2ec48 | 1529 | |
b1379d9a | 1530 | if (skb_queue_empty(&tp->tx_queue)) |
ebc2ec48 | 1531 | break; |
1532 | ||
b1379d9a | 1533 | agg = r8152_get_tx_agg(tp); |
1534 | if (!agg) | |
ebc2ec48 | 1535 | break; |
ebc2ec48 | 1536 | |
b1379d9a | 1537 | res = r8152_tx_agg_fill(tp, agg); |
1538 | if (res) { | |
05e0f1aa | 1539 | struct net_device *netdev = tp->netdev; |
ebc2ec48 | 1540 | |
b1379d9a | 1541 | if (res == -ENODEV) { |
1542 | netif_device_detach(netdev); | |
1543 | } else { | |
05e0f1aa | 1544 | struct net_device_stats *stats = &netdev->stats; |
1545 | unsigned long flags; | |
1546 | ||
b1379d9a | 1547 | netif_warn(tp, tx_err, netdev, |
1548 | "failed tx_urb %d\n", res); | |
1549 | stats->tx_dropped += agg->skb_num; | |
db8515ef | 1550 | |
b1379d9a | 1551 | spin_lock_irqsave(&tp->tx_lock, flags); |
1552 | list_add_tail(&agg->list, &tp->tx_free); | |
1553 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1554 | } | |
ebc2ec48 | 1555 | } |
b1379d9a | 1556 | } while (res == 0); |
ebc2ec48 | 1557 | } |
1558 | ||
1559 | static void bottom_half(unsigned long data) | |
ac718b69 | 1560 | { |
1561 | struct r8152 *tp; | |
ac718b69 | 1562 | |
ebc2ec48 | 1563 | tp = (struct r8152 *)data; |
1564 | ||
1565 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1566 | return; | |
1567 | ||
1568 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
ac718b69 | 1569 | return; |
ebc2ec48 | 1570 | |
7559fb2f | 1571 | /* When link down, the driver would cancel all bulks. */ |
1572 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 1573 | if (!netif_carrier_ok(tp->netdev)) |
ac718b69 | 1574 | return; |
ebc2ec48 | 1575 | |
1576 | rx_bottom(tp); | |
0c3121fc | 1577 | tx_bottom(tp); |
ebc2ec48 | 1578 | } |
1579 | ||
1580 | static | |
1581 | int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) | |
1582 | { | |
1583 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), | |
1584 | agg->head, rx_buf_sz, | |
1585 | (usb_complete_t)read_bulk_callback, agg); | |
1586 | ||
1587 | return usb_submit_urb(agg->urb, mem_flags); | |
ac718b69 | 1588 | } |
1589 | ||
00a5e360 | 1590 | static void rtl_drop_queued_tx(struct r8152 *tp) |
1591 | { | |
1592 | struct net_device_stats *stats = &tp->netdev->stats; | |
d84130a1 | 1593 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
00a5e360 | 1594 | struct sk_buff *skb; |
1595 | ||
d84130a1 | 1596 | if (skb_queue_empty(tx_queue)) |
1597 | return; | |
1598 | ||
1599 | __skb_queue_head_init(&skb_head); | |
2685d410 | 1600 | spin_lock_bh(&tx_queue->lock); |
d84130a1 | 1601 | skb_queue_splice_init(tx_queue, &skb_head); |
2685d410 | 1602 | spin_unlock_bh(&tx_queue->lock); |
d84130a1 | 1603 | |
1604 | while ((skb = __skb_dequeue(&skb_head))) { | |
00a5e360 | 1605 | dev_kfree_skb(skb); |
1606 | stats->tx_dropped++; | |
1607 | } | |
1608 | } | |
1609 | ||
ac718b69 | 1610 | static void rtl8152_tx_timeout(struct net_device *netdev) |
1611 | { | |
1612 | struct r8152 *tp = netdev_priv(netdev); | |
ebc2ec48 | 1613 | int i; |
1614 | ||
4a8deae2 | 1615 | netif_warn(tp, tx_err, netdev, "Tx timeout\n"); |
ebc2ec48 | 1616 | for (i = 0; i < RTL8152_MAX_TX; i++) |
1617 | usb_unlink_urb(tp->tx_info[i].urb); | |
ac718b69 | 1618 | } |
1619 | ||
1620 | static void rtl8152_set_rx_mode(struct net_device *netdev) | |
1621 | { | |
1622 | struct r8152 *tp = netdev_priv(netdev); | |
1623 | ||
40a82917 | 1624 | if (tp->speed & LINK_STATUS) { |
ac718b69 | 1625 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
40a82917 | 1626 | schedule_delayed_work(&tp->schedule, 0); |
1627 | } | |
ac718b69 | 1628 | } |
1629 | ||
1630 | static void _rtl8152_set_rx_mode(struct net_device *netdev) | |
1631 | { | |
1632 | struct r8152 *tp = netdev_priv(netdev); | |
31787f53 | 1633 | u32 mc_filter[2]; /* Multicast hash filter */ |
1634 | __le32 tmp[2]; | |
ac718b69 | 1635 | u32 ocp_data; |
1636 | ||
ac718b69 | 1637 | clear_bit(RTL8152_SET_RX_MODE, &tp->flags); |
1638 | netif_stop_queue(netdev); | |
1639 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
1640 | ocp_data &= ~RCR_ACPT_ALL; | |
1641 | ocp_data |= RCR_AB | RCR_APM; | |
1642 | ||
1643 | if (netdev->flags & IFF_PROMISC) { | |
1644 | /* Unconditionally log net taps. */ | |
1645 | netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); | |
1646 | ocp_data |= RCR_AM | RCR_AAP; | |
1647 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
1648 | } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || | |
1649 | (netdev->flags & IFF_ALLMULTI)) { | |
1650 | /* Too many to filter perfectly -- accept all multicasts. */ | |
1651 | ocp_data |= RCR_AM; | |
1652 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
1653 | } else { | |
1654 | struct netdev_hw_addr *ha; | |
1655 | ||
1656 | mc_filter[1] = mc_filter[0] = 0; | |
1657 | netdev_for_each_mc_addr(ha, netdev) { | |
1658 | int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
1659 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); | |
1660 | ocp_data |= RCR_AM; | |
1661 | } | |
1662 | } | |
1663 | ||
31787f53 | 1664 | tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); |
1665 | tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); | |
ac718b69 | 1666 | |
31787f53 | 1667 | pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); |
ac718b69 | 1668 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); |
1669 | netif_wake_queue(netdev); | |
ac718b69 | 1670 | } |
1671 | ||
1672 | static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, | |
0c3121fc | 1673 | struct net_device *netdev) |
ac718b69 | 1674 | { |
1675 | struct r8152 *tp = netdev_priv(netdev); | |
ac718b69 | 1676 | |
ebc2ec48 | 1677 | skb_tx_timestamp(skb); |
ac718b69 | 1678 | |
61598788 | 1679 | skb_queue_tail(&tp->tx_queue, skb); |
ebc2ec48 | 1680 | |
0c3121fc | 1681 | if (!list_empty(&tp->tx_free)) { |
1682 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { | |
1683 | set_bit(SCHEDULE_TASKLET, &tp->flags); | |
1684 | schedule_delayed_work(&tp->schedule, 0); | |
1685 | } else { | |
1686 | usb_mark_last_busy(tp->udev); | |
1687 | tasklet_schedule(&tp->tl); | |
1688 | } | |
1689 | } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) | |
dd1b119c | 1690 | netif_stop_queue(netdev); |
1691 | ||
ac718b69 | 1692 | return NETDEV_TX_OK; |
1693 | } | |
1694 | ||
1695 | static void r8152b_reset_packet_filter(struct r8152 *tp) | |
1696 | { | |
1697 | u32 ocp_data; | |
1698 | ||
1699 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); | |
1700 | ocp_data &= ~FMC_FCR_MCU_EN; | |
1701 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
1702 | ocp_data |= FMC_FCR_MCU_EN; | |
1703 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
1704 | } | |
1705 | ||
1706 | static void rtl8152_nic_reset(struct r8152 *tp) | |
1707 | { | |
1708 | int i; | |
1709 | ||
1710 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); | |
1711 | ||
1712 | for (i = 0; i < 1000; i++) { | |
1713 | if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) | |
1714 | break; | |
1715 | udelay(100); | |
1716 | } | |
1717 | } | |
1718 | ||
dd1b119c | 1719 | static void set_tx_qlen(struct r8152 *tp) |
1720 | { | |
1721 | struct net_device *netdev = tp->netdev; | |
1722 | ||
1723 | tp->tx_qlen = rx_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN + | |
1724 | sizeof(struct tx_desc)); | |
1725 | } | |
1726 | ||
ac718b69 | 1727 | static inline u8 rtl8152_get_speed(struct r8152 *tp) |
1728 | { | |
1729 | return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); | |
1730 | } | |
1731 | ||
507605a8 | 1732 | static void rtl_set_eee_plus(struct r8152 *tp) |
ac718b69 | 1733 | { |
ebc2ec48 | 1734 | u32 ocp_data; |
ac718b69 | 1735 | u8 speed; |
1736 | ||
1737 | speed = rtl8152_get_speed(tp); | |
ebc2ec48 | 1738 | if (speed & _10bps) { |
ac718b69 | 1739 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); |
ebc2ec48 | 1740 | ocp_data |= EEEP_CR_EEEP_TX; |
ac718b69 | 1741 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
1742 | } else { | |
1743 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); | |
ebc2ec48 | 1744 | ocp_data &= ~EEEP_CR_EEEP_TX; |
ac718b69 | 1745 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
1746 | } | |
507605a8 | 1747 | } |
1748 | ||
00a5e360 | 1749 | static void rxdy_gated_en(struct r8152 *tp, bool enable) |
1750 | { | |
1751 | u32 ocp_data; | |
1752 | ||
1753 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); | |
1754 | if (enable) | |
1755 | ocp_data |= RXDY_GATED_EN; | |
1756 | else | |
1757 | ocp_data &= ~RXDY_GATED_EN; | |
1758 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); | |
1759 | } | |
1760 | ||
507605a8 | 1761 | static int rtl_enable(struct r8152 *tp) |
1762 | { | |
1763 | u32 ocp_data; | |
1764 | int i, ret; | |
ac718b69 | 1765 | |
1766 | r8152b_reset_packet_filter(tp); | |
1767 | ||
1768 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); | |
1769 | ocp_data |= CR_RE | CR_TE; | |
1770 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); | |
1771 | ||
00a5e360 | 1772 | rxdy_gated_en(tp, false); |
ac718b69 | 1773 | |
ebc2ec48 | 1774 | INIT_LIST_HEAD(&tp->rx_done); |
1775 | ret = 0; | |
1776 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
1777 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
1778 | ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); | |
1779 | } | |
ac718b69 | 1780 | |
ebc2ec48 | 1781 | return ret; |
ac718b69 | 1782 | } |
1783 | ||
507605a8 | 1784 | static int rtl8152_enable(struct r8152 *tp) |
1785 | { | |
1786 | set_tx_qlen(tp); | |
1787 | rtl_set_eee_plus(tp); | |
1788 | ||
1789 | return rtl_enable(tp); | |
1790 | } | |
1791 | ||
43779f8d | 1792 | static void r8153_set_rx_agg(struct r8152 *tp) |
1793 | { | |
1794 | u8 speed; | |
1795 | ||
1796 | speed = rtl8152_get_speed(tp); | |
1797 | if (speed & _1000bps) { | |
1798 | if (tp->udev->speed == USB_SPEED_SUPER) { | |
1799 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, | |
1800 | RX_THR_SUPPER); | |
1801 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, | |
1802 | EARLY_AGG_SUPPER); | |
1803 | } else { | |
1804 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, | |
1805 | RX_THR_HIGH); | |
1806 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, | |
1807 | EARLY_AGG_HIGH); | |
1808 | } | |
1809 | } else { | |
1810 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW); | |
1811 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, | |
1812 | EARLY_AGG_SLOW); | |
1813 | } | |
1814 | } | |
1815 | ||
1816 | static int rtl8153_enable(struct r8152 *tp) | |
1817 | { | |
1818 | set_tx_qlen(tp); | |
1819 | rtl_set_eee_plus(tp); | |
1820 | r8153_set_rx_agg(tp); | |
1821 | ||
1822 | return rtl_enable(tp); | |
1823 | } | |
1824 | ||
ac718b69 | 1825 | static void rtl8152_disable(struct r8152 *tp) |
1826 | { | |
ebc2ec48 | 1827 | u32 ocp_data; |
1828 | int i; | |
ac718b69 | 1829 | |
1830 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
1831 | ocp_data &= ~RCR_ACPT_ALL; | |
1832 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
1833 | ||
00a5e360 | 1834 | rtl_drop_queued_tx(tp); |
ebc2ec48 | 1835 | |
1836 | for (i = 0; i < RTL8152_MAX_TX; i++) | |
1837 | usb_kill_urb(tp->tx_info[i].urb); | |
ac718b69 | 1838 | |
00a5e360 | 1839 | rxdy_gated_en(tp, true); |
ac718b69 | 1840 | |
1841 | for (i = 0; i < 1000; i++) { | |
1842 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
1843 | if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) | |
1844 | break; | |
1845 | mdelay(1); | |
1846 | } | |
1847 | ||
1848 | for (i = 0; i < 1000; i++) { | |
1849 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) | |
1850 | break; | |
1851 | mdelay(1); | |
1852 | } | |
1853 | ||
ebc2ec48 | 1854 | for (i = 0; i < RTL8152_MAX_RX; i++) |
1855 | usb_kill_urb(tp->rx_info[i].urb); | |
ac718b69 | 1856 | |
1857 | rtl8152_nic_reset(tp); | |
1858 | } | |
1859 | ||
00a5e360 | 1860 | static void r8152_power_cut_en(struct r8152 *tp, bool enable) |
1861 | { | |
1862 | u32 ocp_data; | |
1863 | ||
1864 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); | |
1865 | if (enable) | |
1866 | ocp_data |= POWER_CUT; | |
1867 | else | |
1868 | ocp_data &= ~POWER_CUT; | |
1869 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); | |
1870 | ||
1871 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); | |
1872 | ocp_data &= ~RESUME_INDICATE; | |
1873 | ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); | |
00a5e360 | 1874 | } |
1875 | ||
21ff2e89 | 1876 | #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
1877 | ||
1878 | static u32 __rtl_get_wol(struct r8152 *tp) | |
1879 | { | |
1880 | u32 ocp_data; | |
1881 | u32 wolopts = 0; | |
1882 | ||
1883 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
1884 | if (!(ocp_data & LAN_WAKE_EN)) | |
1885 | return 0; | |
1886 | ||
1887 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
1888 | if (ocp_data & LINK_ON_WAKE_EN) | |
1889 | wolopts |= WAKE_PHY; | |
1890 | ||
1891 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
1892 | if (ocp_data & UWF_EN) | |
1893 | wolopts |= WAKE_UCAST; | |
1894 | if (ocp_data & BWF_EN) | |
1895 | wolopts |= WAKE_BCAST; | |
1896 | if (ocp_data & MWF_EN) | |
1897 | wolopts |= WAKE_MCAST; | |
1898 | ||
1899 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
1900 | if (ocp_data & MAGIC_EN) | |
1901 | wolopts |= WAKE_MAGIC; | |
1902 | ||
1903 | return wolopts; | |
1904 | } | |
1905 | ||
1906 | static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) | |
1907 | { | |
1908 | u32 ocp_data; | |
1909 | ||
1910 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
1911 | ||
1912 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
1913 | ocp_data &= ~LINK_ON_WAKE_EN; | |
1914 | if (wolopts & WAKE_PHY) | |
1915 | ocp_data |= LINK_ON_WAKE_EN; | |
1916 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
1917 | ||
1918 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
1919 | ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN); | |
1920 | if (wolopts & WAKE_UCAST) | |
1921 | ocp_data |= UWF_EN; | |
1922 | if (wolopts & WAKE_BCAST) | |
1923 | ocp_data |= BWF_EN; | |
1924 | if (wolopts & WAKE_MCAST) | |
1925 | ocp_data |= MWF_EN; | |
1926 | if (wolopts & WAKE_ANY) | |
1927 | ocp_data |= LAN_WAKE_EN; | |
1928 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); | |
1929 | ||
1930 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
1931 | ||
1932 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
1933 | ocp_data &= ~MAGIC_EN; | |
1934 | if (wolopts & WAKE_MAGIC) | |
1935 | ocp_data |= MAGIC_EN; | |
1936 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); | |
1937 | ||
1938 | if (wolopts & WAKE_ANY) | |
1939 | device_set_wakeup_enable(&tp->udev->dev, true); | |
1940 | else | |
1941 | device_set_wakeup_enable(&tp->udev->dev, false); | |
1942 | } | |
1943 | ||
9a4be1bd | 1944 | static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) |
1945 | { | |
1946 | if (enable) { | |
1947 | u32 ocp_data; | |
1948 | ||
1949 | __rtl_set_wol(tp, WAKE_ANY); | |
1950 | ||
1951 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
1952 | ||
1953 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
1954 | ocp_data |= LINK_OFF_WAKE_EN; | |
1955 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
1956 | ||
1957 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
1958 | } else { | |
1959 | __rtl_set_wol(tp, tp->saved_wolopts); | |
1960 | } | |
1961 | } | |
1962 | ||
aa66a5f1 | 1963 | static void rtl_phy_reset(struct r8152 *tp) |
1964 | { | |
1965 | u16 data; | |
1966 | int i; | |
1967 | ||
1968 | clear_bit(PHY_RESET, &tp->flags); | |
1969 | ||
1970 | data = r8152_mdio_read(tp, MII_BMCR); | |
1971 | ||
1972 | /* don't reset again before the previous one complete */ | |
1973 | if (data & BMCR_RESET) | |
1974 | return; | |
1975 | ||
1976 | data |= BMCR_RESET; | |
1977 | r8152_mdio_write(tp, MII_BMCR, data); | |
1978 | ||
1979 | for (i = 0; i < 50; i++) { | |
1980 | msleep(20); | |
1981 | if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) | |
1982 | break; | |
1983 | } | |
1984 | } | |
1985 | ||
4349968a | 1986 | static void rtl_clear_bp(struct r8152 *tp) |
1987 | { | |
1988 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0); | |
1989 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0); | |
1990 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0); | |
1991 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0); | |
1992 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0); | |
1993 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0); | |
1994 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0); | |
1995 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0); | |
1996 | mdelay(3); | |
1997 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0); | |
1998 | ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0); | |
1999 | } | |
2000 | ||
2001 | static void r8153_clear_bp(struct r8152 *tp) | |
2002 | { | |
2003 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0); | |
2004 | ocp_write_byte(tp, MCU_TYPE_USB, USB_BP_EN, 0); | |
2005 | rtl_clear_bp(tp); | |
2006 | } | |
2007 | ||
2008 | static void r8153_teredo_off(struct r8152 *tp) | |
2009 | { | |
2010 | u32 ocp_data; | |
2011 | ||
2012 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); | |
2013 | ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN); | |
2014 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
2015 | ||
2016 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); | |
2017 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); | |
2018 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); | |
2019 | } | |
2020 | ||
2021 | static void r8152b_disable_aldps(struct r8152 *tp) | |
2022 | { | |
2023 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE); | |
2024 | msleep(20); | |
2025 | } | |
2026 | ||
2027 | static inline void r8152b_enable_aldps(struct r8152 *tp) | |
2028 | { | |
2029 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | | |
2030 | LINKENA | DIS_SDSAVE); | |
2031 | } | |
2032 | ||
2033 | static void r8152b_hw_phy_cfg(struct r8152 *tp) | |
2034 | { | |
f0cbe0ac | 2035 | u16 data; |
2036 | ||
2037 | data = r8152_mdio_read(tp, MII_BMCR); | |
2038 | if (data & BMCR_PDOWN) { | |
2039 | data &= ~BMCR_PDOWN; | |
2040 | r8152_mdio_write(tp, MII_BMCR, data); | |
2041 | } | |
2042 | ||
4349968a | 2043 | r8152b_disable_aldps(tp); |
7e9da481 | 2044 | |
2045 | rtl_clear_bp(tp); | |
2046 | ||
2047 | r8152b_enable_aldps(tp); | |
aa66a5f1 | 2048 | set_bit(PHY_RESET, &tp->flags); |
4349968a | 2049 | } |
2050 | ||
ac718b69 | 2051 | static void r8152b_exit_oob(struct r8152 *tp) |
2052 | { | |
db8515ef | 2053 | u32 ocp_data; |
2054 | int i; | |
ac718b69 | 2055 | |
2056 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2057 | ocp_data &= ~RCR_ACPT_ALL; | |
2058 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2059 | ||
00a5e360 | 2060 | rxdy_gated_en(tp, true); |
da9bd117 | 2061 | r8153_teredo_off(tp); |
7e9da481 | 2062 | r8152b_hw_phy_cfg(tp); |
ac718b69 | 2063 | |
2064 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2065 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); | |
2066 | ||
2067 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2068 | ocp_data &= ~NOW_IS_OOB; | |
2069 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2070 | ||
2071 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2072 | ocp_data &= ~MCU_BORW_EN; | |
2073 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2074 | ||
2075 | for (i = 0; i < 1000; i++) { | |
2076 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2077 | if (ocp_data & LINK_LIST_READY) | |
2078 | break; | |
2079 | mdelay(1); | |
2080 | } | |
2081 | ||
2082 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2083 | ocp_data |= RE_INIT_LL; | |
2084 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2085 | ||
2086 | for (i = 0; i < 1000; i++) { | |
2087 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2088 | if (ocp_data & LINK_LIST_READY) | |
2089 | break; | |
2090 | mdelay(1); | |
2091 | } | |
2092 | ||
2093 | rtl8152_nic_reset(tp); | |
2094 | ||
2095 | /* rx share fifo credit full threshold */ | |
2096 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
2097 | ||
2098 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT); | |
2099 | ocp_data &= STAT_SPEED_MASK; | |
2100 | if (ocp_data == STAT_SPEED_FULL) { | |
2101 | /* rx share fifo credit near full threshold */ | |
2102 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
2103 | RXFIFO_THR2_FULL); | |
2104 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
2105 | RXFIFO_THR3_FULL); | |
2106 | } else { | |
2107 | /* rx share fifo credit near full threshold */ | |
2108 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
2109 | RXFIFO_THR2_HIGH); | |
2110 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
2111 | RXFIFO_THR3_HIGH); | |
2112 | } | |
2113 | ||
2114 | /* TX share fifo free credit full threshold */ | |
2115 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); | |
2116 | ||
2117 | ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); | |
8e1f51bd | 2118 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); |
ac718b69 | 2119 | ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, |
2120 | TEST_MODE_DISABLE | TX_SIZE_ADJUST1); | |
2121 | ||
2122 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
2123 | ocp_data &= ~CPCR_RX_VLAN; | |
2124 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2125 | ||
2126 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2127 | ||
2128 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
2129 | ocp_data |= TCR0_AUTO_FIFO; | |
2130 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
2131 | } | |
2132 | ||
2133 | static void r8152b_enter_oob(struct r8152 *tp) | |
2134 | { | |
45f4a19f | 2135 | u32 ocp_data; |
2136 | int i; | |
ac718b69 | 2137 | |
2138 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2139 | ocp_data &= ~NOW_IS_OOB; | |
2140 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2141 | ||
2142 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); | |
2143 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); | |
2144 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); | |
2145 | ||
2146 | rtl8152_disable(tp); | |
2147 | ||
2148 | for (i = 0; i < 1000; i++) { | |
2149 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2150 | if (ocp_data & LINK_LIST_READY) | |
2151 | break; | |
2152 | mdelay(1); | |
2153 | } | |
2154 | ||
2155 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2156 | ocp_data |= RE_INIT_LL; | |
2157 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2158 | ||
2159 | for (i = 0; i < 1000; i++) { | |
2160 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2161 | if (ocp_data & LINK_LIST_READY) | |
2162 | break; | |
2163 | mdelay(1); | |
2164 | } | |
2165 | ||
2166 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2167 | ||
ac718b69 | 2168 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); |
2169 | ocp_data |= CPCR_RX_VLAN; | |
2170 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2171 | ||
2172 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
2173 | ocp_data |= ALDPS_PROXY_MODE; | |
2174 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
2175 | ||
2176 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2177 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
2178 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2179 | ||
00a5e360 | 2180 | rxdy_gated_en(tp, false); |
ac718b69 | 2181 | |
2182 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2183 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
2184 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2185 | } | |
2186 | ||
43779f8d | 2187 | static void r8153_hw_phy_cfg(struct r8152 *tp) |
2188 | { | |
2189 | u32 ocp_data; | |
2190 | u16 data; | |
2191 | ||
2192 | ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); | |
f0cbe0ac | 2193 | data = r8152_mdio_read(tp, MII_BMCR); |
2194 | if (data & BMCR_PDOWN) { | |
2195 | data &= ~BMCR_PDOWN; | |
2196 | r8152_mdio_write(tp, MII_BMCR, data); | |
2197 | } | |
43779f8d | 2198 | |
7e9da481 | 2199 | r8153_clear_bp(tp); |
2200 | ||
43779f8d | 2201 | if (tp->version == RTL_VER_03) { |
2202 | data = ocp_reg_read(tp, OCP_EEE_CFG); | |
2203 | data &= ~CTAP_SHORT_EN; | |
2204 | ocp_reg_write(tp, OCP_EEE_CFG, data); | |
2205 | } | |
2206 | ||
2207 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2208 | data |= EEE_CLKDIV_EN; | |
2209 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2210 | ||
2211 | data = ocp_reg_read(tp, OCP_DOWN_SPEED); | |
2212 | data |= EN_10M_BGOFF; | |
2213 | ocp_reg_write(tp, OCP_DOWN_SPEED, data); | |
2214 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2215 | data |= EN_10M_PLLOFF; | |
2216 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2217 | data = sram_read(tp, SRAM_IMPEDANCE); | |
2218 | data &= ~RX_DRIVING_MASK; | |
2219 | sram_write(tp, SRAM_IMPEDANCE, data); | |
2220 | ||
2221 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
2222 | ocp_data |= PFM_PWM_SWITCH; | |
2223 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
2224 | ||
2225 | data = sram_read(tp, SRAM_LPF_CFG); | |
2226 | data |= LPF_AUTO_TUNE; | |
2227 | sram_write(tp, SRAM_LPF_CFG, data); | |
2228 | ||
2229 | data = sram_read(tp, SRAM_10M_AMP1); | |
2230 | data |= GDAC_IB_UPALL; | |
2231 | sram_write(tp, SRAM_10M_AMP1, data); | |
2232 | data = sram_read(tp, SRAM_10M_AMP2); | |
2233 | data |= AMP_DN; | |
2234 | sram_write(tp, SRAM_10M_AMP2, data); | |
aa66a5f1 | 2235 | |
2236 | set_bit(PHY_RESET, &tp->flags); | |
43779f8d | 2237 | } |
2238 | ||
b9702723 | 2239 | static void r8153_u1u2en(struct r8152 *tp, bool enable) |
43779f8d | 2240 | { |
2241 | u8 u1u2[8]; | |
2242 | ||
2243 | if (enable) | |
2244 | memset(u1u2, 0xff, sizeof(u1u2)); | |
2245 | else | |
2246 | memset(u1u2, 0x00, sizeof(u1u2)); | |
2247 | ||
2248 | usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); | |
2249 | } | |
2250 | ||
b9702723 | 2251 | static void r8153_u2p3en(struct r8152 *tp, bool enable) |
43779f8d | 2252 | { |
2253 | u32 ocp_data; | |
2254 | ||
2255 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); | |
2256 | if (enable) | |
2257 | ocp_data |= U2P3_ENABLE; | |
2258 | else | |
2259 | ocp_data &= ~U2P3_ENABLE; | |
2260 | ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); | |
2261 | } | |
2262 | ||
b9702723 | 2263 | static void r8153_power_cut_en(struct r8152 *tp, bool enable) |
43779f8d | 2264 | { |
2265 | u32 ocp_data; | |
2266 | ||
2267 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); | |
2268 | if (enable) | |
2269 | ocp_data |= PWR_EN | PHASE2_EN; | |
2270 | else | |
2271 | ocp_data &= ~(PWR_EN | PHASE2_EN); | |
2272 | ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
2273 | ||
2274 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
2275 | ocp_data &= ~PCUT_STATUS; | |
2276 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); | |
2277 | } | |
2278 | ||
43779f8d | 2279 | static void r8153_first_init(struct r8152 *tp) |
2280 | { | |
2281 | u32 ocp_data; | |
2282 | int i; | |
2283 | ||
00a5e360 | 2284 | rxdy_gated_en(tp, true); |
43779f8d | 2285 | r8153_teredo_off(tp); |
2286 | ||
2287 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2288 | ocp_data &= ~RCR_ACPT_ALL; | |
2289 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2290 | ||
2291 | r8153_hw_phy_cfg(tp); | |
2292 | ||
2293 | rtl8152_nic_reset(tp); | |
2294 | ||
2295 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2296 | ocp_data &= ~NOW_IS_OOB; | |
2297 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2298 | ||
2299 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2300 | ocp_data &= ~MCU_BORW_EN; | |
2301 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2302 | ||
2303 | for (i = 0; i < 1000; i++) { | |
2304 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2305 | if (ocp_data & LINK_LIST_READY) | |
2306 | break; | |
2307 | mdelay(1); | |
2308 | } | |
2309 | ||
2310 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2311 | ocp_data |= RE_INIT_LL; | |
2312 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2313 | ||
2314 | for (i = 0; i < 1000; i++) { | |
2315 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2316 | if (ocp_data & LINK_LIST_READY) | |
2317 | break; | |
2318 | mdelay(1); | |
2319 | } | |
2320 | ||
2321 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
2322 | ocp_data &= ~CPCR_RX_VLAN; | |
2323 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2324 | ||
2325 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2326 | ||
2327 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
2328 | ocp_data |= TCR0_AUTO_FIFO; | |
2329 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
2330 | ||
2331 | rtl8152_nic_reset(tp); | |
2332 | ||
2333 | /* rx share fifo credit full threshold */ | |
2334 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
2335 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); | |
2336 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); | |
2337 | /* TX share fifo free credit full threshold */ | |
2338 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); | |
2339 | ||
9629e3c0 | 2340 | /* rx aggregation */ |
43779f8d | 2341 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
2342 | ocp_data &= ~RX_AGG_DISABLE; | |
2343 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); | |
2344 | } | |
2345 | ||
2346 | static void r8153_enter_oob(struct r8152 *tp) | |
2347 | { | |
2348 | u32 ocp_data; | |
2349 | int i; | |
2350 | ||
2351 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2352 | ocp_data &= ~NOW_IS_OOB; | |
2353 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2354 | ||
2355 | rtl8152_disable(tp); | |
2356 | ||
2357 | for (i = 0; i < 1000; i++) { | |
2358 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2359 | if (ocp_data & LINK_LIST_READY) | |
2360 | break; | |
2361 | mdelay(1); | |
2362 | } | |
2363 | ||
2364 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2365 | ocp_data |= RE_INIT_LL; | |
2366 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2367 | ||
2368 | for (i = 0; i < 1000; i++) { | |
2369 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2370 | if (ocp_data & LINK_LIST_READY) | |
2371 | break; | |
2372 | mdelay(1); | |
2373 | } | |
2374 | ||
2375 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2376 | ||
43779f8d | 2377 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); |
2378 | ocp_data &= ~TEREDO_WAKE_MASK; | |
2379 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
2380 | ||
2381 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
2382 | ocp_data |= CPCR_RX_VLAN; | |
2383 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2384 | ||
2385 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
2386 | ocp_data |= ALDPS_PROXY_MODE; | |
2387 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
2388 | ||
2389 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2390 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
2391 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2392 | ||
00a5e360 | 2393 | rxdy_gated_en(tp, false); |
43779f8d | 2394 | |
2395 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2396 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
2397 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2398 | } | |
2399 | ||
2400 | static void r8153_disable_aldps(struct r8152 *tp) | |
2401 | { | |
2402 | u16 data; | |
2403 | ||
2404 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2405 | data &= ~EN_ALDPS; | |
2406 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2407 | msleep(20); | |
2408 | } | |
2409 | ||
2410 | static void r8153_enable_aldps(struct r8152 *tp) | |
2411 | { | |
2412 | u16 data; | |
2413 | ||
2414 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2415 | data |= EN_ALDPS; | |
2416 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2417 | } | |
2418 | ||
ac718b69 | 2419 | static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) |
2420 | { | |
43779f8d | 2421 | u16 bmcr, anar, gbcr; |
ac718b69 | 2422 | int ret = 0; |
2423 | ||
2424 | cancel_delayed_work_sync(&tp->schedule); | |
2425 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
2426 | anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | | |
2427 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
43779f8d | 2428 | if (tp->mii.supports_gmii) { |
2429 | gbcr = r8152_mdio_read(tp, MII_CTRL1000); | |
2430 | gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); | |
2431 | } else { | |
2432 | gbcr = 0; | |
2433 | } | |
ac718b69 | 2434 | |
2435 | if (autoneg == AUTONEG_DISABLE) { | |
2436 | if (speed == SPEED_10) { | |
2437 | bmcr = 0; | |
2438 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2439 | } else if (speed == SPEED_100) { | |
2440 | bmcr = BMCR_SPEED100; | |
2441 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
43779f8d | 2442 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
2443 | bmcr = BMCR_SPEED1000; | |
2444 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
ac718b69 | 2445 | } else { |
2446 | ret = -EINVAL; | |
2447 | goto out; | |
2448 | } | |
2449 | ||
2450 | if (duplex == DUPLEX_FULL) | |
2451 | bmcr |= BMCR_FULLDPLX; | |
2452 | } else { | |
2453 | if (speed == SPEED_10) { | |
2454 | if (duplex == DUPLEX_FULL) | |
2455 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2456 | else | |
2457 | anar |= ADVERTISE_10HALF; | |
2458 | } else if (speed == SPEED_100) { | |
2459 | if (duplex == DUPLEX_FULL) { | |
2460 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2461 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
2462 | } else { | |
2463 | anar |= ADVERTISE_10HALF; | |
2464 | anar |= ADVERTISE_100HALF; | |
2465 | } | |
43779f8d | 2466 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
2467 | if (duplex == DUPLEX_FULL) { | |
2468 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2469 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
2470 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
2471 | } else { | |
2472 | anar |= ADVERTISE_10HALF; | |
2473 | anar |= ADVERTISE_100HALF; | |
2474 | gbcr |= ADVERTISE_1000HALF; | |
2475 | } | |
ac718b69 | 2476 | } else { |
2477 | ret = -EINVAL; | |
2478 | goto out; | |
2479 | } | |
2480 | ||
2481 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; | |
2482 | } | |
2483 | ||
aa66a5f1 | 2484 | if (test_bit(PHY_RESET, &tp->flags)) |
2485 | bmcr |= BMCR_RESET; | |
2486 | ||
43779f8d | 2487 | if (tp->mii.supports_gmii) |
2488 | r8152_mdio_write(tp, MII_CTRL1000, gbcr); | |
2489 | ||
ac718b69 | 2490 | r8152_mdio_write(tp, MII_ADVERTISE, anar); |
2491 | r8152_mdio_write(tp, MII_BMCR, bmcr); | |
2492 | ||
aa66a5f1 | 2493 | if (test_bit(PHY_RESET, &tp->flags)) { |
2494 | int i; | |
2495 | ||
2496 | clear_bit(PHY_RESET, &tp->flags); | |
2497 | for (i = 0; i < 50; i++) { | |
2498 | msleep(20); | |
2499 | if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) | |
2500 | break; | |
2501 | } | |
2502 | } | |
2503 | ||
ac718b69 | 2504 | out: |
ac718b69 | 2505 | |
2506 | return ret; | |
2507 | } | |
2508 | ||
2509 | static void rtl8152_down(struct r8152 *tp) | |
2510 | { | |
00a5e360 | 2511 | r8152_power_cut_en(tp, false); |
ac718b69 | 2512 | r8152b_disable_aldps(tp); |
2513 | r8152b_enter_oob(tp); | |
2514 | r8152b_enable_aldps(tp); | |
2515 | } | |
2516 | ||
43779f8d | 2517 | static void rtl8153_down(struct r8152 *tp) |
2518 | { | |
b9702723 | 2519 | r8153_u1u2en(tp, false); |
2520 | r8153_power_cut_en(tp, false); | |
43779f8d | 2521 | r8153_disable_aldps(tp); |
2522 | r8153_enter_oob(tp); | |
2523 | r8153_enable_aldps(tp); | |
2524 | } | |
2525 | ||
ac718b69 | 2526 | static void set_carrier(struct r8152 *tp) |
2527 | { | |
2528 | struct net_device *netdev = tp->netdev; | |
2529 | u8 speed; | |
2530 | ||
40a82917 | 2531 | clear_bit(RTL8152_LINK_CHG, &tp->flags); |
ac718b69 | 2532 | speed = rtl8152_get_speed(tp); |
2533 | ||
2534 | if (speed & LINK_STATUS) { | |
2535 | if (!(tp->speed & LINK_STATUS)) { | |
c81229c9 | 2536 | tp->rtl_ops.enable(tp); |
ac718b69 | 2537 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
2538 | netif_carrier_on(netdev); | |
2539 | } | |
2540 | } else { | |
2541 | if (tp->speed & LINK_STATUS) { | |
2542 | netif_carrier_off(netdev); | |
ebc2ec48 | 2543 | tasklet_disable(&tp->tl); |
c81229c9 | 2544 | tp->rtl_ops.disable(tp); |
ebc2ec48 | 2545 | tasklet_enable(&tp->tl); |
ac718b69 | 2546 | } |
2547 | } | |
2548 | tp->speed = speed; | |
2549 | } | |
2550 | ||
2551 | static void rtl_work_func_t(struct work_struct *work) | |
2552 | { | |
2553 | struct r8152 *tp = container_of(work, struct r8152, schedule.work); | |
2554 | ||
9a4be1bd | 2555 | if (usb_autopm_get_interface(tp->intf) < 0) |
2556 | return; | |
2557 | ||
ac718b69 | 2558 | if (!test_bit(WORK_ENABLE, &tp->flags)) |
2559 | goto out1; | |
2560 | ||
2561 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
2562 | goto out1; | |
2563 | ||
40a82917 | 2564 | if (test_bit(RTL8152_LINK_CHG, &tp->flags)) |
2565 | set_carrier(tp); | |
ac718b69 | 2566 | |
2567 | if (test_bit(RTL8152_SET_RX_MODE, &tp->flags)) | |
2568 | _rtl8152_set_rx_mode(tp->netdev); | |
2569 | ||
0c3121fc | 2570 | if (test_bit(SCHEDULE_TASKLET, &tp->flags) && |
2571 | (tp->speed & LINK_STATUS)) { | |
2572 | clear_bit(SCHEDULE_TASKLET, &tp->flags); | |
2573 | tasklet_schedule(&tp->tl); | |
2574 | } | |
aa66a5f1 | 2575 | |
2576 | if (test_bit(PHY_RESET, &tp->flags)) | |
2577 | rtl_phy_reset(tp); | |
2578 | ||
ac718b69 | 2579 | out1: |
9a4be1bd | 2580 | usb_autopm_put_interface(tp->intf); |
ac718b69 | 2581 | } |
2582 | ||
2583 | static int rtl8152_open(struct net_device *netdev) | |
2584 | { | |
2585 | struct r8152 *tp = netdev_priv(netdev); | |
2586 | int res = 0; | |
2587 | ||
7e9da481 | 2588 | res = alloc_all_mem(tp); |
2589 | if (res) | |
2590 | goto out; | |
2591 | ||
9a4be1bd | 2592 | res = usb_autopm_get_interface(tp->intf); |
2593 | if (res < 0) { | |
2594 | free_all_mem(tp); | |
2595 | goto out; | |
2596 | } | |
2597 | ||
2598 | /* The WORK_ENABLE may be set when autoresume occurs */ | |
2599 | if (test_bit(WORK_ENABLE, &tp->flags)) { | |
2600 | clear_bit(WORK_ENABLE, &tp->flags); | |
2601 | usb_kill_urb(tp->intr_urb); | |
2602 | cancel_delayed_work_sync(&tp->schedule); | |
2603 | if (tp->speed & LINK_STATUS) | |
2604 | tp->rtl_ops.disable(tp); | |
2605 | } | |
2606 | ||
7e9da481 | 2607 | tp->rtl_ops.up(tp); |
2608 | ||
3d55f44f | 2609 | rtl8152_set_speed(tp, AUTONEG_ENABLE, |
2610 | tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, | |
2611 | DUPLEX_FULL); | |
2612 | tp->speed = 0; | |
2613 | netif_carrier_off(netdev); | |
2614 | netif_start_queue(netdev); | |
2615 | set_bit(WORK_ENABLE, &tp->flags); | |
db8515ef | 2616 | |
40a82917 | 2617 | res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
2618 | if (res) { | |
2619 | if (res == -ENODEV) | |
2620 | netif_device_detach(tp->netdev); | |
4a8deae2 HW |
2621 | netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", |
2622 | res); | |
7e9da481 | 2623 | free_all_mem(tp); |
ac718b69 | 2624 | } |
2625 | ||
9a4be1bd | 2626 | usb_autopm_put_interface(tp->intf); |
ac718b69 | 2627 | |
7e9da481 | 2628 | out: |
ac718b69 | 2629 | return res; |
2630 | } | |
2631 | ||
2632 | static int rtl8152_close(struct net_device *netdev) | |
2633 | { | |
2634 | struct r8152 *tp = netdev_priv(netdev); | |
2635 | int res = 0; | |
2636 | ||
2637 | clear_bit(WORK_ENABLE, &tp->flags); | |
3d55f44f | 2638 | usb_kill_urb(tp->intr_urb); |
ac718b69 | 2639 | cancel_delayed_work_sync(&tp->schedule); |
2640 | netif_stop_queue(netdev); | |
9a4be1bd | 2641 | |
2642 | res = usb_autopm_get_interface(tp->intf); | |
2643 | if (res < 0) { | |
2644 | rtl_drop_queued_tx(tp); | |
2645 | } else { | |
2646 | /* | |
2647 | * The autosuspend may have been enabled and wouldn't | |
2648 | * be disable when autoresume occurs, because the | |
2649 | * netif_running() would be false. | |
2650 | */ | |
2651 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { | |
2652 | rtl_runtime_suspend_enable(tp, false); | |
2653 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
2654 | } | |
2655 | ||
2656 | tasklet_disable(&tp->tl); | |
2657 | tp->rtl_ops.down(tp); | |
2658 | tasklet_enable(&tp->tl); | |
2659 | usb_autopm_put_interface(tp->intf); | |
2660 | } | |
ac718b69 | 2661 | |
7e9da481 | 2662 | free_all_mem(tp); |
2663 | ||
ac718b69 | 2664 | return res; |
2665 | } | |
2666 | ||
ac718b69 | 2667 | static void r8152b_enable_eee(struct r8152 *tp) |
2668 | { | |
45f4a19f | 2669 | u32 ocp_data; |
ac718b69 | 2670 | |
2671 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
2672 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
2673 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); | |
2674 | ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN | | |
2675 | EEE_10_CAP | EEE_NWAY_EN | | |
2676 | TX_QUIET_EN | RX_QUIET_EN | | |
2677 | SDRISETIME | RG_RXLPI_MSK_HFDUP | | |
2678 | SDFALLTIME); | |
2679 | ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN | | |
2680 | RG_LDVQUIET_EN | RG_CKRSEL | | |
2681 | RG_EEEPRG_EN); | |
2682 | ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH); | |
2683 | ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR); | |
2684 | ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR); | |
2685 | ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR); | |
2686 | ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA); | |
2687 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); | |
2688 | } | |
2689 | ||
43779f8d | 2690 | static void r8153_enable_eee(struct r8152 *tp) |
2691 | { | |
2692 | u32 ocp_data; | |
2693 | u16 data; | |
2694 | ||
2695 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
2696 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
2697 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); | |
2698 | data = ocp_reg_read(tp, OCP_EEE_CFG); | |
2699 | data |= EEE10_EN; | |
2700 | ocp_reg_write(tp, OCP_EEE_CFG, data); | |
2701 | data = ocp_reg_read(tp, OCP_EEE_CFG2); | |
2702 | data |= MY1000_EEE | MY100_EEE; | |
2703 | ocp_reg_write(tp, OCP_EEE_CFG2, data); | |
2704 | } | |
2705 | ||
ac718b69 | 2706 | static void r8152b_enable_fc(struct r8152 *tp) |
2707 | { | |
2708 | u16 anar; | |
2709 | ||
2710 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
2711 | anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
2712 | r8152_mdio_write(tp, MII_ADVERTISE, anar); | |
2713 | } | |
2714 | ||
ac718b69 | 2715 | static void r8152b_init(struct r8152 *tp) |
2716 | { | |
ebc2ec48 | 2717 | u32 ocp_data; |
ac718b69 | 2718 | |
ac718b69 | 2719 | if (tp->version == RTL_VER_01) { |
2720 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); | |
2721 | ocp_data &= ~LED_MODE_MASK; | |
2722 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
2723 | } | |
2724 | ||
00a5e360 | 2725 | r8152_power_cut_en(tp, false); |
ac718b69 | 2726 | |
ac718b69 | 2727 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); |
2728 | ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; | |
2729 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
2730 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); | |
2731 | ocp_data &= ~MCU_CLK_RATIO_MASK; | |
2732 | ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; | |
2733 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); | |
2734 | ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | | |
2735 | SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; | |
2736 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); | |
2737 | ||
2738 | r8152b_enable_eee(tp); | |
2739 | r8152b_enable_aldps(tp); | |
2740 | r8152b_enable_fc(tp); | |
2741 | ||
ebc2ec48 | 2742 | /* enable rx aggregation */ |
ac718b69 | 2743 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
ebc2ec48 | 2744 | ocp_data &= ~RX_AGG_DISABLE; |
ac718b69 | 2745 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); |
2746 | } | |
2747 | ||
43779f8d | 2748 | static void r8153_init(struct r8152 *tp) |
2749 | { | |
2750 | u32 ocp_data; | |
2751 | int i; | |
2752 | ||
b9702723 | 2753 | r8153_u1u2en(tp, false); |
43779f8d | 2754 | |
2755 | for (i = 0; i < 500; i++) { | |
2756 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & | |
2757 | AUTOLOAD_DONE) | |
2758 | break; | |
2759 | msleep(20); | |
2760 | } | |
2761 | ||
2762 | for (i = 0; i < 500; i++) { | |
2763 | ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK; | |
2764 | if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN) | |
2765 | break; | |
2766 | msleep(20); | |
2767 | } | |
2768 | ||
b9702723 | 2769 | r8153_u2p3en(tp, false); |
43779f8d | 2770 | |
2771 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); | |
2772 | ocp_data &= ~TIMER11_EN; | |
2773 | ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); | |
2774 | ||
43779f8d | 2775 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); |
2776 | ocp_data &= ~LED_MODE_MASK; | |
2777 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
2778 | ||
2779 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL); | |
2780 | ocp_data &= ~LPM_TIMER_MASK; | |
2781 | if (tp->udev->speed == USB_SPEED_SUPER) | |
2782 | ocp_data |= LPM_TIMER_500US; | |
2783 | else | |
2784 | ocp_data |= LPM_TIMER_500MS; | |
2785 | ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); | |
2786 | ||
2787 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); | |
2788 | ocp_data &= ~SEN_VAL_MASK; | |
2789 | ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; | |
2790 | ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); | |
2791 | ||
b9702723 | 2792 | r8153_power_cut_en(tp, false); |
2793 | r8153_u1u2en(tp, true); | |
43779f8d | 2794 | |
43779f8d | 2795 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO); |
2796 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO); | |
2797 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, | |
2798 | PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | | |
2799 | U1U2_SPDWN_EN | L1_SPDWN_EN); | |
2800 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, | |
2801 | PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | | |
2802 | TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN | | |
2803 | EEE_SPDWN_EN); | |
2804 | ||
2805 | r8153_enable_eee(tp); | |
2806 | r8153_enable_aldps(tp); | |
2807 | r8152b_enable_fc(tp); | |
43779f8d | 2808 | } |
2809 | ||
ac718b69 | 2810 | static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) |
2811 | { | |
2812 | struct r8152 *tp = usb_get_intfdata(intf); | |
2813 | ||
9a4be1bd | 2814 | if (PMSG_IS_AUTO(message)) |
2815 | set_bit(SELECTIVE_SUSPEND, &tp->flags); | |
2816 | else | |
2817 | netif_device_detach(tp->netdev); | |
ac718b69 | 2818 | |
2819 | if (netif_running(tp->netdev)) { | |
2820 | clear_bit(WORK_ENABLE, &tp->flags); | |
40a82917 | 2821 | usb_kill_urb(tp->intr_urb); |
ac718b69 | 2822 | cancel_delayed_work_sync(&tp->schedule); |
9a4be1bd | 2823 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
2824 | rtl_runtime_suspend_enable(tp, true); | |
2825 | } else { | |
2826 | tasklet_disable(&tp->tl); | |
2827 | tp->rtl_ops.down(tp); | |
2828 | tasklet_enable(&tp->tl); | |
2829 | } | |
ac718b69 | 2830 | } |
2831 | ||
ac718b69 | 2832 | return 0; |
2833 | } | |
2834 | ||
2835 | static int rtl8152_resume(struct usb_interface *intf) | |
2836 | { | |
2837 | struct r8152 *tp = usb_get_intfdata(intf); | |
2838 | ||
9a4be1bd | 2839 | if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
2840 | tp->rtl_ops.init(tp); | |
2841 | netif_device_attach(tp->netdev); | |
2842 | } | |
2843 | ||
ac718b69 | 2844 | if (netif_running(tp->netdev)) { |
9a4be1bd | 2845 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
2846 | rtl_runtime_suspend_enable(tp, false); | |
2847 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
2848 | if (tp->speed & LINK_STATUS) | |
2849 | tp->rtl_ops.disable(tp); | |
2850 | } else { | |
2851 | tp->rtl_ops.up(tp); | |
2852 | rtl8152_set_speed(tp, AUTONEG_ENABLE, | |
43779f8d | 2853 | tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, |
2854 | DUPLEX_FULL); | |
9a4be1bd | 2855 | } |
40a82917 | 2856 | tp->speed = 0; |
2857 | netif_carrier_off(tp->netdev); | |
ac718b69 | 2858 | set_bit(WORK_ENABLE, &tp->flags); |
40a82917 | 2859 | usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
ac718b69 | 2860 | } |
2861 | ||
2862 | return 0; | |
2863 | } | |
2864 | ||
21ff2e89 | 2865 | static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
2866 | { | |
2867 | struct r8152 *tp = netdev_priv(dev); | |
2868 | ||
9a4be1bd | 2869 | if (usb_autopm_get_interface(tp->intf) < 0) |
2870 | return; | |
2871 | ||
21ff2e89 | 2872 | wol->supported = WAKE_ANY; |
2873 | wol->wolopts = __rtl_get_wol(tp); | |
9a4be1bd | 2874 | |
2875 | usb_autopm_put_interface(tp->intf); | |
21ff2e89 | 2876 | } |
2877 | ||
2878 | static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
2879 | { | |
2880 | struct r8152 *tp = netdev_priv(dev); | |
9a4be1bd | 2881 | int ret; |
2882 | ||
2883 | ret = usb_autopm_get_interface(tp->intf); | |
2884 | if (ret < 0) | |
2885 | goto out_set_wol; | |
21ff2e89 | 2886 | |
2887 | __rtl_set_wol(tp, wol->wolopts); | |
2888 | tp->saved_wolopts = wol->wolopts & WAKE_ANY; | |
2889 | ||
9a4be1bd | 2890 | usb_autopm_put_interface(tp->intf); |
2891 | ||
2892 | out_set_wol: | |
2893 | return ret; | |
21ff2e89 | 2894 | } |
2895 | ||
a5ec27c1 | 2896 | static u32 rtl8152_get_msglevel(struct net_device *dev) |
2897 | { | |
2898 | struct r8152 *tp = netdev_priv(dev); | |
2899 | ||
2900 | return tp->msg_enable; | |
2901 | } | |
2902 | ||
2903 | static void rtl8152_set_msglevel(struct net_device *dev, u32 value) | |
2904 | { | |
2905 | struct r8152 *tp = netdev_priv(dev); | |
2906 | ||
2907 | tp->msg_enable = value; | |
2908 | } | |
2909 | ||
ac718b69 | 2910 | static void rtl8152_get_drvinfo(struct net_device *netdev, |
2911 | struct ethtool_drvinfo *info) | |
2912 | { | |
2913 | struct r8152 *tp = netdev_priv(netdev); | |
2914 | ||
2915 | strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN); | |
2916 | strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN); | |
2917 | usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); | |
2918 | } | |
2919 | ||
2920 | static | |
2921 | int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) | |
2922 | { | |
2923 | struct r8152 *tp = netdev_priv(netdev); | |
2924 | ||
2925 | if (!tp->mii.mdio_read) | |
2926 | return -EOPNOTSUPP; | |
2927 | ||
2928 | return mii_ethtool_gset(&tp->mii, cmd); | |
2929 | } | |
2930 | ||
2931 | static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
2932 | { | |
2933 | struct r8152 *tp = netdev_priv(dev); | |
9a4be1bd | 2934 | int ret; |
2935 | ||
2936 | ret = usb_autopm_get_interface(tp->intf); | |
2937 | if (ret < 0) | |
2938 | goto out; | |
ac718b69 | 2939 | |
9a4be1bd | 2940 | ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex); |
2941 | ||
2942 | usb_autopm_put_interface(tp->intf); | |
2943 | ||
2944 | out: | |
2945 | return ret; | |
ac718b69 | 2946 | } |
2947 | ||
2948 | static struct ethtool_ops ops = { | |
2949 | .get_drvinfo = rtl8152_get_drvinfo, | |
2950 | .get_settings = rtl8152_get_settings, | |
2951 | .set_settings = rtl8152_set_settings, | |
2952 | .get_link = ethtool_op_get_link, | |
a5ec27c1 | 2953 | .get_msglevel = rtl8152_get_msglevel, |
2954 | .set_msglevel = rtl8152_set_msglevel, | |
21ff2e89 | 2955 | .get_wol = rtl8152_get_wol, |
2956 | .set_wol = rtl8152_set_wol, | |
ac718b69 | 2957 | }; |
2958 | ||
2959 | static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) | |
2960 | { | |
2961 | struct r8152 *tp = netdev_priv(netdev); | |
2962 | struct mii_ioctl_data *data = if_mii(rq); | |
9a4be1bd | 2963 | int res; |
2964 | ||
2965 | res = usb_autopm_get_interface(tp->intf); | |
2966 | if (res < 0) | |
2967 | goto out; | |
ac718b69 | 2968 | |
2969 | switch (cmd) { | |
2970 | case SIOCGMIIPHY: | |
2971 | data->phy_id = R8152_PHY_ID; /* Internal PHY */ | |
2972 | break; | |
2973 | ||
2974 | case SIOCGMIIREG: | |
2975 | data->val_out = r8152_mdio_read(tp, data->reg_num); | |
2976 | break; | |
2977 | ||
2978 | case SIOCSMIIREG: | |
2979 | if (!capable(CAP_NET_ADMIN)) { | |
2980 | res = -EPERM; | |
2981 | break; | |
2982 | } | |
2983 | r8152_mdio_write(tp, data->reg_num, data->val_in); | |
2984 | break; | |
2985 | ||
2986 | default: | |
2987 | res = -EOPNOTSUPP; | |
2988 | } | |
2989 | ||
9a4be1bd | 2990 | usb_autopm_put_interface(tp->intf); |
2991 | ||
2992 | out: | |
ac718b69 | 2993 | return res; |
2994 | } | |
2995 | ||
2996 | static const struct net_device_ops rtl8152_netdev_ops = { | |
2997 | .ndo_open = rtl8152_open, | |
2998 | .ndo_stop = rtl8152_close, | |
2999 | .ndo_do_ioctl = rtl8152_ioctl, | |
3000 | .ndo_start_xmit = rtl8152_start_xmit, | |
3001 | .ndo_tx_timeout = rtl8152_tx_timeout, | |
3002 | .ndo_set_rx_mode = rtl8152_set_rx_mode, | |
3003 | .ndo_set_mac_address = rtl8152_set_mac_address, | |
3004 | ||
3005 | .ndo_change_mtu = eth_change_mtu, | |
3006 | .ndo_validate_addr = eth_validate_addr, | |
3007 | }; | |
3008 | ||
3009 | static void r8152b_get_version(struct r8152 *tp) | |
3010 | { | |
3011 | u32 ocp_data; | |
3012 | u16 version; | |
3013 | ||
3014 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); | |
3015 | version = (u16)(ocp_data & VERSION_MASK); | |
3016 | ||
3017 | switch (version) { | |
3018 | case 0x4c00: | |
3019 | tp->version = RTL_VER_01; | |
3020 | break; | |
3021 | case 0x4c10: | |
3022 | tp->version = RTL_VER_02; | |
3023 | break; | |
43779f8d | 3024 | case 0x5c00: |
3025 | tp->version = RTL_VER_03; | |
3026 | tp->mii.supports_gmii = 1; | |
3027 | break; | |
3028 | case 0x5c10: | |
3029 | tp->version = RTL_VER_04; | |
3030 | tp->mii.supports_gmii = 1; | |
3031 | break; | |
3032 | case 0x5c20: | |
3033 | tp->version = RTL_VER_05; | |
3034 | tp->mii.supports_gmii = 1; | |
3035 | break; | |
ac718b69 | 3036 | default: |
3037 | netif_info(tp, probe, tp->netdev, | |
3038 | "Unknown version 0x%04x\n", version); | |
3039 | break; | |
3040 | } | |
3041 | } | |
3042 | ||
e3fe0b1a | 3043 | static void rtl8152_unload(struct r8152 *tp) |
3044 | { | |
00a5e360 | 3045 | if (tp->version != RTL_VER_01) |
3046 | r8152_power_cut_en(tp, true); | |
e3fe0b1a | 3047 | } |
3048 | ||
43779f8d | 3049 | static void rtl8153_unload(struct r8152 *tp) |
3050 | { | |
b9702723 | 3051 | r8153_power_cut_en(tp, true); |
43779f8d | 3052 | } |
3053 | ||
31ca1dec | 3054 | static int rtl_ops_init(struct r8152 *tp, const struct usb_device_id *id) |
c81229c9 | 3055 | { |
3056 | struct rtl_ops *ops = &tp->rtl_ops; | |
31ca1dec | 3057 | int ret = -ENODEV; |
c81229c9 | 3058 | |
3059 | switch (id->idVendor) { | |
3060 | case VENDOR_ID_REALTEK: | |
3061 | switch (id->idProduct) { | |
3062 | case PRODUCT_ID_RTL8152: | |
3063 | ops->init = r8152b_init; | |
3064 | ops->enable = rtl8152_enable; | |
3065 | ops->disable = rtl8152_disable; | |
7e9da481 | 3066 | ops->up = r8152b_exit_oob; |
c81229c9 | 3067 | ops->down = rtl8152_down; |
3068 | ops->unload = rtl8152_unload; | |
31ca1dec | 3069 | ret = 0; |
c81229c9 | 3070 | break; |
43779f8d | 3071 | case PRODUCT_ID_RTL8153: |
3072 | ops->init = r8153_init; | |
3073 | ops->enable = rtl8153_enable; | |
3074 | ops->disable = rtl8152_disable; | |
7e9da481 | 3075 | ops->up = r8153_first_init; |
43779f8d | 3076 | ops->down = rtl8153_down; |
3077 | ops->unload = rtl8153_unload; | |
31ca1dec | 3078 | ret = 0; |
43779f8d | 3079 | break; |
3080 | default: | |
43779f8d | 3081 | break; |
3082 | } | |
3083 | break; | |
3084 | ||
3085 | case VENDOR_ID_SAMSUNG: | |
3086 | switch (id->idProduct) { | |
3087 | case PRODUCT_ID_SAMSUNG: | |
3088 | ops->init = r8153_init; | |
3089 | ops->enable = rtl8153_enable; | |
3090 | ops->disable = rtl8152_disable; | |
7e9da481 | 3091 | ops->up = r8153_first_init; |
43779f8d | 3092 | ops->down = rtl8153_down; |
3093 | ops->unload = rtl8153_unload; | |
31ca1dec | 3094 | ret = 0; |
43779f8d | 3095 | break; |
c81229c9 | 3096 | default: |
c81229c9 | 3097 | break; |
3098 | } | |
3099 | break; | |
3100 | ||
3101 | default: | |
c81229c9 | 3102 | break; |
3103 | } | |
3104 | ||
31ca1dec | 3105 | if (ret) |
3106 | netif_err(tp, probe, tp->netdev, "Unknown Device\n"); | |
3107 | ||
c81229c9 | 3108 | return ret; |
3109 | } | |
3110 | ||
ac718b69 | 3111 | static int rtl8152_probe(struct usb_interface *intf, |
3112 | const struct usb_device_id *id) | |
3113 | { | |
3114 | struct usb_device *udev = interface_to_usbdev(intf); | |
3115 | struct r8152 *tp; | |
3116 | struct net_device *netdev; | |
ebc2ec48 | 3117 | int ret; |
ac718b69 | 3118 | |
ac718b69 | 3119 | netdev = alloc_etherdev(sizeof(struct r8152)); |
3120 | if (!netdev) { | |
4a8deae2 | 3121 | dev_err(&intf->dev, "Out of memory\n"); |
ac718b69 | 3122 | return -ENOMEM; |
3123 | } | |
3124 | ||
ebc2ec48 | 3125 | SET_NETDEV_DEV(netdev, &intf->dev); |
ac718b69 | 3126 | tp = netdev_priv(netdev); |
3127 | tp->msg_enable = 0x7FFF; | |
3128 | ||
e3ad412a | 3129 | tp->udev = udev; |
3130 | tp->netdev = netdev; | |
3131 | tp->intf = intf; | |
3132 | ||
31ca1dec | 3133 | ret = rtl_ops_init(tp, id); |
3134 | if (ret) | |
3135 | goto out; | |
c81229c9 | 3136 | |
ebc2ec48 | 3137 | tasklet_init(&tp->tl, bottom_half, (unsigned long)tp); |
ac718b69 | 3138 | INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); |
3139 | ||
ac718b69 | 3140 | netdev->netdev_ops = &rtl8152_netdev_ops; |
3141 | netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; | |
5bd23881 | 3142 | |
565cab0a | 3143 | netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM; |
3144 | netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM; | |
db8515ef | 3145 | |
ac718b69 | 3146 | SET_ETHTOOL_OPS(netdev, &ops); |
ac718b69 | 3147 | |
3148 | tp->mii.dev = netdev; | |
3149 | tp->mii.mdio_read = read_mii_word; | |
3150 | tp->mii.mdio_write = write_mii_word; | |
3151 | tp->mii.phy_id_mask = 0x3f; | |
3152 | tp->mii.reg_num_mask = 0x1f; | |
3153 | tp->mii.phy_id = R8152_PHY_ID; | |
3154 | tp->mii.supports_gmii = 0; | |
3155 | ||
9a4be1bd | 3156 | intf->needs_remote_wakeup = 1; |
3157 | ||
ac718b69 | 3158 | r8152b_get_version(tp); |
c81229c9 | 3159 | tp->rtl_ops.init(tp); |
ac718b69 | 3160 | set_ethernet_addr(tp); |
3161 | ||
ac718b69 | 3162 | usb_set_intfdata(intf, tp); |
ac718b69 | 3163 | |
ebc2ec48 | 3164 | ret = register_netdev(netdev); |
3165 | if (ret != 0) { | |
4a8deae2 | 3166 | netif_err(tp, probe, netdev, "couldn't register the device\n"); |
ebc2ec48 | 3167 | goto out1; |
ac718b69 | 3168 | } |
3169 | ||
21ff2e89 | 3170 | tp->saved_wolopts = __rtl_get_wol(tp); |
3171 | if (tp->saved_wolopts) | |
3172 | device_set_wakeup_enable(&udev->dev, true); | |
3173 | else | |
3174 | device_set_wakeup_enable(&udev->dev, false); | |
3175 | ||
4a8deae2 | 3176 | netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); |
ac718b69 | 3177 | |
3178 | return 0; | |
3179 | ||
ac718b69 | 3180 | out1: |
ebc2ec48 | 3181 | usb_set_intfdata(intf, NULL); |
ac718b69 | 3182 | out: |
3183 | free_netdev(netdev); | |
ebc2ec48 | 3184 | return ret; |
ac718b69 | 3185 | } |
3186 | ||
ac718b69 | 3187 | static void rtl8152_disconnect(struct usb_interface *intf) |
3188 | { | |
3189 | struct r8152 *tp = usb_get_intfdata(intf); | |
3190 | ||
3191 | usb_set_intfdata(intf, NULL); | |
3192 | if (tp) { | |
3193 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
3194 | tasklet_kill(&tp->tl); | |
3195 | unregister_netdev(tp->netdev); | |
c81229c9 | 3196 | tp->rtl_ops.unload(tp); |
ac718b69 | 3197 | free_netdev(tp->netdev); |
3198 | } | |
3199 | } | |
3200 | ||
3201 | /* table of devices that work with this driver */ | |
3202 | static struct usb_device_id rtl8152_table[] = { | |
c7de7dec | 3203 | {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)}, |
3204 | {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8153)}, | |
3205 | {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, PRODUCT_ID_SAMSUNG)}, | |
ac718b69 | 3206 | {} |
3207 | }; | |
3208 | ||
3209 | MODULE_DEVICE_TABLE(usb, rtl8152_table); | |
3210 | ||
3211 | static struct usb_driver rtl8152_driver = { | |
3212 | .name = MODULENAME, | |
ebc2ec48 | 3213 | .id_table = rtl8152_table, |
ac718b69 | 3214 | .probe = rtl8152_probe, |
3215 | .disconnect = rtl8152_disconnect, | |
ac718b69 | 3216 | .suspend = rtl8152_suspend, |
ebc2ec48 | 3217 | .resume = rtl8152_resume, |
3218 | .reset_resume = rtl8152_resume, | |
9a4be1bd | 3219 | .supports_autosuspend = 1, |
a634782f | 3220 | .disable_hub_initiated_lpm = 1, |
ac718b69 | 3221 | }; |
3222 | ||
b4236daa | 3223 | module_usb_driver(rtl8152_driver); |
ac718b69 | 3224 | |
3225 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
3226 | MODULE_DESCRIPTION(DRIVER_DESC); | |
3227 | MODULE_LICENSE("GPL"); |