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ac718b69 | 1 | /* |
c7de7dec | 2 | * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. |
ac718b69 | 3 | * |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * version 2 as published by the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | ||
ac718b69 | 10 | #include <linux/signal.h> |
11 | #include <linux/slab.h> | |
12 | #include <linux/module.h> | |
ac718b69 | 13 | #include <linux/netdevice.h> |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/mii.h> | |
16 | #include <linux/ethtool.h> | |
17 | #include <linux/usb.h> | |
18 | #include <linux/crc32.h> | |
19 | #include <linux/if_vlan.h> | |
20 | #include <linux/uaccess.h> | |
ebc2ec48 | 21 | #include <linux/list.h> |
5bd23881 | 22 | #include <linux/ip.h> |
23 | #include <linux/ipv6.h> | |
6128d1bb | 24 | #include <net/ip6_checksum.h> |
4c4a6b1b | 25 | #include <uapi/linux/mdio.h> |
26 | #include <linux/mdio.h> | |
d9a28c5b | 27 | #include <linux/usb/cdc.h> |
5ee3c60c | 28 | #include <linux/suspend.h> |
34ee32c9 | 29 | #include <linux/acpi.h> |
ac718b69 | 30 | |
d0942473 | 31 | /* Information for net-next */ |
65b82d69 | 32 | #define NETNEXT_VERSION "09" |
d0942473 | 33 | |
34 | /* Information for net */ | |
b20cb60e | 35 | #define NET_VERSION "9" |
d0942473 | 36 | |
37 | #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION | |
ac718b69 | 38 | #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" |
44d942a9 | 39 | #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" |
ac718b69 | 40 | #define MODULENAME "r8152" |
41 | ||
42 | #define R8152_PHY_ID 32 | |
43 | ||
44 | #define PLA_IDR 0xc000 | |
45 | #define PLA_RCR 0xc010 | |
46 | #define PLA_RMS 0xc016 | |
47 | #define PLA_RXFIFO_CTRL0 0xc0a0 | |
48 | #define PLA_RXFIFO_CTRL1 0xc0a4 | |
49 | #define PLA_RXFIFO_CTRL2 0xc0a8 | |
65bab84c | 50 | #define PLA_DMY_REG0 0xc0b0 |
ac718b69 | 51 | #define PLA_FMC 0xc0b4 |
52 | #define PLA_CFG_WOL 0xc0b6 | |
43779f8d | 53 | #define PLA_TEREDO_CFG 0xc0bc |
65b82d69 | 54 | #define PLA_TEREDO_WAKE_BASE 0xc0c4 |
ac718b69 | 55 | #define PLA_MAR 0xcd00 |
43779f8d | 56 | #define PLA_BACKUP 0xd000 |
ac718b69 | 57 | #define PAL_BDC_CR 0xd1a0 |
43779f8d | 58 | #define PLA_TEREDO_TIMER 0xd2cc |
59 | #define PLA_REALWOW_TIMER 0xd2e8 | |
65b82d69 | 60 | #define PLA_EFUSE_DATA 0xdd00 |
61 | #define PLA_EFUSE_CMD 0xdd02 | |
ac718b69 | 62 | #define PLA_LEDSEL 0xdd90 |
63 | #define PLA_LED_FEATURE 0xdd92 | |
64 | #define PLA_PHYAR 0xde00 | |
43779f8d | 65 | #define PLA_BOOT_CTRL 0xe004 |
ac718b69 | 66 | #define PLA_GPHY_INTR_IMR 0xe022 |
67 | #define PLA_EEE_CR 0xe040 | |
68 | #define PLA_EEEP_CR 0xe080 | |
69 | #define PLA_MAC_PWR_CTRL 0xe0c0 | |
43779f8d | 70 | #define PLA_MAC_PWR_CTRL2 0xe0ca |
71 | #define PLA_MAC_PWR_CTRL3 0xe0cc | |
72 | #define PLA_MAC_PWR_CTRL4 0xe0ce | |
73 | #define PLA_WDT6_CTRL 0xe428 | |
ac718b69 | 74 | #define PLA_TCR0 0xe610 |
75 | #define PLA_TCR1 0xe612 | |
69b4b7a4 | 76 | #define PLA_MTPS 0xe615 |
ac718b69 | 77 | #define PLA_TXFIFO_CTRL 0xe618 |
4f1d4d54 | 78 | #define PLA_RSTTALLY 0xe800 |
ac718b69 | 79 | #define PLA_CR 0xe813 |
80 | #define PLA_CRWECR 0xe81c | |
21ff2e89 | 81 | #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ |
82 | #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ | |
ac718b69 | 83 | #define PLA_CONFIG5 0xe822 |
84 | #define PLA_PHY_PWR 0xe84c | |
85 | #define PLA_OOB_CTRL 0xe84f | |
86 | #define PLA_CPCR 0xe854 | |
87 | #define PLA_MISC_0 0xe858 | |
88 | #define PLA_MISC_1 0xe85a | |
89 | #define PLA_OCP_GPHY_BASE 0xe86c | |
4f1d4d54 | 90 | #define PLA_TALLYCNT 0xe890 |
ac718b69 | 91 | #define PLA_SFF_STS_7 0xe8de |
92 | #define PLA_PHYSTATUS 0xe908 | |
93 | #define PLA_BP_BA 0xfc26 | |
94 | #define PLA_BP_0 0xfc28 | |
95 | #define PLA_BP_1 0xfc2a | |
96 | #define PLA_BP_2 0xfc2c | |
97 | #define PLA_BP_3 0xfc2e | |
98 | #define PLA_BP_4 0xfc30 | |
99 | #define PLA_BP_5 0xfc32 | |
100 | #define PLA_BP_6 0xfc34 | |
101 | #define PLA_BP_7 0xfc36 | |
43779f8d | 102 | #define PLA_BP_EN 0xfc38 |
ac718b69 | 103 | |
65bab84c | 104 | #define USB_USB2PHY 0xb41e |
105 | #define USB_SSPHYLINK2 0xb428 | |
43779f8d | 106 | #define USB_U2P3_CTRL 0xb460 |
65bab84c | 107 | #define USB_CSR_DUMMY1 0xb464 |
108 | #define USB_CSR_DUMMY2 0xb466 | |
ac718b69 | 109 | #define USB_DEV_STAT 0xb808 |
65bab84c | 110 | #define USB_CONNECT_TIMER 0xcbf8 |
65b82d69 | 111 | #define USB_MSC_TIMER 0xcbfc |
65bab84c | 112 | #define USB_BURST_SIZE 0xcfc0 |
65b82d69 | 113 | #define USB_LPM_CONFIG 0xcfd8 |
ac718b69 | 114 | #define USB_USB_CTRL 0xd406 |
115 | #define USB_PHY_CTRL 0xd408 | |
116 | #define USB_TX_AGG 0xd40a | |
117 | #define USB_RX_BUF_TH 0xd40c | |
118 | #define USB_USB_TIMER 0xd428 | |
464ec10a | 119 | #define USB_RX_EARLY_TIMEOUT 0xd42c |
120 | #define USB_RX_EARLY_SIZE 0xd42e | |
65b82d69 | 121 | #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */ |
122 | #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */ | |
ac718b69 | 123 | #define USB_TX_DMA 0xd434 |
65b82d69 | 124 | #define USB_UPT_RXDMA_OWN 0xd437 |
43779f8d | 125 | #define USB_TOLERANCE 0xd490 |
126 | #define USB_LPM_CTRL 0xd41a | |
93fe9b18 | 127 | #define USB_BMU_RESET 0xd4b0 |
65b82d69 | 128 | #define USB_U1U2_TIMER 0xd4da |
ac718b69 | 129 | #define USB_UPS_CTRL 0xd800 |
43779f8d | 130 | #define USB_POWER_CUT 0xd80a |
65b82d69 | 131 | #define USB_MISC_0 0xd81a |
43779f8d | 132 | #define USB_AFE_CTRL2 0xd824 |
65b82d69 | 133 | #define USB_UPS_CFG 0xd842 |
134 | #define USB_UPS_FLAGS 0xd848 | |
43779f8d | 135 | #define USB_WDT11_CTRL 0xe43c |
ac718b69 | 136 | #define USB_BP_BA 0xfc26 |
137 | #define USB_BP_0 0xfc28 | |
138 | #define USB_BP_1 0xfc2a | |
139 | #define USB_BP_2 0xfc2c | |
140 | #define USB_BP_3 0xfc2e | |
141 | #define USB_BP_4 0xfc30 | |
142 | #define USB_BP_5 0xfc32 | |
143 | #define USB_BP_6 0xfc34 | |
144 | #define USB_BP_7 0xfc36 | |
43779f8d | 145 | #define USB_BP_EN 0xfc38 |
65b82d69 | 146 | #define USB_BP_8 0xfc38 |
147 | #define USB_BP_9 0xfc3a | |
148 | #define USB_BP_10 0xfc3c | |
149 | #define USB_BP_11 0xfc3e | |
150 | #define USB_BP_12 0xfc40 | |
151 | #define USB_BP_13 0xfc42 | |
152 | #define USB_BP_14 0xfc44 | |
153 | #define USB_BP_15 0xfc46 | |
154 | #define USB_BP2_EN 0xfc48 | |
ac718b69 | 155 | |
156 | /* OCP Registers */ | |
157 | #define OCP_ALDPS_CONFIG 0x2010 | |
158 | #define OCP_EEE_CONFIG1 0x2080 | |
159 | #define OCP_EEE_CONFIG2 0x2092 | |
160 | #define OCP_EEE_CONFIG3 0x2094 | |
ac244d3e | 161 | #define OCP_BASE_MII 0xa400 |
ac718b69 | 162 | #define OCP_EEE_AR 0xa41a |
163 | #define OCP_EEE_DATA 0xa41c | |
43779f8d | 164 | #define OCP_PHY_STATUS 0xa420 |
65b82d69 | 165 | #define OCP_NCTL_CFG 0xa42c |
43779f8d | 166 | #define OCP_POWER_CFG 0xa430 |
167 | #define OCP_EEE_CFG 0xa432 | |
168 | #define OCP_SRAM_ADDR 0xa436 | |
169 | #define OCP_SRAM_DATA 0xa438 | |
170 | #define OCP_DOWN_SPEED 0xa442 | |
df35d283 | 171 | #define OCP_EEE_ABLE 0xa5c4 |
4c4a6b1b | 172 | #define OCP_EEE_ADV 0xa5d0 |
df35d283 | 173 | #define OCP_EEE_LPABLE 0xa5d2 |
2dd49e0f | 174 | #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */ |
65b82d69 | 175 | #define OCP_PHY_PATCH_STAT 0xb800 |
176 | #define OCP_PHY_PATCH_CMD 0xb820 | |
177 | #define OCP_ADC_IOFFSET 0xbcfc | |
43779f8d | 178 | #define OCP_ADC_CFG 0xbc06 |
65b82d69 | 179 | #define OCP_SYSCLK_CFG 0xc416 |
43779f8d | 180 | |
181 | /* SRAM Register */ | |
65b82d69 | 182 | #define SRAM_GREEN_CFG 0x8011 |
43779f8d | 183 | #define SRAM_LPF_CFG 0x8012 |
184 | #define SRAM_10M_AMP1 0x8080 | |
185 | #define SRAM_10M_AMP2 0x8082 | |
186 | #define SRAM_IMPEDANCE 0x8084 | |
ac718b69 | 187 | |
188 | /* PLA_RCR */ | |
189 | #define RCR_AAP 0x00000001 | |
190 | #define RCR_APM 0x00000002 | |
191 | #define RCR_AM 0x00000004 | |
192 | #define RCR_AB 0x00000008 | |
193 | #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) | |
194 | ||
195 | /* PLA_RXFIFO_CTRL0 */ | |
196 | #define RXFIFO_THR1_NORMAL 0x00080002 | |
197 | #define RXFIFO_THR1_OOB 0x01800003 | |
198 | ||
199 | /* PLA_RXFIFO_CTRL1 */ | |
200 | #define RXFIFO_THR2_FULL 0x00000060 | |
201 | #define RXFIFO_THR2_HIGH 0x00000038 | |
202 | #define RXFIFO_THR2_OOB 0x0000004a | |
43779f8d | 203 | #define RXFIFO_THR2_NORMAL 0x00a0 |
ac718b69 | 204 | |
205 | /* PLA_RXFIFO_CTRL2 */ | |
206 | #define RXFIFO_THR3_FULL 0x00000078 | |
207 | #define RXFIFO_THR3_HIGH 0x00000048 | |
208 | #define RXFIFO_THR3_OOB 0x0000005a | |
43779f8d | 209 | #define RXFIFO_THR3_NORMAL 0x0110 |
ac718b69 | 210 | |
211 | /* PLA_TXFIFO_CTRL */ | |
212 | #define TXFIFO_THR_NORMAL 0x00400008 | |
43779f8d | 213 | #define TXFIFO_THR_NORMAL2 0x01000008 |
ac718b69 | 214 | |
65bab84c | 215 | /* PLA_DMY_REG0 */ |
216 | #define ECM_ALDPS 0x0002 | |
217 | ||
ac718b69 | 218 | /* PLA_FMC */ |
219 | #define FMC_FCR_MCU_EN 0x0001 | |
220 | ||
221 | /* PLA_EEEP_CR */ | |
222 | #define EEEP_CR_EEEP_TX 0x0002 | |
223 | ||
43779f8d | 224 | /* PLA_WDT6_CTRL */ |
225 | #define WDT6_SET_MODE 0x0010 | |
226 | ||
ac718b69 | 227 | /* PLA_TCR0 */ |
228 | #define TCR0_TX_EMPTY 0x0800 | |
229 | #define TCR0_AUTO_FIFO 0x0080 | |
230 | ||
231 | /* PLA_TCR1 */ | |
232 | #define VERSION_MASK 0x7cf0 | |
233 | ||
69b4b7a4 | 234 | /* PLA_MTPS */ |
235 | #define MTPS_JUMBO (12 * 1024 / 64) | |
236 | #define MTPS_DEFAULT (6 * 1024 / 64) | |
237 | ||
4f1d4d54 | 238 | /* PLA_RSTTALLY */ |
239 | #define TALLY_RESET 0x0001 | |
240 | ||
ac718b69 | 241 | /* PLA_CR */ |
242 | #define CR_RST 0x10 | |
243 | #define CR_RE 0x08 | |
244 | #define CR_TE 0x04 | |
245 | ||
246 | /* PLA_CRWECR */ | |
247 | #define CRWECR_NORAML 0x00 | |
248 | #define CRWECR_CONFIG 0xc0 | |
249 | ||
250 | /* PLA_OOB_CTRL */ | |
251 | #define NOW_IS_OOB 0x80 | |
252 | #define TXFIFO_EMPTY 0x20 | |
253 | #define RXFIFO_EMPTY 0x10 | |
254 | #define LINK_LIST_READY 0x02 | |
255 | #define DIS_MCU_CLROOB 0x01 | |
256 | #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) | |
257 | ||
258 | /* PLA_MISC_1 */ | |
259 | #define RXDY_GATED_EN 0x0008 | |
260 | ||
261 | /* PLA_SFF_STS_7 */ | |
262 | #define RE_INIT_LL 0x8000 | |
263 | #define MCU_BORW_EN 0x4000 | |
264 | ||
265 | /* PLA_CPCR */ | |
266 | #define CPCR_RX_VLAN 0x0040 | |
267 | ||
268 | /* PLA_CFG_WOL */ | |
269 | #define MAGIC_EN 0x0001 | |
270 | ||
43779f8d | 271 | /* PLA_TEREDO_CFG */ |
272 | #define TEREDO_SEL 0x8000 | |
273 | #define TEREDO_WAKE_MASK 0x7f00 | |
274 | #define TEREDO_RS_EVENT_MASK 0x00fe | |
275 | #define OOB_TEREDO_EN 0x0001 | |
276 | ||
ac718b69 | 277 | /* PAL_BDC_CR */ |
278 | #define ALDPS_PROXY_MODE 0x0001 | |
279 | ||
65b82d69 | 280 | /* PLA_EFUSE_CMD */ |
281 | #define EFUSE_READ_CMD BIT(15) | |
282 | #define EFUSE_DATA_BIT16 BIT(7) | |
283 | ||
21ff2e89 | 284 | /* PLA_CONFIG34 */ |
285 | #define LINK_ON_WAKE_EN 0x0010 | |
286 | #define LINK_OFF_WAKE_EN 0x0008 | |
287 | ||
ac718b69 | 288 | /* PLA_CONFIG5 */ |
21ff2e89 | 289 | #define BWF_EN 0x0040 |
290 | #define MWF_EN 0x0020 | |
291 | #define UWF_EN 0x0010 | |
ac718b69 | 292 | #define LAN_WAKE_EN 0x0002 |
293 | ||
294 | /* PLA_LED_FEATURE */ | |
295 | #define LED_MODE_MASK 0x0700 | |
296 | ||
297 | /* PLA_PHY_PWR */ | |
298 | #define TX_10M_IDLE_EN 0x0080 | |
299 | #define PFM_PWM_SWITCH 0x0040 | |
300 | ||
301 | /* PLA_MAC_PWR_CTRL */ | |
302 | #define D3_CLK_GATED_EN 0x00004000 | |
303 | #define MCU_CLK_RATIO 0x07010f07 | |
304 | #define MCU_CLK_RATIO_MASK 0x0f0f0f0f | |
43779f8d | 305 | #define ALDPS_SPDWN_RATIO 0x0f87 |
306 | ||
307 | /* PLA_MAC_PWR_CTRL2 */ | |
308 | #define EEE_SPDWN_RATIO 0x8007 | |
65b82d69 | 309 | #define MAC_CLK_SPDWN_EN BIT(15) |
43779f8d | 310 | |
311 | /* PLA_MAC_PWR_CTRL3 */ | |
312 | #define PKT_AVAIL_SPDWN_EN 0x0100 | |
313 | #define SUSPEND_SPDWN_EN 0x0004 | |
314 | #define U1U2_SPDWN_EN 0x0002 | |
315 | #define L1_SPDWN_EN 0x0001 | |
316 | ||
317 | /* PLA_MAC_PWR_CTRL4 */ | |
318 | #define PWRSAVE_SPDWN_EN 0x1000 | |
319 | #define RXDV_SPDWN_EN 0x0800 | |
320 | #define TX10MIDLE_EN 0x0100 | |
321 | #define TP100_SPDWN_EN 0x0020 | |
322 | #define TP500_SPDWN_EN 0x0010 | |
323 | #define TP1000_SPDWN_EN 0x0008 | |
324 | #define EEE_SPDWN_EN 0x0001 | |
ac718b69 | 325 | |
326 | /* PLA_GPHY_INTR_IMR */ | |
327 | #define GPHY_STS_MSK 0x0001 | |
328 | #define SPEED_DOWN_MSK 0x0002 | |
329 | #define SPDWN_RXDV_MSK 0x0004 | |
330 | #define SPDWN_LINKCHG_MSK 0x0008 | |
331 | ||
332 | /* PLA_PHYAR */ | |
333 | #define PHYAR_FLAG 0x80000000 | |
334 | ||
335 | /* PLA_EEE_CR */ | |
336 | #define EEE_RX_EN 0x0001 | |
337 | #define EEE_TX_EN 0x0002 | |
338 | ||
43779f8d | 339 | /* PLA_BOOT_CTRL */ |
340 | #define AUTOLOAD_DONE 0x0002 | |
341 | ||
65bab84c | 342 | /* USB_USB2PHY */ |
343 | #define USB2PHY_SUSPEND 0x0001 | |
344 | #define USB2PHY_L1 0x0002 | |
345 | ||
346 | /* USB_SSPHYLINK2 */ | |
347 | #define pwd_dn_scale_mask 0x3ffe | |
348 | #define pwd_dn_scale(x) ((x) << 1) | |
349 | ||
350 | /* USB_CSR_DUMMY1 */ | |
351 | #define DYNAMIC_BURST 0x0001 | |
352 | ||
353 | /* USB_CSR_DUMMY2 */ | |
354 | #define EP4_FULL_FC 0x0001 | |
355 | ||
ac718b69 | 356 | /* USB_DEV_STAT */ |
357 | #define STAT_SPEED_MASK 0x0006 | |
358 | #define STAT_SPEED_HIGH 0x0000 | |
a3cc465d | 359 | #define STAT_SPEED_FULL 0x0002 |
ac718b69 | 360 | |
65b82d69 | 361 | /* USB_LPM_CONFIG */ |
362 | #define LPM_U1U2_EN BIT(0) | |
363 | ||
ac718b69 | 364 | /* USB_TX_AGG */ |
365 | #define TX_AGG_MAX_THRESHOLD 0x03 | |
366 | ||
367 | /* USB_RX_BUF_TH */ | |
43779f8d | 368 | #define RX_THR_SUPPER 0x0c350180 |
8e1f51bd | 369 | #define RX_THR_HIGH 0x7a120180 |
43779f8d | 370 | #define RX_THR_SLOW 0xffff0180 |
65b82d69 | 371 | #define RX_THR_B 0x00010001 |
ac718b69 | 372 | |
373 | /* USB_TX_DMA */ | |
374 | #define TEST_MODE_DISABLE 0x00000001 | |
375 | #define TX_SIZE_ADJUST1 0x00000100 | |
376 | ||
93fe9b18 | 377 | /* USB_BMU_RESET */ |
378 | #define BMU_RESET_EP_IN 0x01 | |
379 | #define BMU_RESET_EP_OUT 0x02 | |
380 | ||
65b82d69 | 381 | /* USB_UPT_RXDMA_OWN */ |
382 | #define OWN_UPDATE BIT(0) | |
383 | #define OWN_CLEAR BIT(1) | |
384 | ||
ac718b69 | 385 | /* USB_UPS_CTRL */ |
386 | #define POWER_CUT 0x0100 | |
387 | ||
388 | /* USB_PM_CTRL_STATUS */ | |
8e1f51bd | 389 | #define RESUME_INDICATE 0x0001 |
ac718b69 | 390 | |
391 | /* USB_USB_CTRL */ | |
392 | #define RX_AGG_DISABLE 0x0010 | |
e90fba8d | 393 | #define RX_ZERO_EN 0x0080 |
ac718b69 | 394 | |
43779f8d | 395 | /* USB_U2P3_CTRL */ |
396 | #define U2P3_ENABLE 0x0001 | |
397 | ||
398 | /* USB_POWER_CUT */ | |
399 | #define PWR_EN 0x0001 | |
400 | #define PHASE2_EN 0x0008 | |
65b82d69 | 401 | #define UPS_EN BIT(4) |
402 | #define USP_PREWAKE BIT(5) | |
43779f8d | 403 | |
404 | /* USB_MISC_0 */ | |
405 | #define PCUT_STATUS 0x0001 | |
406 | ||
464ec10a | 407 | /* USB_RX_EARLY_TIMEOUT */ |
408 | #define COALESCE_SUPER 85000U | |
409 | #define COALESCE_HIGH 250000U | |
410 | #define COALESCE_SLOW 524280U | |
43779f8d | 411 | |
412 | /* USB_WDT11_CTRL */ | |
413 | #define TIMER11_EN 0x0001 | |
414 | ||
415 | /* USB_LPM_CTRL */ | |
65bab84c | 416 | /* bit 4 ~ 5: fifo empty boundary */ |
417 | #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ | |
418 | /* bit 2 ~ 3: LMP timer */ | |
43779f8d | 419 | #define LPM_TIMER_MASK 0x0c |
420 | #define LPM_TIMER_500MS 0x04 /* 500 ms */ | |
421 | #define LPM_TIMER_500US 0x0c /* 500 us */ | |
65bab84c | 422 | #define ROK_EXIT_LPM 0x02 |
43779f8d | 423 | |
424 | /* USB_AFE_CTRL2 */ | |
425 | #define SEN_VAL_MASK 0xf800 | |
426 | #define SEN_VAL_NORMAL 0xa000 | |
427 | #define SEL_RXIDLE 0x0100 | |
428 | ||
65b82d69 | 429 | /* USB_UPS_CFG */ |
430 | #define SAW_CNT_1MS_MASK 0x0fff | |
431 | ||
432 | /* USB_UPS_FLAGS */ | |
433 | #define UPS_FLAGS_R_TUNE BIT(0) | |
434 | #define UPS_FLAGS_EN_10M_CKDIV BIT(1) | |
435 | #define UPS_FLAGS_250M_CKDIV BIT(2) | |
436 | #define UPS_FLAGS_EN_ALDPS BIT(3) | |
437 | #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4) | |
438 | #define UPS_FLAGS_SPEED_MASK (0xf << 16) | |
439 | #define ups_flags_speed(x) ((x) << 16) | |
440 | #define UPS_FLAGS_EN_EEE BIT(20) | |
441 | #define UPS_FLAGS_EN_500M_EEE BIT(21) | |
442 | #define UPS_FLAGS_EN_EEE_CKDIV BIT(22) | |
443 | #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24) | |
444 | #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25) | |
445 | #define UPS_FLAGS_EN_GREEN BIT(26) | |
446 | #define UPS_FLAGS_EN_FLOW_CTR BIT(27) | |
447 | ||
448 | enum spd_duplex { | |
449 | NWAY_10M_HALF = 1, | |
450 | NWAY_10M_FULL, | |
451 | NWAY_100M_HALF, | |
452 | NWAY_100M_FULL, | |
453 | NWAY_1000M_FULL, | |
454 | FORCE_10M_HALF, | |
455 | FORCE_10M_FULL, | |
456 | FORCE_100M_HALF, | |
457 | FORCE_100M_FULL, | |
458 | }; | |
459 | ||
ac718b69 | 460 | /* OCP_ALDPS_CONFIG */ |
461 | #define ENPWRSAVE 0x8000 | |
462 | #define ENPDNPS 0x0200 | |
463 | #define LINKENA 0x0100 | |
464 | #define DIS_SDSAVE 0x0010 | |
465 | ||
43779f8d | 466 | /* OCP_PHY_STATUS */ |
467 | #define PHY_STAT_MASK 0x0007 | |
c564b871 | 468 | #define PHY_STAT_EXT_INIT 2 |
43779f8d | 469 | #define PHY_STAT_LAN_ON 3 |
470 | #define PHY_STAT_PWRDN 5 | |
471 | ||
65b82d69 | 472 | /* OCP_NCTL_CFG */ |
473 | #define PGA_RETURN_EN BIT(1) | |
474 | ||
43779f8d | 475 | /* OCP_POWER_CFG */ |
476 | #define EEE_CLKDIV_EN 0x8000 | |
477 | #define EN_ALDPS 0x0004 | |
478 | #define EN_10M_PLLOFF 0x0001 | |
479 | ||
ac718b69 | 480 | /* OCP_EEE_CONFIG1 */ |
481 | #define RG_TXLPI_MSK_HFDUP 0x8000 | |
482 | #define RG_MATCLR_EN 0x4000 | |
483 | #define EEE_10_CAP 0x2000 | |
484 | #define EEE_NWAY_EN 0x1000 | |
485 | #define TX_QUIET_EN 0x0200 | |
486 | #define RX_QUIET_EN 0x0100 | |
d24f6134 | 487 | #define sd_rise_time_mask 0x0070 |
4c4a6b1b | 488 | #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */ |
ac718b69 | 489 | #define RG_RXLPI_MSK_HFDUP 0x0008 |
490 | #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ | |
491 | ||
492 | /* OCP_EEE_CONFIG2 */ | |
493 | #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ | |
494 | #define RG_DACQUIET_EN 0x0400 | |
495 | #define RG_LDVQUIET_EN 0x0200 | |
496 | #define RG_CKRSEL 0x0020 | |
497 | #define RG_EEEPRG_EN 0x0010 | |
498 | ||
499 | /* OCP_EEE_CONFIG3 */ | |
d24f6134 | 500 | #define fast_snr_mask 0xff80 |
4c4a6b1b | 501 | #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */ |
ac718b69 | 502 | #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ |
503 | #define MSK_PH 0x0006 /* bit 0 ~ 3 */ | |
504 | ||
505 | /* OCP_EEE_AR */ | |
506 | /* bit[15:14] function */ | |
507 | #define FUN_ADDR 0x0000 | |
508 | #define FUN_DATA 0x4000 | |
509 | /* bit[4:0] device addr */ | |
ac718b69 | 510 | |
43779f8d | 511 | /* OCP_EEE_CFG */ |
512 | #define CTAP_SHORT_EN 0x0040 | |
513 | #define EEE10_EN 0x0010 | |
514 | ||
515 | /* OCP_DOWN_SPEED */ | |
65b82d69 | 516 | #define EN_EEE_CMODE BIT(14) |
517 | #define EN_EEE_1000 BIT(13) | |
518 | #define EN_EEE_100 BIT(12) | |
519 | #define EN_10M_CLKDIV BIT(11) | |
43779f8d | 520 | #define EN_10M_BGOFF 0x0080 |
521 | ||
2dd49e0f | 522 | /* OCP_PHY_STATE */ |
523 | #define TXDIS_STATE 0x01 | |
524 | #define ABD_STATE 0x02 | |
525 | ||
65b82d69 | 526 | /* OCP_PHY_PATCH_STAT */ |
527 | #define PATCH_READY BIT(6) | |
528 | ||
529 | /* OCP_PHY_PATCH_CMD */ | |
530 | #define PATCH_REQUEST BIT(4) | |
531 | ||
43779f8d | 532 | /* OCP_ADC_CFG */ |
533 | #define CKADSEL_L 0x0100 | |
534 | #define ADC_EN 0x0080 | |
535 | #define EN_EMI_L 0x0040 | |
536 | ||
65b82d69 | 537 | /* OCP_SYSCLK_CFG */ |
538 | #define clk_div_expo(x) (min(x, 5) << 8) | |
539 | ||
540 | /* SRAM_GREEN_CFG */ | |
541 | #define GREEN_ETH_EN BIT(15) | |
542 | #define R_TUNE_EN BIT(11) | |
543 | ||
43779f8d | 544 | /* SRAM_LPF_CFG */ |
545 | #define LPF_AUTO_TUNE 0x8000 | |
546 | ||
547 | /* SRAM_10M_AMP1 */ | |
548 | #define GDAC_IB_UPALL 0x0008 | |
549 | ||
550 | /* SRAM_10M_AMP2 */ | |
551 | #define AMP_DN 0x0200 | |
552 | ||
553 | /* SRAM_IMPEDANCE */ | |
554 | #define RX_DRIVING_MASK 0x6000 | |
555 | ||
34ee32c9 ML |
556 | /* MAC PASSTHRU */ |
557 | #define AD_MASK 0xfee0 | |
558 | #define EFUSE 0xcfdb | |
559 | #define PASS_THRU_MASK 0x1 | |
560 | ||
ac718b69 | 561 | enum rtl_register_content { |
43779f8d | 562 | _1000bps = 0x10, |
ac718b69 | 563 | _100bps = 0x08, |
564 | _10bps = 0x04, | |
565 | LINK_STATUS = 0x02, | |
566 | FULL_DUP = 0x01, | |
567 | }; | |
568 | ||
1764bcd9 | 569 | #define RTL8152_MAX_TX 4 |
ebc2ec48 | 570 | #define RTL8152_MAX_RX 10 |
40a82917 | 571 | #define INTBUFSIZE 2 |
8e1f51bd | 572 | #define CRC_SIZE 4 |
573 | #define TX_ALIGN 4 | |
574 | #define RX_ALIGN 8 | |
40a82917 | 575 | |
576 | #define INTR_LINK 0x0004 | |
ebc2ec48 | 577 | |
ac718b69 | 578 | #define RTL8152_REQT_READ 0xc0 |
579 | #define RTL8152_REQT_WRITE 0x40 | |
580 | #define RTL8152_REQ_GET_REGS 0x05 | |
581 | #define RTL8152_REQ_SET_REGS 0x05 | |
582 | ||
583 | #define BYTE_EN_DWORD 0xff | |
584 | #define BYTE_EN_WORD 0x33 | |
585 | #define BYTE_EN_BYTE 0x11 | |
586 | #define BYTE_EN_SIX_BYTES 0x3f | |
587 | #define BYTE_EN_START_MASK 0x0f | |
588 | #define BYTE_EN_END_MASK 0xf0 | |
589 | ||
69b4b7a4 | 590 | #define RTL8153_MAX_PACKET 9216 /* 9K */ |
591 | #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN) | |
ac718b69 | 592 | #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) |
69b4b7a4 | 593 | #define RTL8153_RMS RTL8153_MAX_PACKET |
b8125404 | 594 | #define RTL8152_TX_TIMEOUT (5 * HZ) |
d823ab68 | 595 | #define RTL8152_NAPI_WEIGHT 64 |
b20cb60e | 596 | #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + CRC_SIZE + \ |
597 | sizeof(struct rx_desc) + RX_ALIGN) | |
ac718b69 | 598 | |
599 | /* rtl8152 flags */ | |
600 | enum rtl8152_flags { | |
601 | RTL8152_UNPLUG = 0, | |
ac718b69 | 602 | RTL8152_SET_RX_MODE, |
40a82917 | 603 | WORK_ENABLE, |
604 | RTL8152_LINK_CHG, | |
9a4be1bd | 605 | SELECTIVE_SUSPEND, |
aa66a5f1 | 606 | PHY_RESET, |
d823ab68 | 607 | SCHEDULE_NAPI, |
65b82d69 | 608 | GREEN_ETHERNET, |
ac718b69 | 609 | }; |
610 | ||
611 | /* Define these values to match your device */ | |
612 | #define VENDOR_ID_REALTEK 0x0bda | |
d5b07ccc | 613 | #define VENDOR_ID_MICROSOFT 0x045e |
43779f8d | 614 | #define VENDOR_ID_SAMSUNG 0x04e8 |
347eec34 | 615 | #define VENDOR_ID_LENOVO 0x17ef |
d065c3c1 | 616 | #define VENDOR_ID_NVIDIA 0x0955 |
ac718b69 | 617 | |
618 | #define MCU_TYPE_PLA 0x0100 | |
619 | #define MCU_TYPE_USB 0x0000 | |
620 | ||
4f1d4d54 | 621 | struct tally_counter { |
622 | __le64 tx_packets; | |
623 | __le64 rx_packets; | |
624 | __le64 tx_errors; | |
625 | __le32 rx_errors; | |
626 | __le16 rx_missed; | |
627 | __le16 align_errors; | |
628 | __le32 tx_one_collision; | |
629 | __le32 tx_multi_collision; | |
630 | __le64 rx_unicast; | |
631 | __le64 rx_broadcast; | |
632 | __le32 rx_multicast; | |
633 | __le16 tx_aborted; | |
f37119c5 | 634 | __le16 tx_underrun; |
4f1d4d54 | 635 | }; |
636 | ||
ac718b69 | 637 | struct rx_desc { |
500b6d7e | 638 | __le32 opts1; |
ac718b69 | 639 | #define RX_LEN_MASK 0x7fff |
565cab0a | 640 | |
500b6d7e | 641 | __le32 opts2; |
f5aaaa6d | 642 | #define RD_UDP_CS BIT(23) |
643 | #define RD_TCP_CS BIT(22) | |
644 | #define RD_IPV6_CS BIT(20) | |
645 | #define RD_IPV4_CS BIT(19) | |
565cab0a | 646 | |
500b6d7e | 647 | __le32 opts3; |
f5aaaa6d | 648 | #define IPF BIT(23) /* IP checksum fail */ |
649 | #define UDPF BIT(22) /* UDP checksum fail */ | |
650 | #define TCPF BIT(21) /* TCP checksum fail */ | |
651 | #define RX_VLAN_TAG BIT(16) | |
565cab0a | 652 | |
500b6d7e | 653 | __le32 opts4; |
654 | __le32 opts5; | |
655 | __le32 opts6; | |
ac718b69 | 656 | }; |
657 | ||
658 | struct tx_desc { | |
500b6d7e | 659 | __le32 opts1; |
f5aaaa6d | 660 | #define TX_FS BIT(31) /* First segment of a packet */ |
661 | #define TX_LS BIT(30) /* Final segment of a packet */ | |
662 | #define GTSENDV4 BIT(28) | |
663 | #define GTSENDV6 BIT(27) | |
60c89071 | 664 | #define GTTCPHO_SHIFT 18 |
6128d1bb | 665 | #define GTTCPHO_MAX 0x7fU |
60c89071 | 666 | #define TX_LEN_MAX 0x3ffffU |
5bd23881 | 667 | |
500b6d7e | 668 | __le32 opts2; |
f5aaaa6d | 669 | #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ |
670 | #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ | |
671 | #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ | |
672 | #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ | |
60c89071 | 673 | #define MSS_SHIFT 17 |
674 | #define MSS_MAX 0x7ffU | |
675 | #define TCPHO_SHIFT 17 | |
6128d1bb | 676 | #define TCPHO_MAX 0x7ffU |
f5aaaa6d | 677 | #define TX_VLAN_TAG BIT(16) |
ac718b69 | 678 | }; |
679 | ||
dff4e8ad | 680 | struct r8152; |
681 | ||
ebc2ec48 | 682 | struct rx_agg { |
683 | struct list_head list; | |
684 | struct urb *urb; | |
dff4e8ad | 685 | struct r8152 *context; |
ebc2ec48 | 686 | void *buffer; |
687 | void *head; | |
688 | }; | |
689 | ||
690 | struct tx_agg { | |
691 | struct list_head list; | |
692 | struct urb *urb; | |
dff4e8ad | 693 | struct r8152 *context; |
ebc2ec48 | 694 | void *buffer; |
695 | void *head; | |
696 | u32 skb_num; | |
697 | u32 skb_len; | |
698 | }; | |
699 | ||
ac718b69 | 700 | struct r8152 { |
701 | unsigned long flags; | |
702 | struct usb_device *udev; | |
d823ab68 | 703 | struct napi_struct napi; |
40a82917 | 704 | struct usb_interface *intf; |
ac718b69 | 705 | struct net_device *netdev; |
40a82917 | 706 | struct urb *intr_urb; |
ebc2ec48 | 707 | struct tx_agg tx_info[RTL8152_MAX_TX]; |
708 | struct rx_agg rx_info[RTL8152_MAX_RX]; | |
709 | struct list_head rx_done, tx_free; | |
d823ab68 | 710 | struct sk_buff_head tx_queue, rx_queue; |
ebc2ec48 | 711 | spinlock_t rx_lock, tx_lock; |
a028a9e0 | 712 | struct delayed_work schedule, hw_phy_work; |
ac718b69 | 713 | struct mii_if_info mii; |
b5403273 | 714 | struct mutex control; /* use for hw setting */ |
5ee3c60c | 715 | #ifdef CONFIG_PM_SLEEP |
716 | struct notifier_block pm_notifier; | |
717 | #endif | |
c81229c9 | 718 | |
719 | struct rtl_ops { | |
720 | void (*init)(struct r8152 *); | |
721 | int (*enable)(struct r8152 *); | |
722 | void (*disable)(struct r8152 *); | |
7e9da481 | 723 | void (*up)(struct r8152 *); |
c81229c9 | 724 | void (*down)(struct r8152 *); |
725 | void (*unload)(struct r8152 *); | |
df35d283 | 726 | int (*eee_get)(struct r8152 *, struct ethtool_eee *); |
727 | int (*eee_set)(struct r8152 *, struct ethtool_eee *); | |
2dd49e0f | 728 | bool (*in_nway)(struct r8152 *); |
a028a9e0 | 729 | void (*hw_phy_cfg)(struct r8152 *); |
2609af19 | 730 | void (*autosuspend_en)(struct r8152 *tp, bool enable); |
c81229c9 | 731 | } rtl_ops; |
732 | ||
40a82917 | 733 | int intr_interval; |
21ff2e89 | 734 | u32 saved_wolopts; |
ac718b69 | 735 | u32 msg_enable; |
dd1b119c | 736 | u32 tx_qlen; |
464ec10a | 737 | u32 coalesce; |
ac718b69 | 738 | u16 ocp_base; |
aa7e26b6 | 739 | u16 speed; |
40a82917 | 740 | u8 *intr_buff; |
ac718b69 | 741 | u8 version; |
aa7e26b6 | 742 | u8 duplex; |
743 | u8 autoneg; | |
ac718b69 | 744 | }; |
745 | ||
746 | enum rtl_version { | |
747 | RTL_VER_UNKNOWN = 0, | |
748 | RTL_VER_01, | |
43779f8d | 749 | RTL_VER_02, |
750 | RTL_VER_03, | |
751 | RTL_VER_04, | |
752 | RTL_VER_05, | |
fb02eb4a | 753 | RTL_VER_06, |
c27b32c2 | 754 | RTL_VER_07, |
65b82d69 | 755 | RTL_VER_08, |
756 | RTL_VER_09, | |
43779f8d | 757 | RTL_VER_MAX |
ac718b69 | 758 | }; |
759 | ||
60c89071 | 760 | enum tx_csum_stat { |
761 | TX_CSUM_SUCCESS = 0, | |
762 | TX_CSUM_TSO, | |
763 | TX_CSUM_NONE | |
764 | }; | |
765 | ||
ac718b69 | 766 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
767 | * The RTL chips use a 64 element hash table based on the Ethernet CRC. | |
768 | */ | |
769 | static const int multicast_filter_limit = 32; | |
52aec126 | 770 | static unsigned int agg_buf_sz = 16384; |
ac718b69 | 771 | |
52aec126 | 772 | #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \ |
60c89071 | 773 | VLAN_ETH_HLEN - VLAN_HLEN) |
774 | ||
ac718b69 | 775 | static |
776 | int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
777 | { | |
31787f53 | 778 | int ret; |
779 | void *tmp; | |
780 | ||
781 | tmp = kmalloc(size, GFP_KERNEL); | |
782 | if (!tmp) | |
783 | return -ENOMEM; | |
784 | ||
785 | ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), | |
b209af99 | 786 | RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, |
787 | value, index, tmp, size, 500); | |
31787f53 | 788 | |
789 | memcpy(data, tmp, size); | |
790 | kfree(tmp); | |
791 | ||
792 | return ret; | |
ac718b69 | 793 | } |
794 | ||
795 | static | |
796 | int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
797 | { | |
31787f53 | 798 | int ret; |
799 | void *tmp; | |
800 | ||
c4438f03 | 801 | tmp = kmemdup(data, size, GFP_KERNEL); |
31787f53 | 802 | if (!tmp) |
803 | return -ENOMEM; | |
804 | ||
31787f53 | 805 | ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), |
b209af99 | 806 | RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, |
807 | value, index, tmp, size, 500); | |
31787f53 | 808 | |
809 | kfree(tmp); | |
db8515ef | 810 | |
31787f53 | 811 | return ret; |
ac718b69 | 812 | } |
813 | ||
814 | static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, | |
b209af99 | 815 | void *data, u16 type) |
ac718b69 | 816 | { |
45f4a19f | 817 | u16 limit = 64; |
818 | int ret = 0; | |
ac718b69 | 819 | |
820 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
821 | return -ENODEV; | |
822 | ||
823 | /* both size and indix must be 4 bytes align */ | |
824 | if ((size & 3) || !size || (index & 3) || !data) | |
825 | return -EPERM; | |
826 | ||
827 | if ((u32)index + (u32)size > 0xffff) | |
828 | return -EPERM; | |
829 | ||
830 | while (size) { | |
831 | if (size > limit) { | |
832 | ret = get_registers(tp, index, type, limit, data); | |
833 | if (ret < 0) | |
834 | break; | |
835 | ||
836 | index += limit; | |
837 | data += limit; | |
838 | size -= limit; | |
839 | } else { | |
840 | ret = get_registers(tp, index, type, size, data); | |
841 | if (ret < 0) | |
842 | break; | |
843 | ||
844 | index += size; | |
845 | data += size; | |
846 | size = 0; | |
847 | break; | |
848 | } | |
849 | } | |
850 | ||
67610496 | 851 | if (ret == -ENODEV) |
852 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
853 | ||
ac718b69 | 854 | return ret; |
855 | } | |
856 | ||
857 | static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, | |
b209af99 | 858 | u16 size, void *data, u16 type) |
ac718b69 | 859 | { |
45f4a19f | 860 | int ret; |
861 | u16 byteen_start, byteen_end, byen; | |
862 | u16 limit = 512; | |
ac718b69 | 863 | |
864 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
865 | return -ENODEV; | |
866 | ||
867 | /* both size and indix must be 4 bytes align */ | |
868 | if ((size & 3) || !size || (index & 3) || !data) | |
869 | return -EPERM; | |
870 | ||
871 | if ((u32)index + (u32)size > 0xffff) | |
872 | return -EPERM; | |
873 | ||
874 | byteen_start = byteen & BYTE_EN_START_MASK; | |
875 | byteen_end = byteen & BYTE_EN_END_MASK; | |
876 | ||
877 | byen = byteen_start | (byteen_start << 4); | |
878 | ret = set_registers(tp, index, type | byen, 4, data); | |
879 | if (ret < 0) | |
880 | goto error1; | |
881 | ||
882 | index += 4; | |
883 | data += 4; | |
884 | size -= 4; | |
885 | ||
886 | if (size) { | |
887 | size -= 4; | |
888 | ||
889 | while (size) { | |
890 | if (size > limit) { | |
891 | ret = set_registers(tp, index, | |
b209af99 | 892 | type | BYTE_EN_DWORD, |
893 | limit, data); | |
ac718b69 | 894 | if (ret < 0) |
895 | goto error1; | |
896 | ||
897 | index += limit; | |
898 | data += limit; | |
899 | size -= limit; | |
900 | } else { | |
901 | ret = set_registers(tp, index, | |
b209af99 | 902 | type | BYTE_EN_DWORD, |
903 | size, data); | |
ac718b69 | 904 | if (ret < 0) |
905 | goto error1; | |
906 | ||
907 | index += size; | |
908 | data += size; | |
909 | size = 0; | |
910 | break; | |
911 | } | |
912 | } | |
913 | ||
914 | byen = byteen_end | (byteen_end >> 4); | |
915 | ret = set_registers(tp, index, type | byen, 4, data); | |
916 | if (ret < 0) | |
917 | goto error1; | |
918 | } | |
919 | ||
920 | error1: | |
67610496 | 921 | if (ret == -ENODEV) |
922 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
923 | ||
ac718b69 | 924 | return ret; |
925 | } | |
926 | ||
927 | static inline | |
928 | int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
929 | { | |
930 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); | |
931 | } | |
932 | ||
933 | static inline | |
934 | int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
935 | { | |
936 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); | |
937 | } | |
938 | ||
ac718b69 | 939 | static inline |
940 | int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
941 | { | |
942 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); | |
943 | } | |
944 | ||
945 | static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) | |
946 | { | |
c8826de8 | 947 | __le32 data; |
ac718b69 | 948 | |
c8826de8 | 949 | generic_ocp_read(tp, index, sizeof(data), &data, type); |
ac718b69 | 950 | |
951 | return __le32_to_cpu(data); | |
952 | } | |
953 | ||
954 | static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) | |
955 | { | |
c8826de8 | 956 | __le32 tmp = __cpu_to_le32(data); |
957 | ||
958 | generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); | |
ac718b69 | 959 | } |
960 | ||
961 | static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) | |
962 | { | |
963 | u32 data; | |
c8826de8 | 964 | __le32 tmp; |
ac718b69 | 965 | u8 shift = index & 2; |
966 | ||
967 | index &= ~3; | |
968 | ||
c8826de8 | 969 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 970 | |
c8826de8 | 971 | data = __le32_to_cpu(tmp); |
ac718b69 | 972 | data >>= (shift * 8); |
973 | data &= 0xffff; | |
974 | ||
975 | return (u16)data; | |
976 | } | |
977 | ||
978 | static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) | |
979 | { | |
c8826de8 | 980 | u32 mask = 0xffff; |
981 | __le32 tmp; | |
ac718b69 | 982 | u16 byen = BYTE_EN_WORD; |
983 | u8 shift = index & 2; | |
984 | ||
985 | data &= mask; | |
986 | ||
987 | if (index & 2) { | |
988 | byen <<= shift; | |
989 | mask <<= (shift * 8); | |
990 | data <<= (shift * 8); | |
991 | index &= ~3; | |
992 | } | |
993 | ||
c8826de8 | 994 | tmp = __cpu_to_le32(data); |
ac718b69 | 995 | |
c8826de8 | 996 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 997 | } |
998 | ||
999 | static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) | |
1000 | { | |
1001 | u32 data; | |
c8826de8 | 1002 | __le32 tmp; |
ac718b69 | 1003 | u8 shift = index & 3; |
1004 | ||
1005 | index &= ~3; | |
1006 | ||
c8826de8 | 1007 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 1008 | |
c8826de8 | 1009 | data = __le32_to_cpu(tmp); |
ac718b69 | 1010 | data >>= (shift * 8); |
1011 | data &= 0xff; | |
1012 | ||
1013 | return (u8)data; | |
1014 | } | |
1015 | ||
1016 | static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) | |
1017 | { | |
c8826de8 | 1018 | u32 mask = 0xff; |
1019 | __le32 tmp; | |
ac718b69 | 1020 | u16 byen = BYTE_EN_BYTE; |
1021 | u8 shift = index & 3; | |
1022 | ||
1023 | data &= mask; | |
1024 | ||
1025 | if (index & 3) { | |
1026 | byen <<= shift; | |
1027 | mask <<= (shift * 8); | |
1028 | data <<= (shift * 8); | |
1029 | index &= ~3; | |
1030 | } | |
1031 | ||
c8826de8 | 1032 | tmp = __cpu_to_le32(data); |
ac718b69 | 1033 | |
c8826de8 | 1034 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 1035 | } |
1036 | ||
ac244d3e | 1037 | static u16 ocp_reg_read(struct r8152 *tp, u16 addr) |
e3fe0b1a | 1038 | { |
1039 | u16 ocp_base, ocp_index; | |
1040 | ||
1041 | ocp_base = addr & 0xf000; | |
1042 | if (ocp_base != tp->ocp_base) { | |
1043 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
1044 | tp->ocp_base = ocp_base; | |
1045 | } | |
1046 | ||
1047 | ocp_index = (addr & 0x0fff) | 0xb000; | |
ac244d3e | 1048 | return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); |
e3fe0b1a | 1049 | } |
1050 | ||
ac244d3e | 1051 | static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) |
ac718b69 | 1052 | { |
ac244d3e | 1053 | u16 ocp_base, ocp_index; |
ac718b69 | 1054 | |
ac244d3e | 1055 | ocp_base = addr & 0xf000; |
1056 | if (ocp_base != tp->ocp_base) { | |
1057 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
1058 | tp->ocp_base = ocp_base; | |
ac718b69 | 1059 | } |
ac244d3e | 1060 | |
1061 | ocp_index = (addr & 0x0fff) | 0xb000; | |
1062 | ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); | |
ac718b69 | 1063 | } |
1064 | ||
ac244d3e | 1065 | static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) |
ac718b69 | 1066 | { |
ac244d3e | 1067 | ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); |
1068 | } | |
ac718b69 | 1069 | |
ac244d3e | 1070 | static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) |
1071 | { | |
1072 | return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); | |
ac718b69 | 1073 | } |
1074 | ||
43779f8d | 1075 | static void sram_write(struct r8152 *tp, u16 addr, u16 data) |
1076 | { | |
1077 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
1078 | ocp_reg_write(tp, OCP_SRAM_DATA, data); | |
1079 | } | |
1080 | ||
65b82d69 | 1081 | static u16 sram_read(struct r8152 *tp, u16 addr) |
1082 | { | |
1083 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
1084 | return ocp_reg_read(tp, OCP_SRAM_DATA); | |
1085 | } | |
1086 | ||
ac718b69 | 1087 | static int read_mii_word(struct net_device *netdev, int phy_id, int reg) |
1088 | { | |
1089 | struct r8152 *tp = netdev_priv(netdev); | |
9a4be1bd | 1090 | int ret; |
ac718b69 | 1091 | |
6871438c | 1092 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1093 | return -ENODEV; | |
1094 | ||
ac718b69 | 1095 | if (phy_id != R8152_PHY_ID) |
1096 | return -EINVAL; | |
1097 | ||
9a4be1bd | 1098 | ret = r8152_mdio_read(tp, reg); |
1099 | ||
9a4be1bd | 1100 | return ret; |
ac718b69 | 1101 | } |
1102 | ||
1103 | static | |
1104 | void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) | |
1105 | { | |
1106 | struct r8152 *tp = netdev_priv(netdev); | |
1107 | ||
6871438c | 1108 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1109 | return; | |
1110 | ||
ac718b69 | 1111 | if (phy_id != R8152_PHY_ID) |
1112 | return; | |
1113 | ||
1114 | r8152_mdio_write(tp, reg, val); | |
1115 | } | |
1116 | ||
b209af99 | 1117 | static int |
1118 | r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); | |
ebc2ec48 | 1119 | |
8ba789ab | 1120 | static int rtl8152_set_mac_address(struct net_device *netdev, void *p) |
1121 | { | |
1122 | struct r8152 *tp = netdev_priv(netdev); | |
1123 | struct sockaddr *addr = p; | |
ea6a7112 | 1124 | int ret = -EADDRNOTAVAIL; |
8ba789ab | 1125 | |
1126 | if (!is_valid_ether_addr(addr->sa_data)) | |
ea6a7112 | 1127 | goto out1; |
1128 | ||
1129 | ret = usb_autopm_get_interface(tp->intf); | |
1130 | if (ret < 0) | |
1131 | goto out1; | |
8ba789ab | 1132 | |
b5403273 | 1133 | mutex_lock(&tp->control); |
1134 | ||
8ba789ab | 1135 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); |
1136 | ||
1137 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
1138 | pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); | |
1139 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
1140 | ||
b5403273 | 1141 | mutex_unlock(&tp->control); |
1142 | ||
ea6a7112 | 1143 | usb_autopm_put_interface(tp->intf); |
1144 | out1: | |
1145 | return ret; | |
8ba789ab | 1146 | } |
1147 | ||
34ee32c9 ML |
1148 | /* Devices containing RTL8153-AD can support a persistent |
1149 | * host system provided MAC address. | |
1150 | * Examples of this are Dell TB15 and Dell WD15 docks | |
1151 | */ | |
1152 | static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa) | |
1153 | { | |
1154 | acpi_status status; | |
1155 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
1156 | union acpi_object *obj; | |
1157 | int ret = -EINVAL; | |
1158 | u32 ocp_data; | |
1159 | unsigned char buf[6]; | |
1160 | ||
1161 | /* test for -AD variant of RTL8153 */ | |
1162 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
1163 | if ((ocp_data & AD_MASK) != 0x1000) | |
1164 | return -ENODEV; | |
1165 | ||
1166 | /* test for MAC address pass-through bit */ | |
1167 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE); | |
1168 | if ((ocp_data & PASS_THRU_MASK) != 1) | |
1169 | return -ENODEV; | |
1170 | ||
1171 | /* returns _AUXMAC_#AABBCCDDEEFF# */ | |
1172 | status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer); | |
1173 | obj = (union acpi_object *)buffer.pointer; | |
1174 | if (!ACPI_SUCCESS(status)) | |
1175 | return -ENODEV; | |
1176 | if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) { | |
1177 | netif_warn(tp, probe, tp->netdev, | |
53700f0c | 1178 | "Invalid buffer for pass-thru MAC addr: (%d, %d)\n", |
34ee32c9 ML |
1179 | obj->type, obj->string.length); |
1180 | goto amacout; | |
1181 | } | |
1182 | if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 || | |
1183 | strncmp(obj->string.pointer + 0x15, "#", 1) != 0) { | |
1184 | netif_warn(tp, probe, tp->netdev, | |
1185 | "Invalid header when reading pass-thru MAC addr\n"); | |
1186 | goto amacout; | |
1187 | } | |
1188 | ret = hex2bin(buf, obj->string.pointer + 9, 6); | |
1189 | if (!(ret == 0 && is_valid_ether_addr(buf))) { | |
1190 | netif_warn(tp, probe, tp->netdev, | |
53700f0c | 1191 | "Invalid MAC for pass-thru MAC addr: %d, %pM\n", |
1192 | ret, buf); | |
34ee32c9 ML |
1193 | ret = -EINVAL; |
1194 | goto amacout; | |
1195 | } | |
1196 | memcpy(sa->sa_data, buf, 6); | |
1197 | ether_addr_copy(tp->netdev->dev_addr, sa->sa_data); | |
1198 | netif_info(tp, probe, tp->netdev, | |
1199 | "Using pass-thru MAC addr %pM\n", sa->sa_data); | |
1200 | ||
1201 | amacout: | |
1202 | kfree(obj); | |
1203 | return ret; | |
1204 | } | |
1205 | ||
179bb6d7 | 1206 | static int set_ethernet_addr(struct r8152 *tp) |
ac718b69 | 1207 | { |
1208 | struct net_device *dev = tp->netdev; | |
179bb6d7 | 1209 | struct sockaddr sa; |
8a91c824 | 1210 | int ret; |
ac718b69 | 1211 | |
53700f0c | 1212 | if (tp->version == RTL_VER_01) { |
179bb6d7 | 1213 | ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data); |
53700f0c | 1214 | } else { |
34ee32c9 ML |
1215 | /* if this is not an RTL8153-AD, no eFuse mac pass thru set, |
1216 | * or system doesn't provide valid _SB.AMAC this will be | |
1217 | * be expected to non-zero | |
1218 | */ | |
1219 | ret = vendor_mac_passthru_addr_read(tp, &sa); | |
1220 | if (ret < 0) | |
1221 | ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data); | |
1222 | } | |
8a91c824 | 1223 | |
1224 | if (ret < 0) { | |
179bb6d7 | 1225 | netif_err(tp, probe, dev, "Get ether addr fail\n"); |
1226 | } else if (!is_valid_ether_addr(sa.sa_data)) { | |
1227 | netif_err(tp, probe, dev, "Invalid ether addr %pM\n", | |
1228 | sa.sa_data); | |
1229 | eth_hw_addr_random(dev); | |
1230 | ether_addr_copy(sa.sa_data, dev->dev_addr); | |
1231 | ret = rtl8152_set_mac_address(dev, &sa); | |
1232 | netif_info(tp, probe, dev, "Random ether addr %pM\n", | |
1233 | sa.sa_data); | |
8a91c824 | 1234 | } else { |
179bb6d7 | 1235 | if (tp->version == RTL_VER_01) |
1236 | ether_addr_copy(dev->dev_addr, sa.sa_data); | |
1237 | else | |
1238 | ret = rtl8152_set_mac_address(dev, &sa); | |
ac718b69 | 1239 | } |
179bb6d7 | 1240 | |
1241 | return ret; | |
ac718b69 | 1242 | } |
1243 | ||
ac718b69 | 1244 | static void read_bulk_callback(struct urb *urb) |
1245 | { | |
ac718b69 | 1246 | struct net_device *netdev; |
ac718b69 | 1247 | int status = urb->status; |
ebc2ec48 | 1248 | struct rx_agg *agg; |
1249 | struct r8152 *tp; | |
ac718b69 | 1250 | |
ebc2ec48 | 1251 | agg = urb->context; |
1252 | if (!agg) | |
1253 | return; | |
1254 | ||
1255 | tp = agg->context; | |
ac718b69 | 1256 | if (!tp) |
1257 | return; | |
ebc2ec48 | 1258 | |
ac718b69 | 1259 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1260 | return; | |
ebc2ec48 | 1261 | |
1262 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1263 | return; | |
1264 | ||
ac718b69 | 1265 | netdev = tp->netdev; |
7559fb2f | 1266 | |
1267 | /* When link down, the driver would cancel all bulks. */ | |
1268 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 1269 | if (!netif_carrier_ok(netdev)) |
ac718b69 | 1270 | return; |
1271 | ||
9a4be1bd | 1272 | usb_mark_last_busy(tp->udev); |
1273 | ||
ac718b69 | 1274 | switch (status) { |
1275 | case 0: | |
ebc2ec48 | 1276 | if (urb->actual_length < ETH_ZLEN) |
1277 | break; | |
1278 | ||
2685d410 | 1279 | spin_lock(&tp->rx_lock); |
ebc2ec48 | 1280 | list_add_tail(&agg->list, &tp->rx_done); |
2685d410 | 1281 | spin_unlock(&tp->rx_lock); |
d823ab68 | 1282 | napi_schedule(&tp->napi); |
ebc2ec48 | 1283 | return; |
ac718b69 | 1284 | case -ESHUTDOWN: |
1285 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
1286 | netif_device_detach(tp->netdev); | |
ebc2ec48 | 1287 | return; |
ac718b69 | 1288 | case -ENOENT: |
1289 | return; /* the urb is in unlink state */ | |
1290 | case -ETIME: | |
4a8deae2 HW |
1291 | if (net_ratelimit()) |
1292 | netdev_warn(netdev, "maybe reset is needed?\n"); | |
ebc2ec48 | 1293 | break; |
ac718b69 | 1294 | default: |
4a8deae2 HW |
1295 | if (net_ratelimit()) |
1296 | netdev_warn(netdev, "Rx status %d\n", status); | |
ebc2ec48 | 1297 | break; |
ac718b69 | 1298 | } |
1299 | ||
a0fccd48 | 1300 | r8152_submit_rx(tp, agg, GFP_ATOMIC); |
ac718b69 | 1301 | } |
1302 | ||
ebc2ec48 | 1303 | static void write_bulk_callback(struct urb *urb) |
ac718b69 | 1304 | { |
ebc2ec48 | 1305 | struct net_device_stats *stats; |
d104eafa | 1306 | struct net_device *netdev; |
ebc2ec48 | 1307 | struct tx_agg *agg; |
ac718b69 | 1308 | struct r8152 *tp; |
ebc2ec48 | 1309 | int status = urb->status; |
ac718b69 | 1310 | |
ebc2ec48 | 1311 | agg = urb->context; |
1312 | if (!agg) | |
ac718b69 | 1313 | return; |
1314 | ||
ebc2ec48 | 1315 | tp = agg->context; |
1316 | if (!tp) | |
1317 | return; | |
1318 | ||
d104eafa | 1319 | netdev = tp->netdev; |
05e0f1aa | 1320 | stats = &netdev->stats; |
ebc2ec48 | 1321 | if (status) { |
4a8deae2 | 1322 | if (net_ratelimit()) |
d104eafa | 1323 | netdev_warn(netdev, "Tx status %d\n", status); |
ebc2ec48 | 1324 | stats->tx_errors += agg->skb_num; |
ac718b69 | 1325 | } else { |
ebc2ec48 | 1326 | stats->tx_packets += agg->skb_num; |
1327 | stats->tx_bytes += agg->skb_len; | |
ac718b69 | 1328 | } |
1329 | ||
2685d410 | 1330 | spin_lock(&tp->tx_lock); |
ebc2ec48 | 1331 | list_add_tail(&agg->list, &tp->tx_free); |
2685d410 | 1332 | spin_unlock(&tp->tx_lock); |
ebc2ec48 | 1333 | |
9a4be1bd | 1334 | usb_autopm_put_interface_async(tp->intf); |
1335 | ||
d104eafa | 1336 | if (!netif_carrier_ok(netdev)) |
ebc2ec48 | 1337 | return; |
1338 | ||
1339 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1340 | return; | |
1341 | ||
1342 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1343 | return; | |
1344 | ||
1345 | if (!skb_queue_empty(&tp->tx_queue)) | |
d823ab68 | 1346 | napi_schedule(&tp->napi); |
ac718b69 | 1347 | } |
1348 | ||
40a82917 | 1349 | static void intr_callback(struct urb *urb) |
1350 | { | |
1351 | struct r8152 *tp; | |
500b6d7e | 1352 | __le16 *d; |
40a82917 | 1353 | int status = urb->status; |
1354 | int res; | |
1355 | ||
1356 | tp = urb->context; | |
1357 | if (!tp) | |
1358 | return; | |
1359 | ||
1360 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1361 | return; | |
1362 | ||
1363 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1364 | return; | |
1365 | ||
1366 | switch (status) { | |
1367 | case 0: /* success */ | |
1368 | break; | |
1369 | case -ECONNRESET: /* unlink */ | |
1370 | case -ESHUTDOWN: | |
1371 | netif_device_detach(tp->netdev); | |
1372 | case -ENOENT: | |
d59c876d | 1373 | case -EPROTO: |
1374 | netif_info(tp, intr, tp->netdev, | |
1375 | "Stop submitting intr, status %d\n", status); | |
40a82917 | 1376 | return; |
1377 | case -EOVERFLOW: | |
1378 | netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); | |
1379 | goto resubmit; | |
1380 | /* -EPIPE: should clear the halt */ | |
1381 | default: | |
1382 | netif_info(tp, intr, tp->netdev, "intr status %d\n", status); | |
1383 | goto resubmit; | |
1384 | } | |
1385 | ||
1386 | d = urb->transfer_buffer; | |
1387 | if (INTR_LINK & __le16_to_cpu(d[0])) { | |
51d979fa | 1388 | if (!netif_carrier_ok(tp->netdev)) { |
40a82917 | 1389 | set_bit(RTL8152_LINK_CHG, &tp->flags); |
1390 | schedule_delayed_work(&tp->schedule, 0); | |
1391 | } | |
1392 | } else { | |
51d979fa | 1393 | if (netif_carrier_ok(tp->netdev)) { |
2f25abe6 | 1394 | netif_stop_queue(tp->netdev); |
40a82917 | 1395 | set_bit(RTL8152_LINK_CHG, &tp->flags); |
1396 | schedule_delayed_work(&tp->schedule, 0); | |
1397 | } | |
1398 | } | |
1399 | ||
1400 | resubmit: | |
1401 | res = usb_submit_urb(urb, GFP_ATOMIC); | |
67610496 | 1402 | if (res == -ENODEV) { |
1403 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
40a82917 | 1404 | netif_device_detach(tp->netdev); |
67610496 | 1405 | } else if (res) { |
40a82917 | 1406 | netif_err(tp, intr, tp->netdev, |
4a8deae2 | 1407 | "can't resubmit intr, status %d\n", res); |
67610496 | 1408 | } |
40a82917 | 1409 | } |
1410 | ||
ebc2ec48 | 1411 | static inline void *rx_agg_align(void *data) |
1412 | { | |
8e1f51bd | 1413 | return (void *)ALIGN((uintptr_t)data, RX_ALIGN); |
ebc2ec48 | 1414 | } |
1415 | ||
1416 | static inline void *tx_agg_align(void *data) | |
1417 | { | |
8e1f51bd | 1418 | return (void *)ALIGN((uintptr_t)data, TX_ALIGN); |
ebc2ec48 | 1419 | } |
1420 | ||
1421 | static void free_all_mem(struct r8152 *tp) | |
1422 | { | |
1423 | int i; | |
1424 | ||
1425 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
9629e3c0 | 1426 | usb_free_urb(tp->rx_info[i].urb); |
1427 | tp->rx_info[i].urb = NULL; | |
ebc2ec48 | 1428 | |
9629e3c0 | 1429 | kfree(tp->rx_info[i].buffer); |
1430 | tp->rx_info[i].buffer = NULL; | |
1431 | tp->rx_info[i].head = NULL; | |
ebc2ec48 | 1432 | } |
1433 | ||
1434 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
9629e3c0 | 1435 | usb_free_urb(tp->tx_info[i].urb); |
1436 | tp->tx_info[i].urb = NULL; | |
ebc2ec48 | 1437 | |
9629e3c0 | 1438 | kfree(tp->tx_info[i].buffer); |
1439 | tp->tx_info[i].buffer = NULL; | |
1440 | tp->tx_info[i].head = NULL; | |
ebc2ec48 | 1441 | } |
40a82917 | 1442 | |
9629e3c0 | 1443 | usb_free_urb(tp->intr_urb); |
1444 | tp->intr_urb = NULL; | |
40a82917 | 1445 | |
9629e3c0 | 1446 | kfree(tp->intr_buff); |
1447 | tp->intr_buff = NULL; | |
ebc2ec48 | 1448 | } |
1449 | ||
1450 | static int alloc_all_mem(struct r8152 *tp) | |
1451 | { | |
1452 | struct net_device *netdev = tp->netdev; | |
40a82917 | 1453 | struct usb_interface *intf = tp->intf; |
1454 | struct usb_host_interface *alt = intf->cur_altsetting; | |
1455 | struct usb_host_endpoint *ep_intr = alt->endpoint + 2; | |
ebc2ec48 | 1456 | struct urb *urb; |
1457 | int node, i; | |
1458 | u8 *buf; | |
1459 | ||
1460 | node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; | |
1461 | ||
1462 | spin_lock_init(&tp->rx_lock); | |
1463 | spin_lock_init(&tp->tx_lock); | |
ebc2ec48 | 1464 | INIT_LIST_HEAD(&tp->tx_free); |
98d068ab | 1465 | INIT_LIST_HEAD(&tp->rx_done); |
ebc2ec48 | 1466 | skb_queue_head_init(&tp->tx_queue); |
d823ab68 | 1467 | skb_queue_head_init(&tp->rx_queue); |
ebc2ec48 | 1468 | |
1469 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
52aec126 | 1470 | buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); |
ebc2ec48 | 1471 | if (!buf) |
1472 | goto err1; | |
1473 | ||
1474 | if (buf != rx_agg_align(buf)) { | |
1475 | kfree(buf); | |
52aec126 | 1476 | buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL, |
8e1f51bd | 1477 | node); |
ebc2ec48 | 1478 | if (!buf) |
1479 | goto err1; | |
1480 | } | |
1481 | ||
1482 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1483 | if (!urb) { | |
1484 | kfree(buf); | |
1485 | goto err1; | |
1486 | } | |
1487 | ||
1488 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
1489 | tp->rx_info[i].context = tp; | |
1490 | tp->rx_info[i].urb = urb; | |
1491 | tp->rx_info[i].buffer = buf; | |
1492 | tp->rx_info[i].head = rx_agg_align(buf); | |
1493 | } | |
1494 | ||
1495 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
52aec126 | 1496 | buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); |
ebc2ec48 | 1497 | if (!buf) |
1498 | goto err1; | |
1499 | ||
1500 | if (buf != tx_agg_align(buf)) { | |
1501 | kfree(buf); | |
52aec126 | 1502 | buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, |
8e1f51bd | 1503 | node); |
ebc2ec48 | 1504 | if (!buf) |
1505 | goto err1; | |
1506 | } | |
1507 | ||
1508 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1509 | if (!urb) { | |
1510 | kfree(buf); | |
1511 | goto err1; | |
1512 | } | |
1513 | ||
1514 | INIT_LIST_HEAD(&tp->tx_info[i].list); | |
1515 | tp->tx_info[i].context = tp; | |
1516 | tp->tx_info[i].urb = urb; | |
1517 | tp->tx_info[i].buffer = buf; | |
1518 | tp->tx_info[i].head = tx_agg_align(buf); | |
1519 | ||
1520 | list_add_tail(&tp->tx_info[i].list, &tp->tx_free); | |
1521 | } | |
1522 | ||
40a82917 | 1523 | tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); |
1524 | if (!tp->intr_urb) | |
1525 | goto err1; | |
1526 | ||
1527 | tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); | |
1528 | if (!tp->intr_buff) | |
1529 | goto err1; | |
1530 | ||
1531 | tp->intr_interval = (int)ep_intr->desc.bInterval; | |
1532 | usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), | |
b209af99 | 1533 | tp->intr_buff, INTBUFSIZE, intr_callback, |
1534 | tp, tp->intr_interval); | |
40a82917 | 1535 | |
ebc2ec48 | 1536 | return 0; |
1537 | ||
1538 | err1: | |
1539 | free_all_mem(tp); | |
1540 | return -ENOMEM; | |
1541 | } | |
1542 | ||
0de98f6c | 1543 | static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) |
1544 | { | |
1545 | struct tx_agg *agg = NULL; | |
1546 | unsigned long flags; | |
1547 | ||
21949ab7 | 1548 | if (list_empty(&tp->tx_free)) |
1549 | return NULL; | |
1550 | ||
0de98f6c | 1551 | spin_lock_irqsave(&tp->tx_lock, flags); |
1552 | if (!list_empty(&tp->tx_free)) { | |
1553 | struct list_head *cursor; | |
1554 | ||
1555 | cursor = tp->tx_free.next; | |
1556 | list_del_init(cursor); | |
1557 | agg = list_entry(cursor, struct tx_agg, list); | |
1558 | } | |
1559 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1560 | ||
1561 | return agg; | |
1562 | } | |
1563 | ||
b209af99 | 1564 | /* r8152_csum_workaround() |
6128d1bb | 1565 | * The hw limites the value the transport offset. When the offset is out of the |
1566 | * range, calculate the checksum by sw. | |
1567 | */ | |
1568 | static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, | |
1569 | struct sk_buff_head *list) | |
1570 | { | |
1571 | if (skb_shinfo(skb)->gso_size) { | |
1572 | netdev_features_t features = tp->netdev->features; | |
1573 | struct sk_buff_head seg_list; | |
1574 | struct sk_buff *segs, *nskb; | |
1575 | ||
a91d45f1 | 1576 | features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); |
6128d1bb | 1577 | segs = skb_gso_segment(skb, features); |
1578 | if (IS_ERR(segs) || !segs) | |
1579 | goto drop; | |
1580 | ||
1581 | __skb_queue_head_init(&seg_list); | |
1582 | ||
1583 | do { | |
1584 | nskb = segs; | |
1585 | segs = segs->next; | |
1586 | nskb->next = NULL; | |
1587 | __skb_queue_tail(&seg_list, nskb); | |
1588 | } while (segs); | |
1589 | ||
1590 | skb_queue_splice(&seg_list, list); | |
1591 | dev_kfree_skb(skb); | |
1592 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1593 | if (skb_checksum_help(skb) < 0) | |
1594 | goto drop; | |
1595 | ||
1596 | __skb_queue_head(list, skb); | |
1597 | } else { | |
1598 | struct net_device_stats *stats; | |
1599 | ||
1600 | drop: | |
1601 | stats = &tp->netdev->stats; | |
1602 | stats->tx_dropped++; | |
1603 | dev_kfree_skb(skb); | |
1604 | } | |
1605 | } | |
1606 | ||
b209af99 | 1607 | /* msdn_giant_send_check() |
6128d1bb | 1608 | * According to the document of microsoft, the TCP Pseudo Header excludes the |
1609 | * packet length for IPv6 TCP large packets. | |
1610 | */ | |
1611 | static int msdn_giant_send_check(struct sk_buff *skb) | |
1612 | { | |
1613 | const struct ipv6hdr *ipv6h; | |
1614 | struct tcphdr *th; | |
fcb308d5 | 1615 | int ret; |
1616 | ||
1617 | ret = skb_cow_head(skb, 0); | |
1618 | if (ret) | |
1619 | return ret; | |
6128d1bb | 1620 | |
1621 | ipv6h = ipv6_hdr(skb); | |
1622 | th = tcp_hdr(skb); | |
1623 | ||
1624 | th->check = 0; | |
1625 | th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); | |
1626 | ||
fcb308d5 | 1627 | return ret; |
6128d1bb | 1628 | } |
1629 | ||
c5554298 | 1630 | static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) |
1631 | { | |
df8a39de | 1632 | if (skb_vlan_tag_present(skb)) { |
c5554298 | 1633 | u32 opts2; |
1634 | ||
df8a39de | 1635 | opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb)); |
c5554298 | 1636 | desc->opts2 |= cpu_to_le32(opts2); |
1637 | } | |
1638 | } | |
1639 | ||
1640 | static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) | |
1641 | { | |
1642 | u32 opts2 = le32_to_cpu(desc->opts2); | |
1643 | ||
1644 | if (opts2 & RX_VLAN_TAG) | |
1645 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), | |
1646 | swab16(opts2 & 0xffff)); | |
1647 | } | |
1648 | ||
60c89071 | 1649 | static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, |
1650 | struct sk_buff *skb, u32 len, u32 transport_offset) | |
1651 | { | |
1652 | u32 mss = skb_shinfo(skb)->gso_size; | |
1653 | u32 opts1, opts2 = 0; | |
1654 | int ret = TX_CSUM_SUCCESS; | |
1655 | ||
1656 | WARN_ON_ONCE(len > TX_LEN_MAX); | |
1657 | ||
1658 | opts1 = len | TX_FS | TX_LS; | |
1659 | ||
1660 | if (mss) { | |
6128d1bb | 1661 | if (transport_offset > GTTCPHO_MAX) { |
1662 | netif_warn(tp, tx_err, tp->netdev, | |
1663 | "Invalid transport offset 0x%x for TSO\n", | |
1664 | transport_offset); | |
1665 | ret = TX_CSUM_TSO; | |
1666 | goto unavailable; | |
1667 | } | |
1668 | ||
6e74d174 | 1669 | switch (vlan_get_protocol(skb)) { |
60c89071 | 1670 | case htons(ETH_P_IP): |
1671 | opts1 |= GTSENDV4; | |
1672 | break; | |
1673 | ||
6128d1bb | 1674 | case htons(ETH_P_IPV6): |
fcb308d5 | 1675 | if (msdn_giant_send_check(skb)) { |
1676 | ret = TX_CSUM_TSO; | |
1677 | goto unavailable; | |
1678 | } | |
6128d1bb | 1679 | opts1 |= GTSENDV6; |
6128d1bb | 1680 | break; |
1681 | ||
60c89071 | 1682 | default: |
1683 | WARN_ON_ONCE(1); | |
1684 | break; | |
1685 | } | |
1686 | ||
1687 | opts1 |= transport_offset << GTTCPHO_SHIFT; | |
1688 | opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; | |
1689 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1690 | u8 ip_protocol; | |
5bd23881 | 1691 | |
6128d1bb | 1692 | if (transport_offset > TCPHO_MAX) { |
1693 | netif_warn(tp, tx_err, tp->netdev, | |
1694 | "Invalid transport offset 0x%x\n", | |
1695 | transport_offset); | |
1696 | ret = TX_CSUM_NONE; | |
1697 | goto unavailable; | |
1698 | } | |
1699 | ||
6e74d174 | 1700 | switch (vlan_get_protocol(skb)) { |
5bd23881 | 1701 | case htons(ETH_P_IP): |
1702 | opts2 |= IPV4_CS; | |
1703 | ip_protocol = ip_hdr(skb)->protocol; | |
1704 | break; | |
1705 | ||
1706 | case htons(ETH_P_IPV6): | |
1707 | opts2 |= IPV6_CS; | |
1708 | ip_protocol = ipv6_hdr(skb)->nexthdr; | |
1709 | break; | |
1710 | ||
1711 | default: | |
1712 | ip_protocol = IPPROTO_RAW; | |
1713 | break; | |
1714 | } | |
1715 | ||
60c89071 | 1716 | if (ip_protocol == IPPROTO_TCP) |
5bd23881 | 1717 | opts2 |= TCP_CS; |
60c89071 | 1718 | else if (ip_protocol == IPPROTO_UDP) |
5bd23881 | 1719 | opts2 |= UDP_CS; |
60c89071 | 1720 | else |
5bd23881 | 1721 | WARN_ON_ONCE(1); |
5bd23881 | 1722 | |
60c89071 | 1723 | opts2 |= transport_offset << TCPHO_SHIFT; |
5bd23881 | 1724 | } |
60c89071 | 1725 | |
1726 | desc->opts2 = cpu_to_le32(opts2); | |
1727 | desc->opts1 = cpu_to_le32(opts1); | |
1728 | ||
6128d1bb | 1729 | unavailable: |
60c89071 | 1730 | return ret; |
5bd23881 | 1731 | } |
1732 | ||
b1379d9a | 1733 | static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) |
1734 | { | |
d84130a1 | 1735 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
9a4be1bd | 1736 | int remain, ret; |
b1379d9a | 1737 | u8 *tx_data; |
1738 | ||
d84130a1 | 1739 | __skb_queue_head_init(&skb_head); |
0c3121fc | 1740 | spin_lock(&tx_queue->lock); |
d84130a1 | 1741 | skb_queue_splice_init(tx_queue, &skb_head); |
0c3121fc | 1742 | spin_unlock(&tx_queue->lock); |
d84130a1 | 1743 | |
b1379d9a | 1744 | tx_data = agg->head; |
b209af99 | 1745 | agg->skb_num = 0; |
1746 | agg->skb_len = 0; | |
52aec126 | 1747 | remain = agg_buf_sz; |
b1379d9a | 1748 | |
7937f9e5 | 1749 | while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { |
b1379d9a | 1750 | struct tx_desc *tx_desc; |
1751 | struct sk_buff *skb; | |
1752 | unsigned int len; | |
60c89071 | 1753 | u32 offset; |
b1379d9a | 1754 | |
d84130a1 | 1755 | skb = __skb_dequeue(&skb_head); |
b1379d9a | 1756 | if (!skb) |
1757 | break; | |
1758 | ||
60c89071 | 1759 | len = skb->len + sizeof(*tx_desc); |
1760 | ||
1761 | if (len > remain) { | |
d84130a1 | 1762 | __skb_queue_head(&skb_head, skb); |
b1379d9a | 1763 | break; |
1764 | } | |
1765 | ||
7937f9e5 | 1766 | tx_data = tx_agg_align(tx_data); |
b1379d9a | 1767 | tx_desc = (struct tx_desc *)tx_data; |
60c89071 | 1768 | |
1769 | offset = (u32)skb_transport_offset(skb); | |
1770 | ||
6128d1bb | 1771 | if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { |
1772 | r8152_csum_workaround(tp, skb, &skb_head); | |
1773 | continue; | |
1774 | } | |
60c89071 | 1775 | |
c5554298 | 1776 | rtl_tx_vlan_tag(tx_desc, skb); |
1777 | ||
b1379d9a | 1778 | tx_data += sizeof(*tx_desc); |
1779 | ||
60c89071 | 1780 | len = skb->len; |
1781 | if (skb_copy_bits(skb, 0, tx_data, len) < 0) { | |
1782 | struct net_device_stats *stats = &tp->netdev->stats; | |
1783 | ||
1784 | stats->tx_dropped++; | |
1785 | dev_kfree_skb_any(skb); | |
1786 | tx_data -= sizeof(*tx_desc); | |
1787 | continue; | |
1788 | } | |
1789 | ||
1790 | tx_data += len; | |
b1379d9a | 1791 | agg->skb_len += len; |
60c89071 | 1792 | agg->skb_num++; |
1793 | ||
b1379d9a | 1794 | dev_kfree_skb_any(skb); |
1795 | ||
52aec126 | 1796 | remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); |
b1379d9a | 1797 | } |
1798 | ||
d84130a1 | 1799 | if (!skb_queue_empty(&skb_head)) { |
0c3121fc | 1800 | spin_lock(&tx_queue->lock); |
d84130a1 | 1801 | skb_queue_splice(&skb_head, tx_queue); |
0c3121fc | 1802 | spin_unlock(&tx_queue->lock); |
d84130a1 | 1803 | } |
1804 | ||
0c3121fc | 1805 | netif_tx_lock(tp->netdev); |
dd1b119c | 1806 | |
1807 | if (netif_queue_stopped(tp->netdev) && | |
1808 | skb_queue_len(&tp->tx_queue) < tp->tx_qlen) | |
1809 | netif_wake_queue(tp->netdev); | |
1810 | ||
0c3121fc | 1811 | netif_tx_unlock(tp->netdev); |
9a4be1bd | 1812 | |
0c3121fc | 1813 | ret = usb_autopm_get_interface_async(tp->intf); |
9a4be1bd | 1814 | if (ret < 0) |
1815 | goto out_tx_fill; | |
dd1b119c | 1816 | |
b1379d9a | 1817 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), |
1818 | agg->head, (int)(tx_data - (u8 *)agg->head), | |
1819 | (usb_complete_t)write_bulk_callback, agg); | |
1820 | ||
0c3121fc | 1821 | ret = usb_submit_urb(agg->urb, GFP_ATOMIC); |
9a4be1bd | 1822 | if (ret < 0) |
0c3121fc | 1823 | usb_autopm_put_interface_async(tp->intf); |
9a4be1bd | 1824 | |
1825 | out_tx_fill: | |
1826 | return ret; | |
b1379d9a | 1827 | } |
1828 | ||
565cab0a | 1829 | static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) |
1830 | { | |
1831 | u8 checksum = CHECKSUM_NONE; | |
1832 | u32 opts2, opts3; | |
1833 | ||
19c0f40d | 1834 | if (!(tp->netdev->features & NETIF_F_RXCSUM)) |
565cab0a | 1835 | goto return_result; |
1836 | ||
1837 | opts2 = le32_to_cpu(rx_desc->opts2); | |
1838 | opts3 = le32_to_cpu(rx_desc->opts3); | |
1839 | ||
1840 | if (opts2 & RD_IPV4_CS) { | |
1841 | if (opts3 & IPF) | |
1842 | checksum = CHECKSUM_NONE; | |
1843 | else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF)) | |
1844 | checksum = CHECKSUM_NONE; | |
1845 | else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF)) | |
1846 | checksum = CHECKSUM_NONE; | |
1847 | else | |
1848 | checksum = CHECKSUM_UNNECESSARY; | |
b9a321b4 | 1849 | } else if (opts2 & RD_IPV6_CS) { |
6128d1bb | 1850 | if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) |
1851 | checksum = CHECKSUM_UNNECESSARY; | |
1852 | else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) | |
1853 | checksum = CHECKSUM_UNNECESSARY; | |
565cab0a | 1854 | } |
1855 | ||
1856 | return_result: | |
1857 | return checksum; | |
1858 | } | |
1859 | ||
d823ab68 | 1860 | static int rx_bottom(struct r8152 *tp, int budget) |
ebc2ec48 | 1861 | { |
a5a4f468 | 1862 | unsigned long flags; |
d84130a1 | 1863 | struct list_head *cursor, *next, rx_queue; |
e1a2ca92 | 1864 | int ret = 0, work_done = 0; |
ce594e98 | 1865 | struct napi_struct *napi = &tp->napi; |
d823ab68 | 1866 | |
1867 | if (!skb_queue_empty(&tp->rx_queue)) { | |
1868 | while (work_done < budget) { | |
1869 | struct sk_buff *skb = __skb_dequeue(&tp->rx_queue); | |
1870 | struct net_device *netdev = tp->netdev; | |
1871 | struct net_device_stats *stats = &netdev->stats; | |
1872 | unsigned int pkt_len; | |
1873 | ||
1874 | if (!skb) | |
1875 | break; | |
1876 | ||
1877 | pkt_len = skb->len; | |
ce594e98 | 1878 | napi_gro_receive(napi, skb); |
d823ab68 | 1879 | work_done++; |
1880 | stats->rx_packets++; | |
1881 | stats->rx_bytes += pkt_len; | |
1882 | } | |
1883 | } | |
ebc2ec48 | 1884 | |
d84130a1 | 1885 | if (list_empty(&tp->rx_done)) |
d823ab68 | 1886 | goto out1; |
d84130a1 | 1887 | |
1888 | INIT_LIST_HEAD(&rx_queue); | |
a5a4f468 | 1889 | spin_lock_irqsave(&tp->rx_lock, flags); |
d84130a1 | 1890 | list_splice_init(&tp->rx_done, &rx_queue); |
1891 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
1892 | ||
1893 | list_for_each_safe(cursor, next, &rx_queue) { | |
43a4478d | 1894 | struct rx_desc *rx_desc; |
1895 | struct rx_agg *agg; | |
43a4478d | 1896 | int len_used = 0; |
1897 | struct urb *urb; | |
1898 | u8 *rx_data; | |
43a4478d | 1899 | |
ebc2ec48 | 1900 | list_del_init(cursor); |
ebc2ec48 | 1901 | |
1902 | agg = list_entry(cursor, struct rx_agg, list); | |
1903 | urb = agg->urb; | |
0de98f6c | 1904 | if (urb->actual_length < ETH_ZLEN) |
1905 | goto submit; | |
ebc2ec48 | 1906 | |
ebc2ec48 | 1907 | rx_desc = agg->head; |
1908 | rx_data = agg->head; | |
7937f9e5 | 1909 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1910 | |
7937f9e5 | 1911 | while (urb->actual_length > len_used) { |
43a4478d | 1912 | struct net_device *netdev = tp->netdev; |
05e0f1aa | 1913 | struct net_device_stats *stats = &netdev->stats; |
7937f9e5 | 1914 | unsigned int pkt_len; |
43a4478d | 1915 | struct sk_buff *skb; |
1916 | ||
74544458 | 1917 | /* limite the skb numbers for rx_queue */ |
1918 | if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000)) | |
1919 | break; | |
1920 | ||
7937f9e5 | 1921 | pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; |
ebc2ec48 | 1922 | if (pkt_len < ETH_ZLEN) |
1923 | break; | |
1924 | ||
7937f9e5 | 1925 | len_used += pkt_len; |
1926 | if (urb->actual_length < len_used) | |
1927 | break; | |
1928 | ||
8e1f51bd | 1929 | pkt_len -= CRC_SIZE; |
ebc2ec48 | 1930 | rx_data += sizeof(struct rx_desc); |
1931 | ||
ce594e98 | 1932 | skb = napi_alloc_skb(napi, pkt_len); |
ebc2ec48 | 1933 | if (!skb) { |
1934 | stats->rx_dropped++; | |
5e2f7485 | 1935 | goto find_next_rx; |
ebc2ec48 | 1936 | } |
565cab0a | 1937 | |
1938 | skb->ip_summed = r8152_rx_csum(tp, rx_desc); | |
ebc2ec48 | 1939 | memcpy(skb->data, rx_data, pkt_len); |
1940 | skb_put(skb, pkt_len); | |
1941 | skb->protocol = eth_type_trans(skb, netdev); | |
c5554298 | 1942 | rtl_rx_vlan_tag(rx_desc, skb); |
d823ab68 | 1943 | if (work_done < budget) { |
ce594e98 | 1944 | napi_gro_receive(napi, skb); |
d823ab68 | 1945 | work_done++; |
1946 | stats->rx_packets++; | |
1947 | stats->rx_bytes += pkt_len; | |
1948 | } else { | |
1949 | __skb_queue_tail(&tp->rx_queue, skb); | |
1950 | } | |
ebc2ec48 | 1951 | |
5e2f7485 | 1952 | find_next_rx: |
8e1f51bd | 1953 | rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE); |
ebc2ec48 | 1954 | rx_desc = (struct rx_desc *)rx_data; |
ebc2ec48 | 1955 | len_used = (int)(rx_data - (u8 *)agg->head); |
7937f9e5 | 1956 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1957 | } |
1958 | ||
0de98f6c | 1959 | submit: |
e1a2ca92 | 1960 | if (!ret) { |
1961 | ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); | |
1962 | } else { | |
1963 | urb->actual_length = 0; | |
1964 | list_add_tail(&agg->list, next); | |
1965 | } | |
1966 | } | |
1967 | ||
1968 | if (!list_empty(&rx_queue)) { | |
1969 | spin_lock_irqsave(&tp->rx_lock, flags); | |
1970 | list_splice_tail(&rx_queue, &tp->rx_done); | |
1971 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
ebc2ec48 | 1972 | } |
d823ab68 | 1973 | |
1974 | out1: | |
1975 | return work_done; | |
ebc2ec48 | 1976 | } |
1977 | ||
1978 | static void tx_bottom(struct r8152 *tp) | |
1979 | { | |
ebc2ec48 | 1980 | int res; |
1981 | ||
b1379d9a | 1982 | do { |
1983 | struct tx_agg *agg; | |
ebc2ec48 | 1984 | |
b1379d9a | 1985 | if (skb_queue_empty(&tp->tx_queue)) |
ebc2ec48 | 1986 | break; |
1987 | ||
b1379d9a | 1988 | agg = r8152_get_tx_agg(tp); |
1989 | if (!agg) | |
ebc2ec48 | 1990 | break; |
ebc2ec48 | 1991 | |
b1379d9a | 1992 | res = r8152_tx_agg_fill(tp, agg); |
1993 | if (res) { | |
05e0f1aa | 1994 | struct net_device *netdev = tp->netdev; |
ebc2ec48 | 1995 | |
b1379d9a | 1996 | if (res == -ENODEV) { |
67610496 | 1997 | set_bit(RTL8152_UNPLUG, &tp->flags); |
b1379d9a | 1998 | netif_device_detach(netdev); |
1999 | } else { | |
05e0f1aa | 2000 | struct net_device_stats *stats = &netdev->stats; |
2001 | unsigned long flags; | |
2002 | ||
b1379d9a | 2003 | netif_warn(tp, tx_err, netdev, |
2004 | "failed tx_urb %d\n", res); | |
2005 | stats->tx_dropped += agg->skb_num; | |
db8515ef | 2006 | |
b1379d9a | 2007 | spin_lock_irqsave(&tp->tx_lock, flags); |
2008 | list_add_tail(&agg->list, &tp->tx_free); | |
2009 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
2010 | } | |
ebc2ec48 | 2011 | } |
b1379d9a | 2012 | } while (res == 0); |
ebc2ec48 | 2013 | } |
2014 | ||
d823ab68 | 2015 | static void bottom_half(struct r8152 *tp) |
ac718b69 | 2016 | { |
ebc2ec48 | 2017 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
2018 | return; | |
2019 | ||
2020 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
ac718b69 | 2021 | return; |
ebc2ec48 | 2022 | |
7559fb2f | 2023 | /* When link down, the driver would cancel all bulks. */ |
2024 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 2025 | if (!netif_carrier_ok(tp->netdev)) |
ac718b69 | 2026 | return; |
ebc2ec48 | 2027 | |
d823ab68 | 2028 | clear_bit(SCHEDULE_NAPI, &tp->flags); |
9451a11c | 2029 | |
0c3121fc | 2030 | tx_bottom(tp); |
ebc2ec48 | 2031 | } |
2032 | ||
d823ab68 | 2033 | static int r8152_poll(struct napi_struct *napi, int budget) |
2034 | { | |
2035 | struct r8152 *tp = container_of(napi, struct r8152, napi); | |
2036 | int work_done; | |
2037 | ||
2038 | work_done = rx_bottom(tp, budget); | |
2039 | bottom_half(tp); | |
2040 | ||
2041 | if (work_done < budget) { | |
a3307f9b | 2042 | if (!napi_complete_done(napi, work_done)) |
2043 | goto out; | |
d823ab68 | 2044 | if (!list_empty(&tp->rx_done)) |
2045 | napi_schedule(napi); | |
248b213a | 2046 | else if (!skb_queue_empty(&tp->tx_queue) && |
2047 | !list_empty(&tp->tx_free)) | |
2048 | napi_schedule(napi); | |
d823ab68 | 2049 | } |
2050 | ||
a3307f9b | 2051 | out: |
d823ab68 | 2052 | return work_done; |
2053 | } | |
2054 | ||
ebc2ec48 | 2055 | static |
2056 | int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) | |
2057 | { | |
a0fccd48 | 2058 | int ret; |
2059 | ||
ef827a5b | 2060 | /* The rx would be stopped, so skip submitting */ |
2061 | if (test_bit(RTL8152_UNPLUG, &tp->flags) || | |
2062 | !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev)) | |
2063 | return 0; | |
2064 | ||
ebc2ec48 | 2065 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), |
52aec126 | 2066 | agg->head, agg_buf_sz, |
b209af99 | 2067 | (usb_complete_t)read_bulk_callback, agg); |
ebc2ec48 | 2068 | |
a0fccd48 | 2069 | ret = usb_submit_urb(agg->urb, mem_flags); |
2070 | if (ret == -ENODEV) { | |
2071 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
2072 | netif_device_detach(tp->netdev); | |
2073 | } else if (ret) { | |
2074 | struct urb *urb = agg->urb; | |
2075 | unsigned long flags; | |
2076 | ||
2077 | urb->actual_length = 0; | |
2078 | spin_lock_irqsave(&tp->rx_lock, flags); | |
2079 | list_add_tail(&agg->list, &tp->rx_done); | |
2080 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
d823ab68 | 2081 | |
2082 | netif_err(tp, rx_err, tp->netdev, | |
2083 | "Couldn't submit rx[%p], ret = %d\n", agg, ret); | |
2084 | ||
2085 | napi_schedule(&tp->napi); | |
a0fccd48 | 2086 | } |
2087 | ||
2088 | return ret; | |
ac718b69 | 2089 | } |
2090 | ||
00a5e360 | 2091 | static void rtl_drop_queued_tx(struct r8152 *tp) |
2092 | { | |
2093 | struct net_device_stats *stats = &tp->netdev->stats; | |
d84130a1 | 2094 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
00a5e360 | 2095 | struct sk_buff *skb; |
2096 | ||
d84130a1 | 2097 | if (skb_queue_empty(tx_queue)) |
2098 | return; | |
2099 | ||
2100 | __skb_queue_head_init(&skb_head); | |
2685d410 | 2101 | spin_lock_bh(&tx_queue->lock); |
d84130a1 | 2102 | skb_queue_splice_init(tx_queue, &skb_head); |
2685d410 | 2103 | spin_unlock_bh(&tx_queue->lock); |
d84130a1 | 2104 | |
2105 | while ((skb = __skb_dequeue(&skb_head))) { | |
00a5e360 | 2106 | dev_kfree_skb(skb); |
2107 | stats->tx_dropped++; | |
2108 | } | |
2109 | } | |
2110 | ||
ac718b69 | 2111 | static void rtl8152_tx_timeout(struct net_device *netdev) |
2112 | { | |
2113 | struct r8152 *tp = netdev_priv(netdev); | |
ebc2ec48 | 2114 | |
4a8deae2 | 2115 | netif_warn(tp, tx_err, netdev, "Tx timeout\n"); |
37608f3e | 2116 | |
2117 | usb_queue_reset_device(tp->intf); | |
ac718b69 | 2118 | } |
2119 | ||
2120 | static void rtl8152_set_rx_mode(struct net_device *netdev) | |
2121 | { | |
2122 | struct r8152 *tp = netdev_priv(netdev); | |
2123 | ||
51d979fa | 2124 | if (netif_carrier_ok(netdev)) { |
ac718b69 | 2125 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
40a82917 | 2126 | schedule_delayed_work(&tp->schedule, 0); |
2127 | } | |
ac718b69 | 2128 | } |
2129 | ||
2130 | static void _rtl8152_set_rx_mode(struct net_device *netdev) | |
2131 | { | |
2132 | struct r8152 *tp = netdev_priv(netdev); | |
31787f53 | 2133 | u32 mc_filter[2]; /* Multicast hash filter */ |
2134 | __le32 tmp[2]; | |
ac718b69 | 2135 | u32 ocp_data; |
2136 | ||
ac718b69 | 2137 | netif_stop_queue(netdev); |
2138 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2139 | ocp_data &= ~RCR_ACPT_ALL; | |
2140 | ocp_data |= RCR_AB | RCR_APM; | |
2141 | ||
2142 | if (netdev->flags & IFF_PROMISC) { | |
2143 | /* Unconditionally log net taps. */ | |
2144 | netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); | |
2145 | ocp_data |= RCR_AM | RCR_AAP; | |
b209af99 | 2146 | mc_filter[1] = 0xffffffff; |
2147 | mc_filter[0] = 0xffffffff; | |
ac718b69 | 2148 | } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || |
2149 | (netdev->flags & IFF_ALLMULTI)) { | |
2150 | /* Too many to filter perfectly -- accept all multicasts. */ | |
2151 | ocp_data |= RCR_AM; | |
b209af99 | 2152 | mc_filter[1] = 0xffffffff; |
2153 | mc_filter[0] = 0xffffffff; | |
ac718b69 | 2154 | } else { |
2155 | struct netdev_hw_addr *ha; | |
2156 | ||
b209af99 | 2157 | mc_filter[1] = 0; |
2158 | mc_filter[0] = 0; | |
ac718b69 | 2159 | netdev_for_each_mc_addr(ha, netdev) { |
2160 | int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
b209af99 | 2161 | |
ac718b69 | 2162 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); |
2163 | ocp_data |= RCR_AM; | |
2164 | } | |
2165 | } | |
2166 | ||
31787f53 | 2167 | tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); |
2168 | tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); | |
ac718b69 | 2169 | |
31787f53 | 2170 | pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); |
ac718b69 | 2171 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); |
2172 | netif_wake_queue(netdev); | |
ac718b69 | 2173 | } |
2174 | ||
a5e31255 | 2175 | static netdev_features_t |
2176 | rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, | |
2177 | netdev_features_t features) | |
2178 | { | |
2179 | u32 mss = skb_shinfo(skb)->gso_size; | |
2180 | int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; | |
2181 | int offset = skb_transport_offset(skb); | |
2182 | ||
2183 | if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset) | |
a188222b | 2184 | features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); |
a5e31255 | 2185 | else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz) |
2186 | features &= ~NETIF_F_GSO_MASK; | |
2187 | ||
2188 | return features; | |
2189 | } | |
2190 | ||
ac718b69 | 2191 | static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, |
b209af99 | 2192 | struct net_device *netdev) |
ac718b69 | 2193 | { |
2194 | struct r8152 *tp = netdev_priv(netdev); | |
ac718b69 | 2195 | |
ebc2ec48 | 2196 | skb_tx_timestamp(skb); |
ac718b69 | 2197 | |
61598788 | 2198 | skb_queue_tail(&tp->tx_queue, skb); |
ebc2ec48 | 2199 | |
0c3121fc | 2200 | if (!list_empty(&tp->tx_free)) { |
2201 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { | |
d823ab68 | 2202 | set_bit(SCHEDULE_NAPI, &tp->flags); |
0c3121fc | 2203 | schedule_delayed_work(&tp->schedule, 0); |
2204 | } else { | |
2205 | usb_mark_last_busy(tp->udev); | |
d823ab68 | 2206 | napi_schedule(&tp->napi); |
0c3121fc | 2207 | } |
b209af99 | 2208 | } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { |
dd1b119c | 2209 | netif_stop_queue(netdev); |
b209af99 | 2210 | } |
dd1b119c | 2211 | |
ac718b69 | 2212 | return NETDEV_TX_OK; |
2213 | } | |
2214 | ||
2215 | static void r8152b_reset_packet_filter(struct r8152 *tp) | |
2216 | { | |
2217 | u32 ocp_data; | |
2218 | ||
2219 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); | |
2220 | ocp_data &= ~FMC_FCR_MCU_EN; | |
2221 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
2222 | ocp_data |= FMC_FCR_MCU_EN; | |
2223 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
2224 | } | |
2225 | ||
2226 | static void rtl8152_nic_reset(struct r8152 *tp) | |
2227 | { | |
2228 | int i; | |
2229 | ||
2230 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); | |
2231 | ||
2232 | for (i = 0; i < 1000; i++) { | |
2233 | if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) | |
2234 | break; | |
b209af99 | 2235 | usleep_range(100, 400); |
ac718b69 | 2236 | } |
2237 | } | |
2238 | ||
dd1b119c | 2239 | static void set_tx_qlen(struct r8152 *tp) |
2240 | { | |
2241 | struct net_device *netdev = tp->netdev; | |
2242 | ||
52aec126 | 2243 | tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN + |
2244 | sizeof(struct tx_desc)); | |
dd1b119c | 2245 | } |
2246 | ||
ac718b69 | 2247 | static inline u8 rtl8152_get_speed(struct r8152 *tp) |
2248 | { | |
2249 | return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); | |
2250 | } | |
2251 | ||
507605a8 | 2252 | static void rtl_set_eee_plus(struct r8152 *tp) |
ac718b69 | 2253 | { |
ebc2ec48 | 2254 | u32 ocp_data; |
ac718b69 | 2255 | u8 speed; |
2256 | ||
2257 | speed = rtl8152_get_speed(tp); | |
ebc2ec48 | 2258 | if (speed & _10bps) { |
ac718b69 | 2259 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); |
ebc2ec48 | 2260 | ocp_data |= EEEP_CR_EEEP_TX; |
ac718b69 | 2261 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
2262 | } else { | |
2263 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); | |
ebc2ec48 | 2264 | ocp_data &= ~EEEP_CR_EEEP_TX; |
ac718b69 | 2265 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
2266 | } | |
507605a8 | 2267 | } |
2268 | ||
00a5e360 | 2269 | static void rxdy_gated_en(struct r8152 *tp, bool enable) |
2270 | { | |
2271 | u32 ocp_data; | |
2272 | ||
2273 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); | |
2274 | if (enable) | |
2275 | ocp_data |= RXDY_GATED_EN; | |
2276 | else | |
2277 | ocp_data &= ~RXDY_GATED_EN; | |
2278 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); | |
2279 | } | |
2280 | ||
445f7f4d | 2281 | static int rtl_start_rx(struct r8152 *tp) |
2282 | { | |
2283 | int i, ret = 0; | |
2284 | ||
2285 | INIT_LIST_HEAD(&tp->rx_done); | |
2286 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
2287 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
2288 | ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); | |
2289 | if (ret) | |
2290 | break; | |
2291 | } | |
2292 | ||
7bcf4f60 | 2293 | if (ret && ++i < RTL8152_MAX_RX) { |
2294 | struct list_head rx_queue; | |
2295 | unsigned long flags; | |
2296 | ||
2297 | INIT_LIST_HEAD(&rx_queue); | |
2298 | ||
2299 | do { | |
2300 | struct rx_agg *agg = &tp->rx_info[i++]; | |
2301 | struct urb *urb = agg->urb; | |
2302 | ||
2303 | urb->actual_length = 0; | |
2304 | list_add_tail(&agg->list, &rx_queue); | |
2305 | } while (i < RTL8152_MAX_RX); | |
2306 | ||
2307 | spin_lock_irqsave(&tp->rx_lock, flags); | |
2308 | list_splice_tail(&rx_queue, &tp->rx_done); | |
2309 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
2310 | } | |
2311 | ||
445f7f4d | 2312 | return ret; |
2313 | } | |
2314 | ||
2315 | static int rtl_stop_rx(struct r8152 *tp) | |
2316 | { | |
2317 | int i; | |
2318 | ||
2319 | for (i = 0; i < RTL8152_MAX_RX; i++) | |
2320 | usb_kill_urb(tp->rx_info[i].urb); | |
2321 | ||
d823ab68 | 2322 | while (!skb_queue_empty(&tp->rx_queue)) |
2323 | dev_kfree_skb(__skb_dequeue(&tp->rx_queue)); | |
2324 | ||
445f7f4d | 2325 | return 0; |
2326 | } | |
2327 | ||
507605a8 | 2328 | static int rtl_enable(struct r8152 *tp) |
2329 | { | |
2330 | u32 ocp_data; | |
ac718b69 | 2331 | |
2332 | r8152b_reset_packet_filter(tp); | |
2333 | ||
2334 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); | |
2335 | ocp_data |= CR_RE | CR_TE; | |
2336 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); | |
2337 | ||
00a5e360 | 2338 | rxdy_gated_en(tp, false); |
ac718b69 | 2339 | |
aa2e0926 | 2340 | return 0; |
ac718b69 | 2341 | } |
2342 | ||
507605a8 | 2343 | static int rtl8152_enable(struct r8152 *tp) |
2344 | { | |
6871438c | 2345 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
2346 | return -ENODEV; | |
2347 | ||
507605a8 | 2348 | set_tx_qlen(tp); |
2349 | rtl_set_eee_plus(tp); | |
2350 | ||
2351 | return rtl_enable(tp); | |
2352 | } | |
2353 | ||
65b82d69 | 2354 | static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp) |
2355 | { | |
2356 | ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN, | |
2357 | OWN_UPDATE | OWN_CLEAR); | |
2358 | } | |
2359 | ||
464ec10a | 2360 | static void r8153_set_rx_early_timeout(struct r8152 *tp) |
43779f8d | 2361 | { |
464ec10a | 2362 | u32 ocp_data = tp->coalesce / 8; |
43779f8d | 2363 | |
65b82d69 | 2364 | switch (tp->version) { |
2365 | case RTL_VER_03: | |
2366 | case RTL_VER_04: | |
2367 | case RTL_VER_05: | |
2368 | case RTL_VER_06: | |
2369 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, | |
2370 | ocp_data); | |
2371 | break; | |
2372 | ||
2373 | case RTL_VER_08: | |
2374 | case RTL_VER_09: | |
2375 | /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout | |
2376 | * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns. | |
2377 | */ | |
2378 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, | |
2379 | 128 / 8); | |
2380 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR, | |
2381 | ocp_data); | |
2382 | r8153b_rx_agg_chg_indicate(tp); | |
2383 | break; | |
2384 | ||
2385 | default: | |
2386 | break; | |
2387 | } | |
464ec10a | 2388 | } |
2389 | ||
2390 | static void r8153_set_rx_early_size(struct r8152 *tp) | |
2391 | { | |
65b82d69 | 2392 | u32 ocp_data = agg_buf_sz - rx_reserved_size(tp->netdev->mtu); |
464ec10a | 2393 | |
65b82d69 | 2394 | switch (tp->version) { |
2395 | case RTL_VER_03: | |
2396 | case RTL_VER_04: | |
2397 | case RTL_VER_05: | |
2398 | case RTL_VER_06: | |
2399 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, | |
2400 | ocp_data / 4); | |
2401 | break; | |
2402 | case RTL_VER_08: | |
2403 | case RTL_VER_09: | |
2404 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, | |
2405 | ocp_data / 8); | |
2406 | r8153b_rx_agg_chg_indicate(tp); | |
2407 | break; | |
2408 | default: | |
2409 | WARN_ON_ONCE(1); | |
2410 | break; | |
2411 | } | |
43779f8d | 2412 | } |
2413 | ||
2414 | static int rtl8153_enable(struct r8152 *tp) | |
2415 | { | |
6871438c | 2416 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
2417 | return -ENODEV; | |
2418 | ||
43779f8d | 2419 | set_tx_qlen(tp); |
2420 | rtl_set_eee_plus(tp); | |
464ec10a | 2421 | r8153_set_rx_early_timeout(tp); |
2422 | r8153_set_rx_early_size(tp); | |
43779f8d | 2423 | |
2424 | return rtl_enable(tp); | |
2425 | } | |
2426 | ||
d70b1137 | 2427 | static void rtl_disable(struct r8152 *tp) |
ac718b69 | 2428 | { |
ebc2ec48 | 2429 | u32 ocp_data; |
2430 | int i; | |
ac718b69 | 2431 | |
6871438c | 2432 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
2433 | rtl_drop_queued_tx(tp); | |
2434 | return; | |
2435 | } | |
2436 | ||
ac718b69 | 2437 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); |
2438 | ocp_data &= ~RCR_ACPT_ALL; | |
2439 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2440 | ||
00a5e360 | 2441 | rtl_drop_queued_tx(tp); |
ebc2ec48 | 2442 | |
2443 | for (i = 0; i < RTL8152_MAX_TX; i++) | |
2444 | usb_kill_urb(tp->tx_info[i].urb); | |
ac718b69 | 2445 | |
00a5e360 | 2446 | rxdy_gated_en(tp, true); |
ac718b69 | 2447 | |
2448 | for (i = 0; i < 1000; i++) { | |
2449 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2450 | if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) | |
2451 | break; | |
8ddfa077 | 2452 | usleep_range(1000, 2000); |
ac718b69 | 2453 | } |
2454 | ||
2455 | for (i = 0; i < 1000; i++) { | |
2456 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) | |
2457 | break; | |
8ddfa077 | 2458 | usleep_range(1000, 2000); |
ac718b69 | 2459 | } |
2460 | ||
445f7f4d | 2461 | rtl_stop_rx(tp); |
ac718b69 | 2462 | |
2463 | rtl8152_nic_reset(tp); | |
2464 | } | |
2465 | ||
00a5e360 | 2466 | static void r8152_power_cut_en(struct r8152 *tp, bool enable) |
2467 | { | |
2468 | u32 ocp_data; | |
2469 | ||
2470 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); | |
2471 | if (enable) | |
2472 | ocp_data |= POWER_CUT; | |
2473 | else | |
2474 | ocp_data &= ~POWER_CUT; | |
2475 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); | |
2476 | ||
2477 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); | |
2478 | ocp_data &= ~RESUME_INDICATE; | |
2479 | ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); | |
00a5e360 | 2480 | } |
2481 | ||
c5554298 | 2482 | static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) |
2483 | { | |
2484 | u32 ocp_data; | |
2485 | ||
2486 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
2487 | if (enable) | |
2488 | ocp_data |= CPCR_RX_VLAN; | |
2489 | else | |
2490 | ocp_data &= ~CPCR_RX_VLAN; | |
2491 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2492 | } | |
2493 | ||
2494 | static int rtl8152_set_features(struct net_device *dev, | |
2495 | netdev_features_t features) | |
2496 | { | |
2497 | netdev_features_t changed = features ^ dev->features; | |
2498 | struct r8152 *tp = netdev_priv(dev); | |
405f8a0e | 2499 | int ret; |
2500 | ||
2501 | ret = usb_autopm_get_interface(tp->intf); | |
2502 | if (ret < 0) | |
2503 | goto out; | |
c5554298 | 2504 | |
b5403273 | 2505 | mutex_lock(&tp->control); |
2506 | ||
c5554298 | 2507 | if (changed & NETIF_F_HW_VLAN_CTAG_RX) { |
2508 | if (features & NETIF_F_HW_VLAN_CTAG_RX) | |
2509 | rtl_rx_vlan_en(tp, true); | |
2510 | else | |
2511 | rtl_rx_vlan_en(tp, false); | |
2512 | } | |
2513 | ||
b5403273 | 2514 | mutex_unlock(&tp->control); |
2515 | ||
405f8a0e | 2516 | usb_autopm_put_interface(tp->intf); |
2517 | ||
2518 | out: | |
2519 | return ret; | |
c5554298 | 2520 | } |
2521 | ||
21ff2e89 | 2522 | #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
2523 | ||
2524 | static u32 __rtl_get_wol(struct r8152 *tp) | |
2525 | { | |
2526 | u32 ocp_data; | |
2527 | u32 wolopts = 0; | |
2528 | ||
21ff2e89 | 2529 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); |
2530 | if (ocp_data & LINK_ON_WAKE_EN) | |
2531 | wolopts |= WAKE_PHY; | |
2532 | ||
2533 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
2534 | if (ocp_data & UWF_EN) | |
2535 | wolopts |= WAKE_UCAST; | |
2536 | if (ocp_data & BWF_EN) | |
2537 | wolopts |= WAKE_BCAST; | |
2538 | if (ocp_data & MWF_EN) | |
2539 | wolopts |= WAKE_MCAST; | |
2540 | ||
2541 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
2542 | if (ocp_data & MAGIC_EN) | |
2543 | wolopts |= WAKE_MAGIC; | |
2544 | ||
2545 | return wolopts; | |
2546 | } | |
2547 | ||
2548 | static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) | |
2549 | { | |
2550 | u32 ocp_data; | |
2551 | ||
2552 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
2553 | ||
2554 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2555 | ocp_data &= ~LINK_ON_WAKE_EN; | |
2556 | if (wolopts & WAKE_PHY) | |
2557 | ocp_data |= LINK_ON_WAKE_EN; | |
2558 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
2559 | ||
2560 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
92f7d07d | 2561 | ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN); |
21ff2e89 | 2562 | if (wolopts & WAKE_UCAST) |
2563 | ocp_data |= UWF_EN; | |
2564 | if (wolopts & WAKE_BCAST) | |
2565 | ocp_data |= BWF_EN; | |
2566 | if (wolopts & WAKE_MCAST) | |
2567 | ocp_data |= MWF_EN; | |
21ff2e89 | 2568 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); |
2569 | ||
2570 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2571 | ||
2572 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
2573 | ocp_data &= ~MAGIC_EN; | |
2574 | if (wolopts & WAKE_MAGIC) | |
2575 | ocp_data |= MAGIC_EN; | |
2576 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); | |
2577 | ||
2578 | if (wolopts & WAKE_ANY) | |
2579 | device_set_wakeup_enable(&tp->udev->dev, true); | |
2580 | else | |
2581 | device_set_wakeup_enable(&tp->udev->dev, false); | |
2582 | } | |
2583 | ||
134f98bc | 2584 | static void r8153_mac_clk_spd(struct r8152 *tp, bool enable) |
2585 | { | |
2586 | /* MAC clock speed down */ | |
2587 | if (enable) { | |
2588 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, | |
2589 | ALDPS_SPDWN_RATIO); | |
2590 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, | |
2591 | EEE_SPDWN_RATIO); | |
2592 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, | |
2593 | PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | | |
2594 | U1U2_SPDWN_EN | L1_SPDWN_EN); | |
2595 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, | |
2596 | PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | | |
2597 | TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN | | |
2598 | TP1000_SPDWN_EN); | |
2599 | } else { | |
2600 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0); | |
2601 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0); | |
2602 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0); | |
2603 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0); | |
2604 | } | |
2605 | } | |
2606 | ||
b214396f | 2607 | static void r8153_u1u2en(struct r8152 *tp, bool enable) |
2608 | { | |
2609 | u8 u1u2[8]; | |
2610 | ||
2611 | if (enable) | |
2612 | memset(u1u2, 0xff, sizeof(u1u2)); | |
2613 | else | |
2614 | memset(u1u2, 0x00, sizeof(u1u2)); | |
2615 | ||
2616 | usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); | |
2617 | } | |
2618 | ||
65b82d69 | 2619 | static void r8153b_u1u2en(struct r8152 *tp, bool enable) |
2620 | { | |
2621 | u32 ocp_data; | |
2622 | ||
2623 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG); | |
2624 | if (enable) | |
2625 | ocp_data |= LPM_U1U2_EN; | |
2626 | else | |
2627 | ocp_data &= ~LPM_U1U2_EN; | |
2628 | ||
2629 | ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data); | |
2630 | } | |
2631 | ||
b214396f | 2632 | static void r8153_u2p3en(struct r8152 *tp, bool enable) |
2633 | { | |
2634 | u32 ocp_data; | |
2635 | ||
2636 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); | |
3cb3234e | 2637 | if (enable) |
b214396f | 2638 | ocp_data |= U2P3_ENABLE; |
2639 | else | |
2640 | ocp_data &= ~U2P3_ENABLE; | |
2641 | ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); | |
2642 | } | |
2643 | ||
65b82d69 | 2644 | static void r8153b_ups_flags_w1w0(struct r8152 *tp, u32 set, u32 clear) |
2645 | { | |
2646 | u32 ocp_data; | |
2647 | ||
2648 | ocp_data = ocp_read_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS); | |
2649 | ocp_data &= ~clear; | |
2650 | ocp_data |= set; | |
2651 | ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ocp_data); | |
2652 | } | |
2653 | ||
2654 | static void r8153b_green_en(struct r8152 *tp, bool enable) | |
2655 | { | |
2656 | u16 data; | |
2657 | ||
2658 | if (enable) { | |
2659 | sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */ | |
2660 | sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */ | |
2661 | sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */ | |
2662 | } else { | |
2663 | sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */ | |
2664 | sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */ | |
2665 | sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */ | |
2666 | } | |
2667 | ||
2668 | data = sram_read(tp, SRAM_GREEN_CFG); | |
2669 | data |= GREEN_ETH_EN; | |
2670 | sram_write(tp, SRAM_GREEN_CFG, data); | |
2671 | ||
2672 | r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_GREEN, 0); | |
2673 | } | |
2674 | ||
c564b871 | 2675 | static u16 r8153_phy_status(struct r8152 *tp, u16 desired) |
2676 | { | |
2677 | u16 data; | |
2678 | int i; | |
2679 | ||
2680 | for (i = 0; i < 500; i++) { | |
2681 | data = ocp_reg_read(tp, OCP_PHY_STATUS); | |
2682 | data &= PHY_STAT_MASK; | |
2683 | if (desired) { | |
2684 | if (data == desired) | |
2685 | break; | |
2686 | } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN || | |
2687 | data == PHY_STAT_EXT_INIT) { | |
2688 | break; | |
2689 | } | |
2690 | ||
2691 | msleep(20); | |
2692 | } | |
2693 | ||
2694 | return data; | |
2695 | } | |
2696 | ||
65b82d69 | 2697 | static void r8153b_ups_en(struct r8152 *tp, bool enable) |
2698 | { | |
2699 | u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); | |
2700 | ||
2701 | if (enable) { | |
2702 | ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; | |
2703 | ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
2704 | ||
2705 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff); | |
2706 | ocp_data |= BIT(0); | |
2707 | ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); | |
2708 | } else { | |
2709 | u16 data; | |
2710 | ||
2711 | ocp_data &= ~(UPS_EN | USP_PREWAKE); | |
2712 | ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
2713 | ||
2714 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff); | |
2715 | ocp_data &= ~BIT(0); | |
2716 | ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); | |
2717 | ||
2718 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
2719 | ocp_data &= ~PCUT_STATUS; | |
2720 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); | |
2721 | ||
2722 | data = r8153_phy_status(tp, 0); | |
2723 | ||
2724 | switch (data) { | |
2725 | case PHY_STAT_PWRDN: | |
2726 | case PHY_STAT_EXT_INIT: | |
2727 | r8153b_green_en(tp, | |
2728 | test_bit(GREEN_ETHERNET, &tp->flags)); | |
2729 | ||
2730 | data = r8152_mdio_read(tp, MII_BMCR); | |
2731 | data &= ~BMCR_PDOWN; | |
2732 | data |= BMCR_RESET; | |
2733 | r8152_mdio_write(tp, MII_BMCR, data); | |
2734 | ||
2735 | data = r8153_phy_status(tp, PHY_STAT_LAN_ON); | |
2736 | ||
2737 | default: | |
2738 | if (data != PHY_STAT_LAN_ON) | |
2739 | netif_warn(tp, link, tp->netdev, | |
2740 | "PHY not ready"); | |
2741 | break; | |
2742 | } | |
2743 | } | |
2744 | } | |
2745 | ||
b214396f | 2746 | static void r8153_power_cut_en(struct r8152 *tp, bool enable) |
2747 | { | |
2748 | u32 ocp_data; | |
2749 | ||
2750 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); | |
2751 | if (enable) | |
2752 | ocp_data |= PWR_EN | PHASE2_EN; | |
2753 | else | |
2754 | ocp_data &= ~(PWR_EN | PHASE2_EN); | |
2755 | ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
2756 | ||
2757 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
2758 | ocp_data &= ~PCUT_STATUS; | |
2759 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); | |
2760 | } | |
2761 | ||
65b82d69 | 2762 | static void r8153b_power_cut_en(struct r8152 *tp, bool enable) |
2763 | { | |
2764 | u32 ocp_data; | |
2765 | ||
2766 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); | |
2767 | if (enable) | |
2768 | ocp_data |= PWR_EN | PHASE2_EN; | |
2769 | else | |
2770 | ocp_data &= ~PWR_EN; | |
2771 | ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
2772 | ||
2773 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
2774 | ocp_data &= ~PCUT_STATUS; | |
2775 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); | |
2776 | } | |
2777 | ||
2778 | static void r8153b_queue_wake(struct r8152 *tp, bool enable) | |
2779 | { | |
2780 | u32 ocp_data; | |
2781 | ||
2782 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38a); | |
2783 | if (enable) | |
2784 | ocp_data |= BIT(0); | |
2785 | else | |
2786 | ocp_data &= ~BIT(0); | |
2787 | ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38a, ocp_data); | |
2788 | ||
2789 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38c); | |
2790 | ocp_data &= ~BIT(0); | |
2791 | ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38c, ocp_data); | |
2792 | } | |
2793 | ||
7daed8dc | 2794 | static bool rtl_can_wakeup(struct r8152 *tp) |
2795 | { | |
2796 | struct usb_device *udev = tp->udev; | |
2797 | ||
2798 | return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP); | |
2799 | } | |
2800 | ||
9a4be1bd | 2801 | static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) |
2802 | { | |
2803 | if (enable) { | |
2804 | u32 ocp_data; | |
2805 | ||
2806 | __rtl_set_wol(tp, WAKE_ANY); | |
2807 | ||
2808 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
2809 | ||
2810 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2811 | ocp_data |= LINK_OFF_WAKE_EN; | |
2812 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
2813 | ||
2814 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2815 | } else { | |
f95ae8a0 | 2816 | u32 ocp_data; |
2817 | ||
9a4be1bd | 2818 | __rtl_set_wol(tp, tp->saved_wolopts); |
f95ae8a0 | 2819 | |
2820 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
2821 | ||
2822 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2823 | ocp_data &= ~LINK_OFF_WAKE_EN; | |
2824 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
2825 | ||
2826 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2609af19 | 2827 | } |
2828 | } | |
f95ae8a0 | 2829 | |
2609af19 | 2830 | static void rtl8153_runtime_enable(struct r8152 *tp, bool enable) |
2831 | { | |
2609af19 | 2832 | if (enable) { |
2833 | r8153_u1u2en(tp, false); | |
2834 | r8153_u2p3en(tp, false); | |
134f98bc | 2835 | r8153_mac_clk_spd(tp, true); |
02552754 | 2836 | rtl_runtime_suspend_enable(tp, true); |
2609af19 | 2837 | } else { |
02552754 | 2838 | rtl_runtime_suspend_enable(tp, false); |
134f98bc | 2839 | r8153_mac_clk_spd(tp, false); |
3cb3234e | 2840 | |
2841 | switch (tp->version) { | |
2842 | case RTL_VER_03: | |
2843 | case RTL_VER_04: | |
2844 | break; | |
2845 | case RTL_VER_05: | |
2846 | case RTL_VER_06: | |
2847 | default: | |
2848 | r8153_u2p3en(tp, true); | |
2849 | break; | |
2850 | } | |
2851 | ||
b214396f | 2852 | r8153_u1u2en(tp, true); |
9a4be1bd | 2853 | } |
2854 | } | |
2855 | ||
65b82d69 | 2856 | static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable) |
2857 | { | |
2858 | if (enable) { | |
2859 | r8153b_queue_wake(tp, true); | |
2860 | r8153b_u1u2en(tp, false); | |
2861 | r8153_u2p3en(tp, false); | |
2862 | rtl_runtime_suspend_enable(tp, true); | |
2863 | r8153b_ups_en(tp, true); | |
2864 | } else { | |
2865 | r8153b_ups_en(tp, false); | |
2866 | r8153b_queue_wake(tp, false); | |
2867 | rtl_runtime_suspend_enable(tp, false); | |
2868 | r8153_u2p3en(tp, true); | |
2869 | r8153b_u1u2en(tp, true); | |
2870 | } | |
2871 | } | |
2872 | ||
4349968a | 2873 | static void r8153_teredo_off(struct r8152 *tp) |
2874 | { | |
2875 | u32 ocp_data; | |
2876 | ||
65b82d69 | 2877 | switch (tp->version) { |
2878 | case RTL_VER_01: | |
2879 | case RTL_VER_02: | |
2880 | case RTL_VER_03: | |
2881 | case RTL_VER_04: | |
2882 | case RTL_VER_05: | |
2883 | case RTL_VER_06: | |
2884 | case RTL_VER_07: | |
2885 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); | |
2886 | ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | | |
2887 | OOB_TEREDO_EN); | |
2888 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
2889 | break; | |
2890 | ||
2891 | case RTL_VER_08: | |
2892 | case RTL_VER_09: | |
2893 | /* The bit 0 ~ 7 are relative with teredo settings. They are | |
2894 | * W1C (write 1 to clear), so set all 1 to disable it. | |
2895 | */ | |
2896 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff); | |
2897 | break; | |
2898 | ||
2899 | default: | |
2900 | break; | |
2901 | } | |
4349968a | 2902 | |
2903 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); | |
2904 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); | |
2905 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); | |
2906 | } | |
2907 | ||
93fe9b18 | 2908 | static void rtl_reset_bmu(struct r8152 *tp) |
2909 | { | |
2910 | u32 ocp_data; | |
2911 | ||
2912 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET); | |
2913 | ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); | |
2914 | ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); | |
2915 | ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT; | |
2916 | ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); | |
2917 | } | |
2918 | ||
cda9fb01 | 2919 | static void r8152_aldps_en(struct r8152 *tp, bool enable) |
4349968a | 2920 | { |
cda9fb01 | 2921 | if (enable) { |
2922 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | | |
2923 | LINKENA | DIS_SDSAVE); | |
2924 | } else { | |
2925 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | | |
2926 | DIS_SDSAVE); | |
2927 | msleep(20); | |
2928 | } | |
4349968a | 2929 | } |
2930 | ||
e6449539 | 2931 | static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) |
2932 | { | |
2933 | ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev); | |
2934 | ocp_reg_write(tp, OCP_EEE_DATA, reg); | |
2935 | ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev); | |
2936 | } | |
2937 | ||
2938 | static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) | |
2939 | { | |
2940 | u16 data; | |
2941 | ||
2942 | r8152_mmd_indirect(tp, dev, reg); | |
2943 | data = ocp_reg_read(tp, OCP_EEE_DATA); | |
2944 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); | |
2945 | ||
2946 | return data; | |
2947 | } | |
2948 | ||
2949 | static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) | |
2950 | { | |
2951 | r8152_mmd_indirect(tp, dev, reg); | |
2952 | ocp_reg_write(tp, OCP_EEE_DATA, data); | |
2953 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); | |
2954 | } | |
2955 | ||
2956 | static void r8152_eee_en(struct r8152 *tp, bool enable) | |
2957 | { | |
2958 | u16 config1, config2, config3; | |
2959 | u32 ocp_data; | |
2960 | ||
2961 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
2962 | config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; | |
2963 | config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); | |
2964 | config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; | |
2965 | ||
2966 | if (enable) { | |
2967 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
2968 | config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; | |
2969 | config1 |= sd_rise_time(1); | |
2970 | config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; | |
2971 | config3 |= fast_snr(42); | |
2972 | } else { | |
2973 | ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); | |
2974 | config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | | |
2975 | RX_QUIET_EN); | |
2976 | config1 |= sd_rise_time(7); | |
2977 | config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); | |
2978 | config3 |= fast_snr(511); | |
2979 | } | |
2980 | ||
2981 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); | |
2982 | ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); | |
2983 | ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); | |
2984 | ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); | |
2985 | } | |
2986 | ||
2987 | static void r8152b_enable_eee(struct r8152 *tp) | |
2988 | { | |
2989 | r8152_eee_en(tp, true); | |
2990 | r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX); | |
2991 | } | |
2992 | ||
2993 | static void r8152b_enable_fc(struct r8152 *tp) | |
2994 | { | |
2995 | u16 anar; | |
2996 | ||
2997 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
2998 | anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
2999 | r8152_mdio_write(tp, MII_ADVERTISE, anar); | |
3000 | } | |
3001 | ||
d70b1137 | 3002 | static void rtl8152_disable(struct r8152 *tp) |
3003 | { | |
cda9fb01 | 3004 | r8152_aldps_en(tp, false); |
d70b1137 | 3005 | rtl_disable(tp); |
cda9fb01 | 3006 | r8152_aldps_en(tp, true); |
d70b1137 | 3007 | } |
3008 | ||
4349968a | 3009 | static void r8152b_hw_phy_cfg(struct r8152 *tp) |
3010 | { | |
ef39df8e | 3011 | r8152b_enable_eee(tp); |
3012 | r8152_aldps_en(tp, true); | |
3013 | r8152b_enable_fc(tp); | |
f0cbe0ac | 3014 | |
aa66a5f1 | 3015 | set_bit(PHY_RESET, &tp->flags); |
4349968a | 3016 | } |
3017 | ||
ac718b69 | 3018 | static void r8152b_exit_oob(struct r8152 *tp) |
3019 | { | |
db8515ef | 3020 | u32 ocp_data; |
3021 | int i; | |
ac718b69 | 3022 | |
3023 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
3024 | ocp_data &= ~RCR_ACPT_ALL; | |
3025 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
3026 | ||
00a5e360 | 3027 | rxdy_gated_en(tp, true); |
da9bd117 | 3028 | r8153_teredo_off(tp); |
ac718b69 | 3029 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); |
3030 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); | |
3031 | ||
3032 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3033 | ocp_data &= ~NOW_IS_OOB; | |
3034 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
3035 | ||
3036 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
3037 | ocp_data &= ~MCU_BORW_EN; | |
3038 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
3039 | ||
3040 | for (i = 0; i < 1000; i++) { | |
3041 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3042 | if (ocp_data & LINK_LIST_READY) | |
3043 | break; | |
8ddfa077 | 3044 | usleep_range(1000, 2000); |
ac718b69 | 3045 | } |
3046 | ||
3047 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
3048 | ocp_data |= RE_INIT_LL; | |
3049 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
3050 | ||
3051 | for (i = 0; i < 1000; i++) { | |
3052 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3053 | if (ocp_data & LINK_LIST_READY) | |
3054 | break; | |
8ddfa077 | 3055 | usleep_range(1000, 2000); |
ac718b69 | 3056 | } |
3057 | ||
3058 | rtl8152_nic_reset(tp); | |
3059 | ||
3060 | /* rx share fifo credit full threshold */ | |
3061 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
3062 | ||
a3cc465d | 3063 | if (tp->udev->speed == USB_SPEED_FULL || |
3064 | tp->udev->speed == USB_SPEED_LOW) { | |
ac718b69 | 3065 | /* rx share fifo credit near full threshold */ |
3066 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
3067 | RXFIFO_THR2_FULL); | |
3068 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
3069 | RXFIFO_THR3_FULL); | |
3070 | } else { | |
3071 | /* rx share fifo credit near full threshold */ | |
3072 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
3073 | RXFIFO_THR2_HIGH); | |
3074 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
3075 | RXFIFO_THR3_HIGH); | |
3076 | } | |
3077 | ||
3078 | /* TX share fifo free credit full threshold */ | |
3079 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); | |
3080 | ||
3081 | ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); | |
8e1f51bd | 3082 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); |
ac718b69 | 3083 | ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, |
3084 | TEST_MODE_DISABLE | TX_SIZE_ADJUST1); | |
3085 | ||
c5554298 | 3086 | rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); |
ac718b69 | 3087 | |
3088 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
3089 | ||
3090 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
3091 | ocp_data |= TCR0_AUTO_FIFO; | |
3092 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
3093 | } | |
3094 | ||
3095 | static void r8152b_enter_oob(struct r8152 *tp) | |
3096 | { | |
45f4a19f | 3097 | u32 ocp_data; |
3098 | int i; | |
ac718b69 | 3099 | |
3100 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3101 | ocp_data &= ~NOW_IS_OOB; | |
3102 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
3103 | ||
3104 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); | |
3105 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); | |
3106 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); | |
3107 | ||
d70b1137 | 3108 | rtl_disable(tp); |
ac718b69 | 3109 | |
3110 | for (i = 0; i < 1000; i++) { | |
3111 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3112 | if (ocp_data & LINK_LIST_READY) | |
3113 | break; | |
8ddfa077 | 3114 | usleep_range(1000, 2000); |
ac718b69 | 3115 | } |
3116 | ||
3117 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
3118 | ocp_data |= RE_INIT_LL; | |
3119 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
3120 | ||
3121 | for (i = 0; i < 1000; i++) { | |
3122 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3123 | if (ocp_data & LINK_LIST_READY) | |
3124 | break; | |
8ddfa077 | 3125 | usleep_range(1000, 2000); |
ac718b69 | 3126 | } |
3127 | ||
3128 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
3129 | ||
c5554298 | 3130 | rtl_rx_vlan_en(tp, true); |
ac718b69 | 3131 | |
3132 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
3133 | ocp_data |= ALDPS_PROXY_MODE; | |
3134 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
3135 | ||
3136 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3137 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
3138 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
3139 | ||
00a5e360 | 3140 | rxdy_gated_en(tp, false); |
ac718b69 | 3141 | |
3142 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
3143 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
3144 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
3145 | } | |
3146 | ||
65b82d69 | 3147 | static int r8153_patch_request(struct r8152 *tp, bool request) |
3148 | { | |
3149 | u16 data; | |
3150 | int i; | |
3151 | ||
3152 | data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD); | |
3153 | if (request) | |
3154 | data |= PATCH_REQUEST; | |
3155 | else | |
3156 | data &= ~PATCH_REQUEST; | |
3157 | ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data); | |
3158 | ||
3159 | for (i = 0; request && i < 5000; i++) { | |
3160 | usleep_range(1000, 2000); | |
3161 | if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY) | |
3162 | break; | |
3163 | } | |
3164 | ||
3165 | if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) { | |
3166 | netif_err(tp, drv, tp->netdev, "patch request fail\n"); | |
3167 | r8153_patch_request(tp, false); | |
3168 | return -ETIME; | |
3169 | } else { | |
3170 | return 0; | |
3171 | } | |
3172 | } | |
3173 | ||
e6449539 | 3174 | static void r8153_aldps_en(struct r8152 *tp, bool enable) |
3175 | { | |
3176 | u16 data; | |
3177 | ||
3178 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
3179 | if (enable) { | |
3180 | data |= EN_ALDPS; | |
3181 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
3182 | } else { | |
4214cc55 | 3183 | int i; |
3184 | ||
e6449539 | 3185 | data &= ~EN_ALDPS; |
3186 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
4214cc55 | 3187 | for (i = 0; i < 20; i++) { |
3188 | usleep_range(1000, 2000); | |
3189 | if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100) | |
3190 | break; | |
3191 | } | |
e6449539 | 3192 | } |
3193 | } | |
3194 | ||
65b82d69 | 3195 | static void r8153b_aldps_en(struct r8152 *tp, bool enable) |
3196 | { | |
3197 | r8153_aldps_en(tp, enable); | |
3198 | ||
3199 | if (enable) | |
3200 | r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_ALDPS, 0); | |
3201 | else | |
3202 | r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_ALDPS); | |
3203 | } | |
3204 | ||
e6449539 | 3205 | static void r8153_eee_en(struct r8152 *tp, bool enable) |
3206 | { | |
3207 | u32 ocp_data; | |
3208 | u16 config; | |
3209 | ||
3210 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
3211 | config = ocp_reg_read(tp, OCP_EEE_CFG); | |
3212 | ||
3213 | if (enable) { | |
3214 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
3215 | config |= EEE10_EN; | |
3216 | } else { | |
3217 | ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); | |
3218 | config &= ~EEE10_EN; | |
3219 | } | |
3220 | ||
3221 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); | |
3222 | ocp_reg_write(tp, OCP_EEE_CFG, config); | |
3223 | } | |
3224 | ||
65b82d69 | 3225 | static void r8153b_eee_en(struct r8152 *tp, bool enable) |
3226 | { | |
3227 | r8153_eee_en(tp, enable); | |
3228 | ||
3229 | if (enable) | |
3230 | r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_EEE, 0); | |
3231 | else | |
3232 | r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_EEE); | |
3233 | } | |
3234 | ||
3235 | static void r8153b_enable_fc(struct r8152 *tp) | |
3236 | { | |
3237 | r8152b_enable_fc(tp); | |
3238 | r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_FLOW_CTR, 0); | |
3239 | } | |
3240 | ||
43779f8d | 3241 | static void r8153_hw_phy_cfg(struct r8152 *tp) |
3242 | { | |
3243 | u32 ocp_data; | |
3244 | u16 data; | |
3245 | ||
d768c61b | 3246 | /* disable ALDPS before updating the PHY parameters */ |
3247 | r8153_aldps_en(tp, false); | |
fb02eb4a | 3248 | |
d768c61b | 3249 | /* disable EEE before updating the PHY parameters */ |
3250 | r8153_eee_en(tp, false); | |
3251 | ocp_reg_write(tp, OCP_EEE_ADV, 0); | |
43779f8d | 3252 | |
3253 | if (tp->version == RTL_VER_03) { | |
3254 | data = ocp_reg_read(tp, OCP_EEE_CFG); | |
3255 | data &= ~CTAP_SHORT_EN; | |
3256 | ocp_reg_write(tp, OCP_EEE_CFG, data); | |
3257 | } | |
3258 | ||
3259 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
3260 | data |= EEE_CLKDIV_EN; | |
3261 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
3262 | ||
3263 | data = ocp_reg_read(tp, OCP_DOWN_SPEED); | |
3264 | data |= EN_10M_BGOFF; | |
3265 | ocp_reg_write(tp, OCP_DOWN_SPEED, data); | |
3266 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
3267 | data |= EN_10M_PLLOFF; | |
3268 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
b4d99def | 3269 | sram_write(tp, SRAM_IMPEDANCE, 0x0b13); |
43779f8d | 3270 | |
3271 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
3272 | ocp_data |= PFM_PWM_SWITCH; | |
3273 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
3274 | ||
b4d99def | 3275 | /* Enable LPF corner auto tune */ |
3276 | sram_write(tp, SRAM_LPF_CFG, 0xf70f); | |
43779f8d | 3277 | |
b4d99def | 3278 | /* Adjust 10M Amplitude */ |
3279 | sram_write(tp, SRAM_10M_AMP1, 0x00af); | |
3280 | sram_write(tp, SRAM_10M_AMP2, 0x0208); | |
aa66a5f1 | 3281 | |
af0287ec | 3282 | r8153_eee_en(tp, true); |
3283 | ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); | |
3284 | ||
ef39df8e | 3285 | r8153_aldps_en(tp, true); |
3286 | r8152b_enable_fc(tp); | |
3287 | ||
3cb3234e | 3288 | switch (tp->version) { |
3289 | case RTL_VER_03: | |
3290 | case RTL_VER_04: | |
3291 | break; | |
3292 | case RTL_VER_05: | |
3293 | case RTL_VER_06: | |
3294 | default: | |
3295 | r8153_u2p3en(tp, true); | |
3296 | break; | |
3297 | } | |
3298 | ||
aa66a5f1 | 3299 | set_bit(PHY_RESET, &tp->flags); |
43779f8d | 3300 | } |
3301 | ||
65b82d69 | 3302 | static u32 r8152_efuse_read(struct r8152 *tp, u8 addr) |
3303 | { | |
3304 | u32 ocp_data; | |
3305 | ||
3306 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr); | |
3307 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD); | |
3308 | ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */ | |
3309 | ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA); | |
3310 | ||
3311 | return ocp_data; | |
3312 | } | |
3313 | ||
3314 | static void r8153b_hw_phy_cfg(struct r8152 *tp) | |
3315 | { | |
3316 | u32 ocp_data, ups_flags = 0; | |
3317 | u16 data; | |
3318 | ||
3319 | /* disable ALDPS before updating the PHY parameters */ | |
3320 | r8153b_aldps_en(tp, false); | |
3321 | ||
3322 | /* disable EEE before updating the PHY parameters */ | |
3323 | r8153b_eee_en(tp, false); | |
3324 | ocp_reg_write(tp, OCP_EEE_ADV, 0); | |
3325 | ||
3326 | r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); | |
3327 | ||
3328 | data = sram_read(tp, SRAM_GREEN_CFG); | |
3329 | data |= R_TUNE_EN; | |
3330 | sram_write(tp, SRAM_GREEN_CFG, data); | |
3331 | data = ocp_reg_read(tp, OCP_NCTL_CFG); | |
3332 | data |= PGA_RETURN_EN; | |
3333 | ocp_reg_write(tp, OCP_NCTL_CFG, data); | |
3334 | ||
3335 | /* ADC Bias Calibration: | |
3336 | * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake | |
3337 | * bit (bit3) to rebuild the real 16-bit data. Write the data to the | |
3338 | * ADC ioffset. | |
3339 | */ | |
3340 | ocp_data = r8152_efuse_read(tp, 0x7d); | |
3341 | data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7)); | |
3342 | if (data != 0xffff) | |
3343 | ocp_reg_write(tp, OCP_ADC_IOFFSET, data); | |
3344 | ||
3345 | /* ups mode tx-link-pulse timing adjustment: | |
3346 | * rg_saw_cnt = OCP reg 0xC426 Bit[13:0] | |
3347 | * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt | |
3348 | */ | |
3349 | ocp_data = ocp_reg_read(tp, 0xc426); | |
3350 | ocp_data &= 0x3fff; | |
3351 | if (ocp_data) { | |
3352 | u32 swr_cnt_1ms_ini; | |
3353 | ||
3354 | swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK; | |
3355 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG); | |
3356 | ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini; | |
3357 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data); | |
3358 | } | |
3359 | ||
3360 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
3361 | ocp_data |= PFM_PWM_SWITCH; | |
3362 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
3363 | ||
3364 | /* Advnace EEE */ | |
3365 | if (!r8153_patch_request(tp, true)) { | |
3366 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
3367 | data |= EEE_CLKDIV_EN; | |
3368 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
3369 | ||
3370 | data = ocp_reg_read(tp, OCP_DOWN_SPEED); | |
3371 | data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV; | |
3372 | ocp_reg_write(tp, OCP_DOWN_SPEED, data); | |
3373 | ||
3374 | ocp_reg_write(tp, OCP_SYSCLK_CFG, 0); | |
3375 | ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5)); | |
3376 | ||
3377 | ups_flags |= UPS_FLAGS_EN_10M_CKDIV | UPS_FLAGS_250M_CKDIV | | |
3378 | UPS_FLAGS_EN_EEE_CKDIV | UPS_FLAGS_EEE_CMOD_LV_EN | | |
3379 | UPS_FLAGS_EEE_PLLOFF_GIGA; | |
3380 | ||
3381 | r8153_patch_request(tp, false); | |
3382 | } | |
3383 | ||
3384 | r8153b_ups_flags_w1w0(tp, ups_flags, 0); | |
3385 | ||
3386 | r8153b_eee_en(tp, true); | |
3387 | ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); | |
3388 | ||
3389 | r8153b_aldps_en(tp, true); | |
3390 | r8153b_enable_fc(tp); | |
3391 | r8153_u2p3en(tp, true); | |
3392 | ||
3393 | set_bit(PHY_RESET, &tp->flags); | |
3394 | } | |
3395 | ||
43779f8d | 3396 | static void r8153_first_init(struct r8152 *tp) |
3397 | { | |
3398 | u32 ocp_data; | |
3399 | int i; | |
3400 | ||
134f98bc | 3401 | r8153_mac_clk_spd(tp, false); |
00a5e360 | 3402 | rxdy_gated_en(tp, true); |
43779f8d | 3403 | r8153_teredo_off(tp); |
3404 | ||
3405 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
3406 | ocp_data &= ~RCR_ACPT_ALL; | |
3407 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
3408 | ||
43779f8d | 3409 | rtl8152_nic_reset(tp); |
93fe9b18 | 3410 | rtl_reset_bmu(tp); |
43779f8d | 3411 | |
3412 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3413 | ocp_data &= ~NOW_IS_OOB; | |
3414 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
3415 | ||
3416 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
3417 | ocp_data &= ~MCU_BORW_EN; | |
3418 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
3419 | ||
3420 | for (i = 0; i < 1000; i++) { | |
3421 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3422 | if (ocp_data & LINK_LIST_READY) | |
3423 | break; | |
8ddfa077 | 3424 | usleep_range(1000, 2000); |
43779f8d | 3425 | } |
3426 | ||
3427 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
3428 | ocp_data |= RE_INIT_LL; | |
3429 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
3430 | ||
3431 | for (i = 0; i < 1000; i++) { | |
3432 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3433 | if (ocp_data & LINK_LIST_READY) | |
3434 | break; | |
8ddfa077 | 3435 | usleep_range(1000, 2000); |
43779f8d | 3436 | } |
3437 | ||
c5554298 | 3438 | rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); |
43779f8d | 3439 | |
210c4f70 | 3440 | ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + CRC_SIZE; |
3441 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); | |
69b4b7a4 | 3442 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); |
43779f8d | 3443 | |
3444 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
3445 | ocp_data |= TCR0_AUTO_FIFO; | |
3446 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
3447 | ||
3448 | rtl8152_nic_reset(tp); | |
3449 | ||
3450 | /* rx share fifo credit full threshold */ | |
3451 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
3452 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); | |
3453 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); | |
3454 | /* TX share fifo free credit full threshold */ | |
3455 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); | |
43779f8d | 3456 | } |
3457 | ||
3458 | static void r8153_enter_oob(struct r8152 *tp) | |
3459 | { | |
3460 | u32 ocp_data; | |
3461 | int i; | |
3462 | ||
134f98bc | 3463 | r8153_mac_clk_spd(tp, true); |
3464 | ||
43779f8d | 3465 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
3466 | ocp_data &= ~NOW_IS_OOB; | |
3467 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
3468 | ||
d70b1137 | 3469 | rtl_disable(tp); |
93fe9b18 | 3470 | rtl_reset_bmu(tp); |
43779f8d | 3471 | |
3472 | for (i = 0; i < 1000; i++) { | |
3473 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3474 | if (ocp_data & LINK_LIST_READY) | |
3475 | break; | |
8ddfa077 | 3476 | usleep_range(1000, 2000); |
43779f8d | 3477 | } |
3478 | ||
3479 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
3480 | ocp_data |= RE_INIT_LL; | |
3481 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
3482 | ||
3483 | for (i = 0; i < 1000; i++) { | |
3484 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3485 | if (ocp_data & LINK_LIST_READY) | |
3486 | break; | |
8ddfa077 | 3487 | usleep_range(1000, 2000); |
43779f8d | 3488 | } |
3489 | ||
210c4f70 | 3490 | ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + CRC_SIZE; |
3491 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); | |
43779f8d | 3492 | |
65b82d69 | 3493 | switch (tp->version) { |
3494 | case RTL_VER_03: | |
3495 | case RTL_VER_04: | |
3496 | case RTL_VER_05: | |
3497 | case RTL_VER_06: | |
3498 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); | |
3499 | ocp_data &= ~TEREDO_WAKE_MASK; | |
3500 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
3501 | break; | |
3502 | ||
3503 | case RTL_VER_08: | |
3504 | case RTL_VER_09: | |
3505 | /* Clear teredo wake event. bit[15:8] is the teredo wakeup | |
3506 | * type. Set it to zero. bits[7:0] are the W1C bits about | |
3507 | * the events. Set them to all 1 to clear them. | |
3508 | */ | |
3509 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); | |
3510 | break; | |
3511 | ||
3512 | default: | |
3513 | break; | |
3514 | } | |
43779f8d | 3515 | |
c5554298 | 3516 | rtl_rx_vlan_en(tp, true); |
43779f8d | 3517 | |
3518 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
3519 | ocp_data |= ALDPS_PROXY_MODE; | |
3520 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
3521 | ||
3522 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3523 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
3524 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
3525 | ||
00a5e360 | 3526 | rxdy_gated_en(tp, false); |
43779f8d | 3527 | |
3528 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
3529 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
3530 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
3531 | } | |
3532 | ||
d70b1137 | 3533 | static void rtl8153_disable(struct r8152 *tp) |
3534 | { | |
cda9fb01 | 3535 | r8153_aldps_en(tp, false); |
d70b1137 | 3536 | rtl_disable(tp); |
93fe9b18 | 3537 | rtl_reset_bmu(tp); |
cda9fb01 | 3538 | r8153_aldps_en(tp, true); |
d70b1137 | 3539 | } |
3540 | ||
65b82d69 | 3541 | static void rtl8153b_disable(struct r8152 *tp) |
3542 | { | |
3543 | r8153b_aldps_en(tp, false); | |
3544 | rtl_disable(tp); | |
3545 | rtl_reset_bmu(tp); | |
3546 | r8153b_aldps_en(tp, true); | |
3547 | } | |
3548 | ||
ac718b69 | 3549 | static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) |
3550 | { | |
43779f8d | 3551 | u16 bmcr, anar, gbcr; |
65b82d69 | 3552 | enum spd_duplex speed_duplex; |
ac718b69 | 3553 | int ret = 0; |
3554 | ||
ac718b69 | 3555 | anar = r8152_mdio_read(tp, MII_ADVERTISE); |
3556 | anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | | |
3557 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
43779f8d | 3558 | if (tp->mii.supports_gmii) { |
3559 | gbcr = r8152_mdio_read(tp, MII_CTRL1000); | |
3560 | gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); | |
3561 | } else { | |
3562 | gbcr = 0; | |
3563 | } | |
ac718b69 | 3564 | |
3565 | if (autoneg == AUTONEG_DISABLE) { | |
3566 | if (speed == SPEED_10) { | |
3567 | bmcr = 0; | |
3568 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
65b82d69 | 3569 | speed_duplex = FORCE_10M_HALF; |
ac718b69 | 3570 | } else if (speed == SPEED_100) { |
3571 | bmcr = BMCR_SPEED100; | |
3572 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
65b82d69 | 3573 | speed_duplex = FORCE_100M_HALF; |
43779f8d | 3574 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
3575 | bmcr = BMCR_SPEED1000; | |
3576 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
65b82d69 | 3577 | speed_duplex = NWAY_1000M_FULL; |
ac718b69 | 3578 | } else { |
3579 | ret = -EINVAL; | |
3580 | goto out; | |
3581 | } | |
3582 | ||
65b82d69 | 3583 | if (duplex == DUPLEX_FULL) { |
ac718b69 | 3584 | bmcr |= BMCR_FULLDPLX; |
65b82d69 | 3585 | if (speed != SPEED_1000) |
3586 | speed_duplex++; | |
3587 | } | |
ac718b69 | 3588 | } else { |
3589 | if (speed == SPEED_10) { | |
65b82d69 | 3590 | if (duplex == DUPLEX_FULL) { |
ac718b69 | 3591 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; |
65b82d69 | 3592 | speed_duplex = NWAY_10M_FULL; |
3593 | } else { | |
ac718b69 | 3594 | anar |= ADVERTISE_10HALF; |
65b82d69 | 3595 | speed_duplex = NWAY_10M_HALF; |
3596 | } | |
ac718b69 | 3597 | } else if (speed == SPEED_100) { |
3598 | if (duplex == DUPLEX_FULL) { | |
3599 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
3600 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
65b82d69 | 3601 | speed_duplex = NWAY_100M_FULL; |
ac718b69 | 3602 | } else { |
3603 | anar |= ADVERTISE_10HALF; | |
3604 | anar |= ADVERTISE_100HALF; | |
65b82d69 | 3605 | speed_duplex = NWAY_100M_HALF; |
ac718b69 | 3606 | } |
43779f8d | 3607 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
3608 | if (duplex == DUPLEX_FULL) { | |
3609 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
3610 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
3611 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
3612 | } else { | |
3613 | anar |= ADVERTISE_10HALF; | |
3614 | anar |= ADVERTISE_100HALF; | |
3615 | gbcr |= ADVERTISE_1000HALF; | |
3616 | } | |
65b82d69 | 3617 | speed_duplex = NWAY_1000M_FULL; |
ac718b69 | 3618 | } else { |
3619 | ret = -EINVAL; | |
3620 | goto out; | |
3621 | } | |
3622 | ||
3623 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; | |
3624 | } | |
3625 | ||
fae56178 | 3626 | if (test_and_clear_bit(PHY_RESET, &tp->flags)) |
aa66a5f1 | 3627 | bmcr |= BMCR_RESET; |
3628 | ||
43779f8d | 3629 | if (tp->mii.supports_gmii) |
3630 | r8152_mdio_write(tp, MII_CTRL1000, gbcr); | |
3631 | ||
ac718b69 | 3632 | r8152_mdio_write(tp, MII_ADVERTISE, anar); |
3633 | r8152_mdio_write(tp, MII_BMCR, bmcr); | |
3634 | ||
65b82d69 | 3635 | switch (tp->version) { |
3636 | case RTL_VER_08: | |
3637 | case RTL_VER_09: | |
3638 | r8153b_ups_flags_w1w0(tp, ups_flags_speed(speed_duplex), | |
3639 | UPS_FLAGS_SPEED_MASK); | |
3640 | break; | |
3641 | ||
3642 | default: | |
3643 | break; | |
3644 | } | |
3645 | ||
fae56178 | 3646 | if (bmcr & BMCR_RESET) { |
aa66a5f1 | 3647 | int i; |
3648 | ||
aa66a5f1 | 3649 | for (i = 0; i < 50; i++) { |
3650 | msleep(20); | |
3651 | if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) | |
3652 | break; | |
3653 | } | |
3654 | } | |
3655 | ||
ac718b69 | 3656 | out: |
ac718b69 | 3657 | return ret; |
3658 | } | |
3659 | ||
d70b1137 | 3660 | static void rtl8152_up(struct r8152 *tp) |
3661 | { | |
3662 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
3663 | return; | |
3664 | ||
cda9fb01 | 3665 | r8152_aldps_en(tp, false); |
d70b1137 | 3666 | r8152b_exit_oob(tp); |
cda9fb01 | 3667 | r8152_aldps_en(tp, true); |
d70b1137 | 3668 | } |
3669 | ||
ac718b69 | 3670 | static void rtl8152_down(struct r8152 *tp) |
3671 | { | |
6871438c | 3672 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
3673 | rtl_drop_queued_tx(tp); | |
3674 | return; | |
3675 | } | |
3676 | ||
00a5e360 | 3677 | r8152_power_cut_en(tp, false); |
cda9fb01 | 3678 | r8152_aldps_en(tp, false); |
ac718b69 | 3679 | r8152b_enter_oob(tp); |
cda9fb01 | 3680 | r8152_aldps_en(tp, true); |
ac718b69 | 3681 | } |
3682 | ||
d70b1137 | 3683 | static void rtl8153_up(struct r8152 *tp) |
3684 | { | |
3685 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
3686 | return; | |
3687 | ||
b214396f | 3688 | r8153_u1u2en(tp, false); |
3cb3234e | 3689 | r8153_u2p3en(tp, false); |
cda9fb01 | 3690 | r8153_aldps_en(tp, false); |
d70b1137 | 3691 | r8153_first_init(tp); |
cda9fb01 | 3692 | r8153_aldps_en(tp, true); |
3cb3234e | 3693 | |
3694 | switch (tp->version) { | |
3695 | case RTL_VER_03: | |
3696 | case RTL_VER_04: | |
3697 | break; | |
3698 | case RTL_VER_05: | |
3699 | case RTL_VER_06: | |
3700 | default: | |
3701 | r8153_u2p3en(tp, true); | |
3702 | break; | |
3703 | } | |
3704 | ||
b214396f | 3705 | r8153_u1u2en(tp, true); |
d70b1137 | 3706 | } |
3707 | ||
43779f8d | 3708 | static void rtl8153_down(struct r8152 *tp) |
3709 | { | |
6871438c | 3710 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
3711 | rtl_drop_queued_tx(tp); | |
3712 | return; | |
3713 | } | |
3714 | ||
b9702723 | 3715 | r8153_u1u2en(tp, false); |
b214396f | 3716 | r8153_u2p3en(tp, false); |
b9702723 | 3717 | r8153_power_cut_en(tp, false); |
cda9fb01 | 3718 | r8153_aldps_en(tp, false); |
43779f8d | 3719 | r8153_enter_oob(tp); |
cda9fb01 | 3720 | r8153_aldps_en(tp, true); |
43779f8d | 3721 | } |
3722 | ||
65b82d69 | 3723 | static void rtl8153b_up(struct r8152 *tp) |
3724 | { | |
3725 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
3726 | return; | |
3727 | ||
3728 | r8153b_u1u2en(tp, false); | |
3729 | r8153_u2p3en(tp, false); | |
3730 | r8153b_aldps_en(tp, false); | |
3731 | ||
3732 | r8153_first_init(tp); | |
3733 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B); | |
3734 | ||
3735 | r8153b_aldps_en(tp, true); | |
3736 | r8153_u2p3en(tp, true); | |
3737 | r8153b_u1u2en(tp, true); | |
3738 | } | |
3739 | ||
3740 | static void rtl8153b_down(struct r8152 *tp) | |
3741 | { | |
3742 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { | |
3743 | rtl_drop_queued_tx(tp); | |
3744 | return; | |
3745 | } | |
3746 | ||
3747 | r8153b_u1u2en(tp, false); | |
3748 | r8153_u2p3en(tp, false); | |
3749 | r8153b_power_cut_en(tp, false); | |
3750 | r8153b_aldps_en(tp, false); | |
3751 | r8153_enter_oob(tp); | |
3752 | r8153b_aldps_en(tp, true); | |
3753 | } | |
3754 | ||
2dd49e0f | 3755 | static bool rtl8152_in_nway(struct r8152 *tp) |
3756 | { | |
3757 | u16 nway_state; | |
3758 | ||
3759 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000); | |
3760 | tp->ocp_base = 0x2000; | |
3761 | ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */ | |
3762 | nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a); | |
3763 | ||
3764 | /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */ | |
3765 | if (nway_state & 0xc000) | |
3766 | return false; | |
3767 | else | |
3768 | return true; | |
3769 | } | |
3770 | ||
3771 | static bool rtl8153_in_nway(struct r8152 *tp) | |
3772 | { | |
3773 | u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff; | |
3774 | ||
3775 | if (phy_state == TXDIS_STATE || phy_state == ABD_STATE) | |
3776 | return false; | |
3777 | else | |
3778 | return true; | |
3779 | } | |
3780 | ||
ac718b69 | 3781 | static void set_carrier(struct r8152 *tp) |
3782 | { | |
3783 | struct net_device *netdev = tp->netdev; | |
ce594e98 | 3784 | struct napi_struct *napi = &tp->napi; |
ac718b69 | 3785 | u8 speed; |
3786 | ||
3787 | speed = rtl8152_get_speed(tp); | |
3788 | ||
3789 | if (speed & LINK_STATUS) { | |
51d979fa | 3790 | if (!netif_carrier_ok(netdev)) { |
c81229c9 | 3791 | tp->rtl_ops.enable(tp); |
ac718b69 | 3792 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
de9bf29d | 3793 | netif_stop_queue(netdev); |
ce594e98 | 3794 | napi_disable(napi); |
ac718b69 | 3795 | netif_carrier_on(netdev); |
aa2e0926 | 3796 | rtl_start_rx(tp); |
41cec84c | 3797 | napi_enable(&tp->napi); |
de9bf29d | 3798 | netif_wake_queue(netdev); |
3799 | netif_info(tp, link, netdev, "carrier on\n"); | |
2f25abe6 | 3800 | } else if (netif_queue_stopped(netdev) && |
3801 | skb_queue_len(&tp->tx_queue) < tp->tx_qlen) { | |
3802 | netif_wake_queue(netdev); | |
ac718b69 | 3803 | } |
3804 | } else { | |
51d979fa | 3805 | if (netif_carrier_ok(netdev)) { |
ac718b69 | 3806 | netif_carrier_off(netdev); |
ce594e98 | 3807 | napi_disable(napi); |
c81229c9 | 3808 | tp->rtl_ops.disable(tp); |
ce594e98 | 3809 | napi_enable(napi); |
de9bf29d | 3810 | netif_info(tp, link, netdev, "carrier off\n"); |
ac718b69 | 3811 | } |
3812 | } | |
ac718b69 | 3813 | } |
3814 | ||
3815 | static void rtl_work_func_t(struct work_struct *work) | |
3816 | { | |
3817 | struct r8152 *tp = container_of(work, struct r8152, schedule.work); | |
3818 | ||
a1f83fee | 3819 | /* If the device is unplugged or !netif_running(), the workqueue |
3820 | * doesn't need to wake the device, and could return directly. | |
3821 | */ | |
3822 | if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev)) | |
3823 | return; | |
3824 | ||
9a4be1bd | 3825 | if (usb_autopm_get_interface(tp->intf) < 0) |
3826 | return; | |
3827 | ||
ac718b69 | 3828 | if (!test_bit(WORK_ENABLE, &tp->flags)) |
3829 | goto out1; | |
3830 | ||
b5403273 | 3831 | if (!mutex_trylock(&tp->control)) { |
3832 | schedule_delayed_work(&tp->schedule, 0); | |
3833 | goto out1; | |
3834 | } | |
3835 | ||
216a8349 | 3836 | if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags)) |
40a82917 | 3837 | set_carrier(tp); |
ac718b69 | 3838 | |
216a8349 | 3839 | if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags)) |
ac718b69 | 3840 | _rtl8152_set_rx_mode(tp->netdev); |
3841 | ||
d823ab68 | 3842 | /* don't schedule napi before linking */ |
216a8349 | 3843 | if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) && |
3844 | netif_carrier_ok(tp->netdev)) | |
d823ab68 | 3845 | napi_schedule(&tp->napi); |
aa66a5f1 | 3846 | |
b5403273 | 3847 | mutex_unlock(&tp->control); |
3848 | ||
ac718b69 | 3849 | out1: |
9a4be1bd | 3850 | usb_autopm_put_interface(tp->intf); |
ac718b69 | 3851 | } |
3852 | ||
a028a9e0 | 3853 | static void rtl_hw_phy_work_func_t(struct work_struct *work) |
3854 | { | |
3855 | struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work); | |
3856 | ||
3857 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
3858 | return; | |
3859 | ||
3860 | if (usb_autopm_get_interface(tp->intf) < 0) | |
3861 | return; | |
3862 | ||
3863 | mutex_lock(&tp->control); | |
3864 | ||
3865 | tp->rtl_ops.hw_phy_cfg(tp); | |
3866 | ||
aa7e26b6 | 3867 | rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex); |
9d21c0d8 | 3868 | |
a028a9e0 | 3869 | mutex_unlock(&tp->control); |
3870 | ||
3871 | usb_autopm_put_interface(tp->intf); | |
3872 | } | |
3873 | ||
5ee3c60c | 3874 | #ifdef CONFIG_PM_SLEEP |
3875 | static int rtl_notifier(struct notifier_block *nb, unsigned long action, | |
3876 | void *data) | |
3877 | { | |
3878 | struct r8152 *tp = container_of(nb, struct r8152, pm_notifier); | |
3879 | ||
3880 | switch (action) { | |
3881 | case PM_HIBERNATION_PREPARE: | |
3882 | case PM_SUSPEND_PREPARE: | |
3883 | usb_autopm_get_interface(tp->intf); | |
3884 | break; | |
3885 | ||
3886 | case PM_POST_HIBERNATION: | |
3887 | case PM_POST_SUSPEND: | |
3888 | usb_autopm_put_interface(tp->intf); | |
3889 | break; | |
3890 | ||
3891 | case PM_POST_RESTORE: | |
3892 | case PM_RESTORE_PREPARE: | |
3893 | default: | |
3894 | break; | |
3895 | } | |
3896 | ||
3897 | return NOTIFY_DONE; | |
3898 | } | |
3899 | #endif | |
3900 | ||
ac718b69 | 3901 | static int rtl8152_open(struct net_device *netdev) |
3902 | { | |
3903 | struct r8152 *tp = netdev_priv(netdev); | |
3904 | int res = 0; | |
3905 | ||
7e9da481 | 3906 | res = alloc_all_mem(tp); |
3907 | if (res) | |
3908 | goto out; | |
3909 | ||
9a4be1bd | 3910 | res = usb_autopm_get_interface(tp->intf); |
ca0a7531 GR |
3911 | if (res < 0) |
3912 | goto out_free; | |
9a4be1bd | 3913 | |
b5403273 | 3914 | mutex_lock(&tp->control); |
3915 | ||
7e9da481 | 3916 | tp->rtl_ops.up(tp); |
3917 | ||
3d55f44f | 3918 | netif_carrier_off(netdev); |
3919 | netif_start_queue(netdev); | |
3920 | set_bit(WORK_ENABLE, &tp->flags); | |
db8515ef | 3921 | |
40a82917 | 3922 | res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
3923 | if (res) { | |
3924 | if (res == -ENODEV) | |
3925 | netif_device_detach(tp->netdev); | |
4a8deae2 HW |
3926 | netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", |
3927 | res); | |
ca0a7531 | 3928 | goto out_unlock; |
ac718b69 | 3929 | } |
ca0a7531 | 3930 | napi_enable(&tp->napi); |
ac718b69 | 3931 | |
b5403273 | 3932 | mutex_unlock(&tp->control); |
3933 | ||
9a4be1bd | 3934 | usb_autopm_put_interface(tp->intf); |
5ee3c60c | 3935 | #ifdef CONFIG_PM_SLEEP |
3936 | tp->pm_notifier.notifier_call = rtl_notifier; | |
3937 | register_pm_notifier(&tp->pm_notifier); | |
3938 | #endif | |
ca0a7531 | 3939 | return 0; |
ac718b69 | 3940 | |
ca0a7531 GR |
3941 | out_unlock: |
3942 | mutex_unlock(&tp->control); | |
3943 | usb_autopm_put_interface(tp->intf); | |
3944 | out_free: | |
3945 | free_all_mem(tp); | |
7e9da481 | 3946 | out: |
ac718b69 | 3947 | return res; |
3948 | } | |
3949 | ||
3950 | static int rtl8152_close(struct net_device *netdev) | |
3951 | { | |
3952 | struct r8152 *tp = netdev_priv(netdev); | |
3953 | int res = 0; | |
3954 | ||
5ee3c60c | 3955 | #ifdef CONFIG_PM_SLEEP |
3956 | unregister_pm_notifier(&tp->pm_notifier); | |
3957 | #endif | |
d823ab68 | 3958 | napi_disable(&tp->napi); |
ac718b69 | 3959 | clear_bit(WORK_ENABLE, &tp->flags); |
3d55f44f | 3960 | usb_kill_urb(tp->intr_urb); |
ac718b69 | 3961 | cancel_delayed_work_sync(&tp->schedule); |
3962 | netif_stop_queue(netdev); | |
9a4be1bd | 3963 | |
3964 | res = usb_autopm_get_interface(tp->intf); | |
53543db5 | 3965 | if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) { |
9a4be1bd | 3966 | rtl_drop_queued_tx(tp); |
d823ab68 | 3967 | rtl_stop_rx(tp); |
9a4be1bd | 3968 | } else { |
b5403273 | 3969 | mutex_lock(&tp->control); |
3970 | ||
9a4be1bd | 3971 | tp->rtl_ops.down(tp); |
b5403273 | 3972 | |
3973 | mutex_unlock(&tp->control); | |
3974 | ||
9a4be1bd | 3975 | usb_autopm_put_interface(tp->intf); |
3976 | } | |
ac718b69 | 3977 | |
7e9da481 | 3978 | free_all_mem(tp); |
3979 | ||
ac718b69 | 3980 | return res; |
3981 | } | |
3982 | ||
4f1d4d54 | 3983 | static void rtl_tally_reset(struct r8152 *tp) |
3984 | { | |
3985 | u32 ocp_data; | |
3986 | ||
3987 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); | |
3988 | ocp_data |= TALLY_RESET; | |
3989 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); | |
3990 | } | |
3991 | ||
ac718b69 | 3992 | static void r8152b_init(struct r8152 *tp) |
3993 | { | |
ebc2ec48 | 3994 | u32 ocp_data; |
2dd436da | 3995 | u16 data; |
ac718b69 | 3996 | |
6871438c | 3997 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3998 | return; | |
3999 | ||
2dd436da | 4000 | data = r8152_mdio_read(tp, MII_BMCR); |
4001 | if (data & BMCR_PDOWN) { | |
4002 | data &= ~BMCR_PDOWN; | |
4003 | r8152_mdio_write(tp, MII_BMCR, data); | |
4004 | } | |
4005 | ||
cda9fb01 | 4006 | r8152_aldps_en(tp, false); |
d70b1137 | 4007 | |
ac718b69 | 4008 | if (tp->version == RTL_VER_01) { |
4009 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); | |
4010 | ocp_data &= ~LED_MODE_MASK; | |
4011 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
4012 | } | |
4013 | ||
00a5e360 | 4014 | r8152_power_cut_en(tp, false); |
ac718b69 | 4015 | |
ac718b69 | 4016 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); |
4017 | ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; | |
4018 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
4019 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); | |
4020 | ocp_data &= ~MCU_CLK_RATIO_MASK; | |
4021 | ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; | |
4022 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); | |
4023 | ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | | |
4024 | SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; | |
4025 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); | |
4026 | ||
4f1d4d54 | 4027 | rtl_tally_reset(tp); |
ac718b69 | 4028 | |
ebc2ec48 | 4029 | /* enable rx aggregation */ |
ac718b69 | 4030 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
e90fba8d | 4031 | ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); |
ac718b69 | 4032 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); |
4033 | } | |
4034 | ||
43779f8d | 4035 | static void r8153_init(struct r8152 *tp) |
4036 | { | |
4037 | u32 ocp_data; | |
2dd436da | 4038 | u16 data; |
43779f8d | 4039 | int i; |
4040 | ||
6871438c | 4041 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
4042 | return; | |
4043 | ||
b9702723 | 4044 | r8153_u1u2en(tp, false); |
43779f8d | 4045 | |
4046 | for (i = 0; i < 500; i++) { | |
4047 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & | |
4048 | AUTOLOAD_DONE) | |
4049 | break; | |
4050 | msleep(20); | |
4051 | } | |
4052 | ||
c564b871 | 4053 | data = r8153_phy_status(tp, 0); |
43779f8d | 4054 | |
2dd436da | 4055 | if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 || |
4056 | tp->version == RTL_VER_05) | |
4057 | ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); | |
4058 | ||
4059 | data = r8152_mdio_read(tp, MII_BMCR); | |
4060 | if (data & BMCR_PDOWN) { | |
4061 | data &= ~BMCR_PDOWN; | |
4062 | r8152_mdio_write(tp, MII_BMCR, data); | |
4063 | } | |
4064 | ||
c564b871 | 4065 | data = r8153_phy_status(tp, PHY_STAT_LAN_ON); |
2dd436da | 4066 | |
b9702723 | 4067 | r8153_u2p3en(tp, false); |
43779f8d | 4068 | |
65bab84c | 4069 | if (tp->version == RTL_VER_04) { |
4070 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); | |
4071 | ocp_data &= ~pwd_dn_scale_mask; | |
4072 | ocp_data |= pwd_dn_scale(96); | |
4073 | ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); | |
4074 | ||
4075 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); | |
4076 | ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; | |
4077 | ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); | |
4078 | } else if (tp->version == RTL_VER_05) { | |
4079 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); | |
4080 | ocp_data &= ~ECM_ALDPS; | |
4081 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); | |
4082 | ||
fb02eb4a | 4083 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); |
4084 | if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) | |
4085 | ocp_data &= ~DYNAMIC_BURST; | |
4086 | else | |
4087 | ocp_data |= DYNAMIC_BURST; | |
4088 | ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); | |
4089 | } else if (tp->version == RTL_VER_06) { | |
65bab84c | 4090 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); |
4091 | if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) | |
4092 | ocp_data &= ~DYNAMIC_BURST; | |
4093 | else | |
4094 | ocp_data |= DYNAMIC_BURST; | |
4095 | ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); | |
4096 | } | |
4097 | ||
4098 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); | |
4099 | ocp_data |= EP4_FULL_FC; | |
4100 | ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); | |
4101 | ||
43779f8d | 4102 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); |
4103 | ocp_data &= ~TIMER11_EN; | |
4104 | ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); | |
4105 | ||
43779f8d | 4106 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); |
4107 | ocp_data &= ~LED_MODE_MASK; | |
4108 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
4109 | ||
65bab84c | 4110 | ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; |
2b84af94 | 4111 | if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER) |
43779f8d | 4112 | ocp_data |= LPM_TIMER_500MS; |
34203e25 | 4113 | else |
4114 | ocp_data |= LPM_TIMER_500US; | |
43779f8d | 4115 | ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); |
4116 | ||
4117 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); | |
4118 | ocp_data &= ~SEN_VAL_MASK; | |
4119 | ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; | |
4120 | ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); | |
4121 | ||
65bab84c | 4122 | ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); |
4123 | ||
b9702723 | 4124 | r8153_power_cut_en(tp, false); |
4125 | r8153_u1u2en(tp, true); | |
134f98bc | 4126 | r8153_mac_clk_spd(tp, false); |
ee4761c1 | 4127 | usb_enable_lpm(tp->udev); |
43779f8d | 4128 | |
e31f6367 | 4129 | /* rx aggregation */ |
4130 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); | |
4131 | ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); | |
4132 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); | |
43779f8d | 4133 | |
4f1d4d54 | 4134 | rtl_tally_reset(tp); |
49d10347 | 4135 | |
4136 | switch (tp->udev->speed) { | |
4137 | case USB_SPEED_SUPER: | |
4138 | case USB_SPEED_SUPER_PLUS: | |
4139 | tp->coalesce = COALESCE_SUPER; | |
4140 | break; | |
4141 | case USB_SPEED_HIGH: | |
4142 | tp->coalesce = COALESCE_HIGH; | |
4143 | break; | |
4144 | default: | |
4145 | tp->coalesce = COALESCE_SLOW; | |
4146 | break; | |
4147 | } | |
43779f8d | 4148 | } |
4149 | ||
65b82d69 | 4150 | static void r8153b_init(struct r8152 *tp) |
4151 | { | |
4152 | u32 ocp_data; | |
4153 | u16 data; | |
4154 | int i; | |
4155 | ||
4156 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
4157 | return; | |
4158 | ||
4159 | r8153b_u1u2en(tp, false); | |
4160 | ||
4161 | for (i = 0; i < 500; i++) { | |
4162 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & | |
4163 | AUTOLOAD_DONE) | |
4164 | break; | |
4165 | msleep(20); | |
4166 | } | |
4167 | ||
4168 | data = r8153_phy_status(tp, 0); | |
4169 | ||
4170 | data = r8152_mdio_read(tp, MII_BMCR); | |
4171 | if (data & BMCR_PDOWN) { | |
4172 | data &= ~BMCR_PDOWN; | |
4173 | r8152_mdio_write(tp, MII_BMCR, data); | |
4174 | } | |
4175 | ||
4176 | data = r8153_phy_status(tp, PHY_STAT_LAN_ON); | |
4177 | ||
4178 | r8153_u2p3en(tp, false); | |
4179 | ||
4180 | /* MSC timer = 0xfff * 8ms = 32760 ms */ | |
4181 | ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); | |
4182 | ||
4183 | /* U1/U2/L1 idle timer. 500 us */ | |
4184 | ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); | |
4185 | ||
4186 | r8153b_power_cut_en(tp, false); | |
4187 | r8153b_ups_en(tp, false); | |
4188 | r8153b_queue_wake(tp, false); | |
4189 | rtl_runtime_suspend_enable(tp, false); | |
4190 | r8153b_u1u2en(tp, true); | |
4191 | usb_enable_lpm(tp->udev); | |
4192 | ||
4193 | /* MAC clock speed down */ | |
4194 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); | |
4195 | ocp_data |= MAC_CLK_SPDWN_EN; | |
4196 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); | |
4197 | ||
4198 | set_bit(GREEN_ETHERNET, &tp->flags); | |
4199 | ||
4200 | /* rx aggregation */ | |
4201 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); | |
4202 | ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); | |
4203 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); | |
4204 | ||
4205 | rtl_tally_reset(tp); | |
4206 | ||
4207 | tp->coalesce = 15000; /* 15 us */ | |
4208 | } | |
4209 | ||
e501139a | 4210 | static int rtl8152_pre_reset(struct usb_interface *intf) |
4211 | { | |
4212 | struct r8152 *tp = usb_get_intfdata(intf); | |
4213 | struct net_device *netdev; | |
4214 | ||
4215 | if (!tp) | |
4216 | return 0; | |
4217 | ||
4218 | netdev = tp->netdev; | |
4219 | if (!netif_running(netdev)) | |
4220 | return 0; | |
4221 | ||
de9bf29d | 4222 | netif_stop_queue(netdev); |
e501139a | 4223 | napi_disable(&tp->napi); |
4224 | clear_bit(WORK_ENABLE, &tp->flags); | |
4225 | usb_kill_urb(tp->intr_urb); | |
4226 | cancel_delayed_work_sync(&tp->schedule); | |
4227 | if (netif_carrier_ok(netdev)) { | |
e501139a | 4228 | mutex_lock(&tp->control); |
4229 | tp->rtl_ops.disable(tp); | |
4230 | mutex_unlock(&tp->control); | |
4231 | } | |
4232 | ||
4233 | return 0; | |
4234 | } | |
4235 | ||
4236 | static int rtl8152_post_reset(struct usb_interface *intf) | |
4237 | { | |
4238 | struct r8152 *tp = usb_get_intfdata(intf); | |
4239 | struct net_device *netdev; | |
4240 | ||
4241 | if (!tp) | |
4242 | return 0; | |
4243 | ||
4244 | netdev = tp->netdev; | |
4245 | if (!netif_running(netdev)) | |
4246 | return 0; | |
4247 | ||
4248 | set_bit(WORK_ENABLE, &tp->flags); | |
4249 | if (netif_carrier_ok(netdev)) { | |
4250 | mutex_lock(&tp->control); | |
4251 | tp->rtl_ops.enable(tp); | |
2c561b2b | 4252 | rtl_start_rx(tp); |
e501139a | 4253 | rtl8152_set_rx_mode(netdev); |
4254 | mutex_unlock(&tp->control); | |
e501139a | 4255 | } |
4256 | ||
4257 | napi_enable(&tp->napi); | |
de9bf29d | 4258 | netif_wake_queue(netdev); |
2c561b2b | 4259 | usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
e501139a | 4260 | |
7489bdad | 4261 | if (!list_empty(&tp->rx_done)) |
4262 | napi_schedule(&tp->napi); | |
e501139a | 4263 | |
4264 | return 0; | |
43779f8d | 4265 | } |
4266 | ||
2dd49e0f | 4267 | static bool delay_autosuspend(struct r8152 *tp) |
4268 | { | |
4269 | bool sw_linking = !!netif_carrier_ok(tp->netdev); | |
4270 | bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS); | |
4271 | ||
4272 | /* This means a linking change occurs and the driver doesn't detect it, | |
4273 | * yet. If the driver has disabled tx/rx and hw is linking on, the | |
4274 | * device wouldn't wake up by receiving any packet. | |
4275 | */ | |
4276 | if (work_busy(&tp->schedule.work) || sw_linking != hw_linking) | |
4277 | return true; | |
4278 | ||
4279 | /* If the linking down is occurred by nway, the device may miss the | |
4280 | * linking change event. And it wouldn't wake when linking on. | |
4281 | */ | |
4282 | if (!sw_linking && tp->rtl_ops.in_nway(tp)) | |
4283 | return true; | |
6a0b76c0 | 4284 | else if (!skb_queue_empty(&tp->tx_queue)) |
4285 | return true; | |
2dd49e0f | 4286 | else |
4287 | return false; | |
4288 | } | |
4289 | ||
a9c54ad2 | 4290 | static int rtl8152_runtime_suspend(struct r8152 *tp) |
ac718b69 | 4291 | { |
6cc69f2a | 4292 | struct net_device *netdev = tp->netdev; |
4293 | int ret = 0; | |
ac718b69 | 4294 | |
26afec39 | 4295 | set_bit(SELECTIVE_SUSPEND, &tp->flags); |
4296 | smp_mb__after_atomic(); | |
4297 | ||
8fb28061 | 4298 | if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { |
75dc692e | 4299 | u32 rcr = 0; |
4300 | ||
8fb28061 | 4301 | if (delay_autosuspend(tp)) { |
26afec39 | 4302 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); |
4303 | smp_mb__after_atomic(); | |
6cc69f2a | 4304 | ret = -EBUSY; |
4305 | goto out1; | |
4306 | } | |
4307 | ||
75dc692e | 4308 | if (netif_carrier_ok(netdev)) { |
4309 | u32 ocp_data; | |
4310 | ||
4311 | rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
4312 | ocp_data = rcr & ~RCR_ACPT_ALL; | |
4313 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
4314 | rxdy_gated_en(tp, true); | |
4315 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, | |
4316 | PLA_OOB_CTRL); | |
4317 | if (!(ocp_data & RXFIFO_EMPTY)) { | |
4318 | rxdy_gated_en(tp, false); | |
4319 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); | |
26afec39 | 4320 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); |
4321 | smp_mb__after_atomic(); | |
75dc692e | 4322 | ret = -EBUSY; |
4323 | goto out1; | |
4324 | } | |
4325 | } | |
4326 | ||
8fb28061 | 4327 | clear_bit(WORK_ENABLE, &tp->flags); |
4328 | usb_kill_urb(tp->intr_urb); | |
75dc692e | 4329 | |
8fb28061 | 4330 | tp->rtl_ops.autosuspend_en(tp, true); |
75dc692e | 4331 | |
4332 | if (netif_carrier_ok(netdev)) { | |
ce594e98 | 4333 | struct napi_struct *napi = &tp->napi; |
4334 | ||
4335 | napi_disable(napi); | |
75dc692e | 4336 | rtl_stop_rx(tp); |
4337 | rxdy_gated_en(tp, false); | |
4338 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); | |
ce594e98 | 4339 | napi_enable(napi); |
75dc692e | 4340 | } |
6cc69f2a | 4341 | } |
ac718b69 | 4342 | |
8fb28061 | 4343 | out1: |
4344 | return ret; | |
4345 | } | |
4346 | ||
4347 | static int rtl8152_system_suspend(struct r8152 *tp) | |
4348 | { | |
4349 | struct net_device *netdev = tp->netdev; | |
4350 | int ret = 0; | |
4351 | ||
4352 | netif_device_detach(netdev); | |
4353 | ||
e3bd1a81 | 4354 | if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { |
ce594e98 | 4355 | struct napi_struct *napi = &tp->napi; |
4356 | ||
ac718b69 | 4357 | clear_bit(WORK_ENABLE, &tp->flags); |
40a82917 | 4358 | usb_kill_urb(tp->intr_urb); |
ce594e98 | 4359 | napi_disable(napi); |
8fb28061 | 4360 | cancel_delayed_work_sync(&tp->schedule); |
4361 | tp->rtl_ops.down(tp); | |
ce594e98 | 4362 | napi_enable(napi); |
ac718b69 | 4363 | } |
8fb28061 | 4364 | |
4365 | return ret; | |
4366 | } | |
4367 | ||
4368 | static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) | |
4369 | { | |
4370 | struct r8152 *tp = usb_get_intfdata(intf); | |
4371 | int ret; | |
4372 | ||
4373 | mutex_lock(&tp->control); | |
4374 | ||
4375 | if (PMSG_IS_AUTO(message)) | |
a9c54ad2 | 4376 | ret = rtl8152_runtime_suspend(tp); |
8fb28061 | 4377 | else |
4378 | ret = rtl8152_system_suspend(tp); | |
4379 | ||
b5403273 | 4380 | mutex_unlock(&tp->control); |
4381 | ||
6cc69f2a | 4382 | return ret; |
ac718b69 | 4383 | } |
4384 | ||
4385 | static int rtl8152_resume(struct usb_interface *intf) | |
4386 | { | |
4387 | struct r8152 *tp = usb_get_intfdata(intf); | |
ce594e98 | 4388 | struct net_device *netdev = tp->netdev; |
ac718b69 | 4389 | |
b5403273 | 4390 | mutex_lock(&tp->control); |
4391 | ||
befb2de1 | 4392 | if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) |
ce594e98 | 4393 | netif_device_attach(netdev); |
9a4be1bd | 4394 | |
ce594e98 | 4395 | if (netif_running(netdev) && netdev->flags & IFF_UP) { |
9a4be1bd | 4396 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
ce594e98 | 4397 | struct napi_struct *napi = &tp->napi; |
4398 | ||
2609af19 | 4399 | tp->rtl_ops.autosuspend_en(tp, false); |
ce594e98 | 4400 | napi_disable(napi); |
445f7f4d | 4401 | set_bit(WORK_ENABLE, &tp->flags); |
6f14f443 | 4402 | if (netif_carrier_ok(netdev)) { |
2f25abe6 | 4403 | if (rtl8152_get_speed(tp) & LINK_STATUS) { |
4404 | rtl_start_rx(tp); | |
4405 | } else { | |
6f14f443 | 4406 | netif_carrier_off(netdev); |
2f25abe6 | 4407 | tp->rtl_ops.disable(tp); |
6f14f443 | 4408 | netif_info(tp, link, netdev, |
2f25abe6 | 4409 | "linking down\n"); |
4410 | } | |
4411 | } | |
ce594e98 | 4412 | napi_enable(napi); |
26afec39 | 4413 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); |
4414 | smp_mb__after_atomic(); | |
7489bdad | 4415 | if (!list_empty(&tp->rx_done)) |
4416 | napi_schedule(&tp->napi); | |
9a4be1bd | 4417 | } else { |
4418 | tp->rtl_ops.up(tp); | |
ce594e98 | 4419 | netif_carrier_off(netdev); |
445f7f4d | 4420 | set_bit(WORK_ENABLE, &tp->flags); |
9a4be1bd | 4421 | } |
40a82917 | 4422 | usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
923e1ee3 | 4423 | } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
ce594e98 | 4424 | if (netdev->flags & IFF_UP) |
2609af19 | 4425 | tp->rtl_ops.autosuspend_en(tp, false); |
923e1ee3 | 4426 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); |
ac718b69 | 4427 | } |
4428 | ||
b5403273 | 4429 | mutex_unlock(&tp->control); |
4430 | ||
ac718b69 | 4431 | return 0; |
4432 | } | |
4433 | ||
7ec2541a | 4434 | static int rtl8152_reset_resume(struct usb_interface *intf) |
4435 | { | |
4436 | struct r8152 *tp = usb_get_intfdata(intf); | |
4437 | ||
4438 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
befb2de1 | 4439 | mutex_lock(&tp->control); |
4440 | tp->rtl_ops.init(tp); | |
4441 | queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); | |
4442 | mutex_unlock(&tp->control); | |
7ec2541a | 4443 | return rtl8152_resume(intf); |
4444 | } | |
4445 | ||
21ff2e89 | 4446 | static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
4447 | { | |
4448 | struct r8152 *tp = netdev_priv(dev); | |
4449 | ||
9a4be1bd | 4450 | if (usb_autopm_get_interface(tp->intf) < 0) |
4451 | return; | |
4452 | ||
7daed8dc | 4453 | if (!rtl_can_wakeup(tp)) { |
4454 | wol->supported = 0; | |
4455 | wol->wolopts = 0; | |
4456 | } else { | |
4457 | mutex_lock(&tp->control); | |
4458 | wol->supported = WAKE_ANY; | |
4459 | wol->wolopts = __rtl_get_wol(tp); | |
4460 | mutex_unlock(&tp->control); | |
4461 | } | |
b5403273 | 4462 | |
9a4be1bd | 4463 | usb_autopm_put_interface(tp->intf); |
21ff2e89 | 4464 | } |
4465 | ||
4466 | static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
4467 | { | |
4468 | struct r8152 *tp = netdev_priv(dev); | |
9a4be1bd | 4469 | int ret; |
4470 | ||
7daed8dc | 4471 | if (!rtl_can_wakeup(tp)) |
4472 | return -EOPNOTSUPP; | |
4473 | ||
9a4be1bd | 4474 | ret = usb_autopm_get_interface(tp->intf); |
4475 | if (ret < 0) | |
4476 | goto out_set_wol; | |
21ff2e89 | 4477 | |
b5403273 | 4478 | mutex_lock(&tp->control); |
4479 | ||
21ff2e89 | 4480 | __rtl_set_wol(tp, wol->wolopts); |
4481 | tp->saved_wolopts = wol->wolopts & WAKE_ANY; | |
4482 | ||
b5403273 | 4483 | mutex_unlock(&tp->control); |
4484 | ||
9a4be1bd | 4485 | usb_autopm_put_interface(tp->intf); |
4486 | ||
4487 | out_set_wol: | |
4488 | return ret; | |
21ff2e89 | 4489 | } |
4490 | ||
a5ec27c1 | 4491 | static u32 rtl8152_get_msglevel(struct net_device *dev) |
4492 | { | |
4493 | struct r8152 *tp = netdev_priv(dev); | |
4494 | ||
4495 | return tp->msg_enable; | |
4496 | } | |
4497 | ||
4498 | static void rtl8152_set_msglevel(struct net_device *dev, u32 value) | |
4499 | { | |
4500 | struct r8152 *tp = netdev_priv(dev); | |
4501 | ||
4502 | tp->msg_enable = value; | |
4503 | } | |
4504 | ||
ac718b69 | 4505 | static void rtl8152_get_drvinfo(struct net_device *netdev, |
4506 | struct ethtool_drvinfo *info) | |
4507 | { | |
4508 | struct r8152 *tp = netdev_priv(netdev); | |
4509 | ||
b0b46c77 | 4510 | strlcpy(info->driver, MODULENAME, sizeof(info->driver)); |
4511 | strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); | |
ac718b69 | 4512 | usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); |
4513 | } | |
4514 | ||
4515 | static | |
06144dcf PR |
4516 | int rtl8152_get_link_ksettings(struct net_device *netdev, |
4517 | struct ethtool_link_ksettings *cmd) | |
ac718b69 | 4518 | { |
4519 | struct r8152 *tp = netdev_priv(netdev); | |
8d4a4d72 | 4520 | int ret; |
ac718b69 | 4521 | |
4522 | if (!tp->mii.mdio_read) | |
4523 | return -EOPNOTSUPP; | |
4524 | ||
8d4a4d72 | 4525 | ret = usb_autopm_get_interface(tp->intf); |
4526 | if (ret < 0) | |
4527 | goto out; | |
4528 | ||
b5403273 | 4529 | mutex_lock(&tp->control); |
4530 | ||
82c01a84 | 4531 | mii_ethtool_get_link_ksettings(&tp->mii, cmd); |
8d4a4d72 | 4532 | |
b5403273 | 4533 | mutex_unlock(&tp->control); |
4534 | ||
8d4a4d72 | 4535 | usb_autopm_put_interface(tp->intf); |
4536 | ||
4537 | out: | |
4538 | return ret; | |
ac718b69 | 4539 | } |
4540 | ||
06144dcf PR |
4541 | static int rtl8152_set_link_ksettings(struct net_device *dev, |
4542 | const struct ethtool_link_ksettings *cmd) | |
ac718b69 | 4543 | { |
4544 | struct r8152 *tp = netdev_priv(dev); | |
9a4be1bd | 4545 | int ret; |
4546 | ||
4547 | ret = usb_autopm_get_interface(tp->intf); | |
4548 | if (ret < 0) | |
4549 | goto out; | |
ac718b69 | 4550 | |
b5403273 | 4551 | mutex_lock(&tp->control); |
4552 | ||
06144dcf PR |
4553 | ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed, |
4554 | cmd->base.duplex); | |
aa7e26b6 | 4555 | if (!ret) { |
06144dcf PR |
4556 | tp->autoneg = cmd->base.autoneg; |
4557 | tp->speed = cmd->base.speed; | |
4558 | tp->duplex = cmd->base.duplex; | |
aa7e26b6 | 4559 | } |
9a4be1bd | 4560 | |
b5403273 | 4561 | mutex_unlock(&tp->control); |
4562 | ||
9a4be1bd | 4563 | usb_autopm_put_interface(tp->intf); |
4564 | ||
4565 | out: | |
4566 | return ret; | |
ac718b69 | 4567 | } |
4568 | ||
4f1d4d54 | 4569 | static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { |
4570 | "tx_packets", | |
4571 | "rx_packets", | |
4572 | "tx_errors", | |
4573 | "rx_errors", | |
4574 | "rx_missed", | |
4575 | "align_errors", | |
4576 | "tx_single_collisions", | |
4577 | "tx_multi_collisions", | |
4578 | "rx_unicast", | |
4579 | "rx_broadcast", | |
4580 | "rx_multicast", | |
4581 | "tx_aborted", | |
4582 | "tx_underrun", | |
4583 | }; | |
4584 | ||
4585 | static int rtl8152_get_sset_count(struct net_device *dev, int sset) | |
4586 | { | |
4587 | switch (sset) { | |
4588 | case ETH_SS_STATS: | |
4589 | return ARRAY_SIZE(rtl8152_gstrings); | |
4590 | default: | |
4591 | return -EOPNOTSUPP; | |
4592 | } | |
4593 | } | |
4594 | ||
4595 | static void rtl8152_get_ethtool_stats(struct net_device *dev, | |
4596 | struct ethtool_stats *stats, u64 *data) | |
4597 | { | |
4598 | struct r8152 *tp = netdev_priv(dev); | |
4599 | struct tally_counter tally; | |
4600 | ||
0b030244 | 4601 | if (usb_autopm_get_interface(tp->intf) < 0) |
4602 | return; | |
4603 | ||
4f1d4d54 | 4604 | generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); |
4605 | ||
0b030244 | 4606 | usb_autopm_put_interface(tp->intf); |
4607 | ||
4f1d4d54 | 4608 | data[0] = le64_to_cpu(tally.tx_packets); |
4609 | data[1] = le64_to_cpu(tally.rx_packets); | |
4610 | data[2] = le64_to_cpu(tally.tx_errors); | |
4611 | data[3] = le32_to_cpu(tally.rx_errors); | |
4612 | data[4] = le16_to_cpu(tally.rx_missed); | |
4613 | data[5] = le16_to_cpu(tally.align_errors); | |
4614 | data[6] = le32_to_cpu(tally.tx_one_collision); | |
4615 | data[7] = le32_to_cpu(tally.tx_multi_collision); | |
4616 | data[8] = le64_to_cpu(tally.rx_unicast); | |
4617 | data[9] = le64_to_cpu(tally.rx_broadcast); | |
4618 | data[10] = le32_to_cpu(tally.rx_multicast); | |
4619 | data[11] = le16_to_cpu(tally.tx_aborted); | |
f37119c5 | 4620 | data[12] = le16_to_cpu(tally.tx_underrun); |
4f1d4d54 | 4621 | } |
4622 | ||
4623 | static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) | |
4624 | { | |
4625 | switch (stringset) { | |
4626 | case ETH_SS_STATS: | |
4627 | memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); | |
4628 | break; | |
4629 | } | |
4630 | } | |
4631 | ||
df35d283 | 4632 | static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee) |
4633 | { | |
4634 | u32 ocp_data, lp, adv, supported = 0; | |
4635 | u16 val; | |
4636 | ||
4637 | val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); | |
4638 | supported = mmd_eee_cap_to_ethtool_sup_t(val); | |
4639 | ||
4640 | val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV); | |
4641 | adv = mmd_eee_adv_to_ethtool_adv_t(val); | |
4642 | ||
4643 | val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); | |
4644 | lp = mmd_eee_adv_to_ethtool_adv_t(val); | |
4645 | ||
4646 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
4647 | ocp_data &= EEE_RX_EN | EEE_TX_EN; | |
4648 | ||
4649 | eee->eee_enabled = !!ocp_data; | |
4650 | eee->eee_active = !!(supported & adv & lp); | |
4651 | eee->supported = supported; | |
4652 | eee->advertised = adv; | |
4653 | eee->lp_advertised = lp; | |
4654 | ||
4655 | return 0; | |
4656 | } | |
4657 | ||
4658 | static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee) | |
4659 | { | |
4660 | u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); | |
4661 | ||
4662 | r8152_eee_en(tp, eee->eee_enabled); | |
4663 | ||
4664 | if (!eee->eee_enabled) | |
4665 | val = 0; | |
4666 | ||
4667 | r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); | |
4668 | ||
4669 | return 0; | |
4670 | } | |
4671 | ||
4672 | static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee) | |
4673 | { | |
4674 | u32 ocp_data, lp, adv, supported = 0; | |
4675 | u16 val; | |
4676 | ||
4677 | val = ocp_reg_read(tp, OCP_EEE_ABLE); | |
4678 | supported = mmd_eee_cap_to_ethtool_sup_t(val); | |
4679 | ||
4680 | val = ocp_reg_read(tp, OCP_EEE_ADV); | |
4681 | adv = mmd_eee_adv_to_ethtool_adv_t(val); | |
4682 | ||
4683 | val = ocp_reg_read(tp, OCP_EEE_LPABLE); | |
4684 | lp = mmd_eee_adv_to_ethtool_adv_t(val); | |
4685 | ||
4686 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
4687 | ocp_data &= EEE_RX_EN | EEE_TX_EN; | |
4688 | ||
4689 | eee->eee_enabled = !!ocp_data; | |
4690 | eee->eee_active = !!(supported & adv & lp); | |
4691 | eee->supported = supported; | |
4692 | eee->advertised = adv; | |
4693 | eee->lp_advertised = lp; | |
4694 | ||
4695 | return 0; | |
4696 | } | |
4697 | ||
4698 | static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee) | |
4699 | { | |
4700 | u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); | |
4701 | ||
4702 | r8153_eee_en(tp, eee->eee_enabled); | |
4703 | ||
4704 | if (!eee->eee_enabled) | |
4705 | val = 0; | |
4706 | ||
4707 | ocp_reg_write(tp, OCP_EEE_ADV, val); | |
4708 | ||
4709 | return 0; | |
4710 | } | |
4711 | ||
65b82d69 | 4712 | static int r8153b_set_eee(struct r8152 *tp, struct ethtool_eee *eee) |
4713 | { | |
4714 | u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); | |
4715 | ||
4716 | r8153b_eee_en(tp, eee->eee_enabled); | |
4717 | ||
4718 | if (!eee->eee_enabled) | |
4719 | val = 0; | |
4720 | ||
4721 | ocp_reg_write(tp, OCP_EEE_ADV, val); | |
4722 | ||
4723 | return 0; | |
4724 | } | |
4725 | ||
df35d283 | 4726 | static int |
4727 | rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) | |
4728 | { | |
4729 | struct r8152 *tp = netdev_priv(net); | |
4730 | int ret; | |
4731 | ||
4732 | ret = usb_autopm_get_interface(tp->intf); | |
4733 | if (ret < 0) | |
4734 | goto out; | |
4735 | ||
b5403273 | 4736 | mutex_lock(&tp->control); |
4737 | ||
df35d283 | 4738 | ret = tp->rtl_ops.eee_get(tp, edata); |
4739 | ||
b5403273 | 4740 | mutex_unlock(&tp->control); |
4741 | ||
df35d283 | 4742 | usb_autopm_put_interface(tp->intf); |
4743 | ||
4744 | out: | |
4745 | return ret; | |
4746 | } | |
4747 | ||
4748 | static int | |
4749 | rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) | |
4750 | { | |
4751 | struct r8152 *tp = netdev_priv(net); | |
4752 | int ret; | |
4753 | ||
4754 | ret = usb_autopm_get_interface(tp->intf); | |
4755 | if (ret < 0) | |
4756 | goto out; | |
4757 | ||
b5403273 | 4758 | mutex_lock(&tp->control); |
4759 | ||
df35d283 | 4760 | ret = tp->rtl_ops.eee_set(tp, edata); |
9d31a7b9 | 4761 | if (!ret) |
4762 | ret = mii_nway_restart(&tp->mii); | |
df35d283 | 4763 | |
b5403273 | 4764 | mutex_unlock(&tp->control); |
4765 | ||
df35d283 | 4766 | usb_autopm_put_interface(tp->intf); |
4767 | ||
4768 | out: | |
4769 | return ret; | |
4770 | } | |
4771 | ||
8884f507 | 4772 | static int rtl8152_nway_reset(struct net_device *dev) |
4773 | { | |
4774 | struct r8152 *tp = netdev_priv(dev); | |
4775 | int ret; | |
4776 | ||
4777 | ret = usb_autopm_get_interface(tp->intf); | |
4778 | if (ret < 0) | |
4779 | goto out; | |
4780 | ||
4781 | mutex_lock(&tp->control); | |
4782 | ||
4783 | ret = mii_nway_restart(&tp->mii); | |
4784 | ||
4785 | mutex_unlock(&tp->control); | |
4786 | ||
4787 | usb_autopm_put_interface(tp->intf); | |
4788 | ||
4789 | out: | |
4790 | return ret; | |
4791 | } | |
4792 | ||
efb3dd88 | 4793 | static int rtl8152_get_coalesce(struct net_device *netdev, |
4794 | struct ethtool_coalesce *coalesce) | |
4795 | { | |
4796 | struct r8152 *tp = netdev_priv(netdev); | |
4797 | ||
4798 | switch (tp->version) { | |
4799 | case RTL_VER_01: | |
4800 | case RTL_VER_02: | |
c27b32c2 | 4801 | case RTL_VER_07: |
efb3dd88 | 4802 | return -EOPNOTSUPP; |
4803 | default: | |
4804 | break; | |
4805 | } | |
4806 | ||
4807 | coalesce->rx_coalesce_usecs = tp->coalesce; | |
4808 | ||
4809 | return 0; | |
4810 | } | |
4811 | ||
4812 | static int rtl8152_set_coalesce(struct net_device *netdev, | |
4813 | struct ethtool_coalesce *coalesce) | |
4814 | { | |
4815 | struct r8152 *tp = netdev_priv(netdev); | |
4816 | int ret; | |
4817 | ||
4818 | switch (tp->version) { | |
4819 | case RTL_VER_01: | |
4820 | case RTL_VER_02: | |
c27b32c2 | 4821 | case RTL_VER_07: |
efb3dd88 | 4822 | return -EOPNOTSUPP; |
4823 | default: | |
4824 | break; | |
4825 | } | |
4826 | ||
4827 | if (coalesce->rx_coalesce_usecs > COALESCE_SLOW) | |
4828 | return -EINVAL; | |
4829 | ||
4830 | ret = usb_autopm_get_interface(tp->intf); | |
4831 | if (ret < 0) | |
4832 | return ret; | |
4833 | ||
4834 | mutex_lock(&tp->control); | |
4835 | ||
4836 | if (tp->coalesce != coalesce->rx_coalesce_usecs) { | |
4837 | tp->coalesce = coalesce->rx_coalesce_usecs; | |
4838 | ||
4839 | if (netif_running(tp->netdev) && netif_carrier_ok(netdev)) | |
4840 | r8153_set_rx_early_timeout(tp); | |
4841 | } | |
4842 | ||
4843 | mutex_unlock(&tp->control); | |
4844 | ||
4845 | usb_autopm_put_interface(tp->intf); | |
4846 | ||
4847 | return ret; | |
4848 | } | |
4849 | ||
407a471d | 4850 | static const struct ethtool_ops ops = { |
ac718b69 | 4851 | .get_drvinfo = rtl8152_get_drvinfo, |
ac718b69 | 4852 | .get_link = ethtool_op_get_link, |
8884f507 | 4853 | .nway_reset = rtl8152_nway_reset, |
a5ec27c1 | 4854 | .get_msglevel = rtl8152_get_msglevel, |
4855 | .set_msglevel = rtl8152_set_msglevel, | |
21ff2e89 | 4856 | .get_wol = rtl8152_get_wol, |
4857 | .set_wol = rtl8152_set_wol, | |
4f1d4d54 | 4858 | .get_strings = rtl8152_get_strings, |
4859 | .get_sset_count = rtl8152_get_sset_count, | |
4860 | .get_ethtool_stats = rtl8152_get_ethtool_stats, | |
efb3dd88 | 4861 | .get_coalesce = rtl8152_get_coalesce, |
4862 | .set_coalesce = rtl8152_set_coalesce, | |
df35d283 | 4863 | .get_eee = rtl_ethtool_get_eee, |
4864 | .set_eee = rtl_ethtool_set_eee, | |
06144dcf PR |
4865 | .get_link_ksettings = rtl8152_get_link_ksettings, |
4866 | .set_link_ksettings = rtl8152_set_link_ksettings, | |
ac718b69 | 4867 | }; |
4868 | ||
4869 | static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) | |
4870 | { | |
4871 | struct r8152 *tp = netdev_priv(netdev); | |
4872 | struct mii_ioctl_data *data = if_mii(rq); | |
9a4be1bd | 4873 | int res; |
4874 | ||
6871438c | 4875 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
4876 | return -ENODEV; | |
4877 | ||
9a4be1bd | 4878 | res = usb_autopm_get_interface(tp->intf); |
4879 | if (res < 0) | |
4880 | goto out; | |
ac718b69 | 4881 | |
4882 | switch (cmd) { | |
4883 | case SIOCGMIIPHY: | |
4884 | data->phy_id = R8152_PHY_ID; /* Internal PHY */ | |
4885 | break; | |
4886 | ||
4887 | case SIOCGMIIREG: | |
b5403273 | 4888 | mutex_lock(&tp->control); |
ac718b69 | 4889 | data->val_out = r8152_mdio_read(tp, data->reg_num); |
b5403273 | 4890 | mutex_unlock(&tp->control); |
ac718b69 | 4891 | break; |
4892 | ||
4893 | case SIOCSMIIREG: | |
4894 | if (!capable(CAP_NET_ADMIN)) { | |
4895 | res = -EPERM; | |
4896 | break; | |
4897 | } | |
b5403273 | 4898 | mutex_lock(&tp->control); |
ac718b69 | 4899 | r8152_mdio_write(tp, data->reg_num, data->val_in); |
b5403273 | 4900 | mutex_unlock(&tp->control); |
ac718b69 | 4901 | break; |
4902 | ||
4903 | default: | |
4904 | res = -EOPNOTSUPP; | |
4905 | } | |
4906 | ||
9a4be1bd | 4907 | usb_autopm_put_interface(tp->intf); |
4908 | ||
4909 | out: | |
ac718b69 | 4910 | return res; |
4911 | } | |
4912 | ||
69b4b7a4 | 4913 | static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) |
4914 | { | |
4915 | struct r8152 *tp = netdev_priv(dev); | |
396e2e23 | 4916 | int ret; |
69b4b7a4 | 4917 | |
4918 | switch (tp->version) { | |
4919 | case RTL_VER_01: | |
4920 | case RTL_VER_02: | |
c27b32c2 | 4921 | case RTL_VER_07: |
a52ad514 JW |
4922 | dev->mtu = new_mtu; |
4923 | return 0; | |
69b4b7a4 | 4924 | default: |
4925 | break; | |
4926 | } | |
4927 | ||
396e2e23 | 4928 | ret = usb_autopm_get_interface(tp->intf); |
4929 | if (ret < 0) | |
4930 | return ret; | |
4931 | ||
4932 | mutex_lock(&tp->control); | |
4933 | ||
69b4b7a4 | 4934 | dev->mtu = new_mtu; |
4935 | ||
210c4f70 | 4936 | if (netif_running(dev)) { |
4937 | u32 rms = new_mtu + VLAN_ETH_HLEN + CRC_SIZE; | |
4938 | ||
4939 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms); | |
4940 | ||
4941 | if (netif_carrier_ok(dev)) | |
4942 | r8153_set_rx_early_size(tp); | |
4943 | } | |
396e2e23 | 4944 | |
4945 | mutex_unlock(&tp->control); | |
4946 | ||
4947 | usb_autopm_put_interface(tp->intf); | |
4948 | ||
4949 | return ret; | |
69b4b7a4 | 4950 | } |
4951 | ||
ac718b69 | 4952 | static const struct net_device_ops rtl8152_netdev_ops = { |
4953 | .ndo_open = rtl8152_open, | |
4954 | .ndo_stop = rtl8152_close, | |
4955 | .ndo_do_ioctl = rtl8152_ioctl, | |
4956 | .ndo_start_xmit = rtl8152_start_xmit, | |
4957 | .ndo_tx_timeout = rtl8152_tx_timeout, | |
c5554298 | 4958 | .ndo_set_features = rtl8152_set_features, |
ac718b69 | 4959 | .ndo_set_rx_mode = rtl8152_set_rx_mode, |
4960 | .ndo_set_mac_address = rtl8152_set_mac_address, | |
69b4b7a4 | 4961 | .ndo_change_mtu = rtl8152_change_mtu, |
ac718b69 | 4962 | .ndo_validate_addr = eth_validate_addr, |
a5e31255 | 4963 | .ndo_features_check = rtl8152_features_check, |
ac718b69 | 4964 | }; |
4965 | ||
e3fe0b1a | 4966 | static void rtl8152_unload(struct r8152 *tp) |
4967 | { | |
6871438c | 4968 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
4969 | return; | |
4970 | ||
00a5e360 | 4971 | if (tp->version != RTL_VER_01) |
4972 | r8152_power_cut_en(tp, true); | |
e3fe0b1a | 4973 | } |
4974 | ||
43779f8d | 4975 | static void rtl8153_unload(struct r8152 *tp) |
4976 | { | |
6871438c | 4977 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
4978 | return; | |
4979 | ||
49be1723 | 4980 | r8153_power_cut_en(tp, false); |
43779f8d | 4981 | } |
4982 | ||
65b82d69 | 4983 | static void rtl8153b_unload(struct r8152 *tp) |
4984 | { | |
4985 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
4986 | return; | |
4987 | ||
4988 | r8153b_power_cut_en(tp, false); | |
4989 | } | |
4990 | ||
55b65475 | 4991 | static int rtl_ops_init(struct r8152 *tp) |
c81229c9 | 4992 | { |
4993 | struct rtl_ops *ops = &tp->rtl_ops; | |
55b65475 | 4994 | int ret = 0; |
4995 | ||
4996 | switch (tp->version) { | |
4997 | case RTL_VER_01: | |
4998 | case RTL_VER_02: | |
c27b32c2 | 4999 | case RTL_VER_07: |
55b65475 | 5000 | ops->init = r8152b_init; |
5001 | ops->enable = rtl8152_enable; | |
5002 | ops->disable = rtl8152_disable; | |
5003 | ops->up = rtl8152_up; | |
5004 | ops->down = rtl8152_down; | |
5005 | ops->unload = rtl8152_unload; | |
5006 | ops->eee_get = r8152_get_eee; | |
5007 | ops->eee_set = r8152_set_eee; | |
2dd49e0f | 5008 | ops->in_nway = rtl8152_in_nway; |
a028a9e0 | 5009 | ops->hw_phy_cfg = r8152b_hw_phy_cfg; |
2609af19 | 5010 | ops->autosuspend_en = rtl_runtime_suspend_enable; |
43779f8d | 5011 | break; |
5012 | ||
55b65475 | 5013 | case RTL_VER_03: |
5014 | case RTL_VER_04: | |
5015 | case RTL_VER_05: | |
fb02eb4a | 5016 | case RTL_VER_06: |
55b65475 | 5017 | ops->init = r8153_init; |
5018 | ops->enable = rtl8153_enable; | |
5019 | ops->disable = rtl8153_disable; | |
5020 | ops->up = rtl8153_up; | |
5021 | ops->down = rtl8153_down; | |
5022 | ops->unload = rtl8153_unload; | |
5023 | ops->eee_get = r8153_get_eee; | |
5024 | ops->eee_set = r8153_set_eee; | |
2dd49e0f | 5025 | ops->in_nway = rtl8153_in_nway; |
a028a9e0 | 5026 | ops->hw_phy_cfg = r8153_hw_phy_cfg; |
2609af19 | 5027 | ops->autosuspend_en = rtl8153_runtime_enable; |
c81229c9 | 5028 | break; |
5029 | ||
65b82d69 | 5030 | case RTL_VER_08: |
5031 | case RTL_VER_09: | |
5032 | ops->init = r8153b_init; | |
5033 | ops->enable = rtl8153_enable; | |
5034 | ops->disable = rtl8153b_disable; | |
5035 | ops->up = rtl8153b_up; | |
5036 | ops->down = rtl8153b_down; | |
5037 | ops->unload = rtl8153b_unload; | |
5038 | ops->eee_get = r8153_get_eee; | |
5039 | ops->eee_set = r8153b_set_eee; | |
5040 | ops->in_nway = rtl8153_in_nway; | |
5041 | ops->hw_phy_cfg = r8153b_hw_phy_cfg; | |
5042 | ops->autosuspend_en = rtl8153b_runtime_enable; | |
5043 | break; | |
5044 | ||
c81229c9 | 5045 | default: |
55b65475 | 5046 | ret = -ENODEV; |
5047 | netif_err(tp, probe, tp->netdev, "Unknown Device\n"); | |
c81229c9 | 5048 | break; |
5049 | } | |
5050 | ||
5051 | return ret; | |
5052 | } | |
5053 | ||
33928eed | 5054 | static u8 rtl_get_version(struct usb_interface *intf) |
5055 | { | |
5056 | struct usb_device *udev = interface_to_usbdev(intf); | |
5057 | u32 ocp_data = 0; | |
5058 | __le32 *tmp; | |
5059 | u8 version; | |
5060 | int ret; | |
5061 | ||
5062 | tmp = kmalloc(sizeof(*tmp), GFP_KERNEL); | |
5063 | if (!tmp) | |
5064 | return 0; | |
5065 | ||
5066 | ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), | |
5067 | RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, | |
5068 | PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500); | |
5069 | if (ret > 0) | |
5070 | ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK; | |
5071 | ||
5072 | kfree(tmp); | |
5073 | ||
5074 | switch (ocp_data) { | |
5075 | case 0x4c00: | |
5076 | version = RTL_VER_01; | |
5077 | break; | |
5078 | case 0x4c10: | |
5079 | version = RTL_VER_02; | |
5080 | break; | |
5081 | case 0x5c00: | |
5082 | version = RTL_VER_03; | |
5083 | break; | |
5084 | case 0x5c10: | |
5085 | version = RTL_VER_04; | |
5086 | break; | |
5087 | case 0x5c20: | |
5088 | version = RTL_VER_05; | |
5089 | break; | |
5090 | case 0x5c30: | |
5091 | version = RTL_VER_06; | |
5092 | break; | |
c27b32c2 | 5093 | case 0x4800: |
5094 | version = RTL_VER_07; | |
5095 | break; | |
65b82d69 | 5096 | case 0x6000: |
5097 | version = RTL_VER_08; | |
5098 | break; | |
5099 | case 0x6010: | |
5100 | version = RTL_VER_09; | |
5101 | break; | |
33928eed | 5102 | default: |
5103 | version = RTL_VER_UNKNOWN; | |
5104 | dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data); | |
5105 | break; | |
5106 | } | |
5107 | ||
eb3c28c1 ON |
5108 | dev_dbg(&intf->dev, "Detected version 0x%04x\n", version); |
5109 | ||
33928eed | 5110 | return version; |
5111 | } | |
5112 | ||
ac718b69 | 5113 | static int rtl8152_probe(struct usb_interface *intf, |
5114 | const struct usb_device_id *id) | |
5115 | { | |
5116 | struct usb_device *udev = interface_to_usbdev(intf); | |
33928eed | 5117 | u8 version = rtl_get_version(intf); |
ac718b69 | 5118 | struct r8152 *tp; |
5119 | struct net_device *netdev; | |
ebc2ec48 | 5120 | int ret; |
ac718b69 | 5121 | |
33928eed | 5122 | if (version == RTL_VER_UNKNOWN) |
5123 | return -ENODEV; | |
5124 | ||
10c32717 | 5125 | if (udev->actconfig->desc.bConfigurationValue != 1) { |
5126 | usb_driver_set_configuration(udev, 1); | |
5127 | return -ENODEV; | |
5128 | } | |
5129 | ||
5130 | usb_reset_device(udev); | |
ac718b69 | 5131 | netdev = alloc_etherdev(sizeof(struct r8152)); |
5132 | if (!netdev) { | |
4a8deae2 | 5133 | dev_err(&intf->dev, "Out of memory\n"); |
ac718b69 | 5134 | return -ENOMEM; |
5135 | } | |
5136 | ||
ebc2ec48 | 5137 | SET_NETDEV_DEV(netdev, &intf->dev); |
ac718b69 | 5138 | tp = netdev_priv(netdev); |
5139 | tp->msg_enable = 0x7FFF; | |
5140 | ||
e3ad412a | 5141 | tp->udev = udev; |
5142 | tp->netdev = netdev; | |
5143 | tp->intf = intf; | |
33928eed | 5144 | tp->version = version; |
5145 | ||
5146 | switch (version) { | |
5147 | case RTL_VER_01: | |
5148 | case RTL_VER_02: | |
c27b32c2 | 5149 | case RTL_VER_07: |
33928eed | 5150 | tp->mii.supports_gmii = 0; |
5151 | break; | |
5152 | default: | |
5153 | tp->mii.supports_gmii = 1; | |
5154 | break; | |
5155 | } | |
e3ad412a | 5156 | |
55b65475 | 5157 | ret = rtl_ops_init(tp); |
31ca1dec | 5158 | if (ret) |
5159 | goto out; | |
c81229c9 | 5160 | |
b5403273 | 5161 | mutex_init(&tp->control); |
ac718b69 | 5162 | INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); |
a028a9e0 | 5163 | INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t); |
ac718b69 | 5164 | |
ac718b69 | 5165 | netdev->netdev_ops = &rtl8152_netdev_ops; |
5166 | netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; | |
5bd23881 | 5167 | |
60c89071 | 5168 | netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | |
6128d1bb | 5169 | NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | |
c5554298 | 5170 | NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | |
5171 | NETIF_F_HW_VLAN_CTAG_TX; | |
60c89071 | 5172 | netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | |
6128d1bb | 5173 | NETIF_F_TSO | NETIF_F_FRAGLIST | |
c5554298 | 5174 | NETIF_F_IPV6_CSUM | NETIF_F_TSO6 | |
ccc39faf | 5175 | NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; |
c5554298 | 5176 | netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | |
5177 | NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | | |
5178 | NETIF_F_IPV6_CSUM | NETIF_F_TSO6; | |
db8515ef | 5179 | |
19c0f40d | 5180 | if (tp->version == RTL_VER_01) { |
5181 | netdev->features &= ~NETIF_F_RXCSUM; | |
5182 | netdev->hw_features &= ~NETIF_F_RXCSUM; | |
5183 | } | |
5184 | ||
7ad24ea4 | 5185 | netdev->ethtool_ops = &ops; |
60c89071 | 5186 | netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); |
ac718b69 | 5187 | |
f77f0aee JW |
5188 | /* MTU range: 68 - 1500 or 9194 */ |
5189 | netdev->min_mtu = ETH_MIN_MTU; | |
5190 | switch (tp->version) { | |
5191 | case RTL_VER_01: | |
5192 | case RTL_VER_02: | |
5193 | netdev->max_mtu = ETH_DATA_LEN; | |
5194 | break; | |
5195 | default: | |
5196 | netdev->max_mtu = RTL8153_MAX_MTU; | |
5197 | break; | |
5198 | } | |
5199 | ||
ac718b69 | 5200 | tp->mii.dev = netdev; |
5201 | tp->mii.mdio_read = read_mii_word; | |
5202 | tp->mii.mdio_write = write_mii_word; | |
5203 | tp->mii.phy_id_mask = 0x3f; | |
5204 | tp->mii.reg_num_mask = 0x1f; | |
5205 | tp->mii.phy_id = R8152_PHY_ID; | |
ac718b69 | 5206 | |
aa7e26b6 | 5207 | tp->autoneg = AUTONEG_ENABLE; |
5208 | tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100; | |
5209 | tp->duplex = DUPLEX_FULL; | |
5210 | ||
9a4be1bd | 5211 | intf->needs_remote_wakeup = 1; |
5212 | ||
c81229c9 | 5213 | tp->rtl_ops.init(tp); |
a028a9e0 | 5214 | queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); |
ac718b69 | 5215 | set_ethernet_addr(tp); |
5216 | ||
ac718b69 | 5217 | usb_set_intfdata(intf, tp); |
d823ab68 | 5218 | netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT); |
ac718b69 | 5219 | |
ebc2ec48 | 5220 | ret = register_netdev(netdev); |
5221 | if (ret != 0) { | |
4a8deae2 | 5222 | netif_err(tp, probe, netdev, "couldn't register the device\n"); |
ebc2ec48 | 5223 | goto out1; |
ac718b69 | 5224 | } |
5225 | ||
7daed8dc | 5226 | if (!rtl_can_wakeup(tp)) |
5227 | __rtl_set_wol(tp, 0); | |
5228 | ||
21ff2e89 | 5229 | tp->saved_wolopts = __rtl_get_wol(tp); |
5230 | if (tp->saved_wolopts) | |
5231 | device_set_wakeup_enable(&udev->dev, true); | |
5232 | else | |
5233 | device_set_wakeup_enable(&udev->dev, false); | |
5234 | ||
4a8deae2 | 5235 | netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); |
ac718b69 | 5236 | |
5237 | return 0; | |
5238 | ||
ac718b69 | 5239 | out1: |
d823ab68 | 5240 | netif_napi_del(&tp->napi); |
ebc2ec48 | 5241 | usb_set_intfdata(intf, NULL); |
ac718b69 | 5242 | out: |
5243 | free_netdev(netdev); | |
ebc2ec48 | 5244 | return ret; |
ac718b69 | 5245 | } |
5246 | ||
ac718b69 | 5247 | static void rtl8152_disconnect(struct usb_interface *intf) |
5248 | { | |
5249 | struct r8152 *tp = usb_get_intfdata(intf); | |
5250 | ||
5251 | usb_set_intfdata(intf, NULL); | |
5252 | if (tp) { | |
f561de33 | 5253 | struct usb_device *udev = tp->udev; |
5254 | ||
5255 | if (udev->state == USB_STATE_NOTATTACHED) | |
5256 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
5257 | ||
d823ab68 | 5258 | netif_napi_del(&tp->napi); |
ac718b69 | 5259 | unregister_netdev(tp->netdev); |
a028a9e0 | 5260 | cancel_delayed_work_sync(&tp->hw_phy_work); |
c81229c9 | 5261 | tp->rtl_ops.unload(tp); |
ac718b69 | 5262 | free_netdev(tp->netdev); |
5263 | } | |
5264 | } | |
5265 | ||
d9a28c5b | 5266 | #define REALTEK_USB_DEVICE(vend, prod) \ |
5267 | .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \ | |
5268 | USB_DEVICE_ID_MATCH_INT_CLASS, \ | |
5269 | .idVendor = (vend), \ | |
5270 | .idProduct = (prod), \ | |
5271 | .bInterfaceClass = USB_CLASS_VENDOR_SPEC \ | |
5272 | }, \ | |
5273 | { \ | |
5274 | .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \ | |
5275 | USB_DEVICE_ID_MATCH_DEVICE, \ | |
5276 | .idVendor = (vend), \ | |
5277 | .idProduct = (prod), \ | |
5278 | .bInterfaceClass = USB_CLASS_COMM, \ | |
5279 | .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \ | |
5280 | .bInterfaceProtocol = USB_CDC_PROTO_NONE | |
5281 | ||
ac718b69 | 5282 | /* table of devices that work with this driver */ |
5283 | static struct usb_device_id rtl8152_table[] = { | |
c27b32c2 | 5284 | {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)}, |
d9a28c5b | 5285 | {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)}, |
5286 | {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)}, | |
d5b07ccc RR |
5287 | {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)}, |
5288 | {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)}, | |
d9a28c5b | 5289 | {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)}, |
1006da19 | 5290 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)}, |
d248cafc | 5291 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)}, |
5292 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)}, | |
5293 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)}, | |
5294 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)}, | |
5295 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)}, | |
d065c3c1 | 5296 | {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)}, |
ac718b69 | 5297 | {} |
5298 | }; | |
5299 | ||
5300 | MODULE_DEVICE_TABLE(usb, rtl8152_table); | |
5301 | ||
5302 | static struct usb_driver rtl8152_driver = { | |
5303 | .name = MODULENAME, | |
ebc2ec48 | 5304 | .id_table = rtl8152_table, |
ac718b69 | 5305 | .probe = rtl8152_probe, |
5306 | .disconnect = rtl8152_disconnect, | |
ac718b69 | 5307 | .suspend = rtl8152_suspend, |
ebc2ec48 | 5308 | .resume = rtl8152_resume, |
7ec2541a | 5309 | .reset_resume = rtl8152_reset_resume, |
e501139a | 5310 | .pre_reset = rtl8152_pre_reset, |
5311 | .post_reset = rtl8152_post_reset, | |
9a4be1bd | 5312 | .supports_autosuspend = 1, |
a634782f | 5313 | .disable_hub_initiated_lpm = 1, |
ac718b69 | 5314 | }; |
5315 | ||
b4236daa | 5316 | module_usb_driver(rtl8152_driver); |
ac718b69 | 5317 | |
5318 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
5319 | MODULE_DESCRIPTION(DRIVER_DESC); | |
5320 | MODULE_LICENSE("GPL"); | |
c961e877 | 5321 | MODULE_VERSION(DRIVER_VERSION); |